CN113678261A - Semiconductor device and semiconductor module - Google Patents

Semiconductor device and semiconductor module Download PDF

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Publication number
CN113678261A
CN113678261A CN201980095117.3A CN201980095117A CN113678261A CN 113678261 A CN113678261 A CN 113678261A CN 201980095117 A CN201980095117 A CN 201980095117A CN 113678261 A CN113678261 A CN 113678261A
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China
Prior art keywords
film
region
semiconductor device
outermost peripheral
peripheral region
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CN201980095117.3A
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Inventor
西村一广
上野诚
荒木慎太郎
河本厚信
富冈昌则
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L23/3157—Partial encapsulation or coating
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Abstract

The present invention relates to a semiconductor device, which comprises: a semiconductor substrate having an active region through which a main current flows, and a termination region around the active region; a polyimide film disposed over the active region and over the end region; and a passivation film provided as a lower layer film of the polyimide film, the end region including a withstand voltage holding region and an outermost peripheral region provided in this order from the active region side, the polyimide film being provided with a cut residue portion of the outermost peripheral region excluded, the passivation film being provided as the lower layer film at least in a region where the polyimide film is provided.

Description

Semiconductor device and semiconductor module
Technical Field
The present invention relates to a semiconductor device, and more particularly to a semiconductor device used in the field of power electronics such as an inverter device.
Background
Semiconductor devices such as igbts (insulated Gate Bipolar transistors), MOSFETs (Metal-Oxide Semiconductor Field Effect transistors), and diodes have an active region through which a main current flows and a termination region for maintaining a withstand voltage. In the end region, an insulating film and a passivation film are provided on a semiconductor substrate for the purpose of voltage holding, protection of a semiconductor device, and the like, and polyimide, which is an organic coating film, is provided on the insulating film and the passivation film for the purpose of electrode protection and improvement of insulation.
Such a configuration is disclosed in fig. 1 of patent document 1 and fig. 4 of patent document 2, for example. In the peripheral withstand voltage region shown in fig. 1 of patent document 1, a nitride film as an insulating film and a 1 st passivation film is formed on a semiconductor substrate, and a polyimide film as a 2 nd passivation film is formed on the nitride film.
Generally, polyimide has photosensitivity, but due to fluctuation in photosensitivity, it is difficult to form the end face of the polyimide film to be flush with the end face of the metal layer in the manufacturing process.
Although not explicitly shown in patent document 1, in the voltage-resistant terminal region of fig. 4 of patent document 2, the polyimide film is formed to protrude above the semiconductor substrate so as to cover the insulating film at the edge portion of the semiconductor device, and the polyimide film is formed to be in contact with the semiconductor substrate, which is currently the structure of the edge portion of a general semiconductor device.
Patent document 1: japanese patent No. 5720647
Patent document 2: japanese patent No. 5943819
Disclosure of Invention
Currently, since the polyimide film is in contact with the semiconductor substrate at the edge portion of the semiconductor device, when the semiconductor device is encapsulated with a resin encapsulating material such as epoxy resin, if thermal stress is applied, the stress concentrates on the semiconductor substrate at the end portion of the polyimide film due to the stress of expansion and contraction of the resin encapsulating material and polyimide, and the semiconductor substrate may crack.
The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which the stress in the semiconductor substrate at the end of the polyimide film is reduced and the reliability is improved.
The semiconductor device according to the present invention includes: a semiconductor substrate having an active region through which a main current flows, and a termination region around the active region; a polyimide film disposed over the active region and over the end region; and a passivation film provided as a lower layer film of the polyimide film, the termination region including a withstand voltage holding region and an outermost peripheral region provided in this order from the active region side, the polyimide film being provided with a cut residue portion of the outermost peripheral region excluded, and the passivation film being provided as a lower layer film at least in a region where the polyimide film is provided.
ADVANTAGEOUS EFFECTS OF INVENTION
According to the semiconductor device of the present invention, when thermal stress is applied to the semiconductor device, the passivation film functions as a stress relaxation layer, and the stress applied to the semiconductor substrate can be reduced.
Drawings
Fig. 1 is a cross-sectional view showing a partial structure of an end region and an active region of a semiconductor module according to embodiment 1 of the present invention.
Fig. 2 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 1 of the present invention.
Fig. 3 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 2 of the present invention.
Fig. 4 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 3 of the present invention.
Fig. 5 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 4 of the present invention.
Fig. 6 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 5 of the present invention.
Fig. 7 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor device according to embodiment 6 of the present invention.
Fig. 8 is a partial cross-sectional view showing an outermost chip peripheral region of the semiconductor device according to embodiment 7 of the present invention.
Fig. 9 is a partial cross-sectional view showing an outermost chip peripheral region of the semiconductor device according to embodiment 8 of the present invention.
Fig. 10 is a partial cross-sectional view showing an outermost chip peripheral region of a semiconductor module according to embodiment 9 of the present invention.
Fig. 11 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor module according to embodiment 10 of the present invention.
Fig. 12 is a partial cross-sectional view showing the outermost peripheral region of the chip of the semiconductor module according to embodiment 11 of the present invention.
Fig. 13 is a partial cross-sectional view showing an outermost chip peripheral region of the semiconductor device according to embodiment 12 of the present invention.
Detailed Description
< introduction >
In the following description, the "active region" refers to a region through which a main current flows in an on state of the semiconductor device, and the "end region" refers to a region around the active region. In the following description, "outer" refers to a direction toward the outer periphery of the semiconductor device, and "inner" refers to a direction opposite to the "outer". In the following description, the conductivity type of the impurity is generally defined as "1 st conductivity type" and "2 nd conductivity type" as the P type having the conductivity opposite to the N type.
The drawings are schematically illustrated, and the relationship between the size and the position of the image shown in each of the different drawings is not necessarily described accurately, and can be changed as appropriate. In the following description, the same components are denoted by the same reference numerals and are shown, and their names and functions are also the same. Therefore, detailed description thereof will sometimes be omitted. In the present specification, the terms "above" and "over" do not exclude the presence of an inclusion between constituent elements. For example, the phrase "B provided over a" or "a covers B" may mean that another component C is provided between a and B or that no other component C is provided. In the following description, terms indicating specific positions and directions such as "upper", "lower", "side", "bottom", "front", and "back" are used in some cases, and these terms are used for convenience of understanding of the embodiments and have no relation to the directions in actual practice.
< embodiment 1>
Fig. 1 is a sectional view showing a part of the structure of an end region and an active region of a diode module 200 according to embodiment 1 of the present invention, and fig. 2 is a partial sectional view showing a chip outermost region of a diode chip 100 resin-packaged in the diode module 200. In fig. 2, only a characteristic structure is shown for convenience.
As shown in fig. 1, the semiconductor substrate 1 of the diode module 200 is roughly divided into two regions, an active region and an end region, and the end region is divided into a withstand voltage holding region and a chip outermost region in this order from the active region side. The outermost peripheral region of the chip includes a residual dicing portion that is a residual dicing portion of a dicing section with which a cutting edge for dicing comes into contact when the semiconductor substrate 1 is divided to form semiconductor chips.
The semiconductor substrate 1 shown in fig. 2 is, for example, a silicon (Si) substrate, and has a relatively low concentration (N) in order from the back surface side on which the cathode electrode 9 is provided-) And a drift layer 12 containing an N-type (1 st conductivity type) impurity of a relatively high concentration (N)+) The buffer layer 13 of N-type impurities of (3).
The drift layer 12 has, in its upper layer portion: an anode 9 containing a P-type (2 nd conductivity type) impurity provided in the active region; a plurality of guard rings 10 concentrically provided in the voltage holding region so as to surround the active region, the guard rings including P-type impurities; and a field stop layer 11 provided further outside outermost guard ring 10 and containing an N-type impurity.
Further, a silicon oxide film 2 is provided on the front surface side of the semiconductor substrate 1 so as to cover the end edge portion of the anode 9 to the inner end edge portion of the field stop layer 11, and an interlayer insulating film 3 is provided on the silicon oxide film 2. A metallic anode electrode 14 is provided on the anode 9, and a metallic field stop electrode 5 is provided on the inner edge of the field stop layer 11. The anode electrode 14 and the field stop electrode 5 partly climb on the insulating interlayer film 3, and the passivation film 4 is provided so as to cover the anode electrode 14, the field stop electrode 5, and the insulating interlayer film 3. The edge of the passivation film 4 extends to the outermost peripheral region of the chip, and the end face thereof is flush with the end face of the semiconductor substrate 1.
A polyimide film 6 is provided over the active region and over the end region excluding the dicing residue, and the entire semiconductor substrate 1 is encapsulated with a resin encapsulating material 7 such as epoxy resin, for example, together with the polyimide film 6.
Here, the passivation film 4 is formed using a silicon oxide film (TEOS oxide film) formed using TEOS (tetraethoxysilane) having a young's modulus and a linear expansion coefficient closer to those of polyimide and epoxy resin than the semiconductor substrate 1, which is silicon. Namely, the physical property values of the respective materials are as follows.
Silicon: young's modulus 185 GPa, linear expansion coefficient 2.3 ppm/deg.C
TEOS acidified film: young's modulus 80.1[ Gpa ], linear expansion coefficient 9[ ppm/DEG C ]
Polyimide (I): young's modulus 5[ GPa ], linear expansion coefficient 54[ ppm/DEG C ]
Epoxy resin: young's modulus 16 GPa and linear expansion coefficient 18 ppm/deg.C
In this way, since the passivation film 4 is formed as the lower layer film of the polyimide film 6 and the edge portion of the passivation film 4 extends to the outermost peripheral region of the chip, even when thermal stress is applied to the diode chip 100, the passivation film 4 is closer to the material physical properties of the polyimide film 6 and the resin sealing material 7 than the semiconductor substrate 1, and therefore, the deformation of the semiconductor substrate 1 is reduced, and the passivation film 4 itself functions as a buffer film when stress is applied, and therefore, the stress in the semiconductor substrate 1 at the edge portion of the polyimide film 6 is reduced, and the occurrence of cracks can be suppressed.
In addition, when the TEOS oxide film is used as the passivation film 4, since the adhesion force between the TEOS oxide film and the polyimide film is low, the stress in the semiconductor substrate 1 can be further reduced by utilizing this property.
That is, the interfacial adhesion between the TEOS oxide film and the polyimide is weaker than the interfacial adhesion between the polyimide and silicon and the interfacial adhesion between the epoxy resin and the polyimide, and the polyimide film 6 and the passivation film 4 are in a state of being easily peeled off, and when thermal stress is applied to the diode chip 100, peeling is promoted at the interface between the polyimide film 6 and the passivation film 4, and the stress is dispersed on the surface of the semiconductor substrate 1, whereby the stress in the semiconductor substrate 1 can be reduced.
Further, even when the polyimide film 6 and the passivation film 4 are peeled off, the electrode protection function and the insulating property improving function of the polyimide film 6 may be reduced, but since the function of reducing the stress in the semiconductor substrate 1 is improved, the specification of the semiconductor device is optimized in consideration of the trade-off relationship between these functions in designing the semiconductor device.
In addition, although embodiment 1 exemplifies a diode, the basic structure of the termination region is the same as that of an IGBT and a MOSFET as well as a diode, and therefore the structure of the termination region in embodiment 1 can be applied to an IGBT and a MOSFET as well as to all semiconductor devices having the same termination region.
< embodiment 2>
Fig. 3 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100A according to embodiment 2 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 3, the diode chip 100A is provided with an interlayer insulating film 3 as a lower layer film of the passivation film 4 in the outermost peripheral region of the chip.
The interlayer insulating film 3 is formed of, for example, a silicon oxide film formed by a cvd (chemical vapor deposition) method, a BPSG (boro-silicate glass) film, a PSG (phospho-silicate glass) film, or the like, and the interlayer insulating film 3 is formed in the outermost peripheral region of the chip when the silicon oxide film 2 (thermal oxide film) is formed in the withstand voltage holding region of the semiconductor substrate 1 by, for example, a thermal oxidation method (wet oxidation) and then the interlayer insulating film 3 is formed on the silicon oxide film 2.
By providing the interlayer insulating film 3 as a lower layer film of the passivation film 4 in this way, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced. That is, in the case of the CVD method, various films can be formed without being limited to the silicon oxide film, and the stress buffering function for the semiconductor substrate 1 can be enhanced by selecting a film having a physical property value closer to that of the polyimide film 6 and the passivation film 4.
Further, by providing the interlayer insulating film 3 as a lower layer of the passivation film 4, the difference in level between the passivation film 4 covering the field stop electrode 5 and the base can be reduced, and cracks in the passivation film 4 can be suppressed.
That is, if thermal stress is applied in a state where the diode chip 100A is packaged with epoxy resin or the like, plastic deformation occurs in the field stop electrode 5, stress is applied to the passivation film 4 alone, and cracks may occur at the corner CP where stress is most likely to concentrate. The occurrence of cracks can be suppressed by minimizing the deformation of the field stop electrode 5, and the occurrence of cracks can be suppressed compared to the diode chip 100 of embodiment 1 because the difference in height between the passivation film 4 and the base is reduced by providing the interlayer insulating film 3, and the amount of deformation of the field stop electrode 5 is reduced as compared to the reduction in thickness of the field stop electrode 5.
< embodiment 3>
Fig. 4 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100B according to embodiment 3 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 4, in the outermost peripheral region of the chip, the diode chip 100B has an interlayer insulating film 3 in contact with the passivation film 4 as a lower layer of the passivation film 4, and a silicon oxide film 2 provided as a lower layer of the interlayer insulating film 3.
The silicon oxide film 2 is formed by a thermal oxidation method (wet oxidation), and after the silicon oxide film 2 is formed by the thermal oxidation method on the withstand voltage holding region of the semiconductor substrate 1 and the outermost peripheral region of the chip, any one of a silicon oxide film, a BPSG film, and a PSG film is formed as the interlayer insulating film 3 on the silicon oxide film 2 by, for example, a cvd (chemical vapor deposition) method.
By providing the interlayer insulating film 3 and the silicon oxide film 2 as the lower layer of the passivation film 4 in this way, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.
Further, by providing the interlayer insulating film 3 and the silicon oxide film 2 as the lower layer of the passivation film 4, the difference in level between the passivation film 4 covering the field stop electrode 5 and the base can be reduced, and cracks in the passivation film 4 can be suppressed.
< embodiment 4>
Fig. 5 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100C according to embodiment 4 of the present invention, and shows only a characteristic configuration for convenience as in fig. 2.
As shown in fig. 5, in the outermost peripheral region of the chip, the diode chip 100C has an interlayer insulating film 3 in contact with the passivation film 4 as a lower layer film of the passivation film 4, a polysilicon film 31 provided as a lower layer film of the interlayer insulating film 3, and a silicon oxide film 2 provided as a lower layer film of the polysilicon film 31.
The polysilicon film 31 is formed by, for example, a CVD method, and after the silicon oxide film 2 is formed by a thermal oxidation method in the withstand voltage holding region and the outermost peripheral region of the chip of the semiconductor substrate 1, the polysilicon film 31 is formed by a CVD method on the silicon oxide film 2 in the outermost peripheral region of the chip. Since polysilicon does not function as a conductor and becomes an insulator when it is not doped with an impurity, polysilicon film 31 is formed so as not to be doped with an impurity in embodiment 4.
After the formation of the polysilicon film 31, any one of a silicon oxide film, a BPSG film and a PSG film is formed as the interlayer insulating film 3 on the silicon oxide film 2 in the withstand voltage holding region of the semiconductor substrate 1 and on the polysilicon film 31 in the outermost peripheral region of the chip.
By providing the interlayer insulating film 3, the polysilicon film 31, and the silicon oxide film 2 as the lower layer of the passivation film 4 in this way, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.
Further, by providing the interlayer insulating film 3, the polysilicon film 31, and the silicon oxide film 2 as lower layers of the passivation film 4, it is possible to reduce a difference in level between the passivation film 4 covering the field stop electrode 5 and the base, and to suppress cracking of the passivation film 4.
Further, the polysilicon film is a film used for forming a gate electrode of an IGBT, a MOSFET, or the like, and when the structure of the termination region in embodiment 4 is applied to an IGBT or a MOSFET, the formation of the polysilicon film 31 can be compatible with the formation of the gate electrode, and an additional step for forming the polysilicon film 31 does not need to be provided. In this case, the polysilicon film 31 is doped with impurities and becomes a conductor in the same manner as the gate electrode, but since the polysilicon film 31 is provided in the field stop electrode formation region where the depletion layer does not spread, the performance of the semiconductor device is not affected by being a semiconductor.
< embodiment 5>
Fig. 6 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100D according to embodiment 5 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 6, in the outermost peripheral region of the chip, the diode chip 100D includes, as a lower layer of the passivation film 4, an interlayer insulating film 3 in contact with the passivation film 4, a silicon oxide film 2 provided below the interlayer insulating film 3, a dummy electrode 51 provided concentrically with the field stop electrode 5 above the interlayer insulating film 3, and the passivation film 4 also covers the dummy electrode 51.
The dummy electrode 51 is made of the same material as the field stop electrode 5, for example, AlSi, and is formed by the same manufacturing method, for example, vapor deposition or sputtering.
By providing the dummy electrode 51 below the passivation film 4 in the outermost peripheral region of the chip in this manner, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.
Further, AlSi is an electrode material used in the manufacture of semiconductor devices, and if the anode electrode 14 shown in fig. 1 is formed using AlSi, it is possible to simultaneously form the dummy electrode 51 in the step of forming the anode electrode 14, and it is not necessary to provide an additional step for forming the anode electrode 14. This is also the same as for the field stop electrode 5.
< embodiment 6>
Fig. 7 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100E according to embodiment 6 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 7, in the outermost peripheral region of the chip, the diode chip 100E includes an interlayer insulating film 3 in contact with the passivation film 4 and a silicon oxide film 2 provided below the interlayer insulating film 3 as a lower layer of the passivation film 4, and a plurality of dummy electrodes 51 provided concentrically with the field stop electrodes 5 are provided above the interlayer insulating film 3, and the passivation film 4 also covers the plurality of dummy electrodes 51.
By providing the plurality of dummy electrodes 51 below the passivation film 4 in the outermost peripheral region of the chip, the stress buffering function for the semiconductor substrate 1 can be enhanced, and the stress in the semiconductor substrate 1 can be further reduced.
Further, by providing the plurality of dummy electrodes 51, the unevenness of the passivation film 4 increases, the polyimide film 6 fits into the unevenness, the polyimide film 6 is less likely to peel off due to the anchor effect, and the adhesion force of the polyimide film 6 is improved.
The anchor effect is an effect of increasing the bonding force because the effective area of the film bonded to the surface is increased due to the surface irregularities.
< embodiment 7>
Fig. 8 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100F according to embodiment 7 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 7, in the diode chip 100F, the passivation film 4, the interlayer insulating film 3, and the silicon oxide film 2 are not provided in the dicing residual portion in the outermost peripheral region of the chip, and the surface of the semiconductor substrate 1 is exposed.
As described above, the surface of the semiconductor substrate 1 is exposed at the dicing residual portion in the outermost peripheral region of the diode chip 100F, but this portion is a dicing cut portion in a wafer state, and is a portion having a dicing margin at the time of dicing, meaning that the surface of the semiconductor substrate 1 is exposed at the dicing cut portion.
Since the surface of the semiconductor substrate 1 is exposed at the dicing/cutting portion, the semiconductor substrate 1 is directly cut by a cutting blade (blade) for dicing at the time of dicing, and chipping of the cut surface defect can be reduced and the life of the cutting blade can be prolonged.
< embodiment 8>
Fig. 9 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100G according to embodiment 8 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 9, in the outermost peripheral region of the chip, the diode chip 100G has an interlayer insulating film 3 in contact with the passivation film 4 and a silicon oxide film 2 provided below the interlayer insulating film 3 as a lower layer of the passivation film 4, and the end edge portion of the polyimide film 6 is formed in a shape of a gentle inclined surface protruding downward.
By thus making the shape of the edge portion of the polyimide film 6 a gentle inclined surface in the outermost peripheral region of the chip, the stress applied to the edge portion of the semiconductor substrate 1 is reduced as compared with, for example, a polyimide film 6 having an edge portion that rises steeply as in the diode chip 100B shown in fig. 4.
In fig. 9, the shape of the edge portion of the polyimide film 6 is an inclined surface that is convex downward, but the shape is not limited to this shape, and may be a simple inclined surface, and may be any shape as long as the film thickness gradually decreases outward, or may be a step shape.
< embodiment 9>
Fig. 10 is a partial cross-sectional view showing the outermost peripheral region of the chip of the diode module 200A according to embodiment 9 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
The diode module 200A shown in fig. 10 is a semiconductor chip in which the diode chip 100F of embodiment 7 described with reference to fig. 8 is resin-packaged. In the diode module 200A, the polyimide film 6 is provided on the active region and the end region excluding the dicing residual portion, and the entire semiconductor substrate 1 is encapsulated with a resin encapsulating material 7 such as epoxy resin, for example, together with the polyimide film 6.
In the diode chip 100F, the passivation film 4 is formed as the lower layer film of the polyimide film 6 in the outermost peripheral region of the chip, and therefore, even when thermal stress is applied to the diode chip 100F, the passivation film 4 is closer to the material physical properties of the polyimide film 6 and the resin sealing material 7 than the semiconductor substrate 1, and therefore, deformation of the semiconductor substrate 1 is reduced, and the passivation film 4 itself functions as a buffer film when stress is applied, and therefore, stress in the semiconductor substrate 1 at the edge portion of the polyimide film 6 is reduced, and generation of cracks can be suppressed.
Therefore, even when thermal stress is applied to the diode module 200A in which the diode chip 100F is packaged by the resin package 7, the stress applied to the diode chip 100F from the resin package 7 can be reduced, and the occurrence of cracks in the polyimide film 6 can be suppressed, thereby improving reliability.
In addition, although the description has been made above with the diode module 200A including the diode chip 100F, the present invention is not limited to the diode chip 100F, and may include any of the diode chips 100A to 100E and 100G shown in fig. 2 to 7 and 9.
< embodiment 10>
Fig. 11 is a partial cross-sectional view showing the outermost peripheral region of the chip of the diode module 200B according to embodiment 10 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
The diode module 200B shown in fig. 11 is a semiconductor chip in which the diode chip 100F of embodiment 7 described with reference to fig. 8 is resin-packaged. In the diode module 200B, the upper passivation film 41 is provided so as to cover the surface of the polyimide film 6 of the diode chip 100F and the surface of the outermost peripheral region of the chip.
The upper passivation film 41 uses a TEOS oxide film. The interfacial adhesion between the TEOS oxide film and the epoxy resin is weaker than the interfacial adhesion between the epoxy resin and the polyimide, and when the diode chip 100F is packaged by the resin package 7, the resin package 7 and the upper passivation film 41 are in a state of being easily peeled off, and when thermal stress is applied to the diode module 200B, peeling is promoted at the interface between the resin package 7 and the upper passivation film 41, so that the stress applied to the diode chip 100F from the resin package 7 can be further reduced, and the occurrence of cracks in the polyimide film 6 can be suppressed, thereby improving reliability.
In addition, although the description has been made above with the diode module 200B including the diode chip 100F, the diode module is not limited to the diode chip 100F, and may include any of the diode chips 100A to 100E and 100G shown in fig. 2 to 7 and 9, and the same effects as described above can be obtained by providing the upper passivation film 41 so as to cover the surface of the polyimide film 6 and the surface of the outermost peripheral region of the chip in any of the diode chips.
< embodiment 11>
Fig. 12 is a partial cross-sectional view showing the outermost peripheral region of the chip of the diode module 200C according to embodiment 11 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
The diode module 200C shown in fig. 12 is a semiconductor chip in which the diode chip 100F of embodiment 7 described with reference to fig. 8 is resin-packaged. In the diode module 200C, the stress relaxation film 15 is provided so as to cover the surface of the polyimide film 6 of the diode chip 100F and the surface of the outermost peripheral region of the chip.
The stress buffering film 15 uses silicone gel or silicone rubber which is generally used as an insulating encapsulating material for semiconductor products.
By forming the stress buffering film 15 by applying silicone gel or silicone rubber to the surface of the polyimide film 6 and the surface of the outermost peripheral region of the chip of the diode chip 100F, the stress applied to the diode chip 100F from the resin sealing material 7 can be further reduced, and occurrence of cracks in the polyimide film 6 can be suppressed, thereby improving reliability.
< embodiment 12>
Fig. 13 is a partial cross-sectional view showing the outermost peripheral region of the diode chip 100H according to embodiment 12 of the present invention, and shows only a characteristic configuration for convenience similar to fig. 2.
As shown in fig. 13, the diode chip 100H is provided with a dummy region between the withstand voltage holding region and the dicing residual portion at the outermost peripheral region of the chip.
The dummy region has a dummy electrode 52 provided concentrically with the field stop electrode 5 provided in the withstand voltage holding region, and the passivation film 4 also covers the dummy electrode 52. The polyimide film 6 is provided on the active region and the end region excluding the cut residue, and the passivation film 4, the interlayer insulating film 3, and the silicon oxide film 2 are lower layers of the polyimide film 6.
The dummy electrode 52 is provided on the interlayer insulating film 3, and has a portion penetrating the interlayer insulating film 3 and the silicon oxide film 2 to reach the field stop layer 11 provided in the upper layer of the semiconductor substrate 1.
The dummy electrode 52 is made of the same material as the field stop electrode 5, for example, AlSi, and is formed by the same manufacturing method, for example, vapor deposition or sputtering.
Further, AlSi is an electrode material used in the manufacture of semiconductor devices, and if the anode electrode 14 shown in fig. 1 is formed using AlSi, it is possible to simultaneously form the dummy electrode 52 in the step of forming the anode electrode 14, and it is not necessary to provide an additional step for forming the anode electrode 14. This is also the same as for the field stop electrode 5.
As described above, by providing the dummy region having the dummy electrode 52 in the outermost peripheral region of the chip, when a crack is generated in the passivation film 4 due to application of thermal stress to the diode chip 100H, the electrical characteristics including the withstand voltage of the diode chip 100H may be degraded when the crack has progressed to the withstand voltage holding region, but even when the crack is generated in the passivation film 4, the dummy electrode 52 provided in the dummy region is a metal layer and is a ductile material, and therefore, large plastic deformation does not occur before the crack is generated, the crack does not propagate at a high speed, the progress of the crack to the withstand voltage holding region can be delayed, and the progress of the crack is prevented in the dummy region, and therefore, improvement in reliability and extension of the life of the diode chip 100H can be expected.
< application to silicon carbide semiconductor device >
In embodiments 1 to 12 described above, the semiconductor substrate 1 is a Si substrate, and the diode chips 100 to 100H are Si semiconductor devices, but by using a wide bandgap semiconductor substrate such as a silicon carbide semiconductor substrate as the semiconductor substrate 1, the size of the end region can be reduced, and the semiconductor devices can be miniaturized.
In addition, a semiconductor device using a wide band gap material such as silicon carbide (SiC) can be used for high-temperature and high-voltage applications.
Although the present invention has been described in detail, the above-described invention is merely exemplary in all aspects, and the present invention is not limited thereto. It is to be understood that numerous modifications, not illustrated, can be devised without departing from the scope of the invention.
In the present invention, the embodiments may be freely combined within the scope of the invention, and the embodiments may be appropriately modified or omitted.

Claims (16)

1. A semiconductor device, comprising:
a semiconductor substrate having an active region through which a main current flows, and a termination region around the active region;
a polyimide film disposed over the active region and over the end region; and
a passivation film provided as a lower layer film of the polyimide film,
the end region includes a withstand voltage holding region and an outermost peripheral region which are provided in this order from the active region side,
the polyimide film is provided so as to exclude a cut residue of the outermost peripheral region,
the passivation film is provided as an underlayer film at least in a region where the polyimide film is provided.
2. The semiconductor device according to claim 1,
an interlayer insulating film is provided as a lower layer film of the passivation film in the outermost peripheral region.
3. The semiconductor device according to claim 2,
and a thermally oxidized film provided as a lower layer film of the interlayer insulating film in the outermost peripheral region.
4. The semiconductor device according to claim 3,
and a polysilicon film provided between the interlayer insulating film and the thermal oxide film in the outermost peripheral region.
5. The semiconductor device according to claim 2,
the withstand voltage holding region has a field stop electrode provided concentrically with the active region on the interlayer insulating film,
the outermost peripheral region has at least 1 dummy electrode provided concentrically with the field stop electrode on the interlayer insulating film.
6. The semiconductor device according to claim 5,
the at least 1 dummy electrode includes a plurality of dummy electrodes arranged concentrically.
7. The semiconductor device according to claim 1,
the passivation film is not provided in the dicing residual portion of the outermost peripheral region, and the surface of the semiconductor substrate is exposed in the dicing residual portion.
8. The semiconductor device according to claim 2,
the withstand voltage holding region has a field stop electrode provided concentrically with the active region on the interlayer insulating film,
the end region further includes a dummy region provided between the pressure-resistant holding region and the cut residual portion,
the dummy region has a dummy electrode provided concentrically with the field stop electrode on the interlayer insulating film.
9. The semiconductor device according to any one of claims 1 to 8,
the edge of the polyimide film has a shape in which the film thickness gradually decreases toward the outside.
10. The semiconductor device according to any one of claims 1 to 8,
the passivation film is formed of a TEOS oxide film.
11. The semiconductor device according to claim 1,
the semiconductor substrate is a silicon carbide semiconductor substrate.
12. A semiconductor module in which the semiconductor device according to any one of claims 1 to 8 is encapsulated with a resin encapsulating material.
13. The semiconductor module of claim 12,
and an upper passivation film provided so as to cover a surface of the polyimide film and a surface of the outermost peripheral region.
14. The semiconductor module of claim 13,
the upper passivation film is formed of a TEOS oxide film.
15. The semiconductor module of claim 12,
the polyimide film further includes a stress buffering film provided so as to cover a surface of the polyimide film and a surface of the outermost peripheral region.
16. The semiconductor module of claim 15,
the stress buffering film is formed by silicone gel or silicone rubber.
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