JP2012174895A - High breakdown voltage semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor device in which lowering of breakdown voltage can be minimized when compared with a conventional high breakdown voltage semiconductor device.SOLUTION: A high breakdown voltage semiconductor device 100 comprises an n-type semiconductor layer 110 composed of silicon carbide, a barrier metal layer 128, a second electrode layer 130, a p-type resurf layer 116, a p-type edge termination layer 120, a p-type first guard ring layer 122 formed at a position surrounding the periphery of the edge termination layer 120 while spaced apart therefrom in the resurf layer 116, and a p-type second guard ring layer 118 formed at a position surrounding the periphery of the resurf layer 116 while spaced apart therefrom on the surface of the semiconductor layer 110. The interval of the innermost peripheral first guard ring layer 122 and the edge termination layer 120 is in the range of 3-5 μm.

Description

  The present invention relates to a high voltage semiconductor device, and more particularly to a high voltage semiconductor device made of silicon carbide.

  Conventionally, a high voltage semiconductor device made of silicon carbide is known (for example, see Patent Document 1). FIG. 11 is a diagram for explaining a conventional high voltage semiconductor device 900. FIG. 11A is a plan view of a conventional high voltage semiconductor device 900, and FIG. 11B is a cross-sectional view taken along line AA in FIG.

As shown in FIG. 11, a conventional high voltage semiconductor device 900 includes a first conductivity type (n-type) semiconductor layer 910 (n ⁺ type silicon carbide single crystal substrate 912 and n ⁻ type silicon carbide epitaxial layer made of silicon carbide. 914), a first electrode layer 928 formed of a barrier metal on part of the surface of the semiconductor layer 910, a second electrode layer 930 formed on the back surface of the semiconductor layer 910, and a surface of the semiconductor layer 910 The formed second conductivity type (p ⁻ type) RESURF layer 916 and the RESURF layer 916 are disposed inside the RESURF layer 916 and overlap with the end portion of the first electrode layer 928 in contact with the surface of the semiconductor layer 910. The edge termination layer 920 of the second conductivity type (p ⁺ type) is formed, and the edge of the edge termination layer 920 is formed inside the RESURF layer 916 so as to surround the edge termination layer 920. One or two or more second-conductivity-type (p ⁺ -type) first guard ring layers 922 having the same impurity concentration as the termination layer 920 are separated from the surface of the semiconductor layer 910 around the resurf layer 916. And a second guard ring layer 918 of one or more second conductivity type (p ⁻ type) having an impurity concentration similar to that of the RESURF layer 916. Note that in FIG. 11, reference numeral 924 denotes an insulating layer formed on part of the surface of the semiconductor layer 910 (outside the first electrode layer 928).

  According to the conventional high withstand voltage semiconductor device 900, it is possible to prevent a decrease in withstand voltage even if there are variations in the impurity concentration of the RESURF layer 916 and variations in the width and interval of the second guard ring layer 918 due to mask displacement or the like. .

JP 2003-101039 A

  However, silicon carbide semiconductors are difficult to control epitaxial growth and impurity activation rates, and it is difficult to accurately produce impurity concentrations in semiconductor layers and RESURF layers with current technology. However, there is a problem that the decrease in breakdown voltage cannot be sufficiently suppressed.

  Accordingly, an object of the present invention is to provide a high voltage semiconductor device capable of suppressing a decrease in breakdown voltage compared to the conventional high voltage semiconductor device 900.

[1] A high breakdown voltage semiconductor device of the present invention includes a first conductivity type semiconductor layer made of silicon carbide, a first electrode layer formed on a part of the surface of the semiconductor layer, and a back surface of the semiconductor layer. The formed second electrode layer, the second conductivity type resurf layer formed on the surface of the semiconductor layer, and formed inside the resurf layer, in contact with the surface of the semiconductor layer of the first electrode layer An edge termination layer of a second conductivity type disposed at a position overlapping with an end of the portion; and formed in a position surrounding the periphery of the edge termination layer in the RESURF layer so as to be spaced apart from the edge termination layer. A first guard ring layer of one or more second conductivity types having a certain impurity concentration and a surface of the semiconductor layer that surrounds the resurf layer so as to surround the resurf layer; A high-breakdown-voltage semiconductor device comprising one or two or more second-conductivity-type second guard ring layers having the same impurity concentration as the innermost circumference of the one or two or more first guard-ring layers The distance between the first guard ring layer and the edge termination layer is in the range of 3 μm to 5 μm.

[2] In the high voltage semiconductor device of the present invention, the first electrode layer is preferably made of a barrier metal that forms a Schottky junction with the semiconductor layer.

[3] The high breakdown voltage semiconductor device of the present invention may further include an ohmic layer formed between the edge termination layer and the first electrode layer and forming an ohmic junction with the edge termination layer. preferable.

[4] In the high breakdown voltage semiconductor device of the present invention, a channel stopper layer of a first conductivity type formed on the surface of the semiconductor layer and disposed so as to surround the second guard ring layer in a spaced manner; It is preferable to further include a third electrode layer formed on the channel stopper layer and electrically connected to the second electrode layer.

[5] In the high breakdown voltage semiconductor device of the present invention, it is preferable that the first electrode layer has a field plate region provided with an insulating layer between the first electrode layer and the semiconductor layer.

[6] In the high voltage semiconductor device of the present invention, it is preferable that the field plate region extends to the outside of the edge termination layer.

[7] In the high voltage semiconductor device of the present invention, it is preferable that the field plate region extends to the outside of the RESURF layer.

  According to the high breakdown voltage semiconductor device of the present invention, since the distance between the innermost first guard ring layer and the edge termination layer is in the range of 3 μm to 5 μm, as shown in FIG. Even when the impurity concentration deviates from the design value, the breakdown voltage is lower than when the distance between the innermost first guard ring layer and the edge termination layer is less than 3 μm or more than 5 μm. It is possible to suppress the decrease. For this reason, the high breakdown voltage semiconductor device of the present invention is a high breakdown voltage semiconductor device capable of suppressing a decrease in breakdown voltage as compared with the conventional high breakdown voltage semiconductor device 900.

1 is a diagram for explaining a high voltage semiconductor device 100 according to a first embodiment. 6 is a view for explaining a method of manufacturing the high voltage semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the high voltage semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the high voltage semiconductor device 100 according to the first embodiment. FIG. It is a figure which shows the structure of the high voltage | pressure-resistant semiconductor device 100a which concerns on a test example. It is a graph which shows the proof pressure of the high voltage | pressure-resistant semiconductor device 100a which concerns on a test example. FIG. 6 is a diagram for explaining a high voltage semiconductor device 102 according to a second embodiment. FIG. 10 is a view for explaining a high breakdown voltage semiconductor device 104 according to a first modification. FIG. 10 is a diagram for explaining a high breakdown voltage semiconductor device 106 according to Modification 2. FIG. 11 is a diagram for explaining a high breakdown voltage semiconductor device 108 according to Modification 3. It is a figure shown in order to explain the high voltage semiconductor device 200 concerning modification 4. It is a figure shown in order to demonstrate the conventional high voltage semiconductor device 900.

  Hereinafter, a high voltage semiconductor device of the present invention will be described based on an embodiment shown in the drawings.

[Embodiment 1]
1. Configuration of High Voltage Semiconductor Device 1 According to Embodiment 1 FIG. 1 is a diagram for explaining a high voltage semiconductor device 100 according to Embodiment 1. FIG. FIG. 1A is a plan view of the high voltage semiconductor device 100, and FIG. 1B is a cross-sectional view taken along the line AA in FIG. In FIG. 1A, the insulating layer 124 is not shown. Further, the barrier metal layer 128 is translucent.

As shown in FIG. 1, a high voltage semiconductor device 100 according to the first embodiment includes a semiconductor layer 110 (n ⁺ type silicon carbide single crystal substrate 112 and n ⁻ type silicon carbide epitaxial layer 114) made of n ^- type silicon carbide, A barrier metal layer (first electrode layer) 128 formed on a part of the surface of the semiconductor layer 110 and forming a Schottky junction with the semiconductor layer 110; and a second layer formed on the back surface of the semiconductor layer 110. The electrode layer 130, the p-type RESURF layer 116 formed on the surface of the semiconductor layer 110, the inside of the RESURF layer 116, and the end portion of the barrier metal layer 128 that is in contact with the surface of the semiconductor layer 110. a p ⁺ -type edge termination layer 120 disposed at the position, shape the inside of the RESURF layer 116, surrounding and spaced from the periphery of the edge termination layer 120 located Is a first guard ring layer 122 of one or more p ⁺ type having an impurity concentration substantially equal to that of the edge termination layer 120, the surface of the semiconductor layer 110, a position enclosing spaced apart around the RESURF layer 116 One or two or more p-type second guard ring layers 118 that are formed and have the same impurity concentration as the RESURF layer 116 are provided.

  In the high voltage semiconductor device 100 according to the first embodiment, the distance between the innermost first guard ring layer 122 and the edge termination layer 120 among the one or two or more first guard ring layers 122 is 3 μm to 5 μm. It is in the range. The high breakdown voltage semiconductor device 100 according to the first embodiment is a Schottky barrier diode.

The n ⁺ -type silicon carbide single crystal substrate 112 in the semiconductor layer 110 has an n-type impurity concentration of 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ (for example, 1 × 10 ¹⁹ cm ⁻³ ) and a thickness of The thing of 30 micrometers-400 micrometers (for example, 300 micrometers) can be used. Moreover, as the crystal polymorph of the n ⁺ type silicon carbide single crystal substrate 112, for example, 4H can be used. The n ⁻ type silicon carbide epitaxial layer 114 has an n type impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ (for example, 1 × 10 ¹⁶ cm ⁻³ ) and a thickness of ³ μm to 20 μm. (For example, 10 μm) can be used.

As barrier metal layer 128, a barrier metal layer made of a metal (eg, titanium) that forms a Schottky junction with n ⁻ type silicon carbide epitaxial layer 114 can be used. The barrier metal layer 128 may be used as an anode electrode as it is, or a metal film (for example, a laminated film or nickel film in which titanium and aluminum are laminated) that can be ohmic-connected to the barrier metal layer 128 may be used as an anode electrode. Good.

  As the second electrode layer 130, for example, a layered film in which titanium, nickel, and silver are stacked, a layered film in which nickel, titanium, nickel, and silver are stacked, or the like can be used. The second electrode layer 130 becomes a cathode electrode.

The RESURF layer 116 and the second guard ring layer 118 have the same p-type impurity concentration (for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ ). By optimizing the impurity concentration, width, depth, etc. of the RESURF layer 116 and the second guard ring layer 118, a breakdown voltage close to the ideal breakdown voltage can be obtained.

The edge termination layer 120 and the first guard ring layer 122 have the same p-type impurity concentration (for example, about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ).

  Barrier metal layer 128 has a field plate region provided between semiconductor layer 110 and insulating layer 124. The field plate region extends to the outside of the edge termination layer 120.

2. Method for Manufacturing High-Voltage Semiconductor Device 100 According to Embodiment 1 FIGS. 2 to 4 are views for explaining a method for manufacturing the high-voltage semiconductor device 100 according to the first embodiment. 2A to FIG. 2C, FIG. 3A to FIG. 3C, and FIG. 4A to FIG. 4C are process diagrams.

  The high voltage semiconductor device 1 according to the first embodiment can be manufactured by performing the following steps (S1) to (S8) as shown in FIGS.

(S1) Step of Preparing a Semiconductor Layer An n ⁻ type silicon carbide epitaxial layer 114 (thickness: on the upper surface of an n ⁺ type silicon carbide single crystal substrate 112 (thickness: 300 μm, impurity concentration: 1 × 10 ¹⁹ cm ⁻³ ) A semiconductor layer 110 having 10 μm and an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is prepared (see FIG. 2A).

(S2) First p-type impurity ion implantation step First, after the surface of the semiconductor layer 110 is cleaned, an opening is formed on the surface of the semiconductor layer 110 at a portion corresponding to the RESURF layer 116 and the second guard ring layer 118. A mask M1 is formed. Thereafter, a p-type impurity ion (for example, aluminum ion) is divided into a predetermined portion of the n ⁻ -type silicon carbide epitaxial layer 114 through the mask M1 in a plurality of stages, with a relatively high energy amount and a relatively small amount. Implantation is performed to form p-type impurity ion implantation regions 115 and 117 (see FIG. 2B). Thereafter, the mask M1 is removed. In the first p-type impurity ion implantation step, impurity ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M1.

(S3) Second p-type impurity ion implantation step Next, a mask M2 having openings in portions corresponding to the edge termination layer 120 and the first guard ring layer 122 is formed on the surface of the semiconductor layer 110. At this time, the gap between the innermost first guard ring layer 122 and the edge termination layer 120 is formed in a range of 3 μm to 5 μm. Thereafter, p-type impurity ions (for example, aluminum ions) are applied to a predetermined portion of the n ⁻ -type silicon carbide epitaxial layer 114 through the mask M2 in multiple stages, in the first p-type impurity ion implantation step. Also, a low energy amount and a large amount are implanted to form p-type impurity ion implantation regions 119 and 121 (see FIG. 2C). Thereafter, the mask M2 is removed. In the second impurity ion implantation step, impurity ions may be implanted under conditions where a thin silicon oxide film or the like is present in the opening of the mask M2.

(S4) Impurity Activation Step Next, after forming a protective resist layer (not shown) on the surface of the semiconductor layer 110, the protective resist layer is carbonized to form a graphite mask M3 (FIG. 3A). reference.). Thereafter, the semiconductor layer 110 is heated to a temperature of 1600 ° C. or higher to activate p-type impurities, and the RESURF layer 116, the second guard ring layer 118, the edge termination layer 120, and the first guard ring layer 122 are formed. (See FIG. 3B.) Thereafter, the graphite mask M3 is removed.

(S5) Insulating Layer Formation Step Next, an insulating film 124 is formed on the surface of the semiconductor layer 110 using a mask M4 (not shown). Thereafter, the mask M4 is removed (see FIG. 3C).

(S6) Backside ohmic layer forming step Next, after forming a metal layer (for example, nickel layer) on the backside of the semiconductor layer 110, the backside ohmic layer 130a is formed by heating the semiconductor layer 110 to a temperature of 1000 ° C. or higher. It is formed (see FIG. 4A).

(S7) Barrier Metal Layer Formation Step Next, a titanium layer is formed on part of the surface of the semiconductor layer 110 and the surface of the insulating layer 124 using a mask M5 (not shown), and then the semiconductor layer 110 is brought to a temperature of 500 ° C. The barrier metal layer 128 is formed by heating. Thereafter, the mask M5 is removed (see FIG. 4B).

(S8) Second Electrode Layer Formation Step Next, the second electrode layer 130 is formed by forming a laminated film 130b in which titanium, nickel, and silver are laminated on the surface of the back ohmic layer 130a (FIG. 4C). reference.).

  By performing the above steps, the high voltage semiconductor device 100 according to the first embodiment can be manufactured.

3. Advantageous Effects of High Voltage Semiconductor Device 100 According to Embodiment 1 According to the high voltage semiconductor device 100 according to the first embodiment, as shown in FIG. 6 described later, the innermost first guard ring layer 122 and the edge termination layer 120 are provided. Is within the range of 3 μm to 5 μm, so even if the impurity concentration in the RESURF layer 116 deviates from the design value, the innermost first guard ring layer 122 and the edge termination layer Compared with the case where the distance d to 120 is less than 3 μm or more than 5 μm, it is possible to suppress a decrease in the withstand voltage. Therefore, the high withstand voltage semiconductor device 100 according to the first embodiment is a high withstand voltage semiconductor device that can suppress a decrease in withstand voltage compared to the conventional high withstand voltage semiconductor device 900.

  Further, according to the high voltage semiconductor device 100 according to the first embodiment, since the field plate region in the barrier metal layer 128 extends to the outside of the edge termination layer 120, the impurity concentration in the RESURF layer 116 is less than the design value. Even when it is shifted to a lower side, it is possible to further suppress a decrease in breakdown voltage due to variation in impurity concentration without applying a load to the insulating layer 124.

[Test example]
The test example is the high voltage semiconductor device 100 according to the first embodiment (high voltage semiconductor device in which the distance d between the innermost first guard ring layer 122 and the edge termination layer 120 is in the range of 3 μm to 5 μm). Even when the impurity concentration in the RESURF layer 116 deviates from the design value, the distance d between the innermost first guard ring layer 122 and the edge termination layer 120 is less than 3 μm or more than 5 μm. This is a test example for showing that it is possible to suppress a decrease in breakdown voltage compared to the case.

  FIG. 5 is a diagram showing the structure of the high voltage semiconductor device 100a according to the test example. FIG. 6 is a graph showing the breakdown voltage of the high breakdown voltage semiconductor device 100a according to the test example.

In the test example, when the concentration of the RESURF layer 116 is a design value (3.5 × 10 ¹⁷ cm ⁻³ ) and when the concentration of the RESURF layer 116 is shifted to a lower value from the design value (2.5 × 10 ¹⁷ cm ⁻³ ), how much withstand voltage can be obtained when the distance d between the innermost first guard ring layer 122 and the edge termination layer 120 is changed to 1 μm, 3 μm, 5 μm, and 7 μm. Device fabrication and breakdown voltage measurement were performed. As a result, when the distance d between the innermost first guard ring layer 122 and the edge termination layer 120 is in the range of 3 μm to 5 μm, the concentration of the RESURF layer 116 deviates from the design value. Even when (2.5 × 10 ¹⁷ cm ⁻³ ), as shown in FIG. 6, when the distance d between the innermost first guard ring layer 122 and the edge termination layer 120 is less than 3 μm (for example, 1 μm). It was found that the decrease in the breakdown voltage can be suppressed as compared with the case of exceeding 5 μm (for example, 7 μm) (withstand voltage decrease amount: 400 V → 200 V).

[Embodiment 2]
FIG. 7 is a view for explaining the high voltage semiconductor device 102 according to the second embodiment.
The high withstand voltage semiconductor device 102 according to the second embodiment basically has the same configuration as that of the high withstand voltage semiconductor device 100 according to the first embodiment, but as shown in FIG. 7, the edge termination layer 120 and the barrier metal layer 128. The high-voltage semiconductor device 100 according to the first embodiment is different from the high-voltage semiconductor device 100 according to the first embodiment in that an ohmic layer 126 that forms an ohmic junction with the edge termination layer 120 is further provided.

  As described above, the high breakdown voltage semiconductor device 102 according to the second embodiment is different from the high breakdown voltage semiconductor device 100 according to the first embodiment in that it further includes the ohmic layer 126 described above. Since the distance d between the ring layer 122 and the edge termination layer 120 is in the range of 3 μm to 5 μm, as in the case of the high voltage semiconductor device 100 according to the first embodiment, compared to the case of the conventional high voltage semiconductor device 900. A high breakdown voltage semiconductor device capable of suppressing a decrease in breakdown voltage is obtained.

  The high voltage semiconductor device 102 according to the second embodiment further includes an ohmic layer 126 that is formed between the edge termination layer 120 and the barrier metal layer 128 and forms an ohmic junction with the edge termination layer 120. Thus, the potential of the edge termination layer 120 can be reliably set to the same potential as that of the barrier metal layer 120, so that a high breakdown voltage semiconductor device capable of further suppressing a decrease in breakdown voltage is obtained.

  The high voltage semiconductor device 102 according to the second embodiment further includes an ohmic layer 126 that is formed between the edge termination layer 120 and the barrier metal layer 128 and forms an ohmic junction with the edge termination layer 120. Except for the above, since the configuration is the same as that of the high voltage semiconductor device 100 according to the first embodiment, the corresponding effect among the effects of the high voltage semiconductor device 100 according to the first embodiment is directly provided.

  As mentioned above, although this invention was demonstrated based on said embodiment, this invention is not limited to said embodiment. The present invention can be carried out in various modes without departing from the spirit thereof, and for example, the following modifications are possible.

(1) FIG. 8 is a view for explaining the high breakdown voltage semiconductor device 104 according to the first modification. The high breakdown voltage semiconductor device 104 according to the first modification includes an n ⁺ -type channel stopper layer 132 formed on the surface of the semiconductor layer 110 and arranged so as to surround and surround the second guard ring layer 118. A third electrode 134 formed on the stopper layer 132 and electrically connected to the second electrode 130 is further provided. The high voltage semiconductor device 104 having such a configuration also has the same effect as the high voltage semiconductor device 100 according to the first embodiment.

(2) In the first embodiment, the present invention has been described by taking the high voltage semiconductor device 100 including the two first guard ring layers 122 as an example, but the present invention is not limited to this. FIG. 9 is a diagram for explaining the high breakdown voltage semiconductor device 106 according to the second modification. As shown in FIG. 9, the present invention can also be applied to the high breakdown voltage semiconductor device 106 including one first guard ring layer 122.

(3) In the first embodiment, the present invention has been described by taking the high voltage semiconductor device 100 in which the field plate region in the barrier metal layer 128 extends to the outside of the edge termination layer 120 as an example. It is not limited. FIG. 10 is a diagram for explaining the high breakdown voltage semiconductor device 108 according to the third modification. As shown in FIG. 10, the present invention can also be applied to a high voltage semiconductor device 108 in which the field plate region in the barrier metal layer 128 extends to the outside of the RESURF layer 116. In this case, even when the impurity concentration in the RESURF layer 116 deviates from the designed value, it is possible to further suppress the decrease in breakdown voltage due to the variation in impurity concentration.

(4) In Embodiment 1, aluminum ions are used as p-type impurity ions, but the present invention is not limited to this. Boron ions may be used as the p-type impurity ions.

(5) In the first embodiment, after forming a protective resist layer on the surface of the semiconductor layer 110, the impurity activation step is performed in a state where the protective resist layer is carbonized to form a graphite mask M3 on the surface of the semiconductor layer 110. Although performed, the present invention is not limited to this. After forming a protective resist layer on the front and back surfaces of the semiconductor layer 110, the impurity activation process may be performed in a state where the protective resist layer is carbonized and a graphite mask is formed on the front and back surfaces of the semiconductor layer 110.

(6) In the first embodiment, the present invention has been described by taking the high voltage semiconductor device 100 made of a Schottky barrier diode as an example, but the present invention is not limited to this. FIG. 11 is a diagram for explaining a high-voltage semiconductor device 200 according to the fourth modification. As shown in FIG. 11, the present invention can also be applied to a high voltage semiconductor device 200 made of a pn diode. The present invention can also be applied to power MOSFETs, IGBTs, thyristors and other high voltage semiconductor devices.

100, 102, 104, 106, 108, 200, 900 ... high breakdown voltage semiconductor device, 110, 910 ... semiconductor layer, 112, 912 ... n ⁺ type silicon carbide single crystal substrate, 114, 914 ... n ^- type silicon carbide epitaxial layer 115, 117, 119, 121 ... p-type impurity implantation region, 116, 916 ... RESURF layer, 118, 918 ... second guard ring layer, 120, 920 ... edge termination layer, 122, 922 ... first guard ring layer, 124, 924 ... insulating layer, 126 ... ohmic layer, 128, 928 ... barrier metal layer, 130, 930 ... second electrode layer, 130a ... back ohmic layer, 130b ... laminated film, 132, 932 ... channel stopper, 134, 934 ... third electrode layer, 136 ... ^{p +} -type diffusion layer, 138 ... anode electrode, M1, M2 ... mask M3 ... graphite mask

  Conventionally, a high voltage semiconductor device made of silicon carbide is known (for example, see Patent Document 1). FIG. 12 is a diagram for explaining a conventional high voltage semiconductor device 900. 12A is a plan view of a conventional high voltage semiconductor device 900, and FIG. 12B is a cross-sectional view taken along line AA in FIG. 12A.

As shown in FIG. 12, a conventional high breakdown voltage semiconductor device 900 includes a first conductivity type (n-type) semiconductor layer 910 (n ⁺ type silicon carbide single crystal substrate 912 and n ⁻ type silicon carbide epitaxial layer made of silicon carbide. 914), a first electrode layer 928 formed of a barrier metal on part of the surface of the semiconductor layer 910, a second electrode layer 930 formed on the back surface of the semiconductor layer 910, and a surface of the semiconductor layer 910 The formed second conductivity type (p ⁻ type) RESURF layer 916 and the RESURF layer 916 are disposed inside the RESURF layer 916 and overlap with the end portion of the first electrode layer 928 in contact with the surface of the semiconductor layer 910. The edge termination layer 920 of the second conductivity type (p ⁺ type) is formed, and the edge of the edge termination layer 920 is formed inside the RESURF layer 916 so as to surround the edge termination layer 920. One or two or more second-conductivity-type (p ⁺ -type) first guard ring layers 922 having the same impurity concentration as the termination layer 920 are separated from the surface of the semiconductor layer 910 around the resurf layer 916. And a second guard ring layer 918 of one or more second conductivity type (p ⁻ type) having an impurity concentration similar to that of the RESURF layer 916. Note that in FIG. 12, reference numeral 924 denotes an insulating layer formed on part of the surface of the semiconductor layer 910 (outside the first electrode layer 928).

Claims (7)

A first conductivity type semiconductor layer made of silicon carbide;
A first electrode layer formed on a part of the surface of the semiconductor layer;
A second electrode layer formed on the back surface of the semiconductor layer;
A second conductivity type RESURF layer formed on the surface of the semiconductor layer;
An edge termination layer of a second conductivity type formed in the RESURF layer and disposed at a position overlapping with an end portion of the first electrode layer in contact with the surface of the semiconductor layer;
A first guard ring layer of one or more second conductivity types formed at a position surrounding the edge termination layer in the RESURF layer so as to be spaced apart and having the same impurity concentration as the edge termination layer. When,
One or more second-conductivity-type second guard ring layers formed at positions on the surface of the semiconductor layer so as to surround and surround the RESURF layer and having the same impurity concentration as the RESURF layer. A high voltage semiconductor device comprising:
A high breakdown voltage semiconductor device, wherein a distance between an innermost first guard ring layer of the one or more first guard ring layers and the edge termination layer is in a range of 3 μm to 5 μm. The high voltage semiconductor device according to claim 1,
The high withstand voltage semiconductor device, wherein the first electrode layer is made of a barrier metal that forms a Schottky junction with the semiconductor layer. The high voltage semiconductor device according to claim 2,
A high breakdown voltage semiconductor device, further comprising an ohmic layer formed between the edge termination layer and the first electrode layer and forming an ohmic junction with the edge termination layer. In the high voltage semiconductor device according to claim 1 or 2,
A channel stopper layer of a first conductivity type formed on the surface of the semiconductor layer and disposed so as to surround and surround the second guard ring layer;
A high breakdown voltage semiconductor device, further comprising a third electrode formed on the channel stopper layer and electrically connected to the second electrode. In the high voltage semiconductor device according to any one of claims 1 to 4,
The high-voltage semiconductor device according to claim 1, wherein the first electrode layer has a field plate region provided with an insulating layer between the first electrode layer and the semiconductor layer. The high breakdown voltage semiconductor device according to claim 5,
The high withstand voltage semiconductor device according to claim 1, wherein the field plate region extends to the outside of the edge termination layer. The high breakdown voltage semiconductor device according to claim 5,
The high breakdown voltage semiconductor device, wherein the field plate region extends to the outside of the RESURF layer.