JP2013074148A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of having a sufficient surge current resistance by relaxing electric field concentration, and a manufacturing method thereof.SOLUTION: A semiconductor device comprises: an n-type semiconductor layer 1 as a semiconductor layer of a first conductivity type made of silicon carbide; a p++-type semiconductor layer 5a as a first impurity layer of a second conductivity type formed by surrounding an element region of a schottky diode on a plan view in a surface layer of the n-type semiconductor layer 1; a p++-type semiconductor layer 5b as a second impurity layer of the second conductivity type formed by surrounding the element region from the outside of at least the p++-type semiconductor layer 5a on the plan view in the surface layer of the n-type semiconductor layer 1; and an anode electrode 3 formed on the element region extending to a surface layer of the p++-type semiconductor layer 5a. Impurity concentration of the p++-type semiconductor layer 5a is 1×10cmor higher.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an element structure of a power semiconductor device and a manufacturing method thereof.

  When SiC (Silicon Carbide) -SBD (Schottky Barrier Diode) is used as a free-wheeling diode of an inverter, for example, overcurrent flows through SBD and current concentrates at the Schottky electrode end during reverse recovery when the transistor switches at high speed. However, the Schottky electrode may be destroyed.

  In order to suppress this, there is a structure in which, for example, a p + type semiconductor layer in contact with the Schottky electrode is formed in the vicinity of the Schottky electrode end (for example, Patent Document 1). In Patent Document 1, it is said that the characteristics are further improved by using an n-type injection layer.

  Further, in SiC-JBS (Junction Barrier Schottky), a configuration is also known in which a discrete p-type semiconductor layer is formed under a Schottky electrode to suppress element breakdown even when a forward surge large current flows ( For example, Patent Document 2), which is a preceding example of Patent Document 1.

JP 2009-277809 ([0030]-[0040] and FIG. 4) Japanese Patent No. 3770857 (FIG. 15)

  In order to obtain sufficient surge current resistance, it is necessary to form a p + type semiconductor layer having a relatively high concentration at the end of the anode electrode. However, in an element structure in which a p + type semiconductor layer is formed in the vicinity of the anode electrode end, when a high voltage is applied in the opposite direction, the electric field at the end of the p + type semiconductor layer rises, and in some cases, the element is destroyed. There is a problem that arises.

  In addition, in order to improve the production efficiency, when the junction point between the anode electrode and the p + type semiconductor layer is formed below the substrate surface, the electric field at the end of the p + type semiconductor layer further increases, so an electric field relaxation structure is necessary. It is.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device having sufficient surge current resistance by relaxing electric field concentration and a method for manufacturing the same.

The semiconductor device according to the present invention includes a first conductivity type semiconductor layer made of silicon carbide, and a second conductivity type first layer formed by surrounding the element region of the Schottky diode in plan view in the semiconductor layer surface layer. A second conductivity type second impurity layer formed by surrounding at least the element region from the outside in a plan view of the impurity layer and the semiconductor layer surface layer; and the first impurity layer surface layer And an anode electrode formed on the element region, wherein the impurity concentration of the first impurity layer is 1 × 10 ²⁰ cm ⁻³ or more.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing the semiconductor device described above, wherein (a) an implantation mask is provided on the semiconductor layer, and 1 × 10 ²⁰ cm ⁻ in the semiconductor layer surface layer. A step of implanting an impurity having a concentration of ³ or more; and (b) the first impurity layer and the second impurity layer formed in the step (a) and surrounding the element region of the Schottky diode in plan view in the semiconductor layer surface layer. Etching the surface layer of the semiconductor layer so that the impurity layer is exposed; (c) removing the implantation mask and activating the first impurity layer and the second impurity layer; Sacrificial oxidation of the first impurity layer and the second impurity layer; and (e) a Schottky diode formed by removing the sacrificial oxide film formed in the step (d) and extending to the surface layer of the first impurity layer. Characterized in that it comprises a step of forming an anode electrode of.

According to the semiconductor device of the present invention, the first conductivity type semiconductor layer made of silicon carbide and the second conductivity type semiconductor layer formed on the surface of the semiconductor layer so as to surround the element region of the Schottky diode in plan view. A first impurity layer; a second impurity layer of a second conductivity type formed by surrounding the element region from at least the outer side in plan view of the first impurity layer in the surface layer of the semiconductor layer; and the first impurity And an anode electrode formed on the element region so as to extend to the surface of the layer, and the impurity concentration of the first impurity layer is 1 × 10 ²⁰ cm ⁻³ or more, so that at the end of the first impurity layer Electric field concentration can be alleviated and sufficient surge current resistance can be obtained.

According to a method for manufacturing a semiconductor device according to the present invention, there is provided a method for manufacturing the semiconductor device described above, wherein (a) an implantation mask is provided on the semiconductor layer, and 1 × 10 ²⁰ is provided in the surface layer of the semiconductor layer. a step of implanting an impurity having a concentration of cm ⁻³ or more, and (b) the first impurity layer formed in the step (a) surrounding the element region of the Schottky diode in plan view in the semiconductor layer surface layer and the step Etching the surface layer of the semiconductor layer so that the second impurity layer is exposed; (c) removing the implantation mask and activating the first impurity layer and the second impurity layer; A step of sacrificing the first impurity layer and the second impurity layer; and (e) a Schottky extending from the sacrificial oxide film formed in the step (d) to the surface layer of the first impurity layer. By and forming an anode electrode of the diode, and reduce the electric field concentration in the impurity implantation region end may have a sufficient surge current resistance. Further, the process can be simplified and the manufacturing tact can be improved.

It is sectional drawing which shows the semiconductor device by Embodiment 1 of this invention. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is a characteristic view by Embodiment 1 of this invention. It is a characteristic view by Embodiment 1 of this invention. It is sectional drawing which shows the modification of this invention. It is sectional drawing which shows the semiconductor device by Embodiment 2 of this invention. It is a top view which shows the semiconductor device by Embodiment 2 of this invention. It is a characteristic view by Embodiment 2 of this invention. It is sectional drawing which shows the modification of this invention. It is sectional drawing regarding the manufacturing method of this invention. It is a characteristic view by Embodiment 2 of this invention. It is sectional drawing which shows the modification of this invention. It is sectional drawing which shows the modification of this invention.

<Embodiment 1>
<Configuration>
FIG. 1 is a cross-sectional view showing the configuration of the SiC-SBD according to the first embodiment of the present invention. As shown in FIG. 1, SiC-SBD has, for example, a thickness of 4 to 4 on a silicon carbide substrate 2 having a polytype of 4H and containing an n-type (first conductivity type) impurity at a relatively high concentration (n +). An n-type semiconductor layer 1 which is a drift layer containing an n-type impurity of 30 μm at a relatively low concentration (n−) is provided, and a p-type (second conductivity type) impurity is formed in an upper layer (surface layer) of the n-type semiconductor layer 1 The p− type semiconductor layer 4, the p ++ type semiconductor layer 5 a, and the p ++ type semiconductor layer 5 b including s are selectively disposed. The p− type semiconductor layer 4, the p ++ type semiconductor layer 5 a and the p ++ type semiconductor layer 5 b are formed so as to surround the element region on the n type semiconductor layer 1 in plan view.

  The n-type semiconductor layer 1 can be formed on the silicon carbide substrate 2 by, for example, epitaxial crystal growth using a chemical vapor deposition (CVD) method.

  An anode electrode 3 composed of a Ti (titanium) film is formed by physical vapor deposition so as to cover the upper portion of the n-type semiconductor layer 1 in the element region surrounded by the p− type semiconductor layer 4 and the p ++ type semiconductor layer. Has been. Since Ti has an appropriate work function with respect to SiC, it has a characteristic that can satisfy reverse characteristics at a low on-voltage, and is therefore used as an appropriate material.

  The main surface (back surface) of the silicon carbide substrate 2 opposite to the side on which the anode electrode 3 is disposed is covered with a metal silicide film such as nickel silicide, which is not shown, but becomes an ohmic electrode. The metal silicide film is covered with a metallized film suitable for solder bonding, and the metal silicide film and the metallized film constitute a cathode electrode.

  FIG. 2 is a plan view of the SiC-SBD shown in FIG. 1 viewed from the side on which the anode electrode 3 is formed, but the cathode electrode is omitted here. In addition, the arrow direction cross section in the AB line | wire of FIG. 2 is sectional drawing of FIG.

  The p − type semiconductor layer 4 formed in an annular shape is an example of an electric field relaxation structure for reducing the electric field strength when a reverse voltage is applied. Although a single ring is used here, other structures such as a plurality of ring shapes may be used.

  The p ++ type semiconductor layer 5 a (first impurity layer) and the p ++ type semiconductor layer 5 b (second impurity layer) are selectively formed in a ring shape on the p− type semiconductor layer 4. In the figure, the p ++ type semiconductor layer 5a is separated from the inside of the p ++ type semiconductor layer 5b to surround the element region. In the figure, the p ++ type semiconductor layer 5b has a plurality of ring shapes, but it may be singular.

  When a steep voltage is applied in the reverse direction of SiC-SBD, of the formed p ++ type semiconductor layers, the p ++ type semiconductor layer 5a in contact with the anode electrode 3 (in the drawing, the element region is located on the innermost side). A surge current is caused to flow in the surrounding layer in plan view.

In FIG. 3A, when a reverse surge current having a time length of 1 μs and a rising speed of less than 10 ns is applied to SiC-SBD, the effect of improving the maximum peak surge value (dV / dt) that does not damage the element is obtained. Show. The horizontal axis represents the dose (cm ⁻³ ), and the vertical axis represents the surge resistance ratio based on the SBD in which no p ++ type semiconductor layer is formed. The point described as “SBD” on the horizontal axis is a value in the case of an SBD in which no p ++ type semiconductor layer is formed.

The concentration described in Patent Document 1 [0038], the concentration that can be inferred by performing a process simulation, and the like, and the dose amount 5 × 10 ¹⁴ cm ⁻² in Patent Document 2 are set in multiple stages at an acceleration voltage of 10 to 200 keV. It is a concentration (specifically, less than 2 × 10 ¹⁹ cm ⁻³ ) that can be estimated by performing a process simulation or the like based on the description that a box-type profile is formed by performing ion implantation of aluminum separately. At 1 × 10 ¹⁹ cm ⁻³ , the improvement effect of the maximum peak surge value is not observed (that is, no increase in surge withstand ratio is observed), and the maximum concentration is rapidly increased around 1 × 10 ²⁰ cm ^−3. It has been found that an improvement effect of the peak surge value is produced (that is, a rapid rise in the surge withstand ratio is observed).

FIG. 3B shows the concentration dependence of the contact resistance measured using elements formed in the same wafer. The horizontal axis represents p + concentration (cm ⁻³ ), and the vertical axis represents contact resistance (Ωcm ² ).

On the other hand, the improvement effect of repetitive surge reverse power is considered to depend on the contact resistance between the anode electrode 3 and the p ++ type semiconductor layer 5a, and the concentration of the p ++ type semiconductor layer is changed from 5 × 10 ¹⁹ cm ⁻³ to 1 ×. By setting it to 10 ²⁰ cm ⁻³ , the resistance is reduced by about two digits (in FIG. 3B, from 1 × 10 ¹ (Ωcm ² ) to 1 × 10 ⁻¹ (Ωcm ² )). Low resistance). Therefore, it was confirmed that an effective improvement effect can be obtained by setting the concentration of the p ++ type semiconductor layer to 1 × 10 ²⁰ cm ⁻³ or more.

  FIG. 4 shows an electric field ratio at the time of breakdown generated around the p ++ type semiconductor layer when the formation interval of the plurality of p ++ type semiconductor layers is changed. The horizontal axis represents the p ++ type semiconductor layer formation interval (μm), and the vertical axis represents the maximum electric field strength ratio.

Two rings, which are the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b, were formed at a predetermined interval. The concentration of each p ++ type semiconductor layer was 2 × 10 ²⁰ cm ⁻³ .

  Referring to FIG. 4, it can be seen that when the formation interval is approximately a value of about 2 μm, the electric field relaxation effect is improved as compared with a case where no interval is provided (that is, a single ring shape). On the other hand, the dependency of the width of the p ++ type semiconductor layer on the electric field relaxation effect was not observed.

When the p ++ type semiconductor layer 5a having a high concentration is provided at the end of the anode electrode 3, the concentration of the p− type semiconductor layer 4 is particularly prepared at a low concentration of about 1 × 10 ^{17 to} 2.5 × 10 ¹⁷ cm ^−3. In some cases, it was found that if the p ++ type semiconductor layer is formed as a single ring similar to the conventional case, a high electric field is generated at the outer periphery thereof, and dielectric breakdown may occur at the relevant location immediately before exhibiting the avalanche characteristics. .

  However, as shown in the present embodiment, it has been found that the generation of a high electric field can be suppressed by dividing the p ++ type semiconductor layer into a plurality of ring shapes (p ++ type semiconductor layer 5a and p ++ type semiconductor layer 5b). For example, when the width of each ring of the p ++ type semiconductor layer is 1 μm and provided at intervals of 2 μm, the improvement effect is exhibited.

  Since the end portion of the anode electrode 3 can be protected by the p ++ type semiconductor layer 5a having a sufficiently high concentration, the structure of the p− type semiconductor layer 4 can be freely designed, and the termination structure can be formed by using only two types of p type semiconductor layers. It will be possible to contribute to the downsizing.

<Manufacturing method>
Next, the manufacturing method of SiC-SBD is demonstrated.

  A silicon carbide substrate 2 having a specific resistance of, for example, 15 to 25 mΩcm is prepared, and n-type semiconductor layer 1 is formed on one main surface of silicon carbide substrate 2 by, for example, epitaxial crystal growth using a CVD method.

Here, it is desirable to introduce phosphorus (P) or nitrogen (N) into the n-type semiconductor layer 1 as an n-type impurity at a concentration of 3 × 10 ^{15 to} 3 × 10 ¹⁶ cm ^−3. The thickness of the semiconductor layer 1 was 8 to 9 μm, and the impurity concentration was 6 × 10 ¹⁵ cm ⁻³ .

  Next, an implantation mask having an annular opening is formed on the n-type semiconductor layer 1. The opening of the implantation mask is a portion corresponding to the formation region of the annular p − type semiconductor layer 4.

Thereafter, ion implantation (impurity implantation) of a p-type impurity such as aluminum (Al) is performed from above the implantation mask to form the p − type semiconductor layer 4. Here, the implantation conditions were set so that the concentration was, for example, 1 × 10 ¹⁷ to 2 × 10 ¹⁷ cm ⁻³ . Alternatively, the ion implantation conditions can be set so that the total implantation amount is 7 × 10 ^{12 to} 1.5 × 10 ¹³ cm ⁻² at an acceleration energy of 300 to 700 keV.

Next, the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b are formed by the method described above. In order to form the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b, the implantation conditions were set so that the acceleration energy was about 30 to 90 keV and the concentration was 1 × 10 ^{20 to} 5 × 10 ²⁰ cm ⁻³ . The substrate temperature is 200 ° C., for example, but may be from about 700 ° C. without heating.

  Next, after removing the implantation mask, prior to the activation annealing treatment of the implanted impurities, a graphite film having a thickness of less than 1 μm (for example, 30 nm) is formed on the n-type semiconductor layer 1 by a low pressure CVD method. It is formed on the entire surface layer of the silicon carbide substrate 2.

  In the activation annealing of impurities, when Si and carbon (C) as constituent elements are evaporated from the surface layer of the silicon carbide substrate 2 exposed to a high temperature, the evaporation conditions of Si and C are different and the crystal axis is inclined. Therefore, the evaporation amounts of Si and C are different within the silicon carbide substrate 2 surface. The above graphite film is provided to prevent the formation of an uneven surface called step bunching on the surface layer of the silicon carbide substrate 2 due to different amounts of evaporation of Si and C within the surface of the silicon carbide substrate 2. .

  After the formation of the graphite film, the silicon carbide substrate 2 is subjected to activation annealing at about 1700 ° C. in an argon atmosphere to complete the p− type semiconductor layer 4, the p ++ type semiconductor layer 5 a and the p ++ type semiconductor layer 5 b.

  Next, after removing the graphite film, a sacrificial oxide film is formed by thermal oxidation in an oxygen atmosphere on the entire surface layer of the silicon carbide substrate 2 on which the n-type semiconductor layer 1 is formed.

  The sacrificial oxide film is a film for modifying the surface altered layer in the silicon carbide layer generated by activation annealing or the like into an oxide film and finally removing it. By removing the sacrificial oxide film, a surface layer of the silicon carbide layer that becomes a stable Schottky interface can be obtained.

  Further, sacrificial oxidation is performed and the sacrificial oxide film is removed, so that a portion of the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b that is formed only in a state where the concentration of the outermost layer is low is removed. The contact resistance between the type semiconductor layer 5a and the anode electrode 3 can be made sufficiently small.

  Next, in order to form an ohmic electrode, the back surface of the silicon carbide substrate 2 is removed by machining to a thickness of 1 to 200 μm, and then a Ni film having a thickness of 50 to 200 nm is formed. Thereafter, annealing at 1000 ° C. is performed in vacuum, and the Ni film in contact with the silicon carbide layer is silicided to form a Ni silicide film.

  Next, the sacrificial oxide film remaining on the main surface on the side where the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b are disposed is removed with a hydrofluoric acid solution, and then the p ++ type semiconductor layer 5a and the p ++ type semiconductor are formed by sputtering. A Ti film having a thickness of 100 to 500 nm is formed on the entire main surface on the side where the layer 5b is provided.

Etching is performed so that the Ti film remains on the region where the p ++ type semiconductor layer 5a and the p ++ type semiconductor layer 5b are disposed, and the anode electrode 3 composed of the Ti film is formed. Here, a film thickness of 200 nm was formed at a target power density of ² to 10 Wcm ⁻² .

  Thereafter, in order to stabilize the height of the Schottky barrier, annealing is performed at 400 to 700 ° C., more preferably 450 ° C. in an inert gas atmosphere or in a vacuum.

  Although illustration is omitted, after the anode electrode 3 and the cathode electrode are formed, a wiring layer made of Al or Cu having a thickness of 2 to 20 μm is formed, and the wiring layer and the p − type semiconductor layer 4 are formed. In order to protect the surface layer of the p ++ type semiconductor layer, for example, a polyimide resin layer having a thickness of 3 to 20 μm is formed.

  Further, by forming a metallized film composed of a Ti / Ni / Au laminated film on the Ni silicide film on the back surface of the silicon carbide substrate 2, a cathode electrode is formed by the metal silicide film and the metallized film. Complete.

<Modification>
FIG. 5 is a cross-sectional view of a SiC-SBD provided with a plurality of p ++ type semiconductor layers 51 (first impurity layers) having discrete structures near the end of the anode electrode 3. Although the p ++ type semiconductor layer 51 is divided into two ring shapes in the figure, it can be configured such that, for example, a mesh with a pitch of 4 μm is assumed, and dots of about 2 μm, for example, are arranged therein. Alternatively, a plurality of rings having a width of 1 μm can be arranged at a pitch of 3 μm. As shown in the figure, the anode electrode 3 extends across the surface layers of the plurality of p ++ type semiconductor layers 51.

The plurality of p ++ type semiconductor layers 51 formed so as to be separated from each other has a high electric field generated around the p ++ type semiconductor layer 51 because the effective concentration obtained by spatial averaging decreases to about 10 ¹⁹ cm ^−3. Can be suppressed. In this way, contact with the anode electrode 3 can be ensured, and the electric field can be relaxed.

<Effect>
According to the embodiment of the present invention, in the semiconductor device, the n-type semiconductor layer 1 as the first conductivity type semiconductor layer made of silicon carbide and the Schottky diode element region in the surface layer of the n-type semiconductor layer 1 are provided. In the p ++ type semiconductor layer 5a as the first impurity layer of the second conductivity type and the surface layer of the n-type semiconductor layer 1 formed so as to be surrounded in plan view, at least the element region is outside in plan view of the p ++ type semiconductor layer 5a. A p ++ type semiconductor layer 5b as a second impurity layer of the second conductivity type, and an anode electrode 3 extending to the surface layer of the p ++ type semiconductor layer 5a and formed on the element region. When the impurity concentration of the p ++ type semiconductor layer 5a is 1 × 10 ²⁰ cm ⁻³ or more, the electric field concentration at the end of the p ++ type semiconductor layer 5a is alleviated, and a high voltage is applied in the forward and reverse directions. Ten It may have a surge current resistance.

  Even if the concentration of the p ++ type semiconductor layer 5a is increased, the p ++ type semiconductor layer 5b surrounds the p ++ type semiconductor layer 5a to form an electric field relaxation structure, thereby reducing the p− type semiconductor layer 4 as shown in FIG. The p − type semiconductor layer 4 can be designed to be small.

According to the embodiment of the present invention, in the semiconductor device, the p ++ type semiconductor layer 5b as the second impurity layer is formed apart from the p ++ type semiconductor layer 5a as the first impurity layer. When the impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more, the p ++ type semiconductor layer 5b is surrounded by the p ++ type semiconductor layer 5b so as to form an electric field relaxation structure.

  Further, according to the embodiment of the present invention, in the semiconductor device, a plurality of p ++ type semiconductor layers 51 as the first impurity layers are formed apart from each other so as to surround the element region in plan view. By being a layer, the effective concentration obtained by spatial averaging is reduced, so that the electric field at the end of the p ++ type semiconductor layer 51 can be relaxed.

  Further, according to the embodiment of the present invention, in the semiconductor device, the p ++ type semiconductor layer 5a as the first impurity layer and the p ++ type semiconductor layer 5b as the second impurity layer are spaced from each other by 1 to 3 μm. By forming them apart from each other, the forward surge resistance and the reverse recovery surge resistance can be improved.

<Embodiment 2>
<Configuration>
FIG. 6 is a cross-sectional view showing the configuration of the SiC-JBS diode according to the second embodiment of the present invention. The structure is almost the same as that shown in the first embodiment, except that a p ++ type semiconductor layer 50 is formed below the anode electrode 3.

  A Ti (titanium) film is used for the anode electrode 3. Since Ti has an appropriate work function, it has a low on-voltage and can satisfy reverse characteristics, and is therefore used as an appropriate material.

  FIG. 7 is a plan view of the SiC-JBS diode shown in FIG. 6 as viewed from the side on which the anode electrode 3 is formed, but the cathode electrode is omitted here. In addition, the arrow direction cross section in the AB line | wire of FIG. 7 is sectional drawing of FIG.

  For example, as shown in FIG. 7, the p ++ type semiconductor layers 50 (fourth impurity layers) each have a stripe-like plan view shape, and are distributed on the element region of the n-type semiconductor layer 1 so as to be separated from each other. Yes. As an example of the arrangement, striped p ++ type semiconductor layers 50 having a width of 2 to 30 μm are arranged with an interval of 1 to 20 μm.

  6 and 7 show an example in which two p ++ type semiconductor layers 50 are arranged for simplification. However, since the semiconductor device is actually a square having a side of several millimeters, more and more are shown. The p ++ type semiconductor layer 50 is disposed.

  The operation of this SiC-JBS type diode is as follows. In the element region on the n-type semiconductor layer 1 where the p ++ type semiconductor layer 50 is not provided, when the voltage is applied in the forward direction, It functions as a Schottky junction diode in which a current flows toward the type semiconductor layer 1.

  At this time, not only the current flows vertically downward from the n-type semiconductor layer 1 in contact with the anode electrode 3, but also the current flows with a horizontal spread angle, so that the current flows from the anode electrode 3 in the vicinity of the p ++ type semiconductor layer 50. The flowing current also flows into the n-type semiconductor layer 1 below the p ++ type semiconductor layer 50. Thus, the forward resistance decreases as the current spreads in the horizontal direction.

  On the other hand, when a voltage is applied to the SiC-JBS type diode in the reverse direction, a depletion layer is formed so as to spread all over the p ++ type semiconductor layer 50 and the p− type semiconductor layer 4, so that the voltage is maintained. And a low reverse current is maintained.

  Here, when a forward voltage that causes an overcurrent far exceeding the rated current is applied to the SiC-JBS type diode, the p ++ type semiconductor layer 50 and the n type semiconductor layer 1 are configured. Also in the pn junction diode, the on-voltage is exceeded, and a current flows from the p ++ type semiconductor layer 50 toward the n type semiconductor layer 1.

FIG. 8 shows the result of measuring the forward surge resistance (current square time product) with a half-wave sine wave having a time length of 10 ms when the anode electrode 3 formed of Ti is used. The horizontal axis represents the dose (cm ⁻³ ), and the vertical axis represents the surge resistance ratio based on the SBD in which no p ++ type semiconductor layer is formed. The point described as “SBD” on the horizontal axis is a value in the case of an SBD in which no p ++ type semiconductor layer is formed.

When the concentration of the p ++ type semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ , which is the concentration described in Patent Document 1 and Patent Document 2, no effect of improving the forward surge resistance is observed (that is, the surge resistance). No increase in the ratio was observed), and it was found that the effect of improving the maximum peak surge value abruptly occurred in the vicinity of the concentration of 1 × 10 ²⁰ cm ⁻³ (that is, a rapid increase in the surge withstand ratio was observed).

<Modification 1>
FIG. 9 is a cross-sectional view showing a modification of the SiC-JBS type diode of the second embodiment. As shown in FIG. 9, the p ++ type semiconductor layer 52a (first impurity layer), the p ++ type semiconductor layer 52b (second impurity layer), and the p ++ type semiconductor layer 53 (fourth impurity layer) are each a p− type semiconductor layer. It is formed in a concave structure with four surface layers and one surface layer of the n-type semiconductor layer. The p ++ type semiconductor layer 52a may be divided into a plurality of ring shapes as shown in FIG.

  Since the p ++ type semiconductor layer has a high concentration, in order to form by ion implantation, it may be desirable to use an implantation energy of medium acceleration or higher that can obtain a high beam current without using low acceleration energy.

  In such a case, low acceleration implantation in which ions of a sufficient concentration are implanted into these surface layers may cause a decrease in throughput and a decrease in stability. Therefore, a structure formed when an implantation energy of medium acceleration or higher is used will be described below.

  10A to 10C show a process for forming the p ++ type semiconductor layer 52a, the p ++ type semiconductor layer 52b, and the p ++ type semiconductor layer 53. FIG. A mask 10 made of silicon oxide, silicon nitride, high heat resistant resin, or the like is formed at a desired location (FIG. 10A).

For example, the aluminum ions 11 are implanted so that the energy in the range from 120 to 190 nm is 2 × 10 ²⁰ cm ⁻³ at an energy of 90 to 150 keV (FIG. 10B).

  Subsequently, etching is performed to a desired depth such as 140 nm with a fluorocarbon gas to obtain a desired surface layer concentration (FIG. 10C).

  In order to improve the resistance at the time of reverse recovery in the JBS type diode, when a p ++ type semiconductor layer is provided at the end of the anode electrode 3, the p ++ type semiconductor layer 52a, the p ++ type semiconductor layer 52b, and the p ++ type semiconductor layer are formed to reduce the manufacturing process cost. 53 is manufactured in the same process. At this time, if the p ++ type semiconductor layer becomes a single ring similar to the conventional example, a high electric field is generated at the outer periphery of the p ++ type semiconductor layer, immediately before the avalanche characteristic is exhibited. Dielectric breakdown can occur at the location.

  FIG. 11 shows the maximum electric field value at the time of breakdown generated around the p ++ type semiconductor layer when the formation interval of the plurality of p ++ type semiconductor layers is changed. The horizontal axis indicates the p ++ type semiconductor layer formation interval (μm), and the vertical axis indicates the electric field strength (MV / cm).

The width of the p ++ type semiconductor layer itself was 1 μm, and the two rings were set at a predetermined interval. The concentration of the p ++ type semiconductor layer was 2 × 10 ²⁰ cm ⁻³ (Legend ○) and 1 × 10 ²⁰ cm ⁻³ (Legend ×). Moreover, the dent structure was 100 nm deep.

  Referring to FIG. 11, it can be seen that when the formation interval is set to a value centering around 3 μm, the electric field relaxation effect is improved as compared with the case where no interval is provided (that is, in the case of a single ring shape). Specifically, it can be seen that the electric field strength can be halved. On the other hand, the dependency of the width of the p ++ type semiconductor layer on the electric field relaxation effect was not observed.

  Further, when the depth of the dent structure is 50 nm or more and several hundred nm or less, no significant characteristic change was observed.

  Thus, it has been found that the generation of a high electric field can be suppressed by dividing the p ++ type semiconductor layer into a plurality of ring shapes (p ++ type semiconductor layer 52a and p ++ type semiconductor layer 52b). For example, the improvement effect was exhibited by setting the width of each ring of the p ++ type semiconductor layer 52a and the p ++ type semiconductor layer 52b to 1 μm and providing them at intervals of 3 μm.

<Modification 2>
In FIG. 12, a p + type semiconductor layer 6 (second impurity layer) is formed on the surface layer of the p − type semiconductor layer 4 (third impurity layer), and a p + type semiconductor having a single ring shape is formed on the surface layer of the p + type semiconductor layer 6. It is sectional drawing of the structure in which layer 52a (1st impurity layer) was formed. In FIG. 12, the p ++ type semiconductor layer 52a, the p + type semiconductor layer 6, and the p ++ type semiconductor layer 53 are formed in the concave structure of the surface layer of the n type semiconductor layer 1, but are formed in a portion that is not the concave structure. There may be. Further, the p ++ type semiconductor layer 53 may not be provided.

The p + type semiconductor layer 6 (second impurity layer) is formed deeper than the p + + type semiconductor layer 52a (first impurity layer), for example, at a concentration of 3 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . Alternatively, it is effectively formed deeper than the p ++ type semiconductor layer 52a with an implantation amount of 2 × 10 ^{13 to} 5 × 10 ¹⁴ cm ⁻² .

  Although the implantation step is increased once compared with the case of the above embodiment, the p ++ type semiconductor layer 52a can be formed efficiently, so that an expected device can be efficiently produced with only a slight decrease in throughput.

  FIG. 13 is a cross-sectional view of a floating guard ring structure with a medium concentration p + -type semiconductor layer 60 (second impurity layer). A p + type semiconductor layer 6 (second impurity layer) is formed on the surface layer of the n type semiconductor layer 1, and a single ring-shaped p ++ type semiconductor layer 52 a (first impurity layer) is formed on the surface layer of the p + type semiconductor layer 6. In addition, in the surface layer of the n-type semiconductor layer 1, p + -type semiconductor layers 60 that are separated from each other are formed so as to surround the p + -type semiconductor layer 6 in plan view.

  In FIG. 13, the p ++ type semiconductor layer 52a, the p + type semiconductor layer 6, and the p ++ type semiconductor layer 53 are formed in a single-surface recess structure, but may be formed in a place other than the recess structure. . Further, the p ++ type semiconductor layer 53 may not be provided.

The p + type semiconductor layer 6 and the p + type semiconductor layer 60 are formed with a concentration of 3 × 10 ¹⁷ cm ⁻³ , for example, and the p + type semiconductor layer 6 is formed deeper than the p + + type semiconductor layer 52a. Alternatively, it is effectively formed deeper than the p ++ type semiconductor layer 52a with an implantation amount of 2 × 10 ^{13 to} 2.5 × 10 ¹³ cm ⁻² .

  Even in this structure, since the p ++ type semiconductor layer 52a can be formed efficiently, an element expected efficiently can be manufactured with only a slight decrease in throughput.

<Effect>
According to the embodiment of the present invention, in the semiconductor device, the p + type semiconductor layer 60 as the second impurity layer is a plurality of layers formed so as to be separated from each other so as to surround the element region in plan view. The impurity concentration is lower than the impurity concentration of the p ++ type semiconductor layer 52a as the first impurity layer, and the p ++ type semiconductor layer 52a is formed on the surface layer of the p + type semiconductor layer 6 as the second impurity layer surrounding the element region from the innermost side. Thus, an electric field relaxation structure is formed by the intermediate concentration p + type semiconductor layer 6 and the p + type semiconductor layer 60 surrounding the high concentration p + + type semiconductor layer 52a, and a high electric field generated at the end of the p + + type semiconductor layer 52a. Can be suppressed.

  According to the embodiment of the present invention, in the semiconductor device, in the surface layer of the n-type semiconductor layer 1 as the semiconductor layer, the element region is formed in plan view, and the impurity concentration is as the second impurity layer. A p − type semiconductor layer 4 as a third impurity layer of the second conductivity type lower than the p + type semiconductor layer 6 is further provided, and the p + type semiconductor layer 6 is formed in the surface layer of the p − type semiconductor layer 4, and its impurity concentration Is lower than the impurity concentration of the p ++ type semiconductor layer 52a as the first impurity layer, and the p ++ type semiconductor layer 52a is formed in the surface layer of the p + type semiconductor layer 6 so that an intermediate concentration surrounding the high concentration p ++ type semiconductor layer 52a is formed. The p + type semiconductor layer 6 and the p − type semiconductor layer 4 surrounding the intermediate concentration p + type semiconductor layer 6 form an electric field relaxation structure to suppress a high electric field generated at the end of the p + + type semiconductor layer 52a. It can be.

  Further, according to the embodiment of the present invention, in the semiconductor device, the p ++ type semiconductor layer 52a as the first impurity layer and the p ++ type semiconductor layer 52b as the second impurity layer are the n type semiconductor as the semiconductor layer. By forming the p ++ type semiconductor layer 52a and the p ++ type semiconductor layer 52b apart from each other at an interval of 2.5 to 3 μm, the injection energy of medium acceleration or higher is used. Even when impurities are implanted, the forward surge resistance and reverse recovery surge resistance can be improved.

  Moreover, according to the embodiment of the present invention, in the semiconductor device, p ++ as the second conductivity type fourth impurity layer selectively formed on the surface layer of the n-type semiconductor layer 1 as the semiconductor layer in the element region. By further providing the type semiconductor layer 50, the current flows with a horizontal spread angle, so the forward resistance decreases. On the other hand, in the reverse direction, a depletion layer is formed so as to spread over the entire lower surface of the p ++ type semiconductor layer 50 and the p− type semiconductor layer 4, and a low reverse current is maintained.

  According to the embodiment of the present invention, in the semiconductor device, the p ++ type semiconductor layer 52a as the first impurity layer, the p ++ type semiconductor layer 52b as the second impurity layer, and the p ++ type semiconductor as the fourth impurity layer. Since the layer 53 is formed in the concave portion of the surface layer of the n-type semiconductor layer 1 as a semiconductor layer, the forward surge resistance and reverse recovery surge can be obtained even when impurities are implanted using an implantation energy of medium acceleration or higher. The amount of resistance can be improved.

According to the embodiment of the present invention, in the method of manufacturing a semiconductor device, (a) an implantation mask is disposed on the n-type semiconductor layer 1 as a semiconductor layer, and 1 is formed in the surface layer of the n-type semiconductor layer 1. A step of implanting an impurity having a concentration of × 10 ²⁰ cm ⁻³ or higher; and (b) a first impurity formed in step (a) surrounding the element region of the Schottky diode in a plan view in the n-type semiconductor layer 1 surface layer. Etching the surface layer of the n-type semiconductor layer 1 so that the p ++ type semiconductor layer 52a as the layer and the p ++ type semiconductor layer 52b as the second impurity layer are exposed, and (c) removing the implantation mask and removing the p ++ type semiconductor layer A step of activating the layer 52a and the p ++ type semiconductor layer 52b, a step of (d) sacrificing the p ++ type semiconductor layer 52a and the p ++ type semiconductor layer 52b, and (e) a shape in the step (d). The step of removing the sacrificial oxide film and forming the anode electrode 3 of the Schottky diode extending to the surface layer of the p ++ type semiconductor layer 52a. It can have surge current resistance. Further, the number of steps can be reduced by simplifying the process, and the manufacturing tact can be improved. Therefore, reduction of manufacturing cost and improvement of mass productivity can be expected.

  In the embodiment of the present invention, the material, material, conditions for implementation, etc. of each component are also described, but these are examples and are not limited to those described.

  In the present invention, within the scope of the invention, free combinations of the respective embodiments, modifications of arbitrary components of the respective embodiments, or omission of arbitrary components of the respective embodiments are possible. .

  1 n-type semiconductor layer, 2 silicon carbide substrate, 3 anode electrode, 4 p-type semiconductor layer, 5a, 5b, 50, 51, 52a, 52b, 53 p ++ type semiconductor layer, 6, 60 p + type semiconductor layer, 10 mask 11 Aluminum ions.

Claims (10)

A first conductivity type semiconductor layer made of silicon carbide;
A first impurity layer of a second conductivity type formed on the surface of the semiconductor layer so as to surround the element region of the Schottky diode in plan view;
In the semiconductor layer surface layer, a second impurity layer of a second conductivity type formed so as to surround the element region from at least the outside in a plan view of the first impurity layer;
An anode electrode extending to the surface layer of the first impurity layer and formed on the element region;
The impurity concentration of the first impurity layer is 1 × 10 ²⁰ cm ⁻³ or more,
Semiconductor device. The second impurity layer is formed apart from the first impurity layer and has an impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more.
The semiconductor device according to claim 1. The second impurity layer is a plurality of layers formed so as to be separated from each other so as to surround the element region in plan view, and the impurity concentration thereof is lower than the impurity concentration of the first impurity layer,
The first impurity layer is formed on the surface layer of the second impurity layer surrounding the element region from the innermost side.
The semiconductor device according to claim 1. The semiconductor layer further includes a third impurity layer of a second conductivity type formed so as to surround the element region in plan view and having an impurity concentration lower than that of the second impurity layer.
The second impurity layer is formed on a surface layer of the third impurity layer, and an impurity concentration thereof is lower than an impurity concentration of the first impurity layer;
The first impurity layer is formed on a surface layer of the second impurity layer,
The semiconductor device according to claim 1. The first impurity layer is a plurality of layers formed so as to be separated from each other so as to surround the element region in plan view,
The semiconductor device according to claim 1. The first impurity layer and the second impurity layer are formed to be spaced apart from each other by 1 to 3 μm,
The semiconductor device according to claim 1. The first impurity layer and the second impurity layer are formed in a recess of the semiconductor layer surface layer;
The first impurity layer and the second impurity layer are formed apart from each other at an interval of 2.5 to 3 μm,
The semiconductor device according to claim 1. A fourth impurity layer of a second conductivity type, which is selectively formed on the surface layer of the semiconductor layer in the element region;
The semiconductor device according to claim 1. The first impurity layer, the second impurity layer, and the fourth impurity layer are formed in a recess of a surface layer of the semiconductor layer,
The semiconductor device according to claim 8. A method for manufacturing the semiconductor device according to claim 1,
(A) disposing an implantation mask on the semiconductor layer, and implanting an impurity having a concentration of 1 × 10 ²⁰ cm ⁻³ or more into the semiconductor layer surface layer;
(B) The semiconductor layer surface layer formed in the step (a) so that the first impurity layer and the second impurity layer surrounding the element region of the Schottky diode in plan view are exposed in the semiconductor layer surface layer Etching the step;
(C) removing the implantation mask and activating the first impurity layer and the second impurity layer;
(D) sacrificial oxidation of the first impurity layer and the second impurity layer;
(E) removing the sacrificial oxide film formed in the step (d) and forming an anode electrode of a Schottky diode extended to the surface layer of the first impurity layer.
A method for manufacturing a semiconductor device.

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