JP2008034646A - High breakdown voltage semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor device in which the breakdown voltage deterioration due to the anisotropy of breakdown voltage is prevented. <P>SOLUTION: The high breakdown voltage semiconductor device includes a first conductive SiC layer formed on the upper surface of a SiC substrate, a first SiC region of a second conductive type formed on the surface of the SiC layer so as to surround an active layer of about center of this layer, a second SiC region having lower concentration than the impurity concentration of a first region formed in contact with the exterior of the first SiC region, a first electrode prepared on the active layer, and a second electrode prepared on the backside of the substrate. When the specific inductive capacity of SiC is set to ε, the breakdown electric field strength of SiC in the direction <0001> and the direction <11-20> to Ec1, Ec2, respectively, the elementary charge to q, and the donor concentration in the SiC layer to Nd; the amount of dose of the first region is 1.2εEc1/q or less and 0.8εEc1/q or more, the width is (εEc1/qNd-0.4εEc2/qNd) or more, the amount of dose of the second region is 1.1εEc2/q or less and 0.4εEc2/q or more, and the width is 0.4εEc2/qNd or more. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high voltage semiconductor device such as a Schottky barrier diode, a PN diode, a MOSFET, or an IGBT.

  In semiconductor power devices, device structures and device materials that minimize on-resistance and maximize breakdown voltage are required. Conventionally, a semiconductor power device is made using silicon as a semiconductor material, and the location where electric field concentration occurs at the device termination is a PN junction formed on the surface called JTE (Junction Termination Extension) or a p-type layer on the surface of the n-type semiconductor substrate. A ring structure has been created and designed to relieve the electric field, thereby increasing the breakdown voltage.

Conventionally, for example, in a Schottky diode, a p ⁻ layer (so-called RESURF layer) as a JTE is formed continuously from the Schottky electrode portion to deplete the p ⁻ layer when a reverse bias is applied. A high breakdown voltage is obtained by relaxing the electric field at the electrode end. The breakdown voltage mainly depends on the amount obtained by integrating the concentration of the p ⁻ layer in the depth direction, that is, the dose of ion implantation for forming the p ⁻ layer. In order to obtain an ideal withstand voltage, the dose amount needs to be a value close to εEc / q where the breakdown electric field strength is Ec, the dielectric constant is ε, and the elementary charge amount is q (see Non-Patent Document 1).

  Recently, power devices made of silicon carbide (SiC) have been developed that dramatically surpass the performance of power devices made of silicon. Silicon carbide is a wide band gap semiconductor, and since the breakdown electric field strength is nearly 10 times as large as that of silicon, the trade-off between the breakdown voltage and on-resistance of the power semiconductor can be improved (see Non-Patent Document 2). In a high voltage semiconductor device made of silicon carbide, a high voltage resistance has been achieved by forming a JTE structure on the surface like silicon.

  However, since the breakdown electric field strength is anisotropic in silicon carbide, the electric field at the end of the JTE structure is obliquely shifted from the C-axis direction where the breakdown electric field strength is the highest, and the breakdown voltage is significantly reduced. There was a problem. In the C-axis (<0001> direction) and the A-axis (<11-20> direction orthogonal thereto, where the symbol “-” represents “-” (bar) added on the number in crystallography) It has been reported that Ec1 and Ec2 are expressed by the following equations, assuming that the breakdown electric field strength is Ec1 and Ec2, respectively, and the donor concentration in the SiC substrate is Nd (see Non-Patent Document 3).

Ec1 = 2.70 × 10 ⁶ (Nd / 10 ¹⁶ ) ^0.1 [V / cm] (1)
Ec2 = 2.12 × 10 ⁶ (Nd / 10 ¹⁶ ) ^0.1 [V / cm] (2)
From the anisotropy of the breakdown voltage, it can be seen that the breakdown voltage is 10% lower than the ideal breakdown voltage of the C axis in the A-axis direction.
“Power semiconductor devices”, B. Jayant Baliga, PWS publishing Basics and applications of SiC devices, Kazuo Arai, Ohmsha, pp.165-168 “Physical modeling and scaling properties of 4H-SiC power devices”, T. Hatakeyama, C. Ohta, J. Nishio, T. Shinohe, Proc. Of 2005 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) P.171- 17 (2005)

  The present invention has been made in view of such problems, and an object of the present invention is to provide a high voltage semiconductor device in which a decrease in breakdown voltage due to anisotropy of breakdown voltage is prevented.

  In order to solve the above problems, a first semiconductor device of the present invention includes a semiconductor substrate made of silicon carbide, a first conductivity type semiconductor layer made of silicon carbide formed on an upper surface of the semiconductor substrate, and the semiconductor A first semiconductor region of a second conductivity type made of silicon carbide formed on the surface of the semiconductor layer so as to surround an active layer in a substantially central portion of the layer, and a surface of the semiconductor layer, A second semiconductor region of a second conductivity type formed of silicon carbide formed in contact with the outside of the semiconductor region and having a lower concentration than the impurity concentration of the first semiconductor region; and provided on the active layer of the semiconductor layer And a second dielectric electrode provided on the back surface of the semiconductor substrate, wherein the relative dielectric constant of the silicon carbide is ε, the <0001> direction of the silicon carbide, <11-20> Direction breakdown electric field strengths Ec1 and Ec2, respectively When the elementary charge amount is q and the donor concentration in the semiconductor layer is Nd, the product of the impurity concentration and the depth of the first semiconductor region is 0.8εEc1 / q or more and 1.2εEc1 / q or less, The product of the impurity concentration and the depth of the second semiconductor region is 0.4εEc2 / q or more and 1.1εEc2 / q or less.

  According to a second aspect of the semiconductor device of the present invention, there is provided a semiconductor substrate made of silicon carbide, a first conductivity type semiconductor layer made of silicon carbide formed on an upper surface of the semiconductor substrate, and a substantially central portion of the semiconductor layer. A first semiconductor region of a second conductivity type made of silicon carbide formed on the surface of the semiconductor layer so as to surround the active layer, and a surface of the semiconductor layer in contact with the outside of the first semiconductor region. A second conductivity type second semiconductor region made of silicon carbide having a lower concentration than the impurity concentration of the first semiconductor region, and in the second semiconductor region, of the first semiconductor region A plurality of third semiconductor regions formed on the outside and made of silicon carbide having substantially the same concentration as the donor concentration of the first semiconductor region; and a first semiconductor layer provided on the active layer of the semiconductor layer Electrodes and the back of the semiconductor substrate A dielectric constant of the silicon carbide is ε, and breakdown electric field strengths of the silicon carbide in the <0001> direction and the <11-20> direction are Ec1, Ec2, and elementary charge, respectively. When the amount is q and the donor concentration in the semiconductor layer is Nd, the product of the impurity concentration and the depth of the first semiconductor region is 0.8εEc1 / q to 8εEc1 / q, and the second The product of the impurity concentration and the depth of the semiconductor region is 0.4εEc2 / q or more and 1.1εEc2 / q or less.

  According to the present invention, it is possible to prevent a decrease in breakdown voltage due to anisotropy of breakdown electric field strength in a semiconductor having anisotropy of breakdown electric field strength. Since the withstand voltage can be maximized according to the present invention, the inherent performance of the semiconductor can be derived, and the on-resistance per area can be minimized to provide a high withstand voltage semiconductor device exhibiting the highest withstand voltage. Thereby, it is possible to achieve high breakdown voltage and high current density of the element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
1 and 2 are a schematic cross-sectional view and a top view of the high voltage semiconductor device according to the first embodiment of the present invention, and FIG. 1 corresponds to a cross section taken along the line AA ′ of FIG. To do. Here, a Schottky barrier diode will be described as one of high voltage semiconductor devices.

As shown in FIG. 1, the Schottky barrier diode of the first embodiment is formed in an n ⁻ type SiC semiconductor layer 2 epitaxially grown on an n ⁺ type SiC semiconductor substrate 1. On the surface of the n ⁻ type semiconductor layer 2, a first p ⁻ type region 6 having a low impurity concentration as a JTE structure is formed. The first p ⁻ -type region 6 is partially connected to the Schottky electrode 3 and extends around the electrode 3. Further, a second p ⁻ type region 7 having a lower concentration than that of the first p ⁻ type region 6 is formed outside the first p ⁻ type region 6. The impurity concentration of the second p ⁻ type region 7 is set lower than the impurity concentration of the first p ⁻ type region 6. Further, an n ⁺ type channel stopper region 8 is formed at the surface end portion of the n ⁻ type semiconductor layer 2. The outer end portion of the second p ⁻ type region 7 and the inner end portion of the n ⁺ type channel stopper region 8 are separated from each other.

The upper surface of the n ⁻ type semiconductor layer 2 is covered with a silicon oxide film 9, and after opening the upper part of the Schottky electrode 3 made of, for example, Ti, a first electrode (anode electrode) 4 made of, for example, Al is formed. Has been. Further, the entire surface is covered with a protective film 10 such as polyimide, and the upper portion of the first electrode 4 is opened. On the back surface of the n ⁺ -type SiC semiconductor substrate 1, a second electrode (cathode electrode) 5 made of, for example, Ni is formed.

In plan view, as shown in FIG. 3, a Schottky electrode 3 is formed at the center, and a first p ⁻ -type region 6 and a second p ⁻ -type region 7 as JTE are formed around it. . 2 is a top view immediately after the first p ⁻ type region 6, the second p ⁻ type region 7, and the Schottky electrode 3 are formed in the semiconductor layer 2. As will be described later, the widths w1 and w2 of the first p ⁻ type region 6 and the second p ⁻ type region 7 depend on the donor concentration (Nd) of the drift layer (n ⁻ type semiconductor layer) 2 of the Schottky diode. It is determined.

Here, a region outside the first p ⁻ type region 6 is referred to as a termination region 11, and a region combining the first p ⁻ type region 6 and the second p ⁻ type region 7 is a junction termination structure (JTE). Called. A central region surrounded by the first p ⁻ type region 6 is an active region as a Schottky diode.

  The SiC semiconductor substrate used in this embodiment has anisotropy in breakdown voltage as described above. Assuming that the breakdown electric field strength in the <0001> direction is Ec1, and the breakdown voltage strength in the <11-20> direction is Ec2, as shown in FIG. 3, Ec1> Ec2. Each numerical value can be calculated by the above-described equations (1) and (2).

  In addition, the production of a SiC substrate requires the epitaxial growth of SiC from the viewpoint of the quality of the SiC crystal. The SiC epitaxial growth film is formed on a SiC surface slightly inclined from the <0001> direction called the C-axis of the crystal angle. Usually, the main surface of the SiC substrate has a normal line inclined (turned off) by 8 degrees or less with respect to the <0001> direction.

  The breakdown voltage intensity according to the above formulas (1) and (2) is for the case where the off angle is 0 degree, but the breakdown voltage intensity Ec1 ′ in the direction perpendicular to the substrate and the direction parallel to the substrate at 8 degrees off. The breakdown voltage intensity Ec2 ′ is given by the following equations, respectively.

Ec1 ′ = 2.68 × 10 ⁶ (Nd / 10 ¹⁶ ) ^0.1 [V / cm] (3)
Ec2 ′ = 2.14 × 10 ⁶ (Nd / 10 ¹⁶ ) ^0.1 [V / cm] (4)
That is, the difference between the formula (1) and the formula (3) and the difference between the formula (2) and the formula (4) are less than 1%.

FIG. 4 is a simulation result showing deterioration of breakdown voltage due to anisotropy of the breakdown electric field strength in a conventional Schottky barrier diode (equipped with one normal RESURF layer). As the semiconductor layer, 4H—SiC (silicon carbide) is used. The horizontal axis represents the impurity concentration of the p ⁻ semiconductor region (RESURF), and the vertical axis represents the breakdown voltage. In general, the breakdown voltage is a function of the product of the concentration and depth of a semiconductor region. In this calculation, the depth of the semiconductor region is set to 0.6 μm. Assuming that the breakdown field strength is isotropic, the simulation result in which the absolute value is set to the value in the <0001> direction is indicated by the data with a circle. According to this result, if the concentration of the first semiconductor region is optimized, the breakdown voltage can be almost equal to the ideal breakdown voltage in the <0001> direction (shown as the <0001> limit).

On the other hand, anisotropy of breakdown electric field strength was introduced in accordance with the actual situation, the breakdown electric field strengths in the <0001> direction and <1120> direction were set to experimental values, and the breakdown breakdown voltage was calculated. Shown in data. According to the calculation results, the dielectric breakdown voltage is reduced by about 10% compared to the ideal breakdown voltage in the <0001> direction, and the optimum concentration in the p ⁻ region (RESURF) is also different from that in the ideal breakdown voltage. When the design concentration of the p ⁻ layer (RESURF) is set to an optimum value by a conventional design method (isotropic simulation), the breakdown voltage is reduced by 50% or more.

FIG. 5 is a diagram showing that the breakdown voltage reduction of the element according to the conventional technique is in the anisotropy of the breakdown field strength. When the design concentration of the p ⁻ layer is set to the optimum value of the conventional design, the direction of the electric field is shifted in the direction perpendicular to the C axis at the end of the termination structure, so that the breakdown voltage decreases. It can be seen that at the end of RESURF, where the arrow indicates the magnitude and direction of the electric field, the arrow extends greatly in the direction parallel to the substrate surface. Since the breaking strength in this direction is smaller than the direction perpendicular to the substrate surface as described with reference to FIG. 3, the breakdown voltage is reduced. The electric field strength distribution is shown by an equal wire.

FIG. 6 shows a diamond-shaped data including only the high-voltage semiconductor device shown in FIG. 1 (indicated by data indicated by x) and the conventional high-voltage semiconductor device (only RESURF corresponding to the first p ⁻ -type layer of the present invention). It is the figure which compared the pressure | voltage resistance of (shown by) by simulation. The horizontal axis represents the dose of the p ⁻ -type layer (RESURF) (concentration integrated in the depth direction) in the conventional technique, and in this embodiment, the dose of the first p ⁻ -type layer 6 on the inside. is there. According to the present embodiment, the breakdown voltage can be improved to the limit value in the <0001> direction. With respect to the product of the impurity concentration and the depth of the first p ⁻ -type layer 6, the maximum effect is obtained at εEc1 / q from FIG. 6, and the effect is observed from 0.8εEc1 / q to 1.2εEc1 / q. .

More specifically, when the dose amount is larger than the prescribed amount, electric field concentration occurs at the end of the RESURF layer, whereas when the dose amount is small, the RESURF layer is completely depleted, and the electric field shielding effect of the RESURF layer is insufficient. Therefore, electric field concentration occurs at the electrode ends. Accordingly, the dose amount of the first p ⁻ -type layer is preferably εEc1 / q, and 0.8εEc1 / q or more and 1.2εEc1 / q or less are recognized in consideration of a margin.

7 and 8 are drawings for explaining the effect of the first embodiment. FIG. 7 is an enlarged view of the maximum electric field portion (end portion of the first p ⁻ -type region 6) in the element. In the present embodiment, the direction of the maximum electric field is aligned in the <0001> direction (direction perpendicular to the substrate surface). That is, the structure is such that the electric field from the lateral side where the breaking strength is weak is suppressed by 7 in the second p ⁻ -type region, and the electric field is received in the vertical direction where the breaking strength is strong.

FIG. 8 is a diagram showing the direction and distribution of the electric field at the end of the second p ⁻ -type region 7. The electric field at the end of the second p ⁻ -type region is suppressed below the maximum electric field in the <1120> direction. In the present embodiment, the outer termination structure (second p ⁻ -type region 7) is intended for electric field relaxation in the <1120> direction, and the inner termination structure (first p ⁻ -type region 6) is in the <0001> direction. This figure shows that it contributes to the electric field relaxation structure.

FIG. 9 is a diagram in which the optimum concentration range of the second p ⁻ -type region 7 is obtained by simulation. When the dose amount of the second p ⁻ -type region 7 exceeds 1.1εEc2 / q, electric field concentration occurs at the end of this region, and the breakdown voltage drops sharply. On the other hand, the effect is recognized up to 0.4εEc2 / q for the lower limit.

FIG. 10 shows that when the dose amount of the second p ⁻ -type region 7 becomes smaller than the optimum value, the breakdown voltage margin of the first p ⁻ -type region 6 becomes smaller. Since it exceeds the limit value, it can be seen that the effect of the transverse electric field relaxation is sustained. The single JTE withstand voltage limit value is a limit value at which the withstand voltage cannot be increased any more when there is one JTE (RESURF).

The length of the JTE region is set to be equal to or greater than the lateral direction of the depletion layer around the electrode, and the electric lines of force from the depletion layer in this region are terminated. The spread of the depletion layer in the horizontal direction is the same as the length of the depletion layer in the vertical direction and is expressed by εEc / qNd. In the present embodiment, the JTE is composed of the first p ⁻ -type layer 6 and the second p ⁻ -type layer 7 adjacent to the first p ⁻ -type layer 6, and it is sufficient that these two satisfy εEc / qNd. Since the second p ⁻ type layer 7 has only to bear about 40%, in order for the second p ⁻ type layer 7 to be fully depleted, its width w 2 is 0.4εEc 2 / qNd or more and εEc 2 / qNd or less. It becomes. Further, in order to prevent the first p ⁻ type layer 6 from being completely depleted, the width w1 may be εEc1 / qNd−εEc2 / qNd or more, preferably εEc1 / qNd−0.4εEc2 / qNd or more. . However, in the above equation, the dielectric constant of SiC is ε, the breakdown electric field strength of SiC in the <0001> direction and the <11-20> direction is Ec1, Ec2, the elementary charge is q, and the donor in the SiC layer The density is Nd.

As described above, according to the first embodiment, the second p ⁻ type layer having a lower concentration than the low concentration first p ⁻ type layer is provided on the outside of the first p ⁻ type layer. Since the breakdown voltage can be maximized in a semiconductor having an anisotropy in breakdown electric field strength, the original performance of the semiconductor can be extracted.

(Second Embodiment)
FIG. 11 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

The second embodiment is different from the first embodiment in that the second p ⁻ -type layer 7 has a plurality of rings 6 ′ having the same concentration as the first p ⁻ -type layer 6. It is.

By arranging a ring 6 ′ having a concentration similar to this around the first p ⁻ -type layer 6, the electric field concentration on the first p ⁻ -type layer is alleviated, and the first p ⁻ -type is reduced. It becomes possible to widen the margin of the layer dose by 7 times or more. More specifically, the dose (product of impurity concentration and depth) of the first p ⁻ -type layer 6 may be 0.8εEc1 / q or more and 8εEc1 / q or less. Similarly to the first embodiment, the dose of the second p ⁻ -type layer 7 can be 0.4εEc2 / q or more and 1.1εEc2 / q or less. Regarding the width, the width w2 of the second p ^- type layer 7 is 0.4εEc2 / qNd to εEc2 / qNd and the width w1 of the first p ^- type layer 6 is preferably εEc1 / qNd−εEc2 / qNd, preferably May be εEc1 / qNd−0.4εEc2 / qNd or more.

(Third embodiment)
FIG. 12 is a cross-sectional view of a semiconductor device according to the third embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

The third embodiment is different from the first embodiment in that the depth of the second p ⁻ -type layer 7 is made deeper than that of the first p ⁻ -type layer 6.

By increasing the depth of the second p ⁻ -type layer 7, it is possible to enhance the effect of blocking the horizontal electric field.

(Fourth embodiment)
FIG. 13 is a cross-sectional view of a semiconductor device according to the fourth embodiment of the present invention. The same parts as those in the third embodiment are denoted by the same reference numerals, and redundant description is omitted.

The fourth embodiment is the third embodiment differs from the second p ^- the depth of the mold layer 7 first p ^- deeper than -type layer 6, and the first p ^- type layer 6 Is wrapped from below and from the side.

By increasing the depth of the second p ⁻ -type layer 7, it is possible to enhance the blocking effect of the lateral electric field, and it is possible to reduce the electric field concentration at the corner outside the JTE by enveloping.

(Fifth embodiment)
FIG. 14 is a cross-sectional view of a semiconductor device according to the fifth embodiment of the present invention. The same parts as those in the fourth embodiment are denoted by the same reference numerals, and redundant description is omitted.

The fifth embodiment differs from the fourth embodiment, the second p ^- the depth of the mold layer 7 first p ^- deeper than -type layer 6, first p ^- -type layer 6 That is, the second p ⁻ -type layer 7 is surrounded by a plurality of rings 6 ′ having the same concentration as that of the first p ⁻ -type layer 6.

By increasing the depth of the second p ⁻ -type layer 7, it becomes possible to enhance the effect of blocking the lateral electric field, and also to reduce the electric field concentration at the corner outside the JTE, and the dose margin. Can be expanded.

(Sixth embodiment)
FIG. 15 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

The sixth embodiment differs from the first embodiment in that the semiconductor device is changed from a Schottky diode to a pn diode. That is, the p ⁺ anode region 11 is provided on the surface of the active region surrounded by the first p ⁻ type layer 6, and the anode electrode 4 is provided thereon.

  Even if comprised in this way, there can exist an effect similar to 1st Embodiment. In addition, it cannot be overemphasized that it can carry out similarly to the 2nd-5th embodiment regarding a JTE structure.

(Seventh embodiment)
FIG. 16 is a cross-sectional view of a semiconductor device according to the seventh embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

The seventh embodiment is different from the first embodiment in that the semiconductor device is changed from a Schottky diode to a vertical MOSFET. In the figure, reference numeral 12 is a p-type region. A first p ⁻ -type layer 6 is formed between the p-type region 12 and the second p ⁻ -type layer 7. Reference numeral 15 is an n-type source region, 16 is an insulating film, 17 is a gate electrode, and 18 is a source electrode (first electrode).

  The n + -type semiconductor substrate 1 becomes a drain region, but if this is changed to p-type, an IGBT can be formed.

  Even if comprised in this way, there can exist an effect similar to 1st Embodiment. In addition, it cannot be overemphasized that it can carry out similarly to the 2nd-5th embodiment regarding a JTE structure.

  As mentioned above, although this invention was demonstrated through embodiment, this invention is not limited to the said embodiment as it is, A component can be deform | transformed and embodied in the range which does not deviate from the summary in an implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 1 is a top view of a semiconductor device according to a first embodiment. The figure explaining the surface orientation dependence of the proof pressure of silicon carbide. The figure which shows the result of having simulated the resurf layer (JTE) doping density | concentration dependence of a proof pressure regarding the isotropy and anisotropy of a proof pressure, respectively. The figure which shows the result of having simulated the electric field distribution in the single resurf layer (JTE), the direction of electric field strength, and a magnitude | size. The figure which shows the relationship between the dosage of a 1st p < ^- > type | mold layer, and a proof pressure in 1st Embodiment. The figure which shows the electric field distribution near the boundary of the 1st p < ^- > type layer and the 2nd p < ^- > type layer in 1st Embodiment. The figure which shows electric field distribution near the termination | terminus part of the 2nd p < ^- > type layer in 1st Embodiment. The figure which shows the relationship between the dose amount of a 2nd p < ^- > type layer, and a proof pressure in 1st Embodiment. The figure which shows the relationship between the dose amount of a 1st p < ^- > type layer, and a proof pressure in 1st Embodiment in relation to the dose amount of a 2nd p < ^- > type layer. Sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 3rd Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 6th Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the 7th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon carbide (SiC) substrate 2 ... Silicon carbide (SiC) layer 3 ... Schottky electrode 4 ... 1st electrode 5 ... 2nd electrode 6 ... 1st p < ^- > type layer 7 ... 2nd p < ^- > type Layer 8 ... Channel stopper layer 9 ... Silicon oxide film 10 ... Protective film 11 ... p-type region 12 ... p-type region 15 ... Source region 16 ... Gate insulating film 17 ... Gate electrode 18 ... Source electrode (first electrode)

Claims (12)

A semiconductor substrate made of silicon carbide;
A first conductivity type semiconductor layer made of silicon carbide formed on the upper surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type made of silicon carbide formed on the surface of the semiconductor layer so as to surround an active layer at a substantially central portion of the semiconductor layer;
A second semiconductor region of a second conductivity type formed of silicon carbide on the surface of the semiconductor layer and in contact with the outside of the first semiconductor region and having a lower concentration than the impurity concentration of the first semiconductor region; ,
A first electrode provided on the active layer of the semiconductor layer;
A second electrode provided on the back surface of the semiconductor substrate;
The dielectric constant of the silicon carbide is ε, the breakdown electric field strength of the silicon carbide in the <0001> direction and the <11-20> direction is Ec1, Ec2, the elementary charge is q, When the donor concentration is Nd,
The product of the impurity concentration and the depth of the first semiconductor region is 0.8εEc1 / q to 1.2εEc1 / q, and the product of the impurity concentration and the depth of the second semiconductor region is 0.4εEc2 / A semiconductor device characterized in that it is not less than q and not more than 1.1εEc2 / q.   The semiconductor device according to claim 1, wherein a depth of the second semiconductor region is deeper than a depth of the first semiconductor region. A semiconductor substrate made of silicon carbide;
A first conductivity type semiconductor layer made of silicon carbide formed on the upper surface of the semiconductor substrate;
A first semiconductor region of a second conductivity type made of silicon carbide formed on the surface of the semiconductor layer so as to surround an active layer at a substantially central portion of the semiconductor layer;
A second semiconductor region of a second conductivity type formed of silicon carbide on the surface of the semiconductor layer and in contact with the outside of the first semiconductor region and having a lower concentration than the impurity concentration of the first semiconductor region; ,
A plurality of third semiconductor regions made of silicon carbide formed outside the first semiconductor region and having substantially the same concentration as the donor concentration of the first semiconductor region in the second semiconductor region; ,
A first electrode provided on the active layer of the semiconductor layer;
A second electrode provided on the back surface of the semiconductor substrate;
The dielectric constant of the silicon carbide is ε, the breakdown electric field strength of the silicon carbide in the <0001> direction and the <11-20> direction is Ec1, Ec2, the elementary charge is q, When the donor concentration is Nd,
A product of the impurity concentration and the depth of the first semiconductor region is not less than 0.8εEc1 / q and not more than 8εEc1 / q;
A semiconductor device, wherein a product of impurity concentration and depth of the second semiconductor region is not less than 0.4εEc2 / q and not more than 1.1εEc2 / q.   The semiconductor device according to claim 3, wherein the plurality of third semiconductor regions have a ring shape surrounding the first semiconductor region.   The depth of the second semiconductor region is deeper than the depth of the first semiconductor region, and the second semiconductor region surrounds the first semiconductor region from the bottom and sides thereof. The semiconductor device according to claim 1 or 3, characterized in that:   A fourth semiconductor region of a first conductivity type formed at a surface end portion of the semiconductor layer; and the second semiconductor region is separated from an inner end portion of the fourth semiconductor region. The semiconductor device according to claim 1, wherein:   The semiconductor device according to claim 1, wherein the first semiconductor region is connected to the first electrode.   8. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is of a first conductivity type, the first electrode is in Schottky contact with the semiconductor layer, and a Schottky barrier diode structure is formed in the active layer. A semiconductor device according to 1. A second conductivity type fifth semiconductor region on the upper surface of the active layer surrounded by the first semiconductor region;
The semiconductor device according to claim 1, wherein the semiconductor substrate is of a first conductivity type, and a pn diode structure is formed in the active layer.   The semiconductor device according to claim 1, wherein the semiconductor substrate is of a first conductivity type, and a MOSFET structure is formed in the active layer.   The semiconductor device according to claim 1, wherein the semiconductor substrate is of a second conductivity type, and an IGBT structure is formed in the active layer.   2. The semiconductor substrate according to claim 1, wherein a normal vector of a surface is a <0001> direction or a <000-1> direction, or a deviation of 8 degrees or less with respect to any one of the directions. The semiconductor device in any one of -11.

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