CN115579382A - Terminal structure of semiconductor device and semiconductor device thereof - Google Patents
Terminal structure of semiconductor device and semiconductor device thereof Download PDFInfo
- Publication number
- CN115579382A CN115579382A CN202211588280.3A CN202211588280A CN115579382A CN 115579382 A CN115579382 A CN 115579382A CN 202211588280 A CN202211588280 A CN 202211588280A CN 115579382 A CN115579382 A CN 115579382A
- Authority
- CN
- China
- Prior art keywords
- region
- layer
- epitaxial layer
- junction
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000002347 injection Methods 0.000 claims abstract description 65
- 239000007924 injection Substances 0.000 claims abstract description 65
- 230000007704 transition Effects 0.000 claims abstract description 30
- 238000002161 passivation Methods 0.000 claims abstract description 24
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 239000007943 implant Substances 0.000 claims description 53
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 33
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- -1 silicon carbide metal oxide Chemical class 0.000 claims description 3
- 210000003850 cellular structure Anatomy 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 214
- 238000002513 implantation Methods 0.000 description 29
- 230000005684 electric field Effects 0.000 description 24
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 239000010936 titanium Substances 0.000 description 11
- 238000009826 distribution Methods 0.000 description 10
- 238000000407 epitaxy Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application discloses a terminal structure of a semiconductor device and the semiconductor device thereof, relating to the technical field of semiconductors. The terminal structure comprises a cellular structure and a bottom structure, wherein the cellular structure comprises a passivation layer, an oxidation layer, a transition region, a terminal injection region, a first epitaxial layer and a second epitaxial layer, the oxidation layer is positioned below the passivation layer, the second epitaxial layer is positioned below the oxidation layer, the transition region and the terminal injection region are positioned between the oxidation layer and the second epitaxial layer, the terminal injection region is positioned on one side of the transition region, a first buried layer region is arranged in the first epitaxial layer, the first buried layer region and the transition region are positioned on the same side, a second buried layer region is arranged in the second epitaxial layer, and the second buried layer region and the terminal injection region are positioned on the same side; the bottom structure is located below the first epitaxial layer. The embodiment of the application can shorten the length of the terminal, thereby reducing the size of the terminal structure and further reducing the cost.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a terminal structure of a semiconductor device and a semiconductor device thereof.
Background
In the actual process, lateral diffusion inevitably occurs after ion implantation, so that a cylindrical junction or a spherical junction appears at the edge of a mask window. The electric field concentration effect is easy to occur at the position of the non-parallel plane junction, so that the electric field intensity at the cylindrical junction and the spherical junction reaches the critical breakdown field intensity in advance, the breakdown voltage of the device is reduced, the problems can be solved through a field limiting ring, junction terminal expansion, a mixed type terminal and the like, and the research on the terminal structure of the semiconductor device is relatively mature. However, to achieve the desired termination efficiency, the size of the terminations tends to increase, which increases the chip area of the device, with a consequent increase in cost.
Disclosure of Invention
The present application is directed to solving at least one of the problems in the prior art. Therefore, the present application provides a terminal structure of a semiconductor device and a semiconductor device thereof, which can shorten the length of the terminal, thereby reducing the size of the terminal structure and further reducing the cost.
The technical scheme of the embodiment of the application is as follows:
in a first aspect, an embodiment of the present application provides a terminal structure of a semiconductor device, including:
the cell structure comprises a passivation layer, an oxide layer, a transition region, a terminal injection region, a first epitaxial layer and a second epitaxial layer, wherein the oxide layer is positioned below the passivation layer, the second epitaxial layer is positioned below the oxide layer, the transition region and the terminal injection region are positioned between the oxide layer and the second epitaxial layer, the terminal injection region is positioned on one side of the transition region, a first buried layer region is arranged in the first epitaxial layer, the first buried layer region and the transition region are positioned on the same side, a second buried layer region is arranged in the second epitaxial layer, and the second buried layer region and the terminal injection region are positioned on the same side;
a bottom structure located below the first epitaxial layer.
According to some embodiments of the present application, the first buried layer region comprises a first junction deep implant region, a second junction deep implant region and a third junction deep implant region, the second junction deep implant region being located between the first junction deep implant region and the third junction deep implant region.
According to some embodiments of the present application, the second buried layer region comprises a fourth junction-depth implant region, a fifth junction-depth implant region and a sixth junction-depth implant region, the fifth junction-depth implant region being located between the fourth junction-depth implant region and the sixth junction-depth implant region.
According to some embodiments of the present application, the cell structure comprises a silicon carbide mosfet, the silicon carbide mosfet further comprising an active region between the passivation layer and the second epitaxial layer, the active region being located on a side away from the terminal implant region.
According to some embodiments of the present application, the oxide layer is divided into a first gate oxide layer and a second gate oxide layer;
the active region comprises a grid electrode, a source electrode metal, a first dielectric layer, a second dielectric layer, a P trap injection region, an N + region and a P + region, the grid electrode is located between the first dielectric layer and the first gate oxide layer, the grid electrode is surrounded on the first dielectric layer, the second gate oxide layer is surrounded on the second dielectric layer, the first dielectric layer, the second dielectric layer and the passivation layer form a source electrode open hole region, the source electrode metal is located in the source electrode open hole region, the P + region is located on one side far away from the terminal injection region, the N + region is connected with the P + region, the first injection region of the P trap injection region is located under the N + region and the P + region, the second injection region of the P trap injection region is located under the first gate oxide layer, and the P trap injection region is located above the second epitaxial layer.
According to some embodiments of the present application, the cell structure includes a silicon carbide junction barrier schottky diode, the junction barrier schottky diode further includes an anode metal, a schottky contact, and a P + injection region, the P + injection region is located above the second epitaxial layer, the P + injection region is located on a side away from the terminal injection region, the schottky contact is embedded in the P + injection region, the anode metal includes a first metal body and a second metal body, the first metal body is located directly above the P + injection region and is exposed outward, the second metal body is located between the passivation layer and the oxide layer.
According to some embodiments of the present application, the first epitaxial layer and the second epitaxial layer are each 6 microns thick.
According to some embodiments of the present application, the bottom structure comprises a substrate underlying the first epitaxial layer and a backside metal underlying the substrate.
According to some embodiments of the application, the substrate has a thickness of 150 microns.
In a second aspect, embodiments of the present application provide a semiconductor device comprising a termination structure of the semiconductor device described in the first aspect.
The technical scheme provided by the embodiment of the application has the following beneficial effects:
the embodiment of the application provides a terminal structure of a semiconductor device and the semiconductor device thereof, wherein the terminal structure of the semiconductor device comprises: the cell structure comprises a passivation layer, an oxidation layer, a transition region, a terminal injection region, a first epitaxial layer and a second epitaxial layer, wherein the oxidation layer is positioned below the passivation layer, the second epitaxial layer is positioned below the oxidation layer, the transition region and the terminal injection region are positioned between the oxidation layer and the second epitaxial layer, the terminal injection region is positioned on one side of the transition region, a first buried layer region is arranged in the first epitaxial layer, the first buried layer region and the transition region are positioned on the same side, a second buried layer region is arranged in the second epitaxial layer, the second buried layer region and the terminal injection region are positioned on the same side, and through secondary epitaxy of the first epitaxial layer and the second epitaxial layer and the plurality of buried layer regions, the electric field intensity can be effectively reduced and the terminal length can be shortened; the bottom structure is located below the first epitaxial layer. Compared with the terminal structure with larger size in the prior art, the terminal structure has the advantages that the length of the terminal is shortened by secondary epitaxy on the first epitaxial layer and the second epitaxial layer and the design of the plurality of buried layer regions, so that the size of the terminal structure is reduced, and the cost is reduced.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram of a terminal structure of a semiconductor device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a termination structure of a silicon carbide metal oxide semiconductor field effect transistor according to an embodiment of the present application;
fig. 3 is a schematic diagram of a termination structure of a silicon carbide junction barrier schottky diode according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different from that in the flowcharts. The terms "first," "second," "third," "fourth," "fifth," "sixth," and the like in the description and in the claims and in the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Silicon carbide (SiC) material is a typical representative of the third generation wide bandgap semiconductor material, and has the advantages of higher critical breakdown electric field intensity, higher carrier saturation drift velocity, higher thermal conductivity and the like, so that the SiC material becomes an ideal material for manufacturing high-power, high-temperature, high-frequency and anti-radiation devices. The SiC power electronic device has great advantages in the high-voltage field of 1.2-10 kV and the ultrahigh-voltage field of more than 10kV, and is widely applied to the new energy fields of electric automobiles, locomotive traction, high-voltage direct-current transmission, wind power generation and the like. The problem of large terminal size still exists with the terminal structure of silicon carbide semiconductor devices.
Based on this, the embodiment of the application provides a terminal structure of a semiconductor device and the semiconductor device thereof, the terminal structure of the semiconductor device comprises a cell structure and a bottom structure, the cell structure comprises a passivation layer, an oxide layer, a transition region, a terminal injection region, a first epitaxial layer and a second epitaxial layer, the oxide layer is located below the passivation layer, the second epitaxial layer is located below the oxide layer, the transition region and the terminal injection region are located between the oxide layer and the second epitaxial layer, the terminal injection region is located at one side of the transition region, a first buried layer region is arranged in the first epitaxial layer, the first buried layer region and the transition region are located at the same side, a second buried layer region is arranged in the second epitaxial layer, the second buried layer region and the terminal injection region are located at the same side, and through secondary epitaxy of the first epitaxial layer and the second epitaxial layer, the electric field intensity can be effectively reduced and the terminal length can be shortened through the design of the plurality of buried layer regions; the bottom structure is located below the first epitaxial layer. The embodiment of the application adopts the secondary epitaxy at the first epitaxial layer and the second epitaxial layer, and the electric field intensity can be effectively reduced through the design of a plurality of buried layer regions, so that the terminal length is shortened while the electric field distribution is optimized, the size of the terminal structure is reduced, the cost is reduced, and the sensitivity of the terminal to an interface state is relieved.
The embodiments of the present application will be further explained with reference to the drawings.
Referring to fig. 1, fig. 1 shows a schematic diagram of a termination structure of a semiconductor device provided in an embodiment of the present application, the termination structure of the semiconductor device includes a cell structure and a bottom structure, the cell structure includes a passivation layer 101, an oxide layer 102, a transition region 110, a termination implantation region 109, a first epitaxial layer 104 and a second epitaxial layer 103, the oxide layer 102 is located below the passivation layer 101, the passivation layer 101 can isolate oxidation and prevent the termination from being oxidized too fast, the second epitaxial layer 103 is located below the oxide layer 102, the transition region 110 and the termination implantation region 109 are located between the oxide layer 102 and the second epitaxial layer 103, the termination implantation region 109 is located at one side of the transition region 110, a first buried layer region 107 is disposed in the first epitaxial layer 104, the first buried layer region 107 is located at the same side as the transition region 110, a second buried layer region 108 is disposed in the second epitaxial layer 103, the second buried layer 108 is located at the same side as the termination implantation region 109, and the field strength and the termination length can be effectively reduced through secondary epitaxy of the first epitaxial layer 104 and the second epitaxial layer 103; the bottom structure is located below the first epitaxial layer 104, and the cell structure is combined to form a complete terminal structure, so that the electric field intensity can be effectively reduced, the sensitivity of a terminal to an interface state is relieved while the electric field distribution is optimized, the length of the terminal is shortened, the size of the terminal structure is reduced, and the cost is reduced.
In an embodiment, the cell structure includes a silicon carbide Metal-Oxide-Semiconductor Field-Effect Transistor (SiC MOSFET), a silicon carbide Junction Barrier Schottky Diode (SiC JBS), a hybrid PIN Schottky Diode (MPS), and the like, and the terminal structure of the Semiconductor device provided in the embodiment of the present application may be configured with different cell structures, which is not described herein.
In an embodiment, the silicon carbide MOSFET may be a 4H-SiC MOSFET cell structure, the 4H-SiC MOSFET cell structure further comprising an active region, the active region being located between the passivation layer 101 and the second epitaxial layer 103, the active region being located on a side away from the terminal implant region 109.
As shown in fig. 2, the oxide layer 102 is divided into a first gate oxide layer 102 and a second gate oxide layer 102; the active region comprises a gate 201, a source metal 203, a first dielectric layer 202, a second dielectric layer 206, a P-well injection region 205, an N + region 204 and a P + region 207, the gate 201 is located between the first dielectric layer 202 and the first gate oxide layer 102, and the gate 201 can be formed by polysilicon deposition. The gate 201 is surrounded on the first dielectric layer 202, the second gate oxide layer 102 is surrounded on the second dielectric layer 206, and the first dielectric layer 202 and the second dielectric layer 206 are interlayer dielectric layers. The first dielectric layer 202, the second dielectric layer 206 and the passivation layer 101 form a source opening region, the source metal 203 is located in the source opening region, and the source metal 203 can be formed by a titanium Ti or aluminum Al metal sputtering method. The P + region 207 is located on one side far away from the terminal injection region 109, the N + region 204 is connected with the P + region 207, the first injection region of the P well injection region 205 is located right below the N + region 204 and the P + region 207, the second injection region of the P well injection region 205 is located below the first gate oxide layer 102, the P well injection region 205 is located above the second epitaxial layer 103, and the P well injection region 205, the N + region 204 and the P + region 207 are formed in a high-temperature ion injection mode.
As shown in fig. 3, the SiC junction barrier schottky diode may have a 4H-SiC JBS cell structure, and further includes an anode metal 301, a schottky contact 303, and a P + implantation region 302, wherein the P + implantation region 302 is located above the second epitaxial layer 103, the P + implantation region 302 is located at a side far from the terminal implantation region, and the P + implantation region 302 is formed by high temperature ion implantation. The schottky contact 303 is embedded in the P + implantation region 302, and the schottky contact 303 is formed by a Ti metal high temperature annealing method. The anode metal 301 includes a first metal body directly above the P + implantation region 302 and exposed to the outside, and a second metal body between the passivation layer 101 and the oxide layer 102, and the anode metal 301 is made of titanium Ti. The silicon carbide junction barrier Schottky diode structure has good reverse recovery performance and reduces reverse leakage.
In an embodiment, first buried layer region 107 includes a first junction deep implant region, a second junction deep implant region, and a third junction deep implant region, the second junction deep implant region being located between the first junction deep implant region and the third junction deep implant region. The first junction deep implantation region, the second junction deep implantation region and the third junction deep implantation region are three different junction deep implantations, the depths of the three junction deep implantation regions are 1.5 micrometers to 2.5 micrometers, and illustratively, the junction depths of the first junction deep implantation region, the second junction deep implantation region and the third junction deep implantation region are respectively 2.5 micrometers, 2 micrometers and 1.5 micrometers in sequence. Taking a planar structure as an example, the X direction is provided with a spacing distance (i.e. sequentially arranged from left to right), the Y direction is also provided with a spacing distance (i.e. sequentially arranged from top to bottom), and exemplarily, the X direction is provided with a spacing distanceThe distance was 5 microns and the spacing distance in the Y direction was also set to 0.5 microns. The doping concentration of the high energy implants of the first, second and third junction deep implants may be 5E17cm -3 To 5E18cm -3 . The first buried layer region 107 is formed by implanting high-energy aluminum Al ions into the first epitaxial layer 104, and according to a plurality of buried layers with different depths, the electric field intensity can be effectively reduced, and the electric field distribution is optimized.
In an embodiment, second buried layer region 108 includes a fourth junction depth implant, a fifth junction depth implant, and a sixth junction depth implant, the fifth junction depth implant being located between the fourth junction depth implant and the sixth junction depth implant. The fourth junction depth implantation region, the fifth junction depth implantation region and the sixth junction depth implantation region are three different junction depth implantations with a depth of 1.5 micrometers to 2.5 micrometers, illustratively, the junction depths of the fourth junction depth implantation region, the fifth junction depth implantation region and the sixth junction depth implantation region are respectively 2.5 micrometers, 2 micrometers and 1.5 micrometers in sequence. Taking a planar structure as an example, the X direction is provided with a spacing distance (i.e., the spacing distances are sequentially arranged from left to right), and the Y direction is also provided with a spacing distance (i.e., the spacing distances are sequentially arranged from top to bottom), illustratively, the spacing distance in the X direction is 5 micrometers, and the spacing distance in the Y direction is also 0.5 micrometers. The doping concentration of the high energy implants of the fourth, fifth and sixth junction depth implant regions may be 5E17cm -3 To 5E18cm -3 . The second buried layer region 108 is formed by implanting high-energy aluminum Al ions into the second epitaxial layer 103, and the electric field intensity can be effectively reduced and the electric field distribution can be optimized by the buried layers of different depths.
In an embodiment, the thicknesses of the first epitaxial layer 104 and the second epitaxial layer 103 are both 6 microns, and the secondary epitaxial technology is adopted to optimize the electric field distribution, shorten the length of the terminal and reduce the size of the terminal structure. The epitaxial concentration of the first epitaxial layer 104 and the second epitaxial layer 103 are both 1E16cm -3 。
In an embodiment, it may be that the first epitaxial layer 104 is above the second epitaxial layer 103, the first buried layer region 107 is located in the first epitaxial layer 104, and the second buried layer region 108 is located in the second epitaxial layer 103; it may also be that the first epitaxial layer 104 is above the second epitaxial layer 103, the first buried layer region 107 is located in the second epitaxial layer 103, and the second buried layer region 108 is located in the first epitaxial layer 104, where the positions of the first epitaxial layer and the second epitaxial layer may be interchanged, and epitaxy is performed on the basis of one epitaxial layer, so as to implement secondary epitaxy and buried layers of different depths, which is not described herein.
In one embodiment, the bottom structure comprises a substrate 105 and a backside metal 106, the substrate 105 is located below the first epitaxial layer 104, the substrate 105 has a thickness of 150 microns, the substrate 105 comprises an N + substrate 105, the concentration of the N + substrate 105 is 1E19cm -3 N-type doping. The back metal 106 is located below the substrate 105, and the back metal 106 includes a drain metal formed by sputtering nickel Ni metal and a cathode metal formed by metal nickel Ni.
The first embodiment is as follows: in the case of a 4H-SiC MOSFET cell structure
The back metal 106 is a drain metal, and the drain metal is formed below the N + substrate 105 by a nickel Ni metal sputtering method; the P well injection region 205, the P + region 207, the transition region 110, the N + region 204, the terminal injection region 109, the first buried layer region 107 and the second buried layer region 108 are formed in a high-temperature ion injection mode; the source metal 203 is formed by a titanium Ti or aluminum Al metal sputtering method; the first gate oxide layer 102 and the second gate oxide layer 102 are formed by adopting a thermal oxidation mode; the grid 201 is formed by adopting a polycrystalline silicon deposition mode; the second epitaxial layer 103 is secondarily epitaxial on the first epitaxial layer 104. The first buried layer region 107 is formed by implanting high-energy Al ions into the first epitaxial layer 104, the first buried layer region 107 comprises three sections of high-energy implants with different junction depths, the junction depths are 2.5 micrometers, 2 micrometers and 1.5 micrometers from left to right in sequence, and the doping concentration is 5E17cm -3 . The X-direction sizes of the three sections of injection regions are all 3 micrometers, and the interval is 5 micrometers; the dimension in the Y direction was 0.5 μm with a spacing of 0. The second buried layer region 108 is formed by implanting high-energy Al ions into the second epitaxial layer 103, the second buried layer region 108 comprises three sections of high-energy implants with different junction depths, the junction depths are 2.5 micrometers, 2 micrometers and 1.5 micrometers from left to right in sequence, and the doping concentration is 5E17cm -3 . The X-direction sizes of the three sections of injection regions are all 3 micrometers, and the intervals are 5 micrometers; dimension in Y direction of 0.5. Mu.mMeter, interval 0. The thickness of the first epitaxial layer 104 and the second epitaxial layer 103 are both 6 microns, and the epitaxial concentration is both 1E16cm -3 。
In one embodiment, simulation software can be used for building a terminal structure of the semiconductor device, and 1200V SiC MOSFETs are taken as an example for simulation analysis. The method specifically comprises the following steps: the drain electrode metal adopts metal Ni; the N + substrate 105 is 1E19cm thick -3 N + substrate 105 is 150 microns thick; the P-well implantation region 205 is implanted with Monte Carlo Al ions, and has a peak concentration of 4E18cm -3 Peak concentration depth of 0.5 micron; the N + region 204 is formed into a box-shaped distribution with a concentration of 2E19cm by N ion implantation -3 (ii) a The P + region 207 is formed in a box-shaped distribution by Al ion implantation, and has a concentration of 1E19cm -3 (ii) a The gate oxide layer 102 is formed by thermal oxidation and has a thickness of 0.05 micron; the gate 201 is formed on the first gate oxide layer 102 by polysilicon deposition. The withstand voltage performance of the terminal structure of the SiC MOSFET is compared with that of a conventional terminal structure, wherein the withstand voltage performance comprises the maximum electric field intensity of a terminal and reverse breakdown voltage, when the reverse voltage is 1600V, the maximum electric field intensity of the terminal structure of the SiC MOSFET is lower than that of the conventional structure, and after the length of the terminal injection region 109 is shortened by 10 micrometers, the maximum electric field intensity of the terminal structure of the SiC MOSFET is still lower than that of the conventional structure. Under the same condition of terminal injection region 109 width, the reverse breakdown voltage of the terminal structure adopting the SiC MOSFET is higher than that of the MOSFET device adopting the conventional terminal, under the condition of shortening the width of terminal injection region 109, the reverse breakdown voltage of the terminal structure adopting the SiC MOSFET is higher than that of the conventional terminal, the conventional terminal is the MOSFET device with unchanged terminal injection region 109 width, therefore, the electric field strength can be effectively reduced by adopting secondary epitaxy and the design of a plurality of buried layer regions, the terminal length is shortened while the electric field distribution is optimized, the size of the terminal structure is reduced, and the cost is further reduced.
Example two: in the case of 4H-SiC JBS cell structure
The terminal injection region 109 is a field limiting ring terminal region, and cathode metal is formed on the N + substrate 105 by adopting a nickel Ni metal sputtering method; p + implantation region 302, transition region 110,The field limiting ring terminal region, the first buried layer region 107 and the second buried layer region 108 are all formed in a high-temperature ion implantation mode; the Schottky contact 3032 is formed by adopting a titanium Ti metal high-temperature annealing method; the second epitaxial layer 103 is secondarily epitaxial on the first epitaxial layer 104. The first buried layer region 107 is formed by implanting high-energy Al ions into the first epitaxial layer 104, the first buried layer region 107 comprises three sections of high-energy implants with different junction depths, the junction depths are 2.5 micrometers, 2 micrometers and 1.5 micrometers from left to right in sequence, and the doping concentration is 5E17cm -3 . The X-direction sizes of the three sections of injection regions are all 3 micrometers, and the intervals are 5 micrometers; the first buried layer region 107 is adjacent to the left side of the termination region of the field limiting ring in a Y-direction dimension of 0.5 microns at a spacing of 0,X. The second buried layer region 108 is formed by implanting high-energy Al ions into the second epitaxial layer 103, the second buried layer region 108 comprises three sections of high-energy implants with different junction depths, the junction depths are 2.5 micrometers, 2 micrometers and 1.5 micrometers from left to right in sequence, and the doping concentration is 5E17cm -3 . The X-direction sizes of the three sections of injection regions are all 3 micrometers, and the intervals are 5 micrometers; the second buried layer region 108 is adjacent to the right side of the termination region of the field limiting ring with a Y-dimension of 0.5 microns and a spacing of 0,X. The thickness of the first epitaxial layer 104 and the second epitaxial layer 103 are both 6 microns, and the epitaxial concentration is both 1E16cm -3 。
In one embodiment, simulation software can be used for building a terminal structure of the semiconductor device, and 1200V SiC JBS is taken as an example for simulation analysis. The method specifically comprises the following steps: the cathode metal in the JBS adopts metallic nickel Ni; the N + substrate 105 is 1E19cm thick -3 N + substrate 105 is 150 microns thick; the P + implantation region 302 adopts aluminum Al ion implantation to form box distribution with concentration of 1E19cm -3 (ii) a The anode metal 301 adopts metal titanium Ti; the schottky contact 303 uses a high temperature annealing process with a schottky barrier height of 1.2eV. And comparing the voltage endurance performance of the terminal structure of the SiC JBS with that of the conventional terminal structure, wherein the voltage endurance performance comprises the maximum electric field intensity and the reverse breakdown voltage of the terminal. At a reverse voltage of 1600V, the maximum electric field strength of the termination structure of SiC JBS is lower than that of the conventional structure. Under the condition of the same number and spacing of field limiting rings, the reverse breakdown voltage of the terminal structure adopting the SiC JBS is higher than that of a JBS device adopting a conventional terminal.
In one embodiment, the semiconductor device comprises a terminal structure of the semiconductor device, the terminal structure of the semiconductor device comprises a cell structure and a bottom structure, the cell structure comprises a passivation layer 101, an oxide layer 102, a transition region 110, a terminal injection region 109, a first epitaxial layer 104 and a second epitaxial layer 103, the oxide layer 102 is located below the passivation layer 101, the second epitaxial layer 103 is located below the oxide layer 102, the transition region 110 and the terminal injection region 109 are located between the oxide layer 102 and the second epitaxial layer 103, the terminal injection region 109 is located at one side of the transition region 110, a first buried layer region 107 is arranged in the first epitaxial layer 104, the first buried layer region 107 and the transition region 110 are located at the same side, a second buried layer region 108 is arranged in the second epitaxial layer 103, the second buried layer region 108 and the terminal injection region 109 are located at the same side, and the electric field intensity can be effectively reduced and the terminal length can be shortened through secondary epitaxy of the first epitaxial layer 104 and the second epitaxial layer 103 and through the design of multiple buried layer regions; the bottom structure is located below the first epitaxial layer 104. The embodiment of the application adopts the secondary epitaxy on the first epitaxial layer 104 and the second epitaxial layer 103 and the design of a plurality of buried layer regions, so that the electric field intensity can be effectively reduced, the distribution of an electric field is optimized, the length of a terminal is shortened, the size of a terminal structure is reduced, the cost is reduced, and the sensitivity of the terminal to an interface state is relieved.
While the preferred embodiments of the present application have been described in detail, the present application is not limited to the above embodiments, and those skilled in the art will appreciate that the present application is not limited thereto. Under the shared conditions, various equivalent modifications or substitutions can be made, and the equivalent modifications or substitutions are included in the scope defined by the claims of the present application.
Claims (10)
1. A termination structure for a semiconductor device, comprising:
the cell structure comprises a passivation layer, an oxidation layer, a transition region, a terminal injection region, a first epitaxial layer and a second epitaxial layer, wherein the oxidation layer is positioned below the passivation layer, the second epitaxial layer is positioned below the oxidation layer, the transition region and the terminal injection region are positioned between the oxidation layer and the second epitaxial layer, the terminal injection region is positioned on one side of the transition region, a first buried layer region is arranged in the first epitaxial layer, the first buried layer region and the transition region are positioned on the same side, a second buried layer region is arranged in the second epitaxial layer, and the second buried layer region and the terminal injection region are positioned on the same side;
a bottom structure located below the first epitaxial layer.
2. The termination structure of the semiconductor device of claim 1, wherein the first buried layer region comprises a first junction deep implant region, a second junction deep implant region, and a third junction deep implant region, the second junction deep implant region being located between the first junction deep implant region and the third junction deep implant region.
3. The termination structure of the semiconductor device of claim 1, wherein the second buried layer region comprises a fourth junction depth implant region, a fifth junction depth implant region, and a sixth junction depth implant region, the fifth junction depth implant region being located between the fourth junction depth implant region and the sixth junction depth implant region.
4. The termination structure of a semiconductor device of claim 1, wherein the cell structure comprises a silicon carbide metal oxide field effect transistor, the silicon carbide metal oxide field effect transistor further comprising an active region, the active region being located between the passivation layer and the second epitaxial layer, the active region being located on a side away from the termination implant region.
5. The termination structure of a semiconductor device according to claim 4, wherein said oxide layer is divided into a first gate oxide layer and a second gate oxide layer;
the active region comprises a grid electrode, a source electrode metal, a first dielectric layer, a second dielectric layer, a P trap injection region, an N + region and a P + region, the grid electrode is located between the first dielectric layer and the first gate oxide layer, the grid electrode is surrounded on the first dielectric layer, the second gate oxide layer is surrounded on the second dielectric layer, the first dielectric layer, the second dielectric layer and the passivation layer form a source electrode open hole region, the source electrode metal is located in the source electrode open hole region, the P + region is located on one side far away from the terminal injection region, the N + region is connected with the P + region, the first injection region of the P trap injection region is located under the N + region and the P + region, the second injection region of the P trap injection region is located under the first gate oxide layer, and the P trap injection region is located above the second epitaxial layer.
6. The termination structure of a semiconductor device according to claim 1, wherein the cell structure comprises a silicon carbide junction barrier schottky diode, the junction barrier schottky diode further comprising an anode metal, a schottky contact and a P + implant region, the P + implant region being located above the second epitaxial layer, the P + implant region being located on a side away from the termination implant region, the schottky contact being in engagement with the P + implant region, the anode metal comprising a first metal body directly above the P + implant region and exposed outward, and a second metal body located between the passivation layer and the oxide layer.
7. A termination structure for a semiconductor device according to claim 1, wherein the first and second epitaxial layers are each 6 microns thick.
8. The termination structure of the semiconductor device of claim 1, wherein the bottom structure comprises a substrate underlying the first epitaxial layer and a backside metal underlying the substrate.
9. The termination structure of claim 8, wherein the substrate has a thickness of 150 microns.
10. A semiconductor device characterized by comprising a termination structure of a semiconductor device according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211588280.3A CN115579382A (en) | 2022-12-12 | 2022-12-12 | Terminal structure of semiconductor device and semiconductor device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211588280.3A CN115579382A (en) | 2022-12-12 | 2022-12-12 | Terminal structure of semiconductor device and semiconductor device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115579382A true CN115579382A (en) | 2023-01-06 |
Family
ID=84590247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211588280.3A Pending CN115579382A (en) | 2022-12-12 | 2022-12-12 | Terminal structure of semiconductor device and semiconductor device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115579382A (en) |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303956A (en) * | 2002-04-11 | 2003-10-24 | Fuji Electric Co Ltd | Silicon carbide semiconductor device and manufacturing method thereof |
| US20070272979A1 (en) * | 2006-05-16 | 2007-11-29 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20100044825A1 (en) * | 2008-08-19 | 2010-02-25 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
| CN101803029A (en) * | 2007-09-21 | 2010-08-11 | 罗伯特·博世有限公司 | Semiconductor device and method for the production thereof |
| JP2011114028A (en) * | 2009-11-24 | 2011-06-09 | Toyota Motor Corp | SiC SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME |
| CN102194858A (en) * | 2010-03-03 | 2011-09-21 | 株式会社东芝 | Semiconductor device |
| US20150372075A1 (en) * | 2014-06-18 | 2015-12-24 | Stmicroelectronics S.R.L. | Edge termination structure for a power integrated device and corresponding manufacturing process |
| US20200091283A1 (en) * | 2018-09-15 | 2020-03-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN113140612A (en) * | 2020-01-17 | 2021-07-20 | 珠海零边界集成电路有限公司 | Terminal structure of silicon carbide power device and preparation method thereof |
| CN113555447A (en) * | 2021-06-09 | 2021-10-26 | 浙江芯国半导体有限公司 | 4H-SiC Schottky diode based on diamond terminal structure and manufacturing method |
| CN113658996A (en) * | 2021-08-20 | 2021-11-16 | 电子科技大学 | Transverse variable doping terminal structure and design method thereof |
| CN113990935A (en) * | 2021-11-25 | 2022-01-28 | 芜湖启迪半导体有限公司 | Groove silicon carbide MOSFET device and preparation method thereof |
| CN114864661A (en) * | 2022-04-21 | 2022-08-05 | 西安电子科技大学 | Stepped JTE-Rings super junction power device terminal structure and preparation method thereof |
| CN114883383A (en) * | 2022-03-30 | 2022-08-09 | 西安电子科技大学 | SIMS-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof |
-
2022
- 2022-12-12 CN CN202211588280.3A patent/CN115579382A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303956A (en) * | 2002-04-11 | 2003-10-24 | Fuji Electric Co Ltd | Silicon carbide semiconductor device and manufacturing method thereof |
| US20070272979A1 (en) * | 2006-05-16 | 2007-11-29 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN101803029A (en) * | 2007-09-21 | 2010-08-11 | 罗伯特·博世有限公司 | Semiconductor device and method for the production thereof |
| US20100044825A1 (en) * | 2008-08-19 | 2010-02-25 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
| JP2011114028A (en) * | 2009-11-24 | 2011-06-09 | Toyota Motor Corp | SiC SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME |
| CN102194858A (en) * | 2010-03-03 | 2011-09-21 | 株式会社东芝 | Semiconductor device |
| US20150372075A1 (en) * | 2014-06-18 | 2015-12-24 | Stmicroelectronics S.R.L. | Edge termination structure for a power integrated device and corresponding manufacturing process |
| US20200091283A1 (en) * | 2018-09-15 | 2020-03-19 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN113140612A (en) * | 2020-01-17 | 2021-07-20 | 珠海零边界集成电路有限公司 | Terminal structure of silicon carbide power device and preparation method thereof |
| CN113555447A (en) * | 2021-06-09 | 2021-10-26 | 浙江芯国半导体有限公司 | 4H-SiC Schottky diode based on diamond terminal structure and manufacturing method |
| CN113658996A (en) * | 2021-08-20 | 2021-11-16 | 电子科技大学 | Transverse variable doping terminal structure and design method thereof |
| CN113990935A (en) * | 2021-11-25 | 2022-01-28 | 芜湖启迪半导体有限公司 | Groove silicon carbide MOSFET device and preparation method thereof |
| CN114883383A (en) * | 2022-03-30 | 2022-08-09 | 西安电子科技大学 | SIMS-JTE terminal structure of novel floating junction silicon carbide power device and preparation method thereof |
| CN114864661A (en) * | 2022-04-21 | 2022-08-05 | 西安电子科技大学 | Stepped JTE-Rings super junction power device terminal structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104051540B (en) | Super-junction device and its manufacturing method | |
| US11961904B2 (en) | Semiconductor device including trench gate structure and buried shielding region and method of manufacturing | |
| CN109065621B (en) | Insulated gate bipolar transistor and preparation method thereof | |
| CN108682624B (en) | Manufacturing method of IGBT chip with composite gate | |
| CN111081779A (en) | Shielding gate trench type MOSFET and manufacturing method thereof | |
| CN115332317A (en) | SBD-integrated silicon carbide planar MOSFET and manufacturing method thereof | |
| US11355592B2 (en) | Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator | |
| CN114038908B (en) | Diode-integrated trench gate silicon carbide MOSFET device and method of manufacture | |
| CN116387362A (en) | HJD integrated SiC UMOSFET device and preparation method thereof | |
| CN115579397A (en) | Two-stage trench gate silicon carbide MOSFET and preparation method thereof | |
| CN110534576B (en) | Split-gate 4H-SiC VDMOS device | |
| CN117316983A (en) | Structure for improving short circuit robustness of SIC power device and manufacturing method | |
| CN117253923A (en) | Boss split gate silicon carbide MOSFET integrated with JBS and preparation process | |
| WO2024052643A1 (en) | Silicon carbide lateral power semiconductor device | |
| CN116404034A (en) | Silicon carbide power device matched with floating junction to introduce sheet-shaped P channel | |
| WO2023183215A1 (en) | Support shield structures for trenched semiconductor devices | |
| CN113054015A (en) | Silicon carbide MOSFET chip | |
| CN214956891U (en) | Shielding grid MOSFET device with high avalanche tolerance | |
| CN115579382A (en) | Terminal structure of semiconductor device and semiconductor device thereof | |
| CN115842056A (en) | HJD-integrated SiC DMOSFET device and preparation method thereof | |
| CN114050183A (en) | Reverse conducting power chip manufacturing method | |
| CN113224135A (en) | Shielding gate MOSFET device with high avalanche tolerance and manufacturing method thereof | |
| CN221008960U (en) | High short-circuit tolerance trench gate silicon carbide MOSFET structure | |
| CN117293191B (en) | Layout structure, semiconductor device and manufacturing method thereof | |
| CN114203797B (en) | Super junction gallium oxide transistor based on heterojunction and manufacturing method and application thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20230106 |