CN117316983A - Structure for improving short circuit robustness of SIC power device and manufacturing method - Google Patents

Structure for improving short circuit robustness of SIC power device and manufacturing method Download PDF

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CN117316983A
CN117316983A CN202311405648.2A CN202311405648A CN117316983A CN 117316983 A CN117316983 A CN 117316983A CN 202311405648 A CN202311405648 A CN 202311405648A CN 117316983 A CN117316983 A CN 117316983A
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layer
type
csl
power device
well region
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陈鸿骏
杨程
裘俊庆
赵耀
万胜堂
王坤
王正
王毅
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Yangzhou Yangjie Electronic Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

A structure and a manufacturing method for improving short-circuit robustness of SIC power devices. Relates to the technical field of power semiconductors. The method comprises the following steps: step 001, providing an N-type heavily doped substrate, namely an N+ type SiC semiconductor substrate, wherein the doping concentration is 360-400 um, and the doping concentration is 1e19cm ‑2 The method comprises the steps of carrying out a first treatment on the surface of the The N+ type substrate has two surfaces, which are divided into a front surface and a back surface, and an N type buffer layer is formed on the front surface, the thickness is 0.8-1 um, the doping concentration is 1e18cm ‑2 The method comprises the steps of carrying out a first treatment on the surface of the The N-type buffer layer is covered with an N-type lightly doped drift layer, namely an N-type drift layer with the thickness of 5-15 um and the doping concentration of 5e 15-1 e16cm ‑2 Forming a metal electrode layer on the back surface; 002, P-type doping is carried out on the surface of the drift layer through a photoetching mask to form a P-Well region; the invention has simple manufacturing process and obvious effect,the method can be applied to the manufacture of novel silicon carbide MOSFET power devices.

Description

Structure for improving short circuit robustness of SIC power device and manufacturing method
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a structure for improving the short circuit robustness of a SIC power device and a manufacturing method thereof.
Background
The power device is used as a core element in the field of power electronics, is widely applied to the fields of vehicles, industry, medical treatment, household electronics and the like, and has important influence in human life and social economy. Today there is a shortage of global resources and increasingly changing climate, and the semiconductor industry is pursuing maximum utilization of resources. Silicon carbide is used as a representative of a third generation wide bandgap semiconductor, and has been widely developed in various countries due to its excellent performance in high-temperature environments, high-power applications and heat dissipation.
SIC MOSFET has advantages of low on-resistance, high withstand voltage, low switching loss, fast frequency and the like, and is expected to gradually replace the trend of silicon-based IGBT. SIC MOSFETs are often operated in severe operating conditions, and short circuit testing is an important test for characterizing the reliability of devices. Because of artificial factors or faults of machine equipment, the risk of short circuit of the power device occurs, and once the short circuit of the device in the circuit is detected, the protection circuit triggers the protection mechanism to cut off the circuit, but the triggering protection circuit has a certain reaction time, the power device is required to bear short-term short circuit capacity, and the short circuit robustness of the device is fed back. The short-circuit time is only on the order of microseconds in time, but the device can also flow a current with larger density instantaneously, so that a large amount of heat is generated, and finally the thermal failure of the device is caused.
Most researchers at home and abroad explore how to improve the short-circuit robustness of the device from the failure phenomenon of the short-circuit device and an external protection circuit, but how to improve the short-circuit robustness of the device has important significance. The SiC breakdown field strength is high, the forbidden bandwidth is wider, so that the doping concentration of the epitaxial layer can be higher than that of a silicon-based device, and the SiC chip has stronger through-current capability and smaller size. Experiments prove that the short-circuit time of the conventional Si IGBT can reach more than 10us, and the short-circuit time of the SiC MOSFET is only 3-5 us, because the temperature is too high due to the large short-circuit current density of the SiC MOSFET, the heat dissipation is slower due to the small chip size, and the short-circuit robustness of the SiC MOSFET is lower than that of the SiIGBT.
Therefore, how to improve the short-circuit robustness of the SiC MOSFET to adapt to the application under the circuit environment with severe working conditions is a task that needs to be solved currently.
Disclosure of Invention
Aiming at the problems, the invention provides a structure for improving the short circuit robustness of a SIC power device and a manufacturing method thereof, wherein the structure is used for improving the short circuit robustness of a trench gate SiC MOSFET structure.
The technical scheme of the invention is as follows: a structure manufacturing method for improving short circuit robustness of SIC power devices comprises the following steps:
step 001, providing an N-type heavily doped substrate, namely an N+ type SiC semiconductor substrate, wherein the doping concentration is 360-400 um, and the doping concentration is 1e19cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The N+ type substrate has two surfaces, which are divided into a front surface and a back surface, and an N type buffer layer is formed on the front surface, the thickness is 0.8-1 um, the doping concentration is 1e18cm -2 (II), (III), (V), (; the N-type buffer layer is covered with an N-type lightly doped drift layer, namely an N-type drift layer with the thickness of 5-15 um and the doping concentration of 5e 15-1 e16cm -2 Forming a metal electrode layer on the back surface;
002, P-type doping is carried out on the surface of the drift layer through a photoetching mask to form a P-Well region;
step 003, after determining the P-Well region, lightly doping twice through a secondary mask, forming buried doping under the P-Well region to form a carrier extension layer CSL-1 and a carrier extension layer CSL-2;
step 004, N-type heavily doping is carried out on the surface of the P-Well region through a photoetching mask to form a source region;
step 005, P-type heavily doping is carried out on the surface of the P-Well region through a photoetching mask to form an ohmic contact region;
step 006, forming a groove structure in the center of the P-Well region by dry etching through a photoetching mask, and injecting P-type ions into the bottom of the groove by ion injection to carry out P-type heavy doping; forming a shielding layer;
step 007, forming a gate oxide layer on the surface of the groove through a dry-oxygen thermal oxidation process, forming a channel at the interface of the gate oxide layer and the P-Well region, and depositing Ploy silicon on the surface of the gate oxide layer to form a gate electrode structure;
step 008, isolating the gate electrode structure from the ohmic contact region by depositing a passivation layer;
step 009, forming an ohmic contact window by etching the passivation layer, and forming a good source ohmic contact layer by alloying deposited metal and high-temperature annealing;
step 010, forming source metal on the front surface by depositing electrode metal;
step 011, thinning the substrate by a thinning process on the back surface in sequence; depositing metal to form a back drain ohmic contact layer; and depositing electrode metal on the back surface to form a drain electrode contact electrode.
Specifically, the N-type heavily doped substrate in the step 001 is a 4H-SiC substrate with a doping concentration of 1e19cm -2 。
Specifically, in step 002, the P-Well region is doped with P-type material, and a layer of SiO of 20-50 nm is formed on the surface of the drift layer before implantation 2 The film cushion layer prevents the surface of the SiC drift layer from being damaged by high-energy ion implantation.
Specifically, in step 003, the carrier extension layer CSL-1 is doped with P type, and the N type doping concentration of the drift layer is compensated by the N type doping concentration of the drift layer, so that the N type doping concentration of the drift layer is reduced, the carrier extension layer CSL-2 is doped with N type doping, so that the N type doping concentration of the carrier extension layer CSL-2 is increased, and a layer of SiO of 20-50 nm is formed on the surface of the drift layer before injection 2 The film cushion layer prevents the surface of the SiC drift layer from being damaged by high-energy ion implantation.
Specifically, in step 004, the source region is doped with N-type dopant.
Specifically, in step 005, the ohmic contact region is doped with P-type material.
Specifically, in the step 6, the shielding layer adopts P-type doping; and after the ion implantation is finished, activating annealing is required, in this case, a high-temperature vacuum annealing furnace is adopted, the annealing temperature is 1650-1750 ℃, and the annealing time is 10-30 min.
Specifically, in the step 7, the temperature of the gate oxide growth is 1250-1350 ℃, the thickness of the grown gate oxide structure is 50-60 nm, the grown gate oxide structure is subjected to NO annealing treatment, the interface state of the gate oxide growth is reduced, the on mobility is improved, and the annealing temperature and the annealing time are 1250 ℃ and 1H respectively.
The structure for improving the short circuit robustness of the SIC power device is characterized by sequentially comprising a drain electrode contact electrode, a drain ohmic contact layer, a substrate, an N-type buffer layer, a drift layer and a P-Well region from bottom to top;
carrier expansion layers CSL-1 and CSL-2 connected with the drift layer are arranged in the P-Well region;
an ohmic contact region connected with the carrier extension layer CSL-2 is arranged at the end part of the P-Well region;
a source region connected with the ohmic contact region is arranged at the top of the P-Well region;
a channel which downwards extends into the drift layer is arranged in the middle of the top surface of the source region;
a shielding layer and a gate oxide layer are arranged in the channel; a wrapped gate electrode (5) is arranged in the gate oxide layer;
the top surface of the gate oxide layer (10) is provided with a gate passivation layer (15) extending upwards;
the ohmic contact region (6), the source region (14) and the top surface of the gate passivation layer (15) are covered by a source metal (8).
Specifically, the carrier extension layer CSL-1 (11) is positioned in the middle of the carrier extension layer CSL-2 (12).
Specifically, the N-type doping concentration of the carrier extension layer CSL-2 (12) is 5e 16-8 e16cm -2 ；
The concentration of the carrier extension layer CSL-1 (11) is 1e 15-5 e15cm -2 。
The invention provides the doping concentrations of two different areas in the carrier expansion layer, namely CSL-1 and CSL-2, wherein the doping concentration of the CSL-2 area close to one side of a channel is higher than that of the CSL-1, when a lower voltage is applied to a drain electrode of the device, the device works in a linear area, a P-Well area and a shielding layer at the bottom of the channel hardly generate a depletion layer, and a current path is wider; when the device encounters a short circuit condition, as shown in fig. 11, the voltage applied by the drain is higher, the P-Well region and the shielding layer at the bottom of the trench generate a depletion layer to be wider, and the current path is deviated, as shown in fig. 12. When the high-resistance power-on-state circuit is normally conducted, the CSL-2 high-doped region is added, so that the overall on-resistance is reduced, and when the high-resistance power-on-state circuit is in short circuit, the current flows through the high-resistance region CSL-1, the current density is reduced, the short circuit power consumption is effectively reduced, and the short circuit robustness is enhanced.
The method has simple manufacturing process and obvious effect, and can be applied to manufacturing of novel silicon carbide MOSFET power devices.
Drawings
FIG. 1 provides a substrate schematic of a SiC MOSFET;
FIG. 2 provides a schematic illustration of SiC MOSFET formation epitaxy;
FIG. 3 provides a schematic illustration of a SiC MOSFET forming a P-Well region;
FIG. 4 provides a schematic diagram of a SiC MOSFET forming carrier extension layers CSL-1, CSL-2;
FIG. 5 provides a schematic illustration of an SiC MOSFET forming an ohmic contact region, a source region;
FIG. 6 provides a schematic illustration of a SiC MOSFET forming trenches and shielding regions;
FIG. 7 provides a schematic diagram of a SiC MOSFET forming a gate structure;
FIG. 8 provides a schematic diagram of a SiC MOSFET formed gate passivation;
FIG. 9 provides a schematic diagram of a SiC MOSFET forming a source contact;
FIG. 10 provides a schematic diagram of a SiC MOSFET forming a drain contact;
FIG. 11 provides current paths when the SiC MOSFET is normally on;
FIG. 12 provides current paths during a SiC MOSFET short circuit condition;
in the figure, 1 is a drain contact electrode, 2 is a drain ohmic contact layer, 3 is a substrate, 4 is a drift layer, 5 is a gate electrode, 6 is an ohmic contact region, 7 is a source ohmic contact layer, 8 is a source metal, 9 is a shielding layer, 10 is a gate oxide layer, 11 is a carrier extension layer CSL-1, 12 is a carrier extension layer CSL-2, 13 is a P-Well region, 14 is a source region, 15 is a gate passivation layer, 16 is a channel, and 17 is an N-type buffer layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Embodiments in accordance with the present invention are described below with reference to fig. 1-12;
a structure manufacturing method for improving short circuit robustness of SIC power devices comprises the following steps:
step 001, providing an N-type heavily doped substrate 3, referring to fig. 1, which is an n+ type SiC semiconductor substrate, wherein the n+ type substrate has two surfaces, namely a front surface and a back surface; referring to fig. 2, an N-type buffer layer 17 is formed on the front surface, the N-type buffer layer 17 covers the N-type lightly doped drift layer 4, and a metal electrode layer is formed on the back surface;
step 002, referring to fig. 3, performing second doping type doping on the surface of the epitaxial layer 4 through a photolithography mask to form a P-Well region 13;
step 003, after determining the Well region, lightly doping twice through a secondary mask, forming buried doping under the P-Well region 13, and forming a carrier extension layer CSL-1 11 and a carrier extension layer CSL-2 12;
step 004, N-type heavily doping is carried out on the surface of the well region through a photoetching mask to form a source region 14; referring to fig. 4;
step 005, P-type heavily doping is carried out on the surface of the well region through a photoetching mask to form an ohmic contact region 6; referring to fig. 5;
step 006, forming a channel 16 in the center of the well region by dry etching through a photoetching mask, injecting ions of a second doping type into the bottom of the channel by ion injection, and carrying out P-type heavy doping to form a shielding layer 9, as shown in fig. 6;
step 007, forming a gate oxide layer 10 on the surface of the channel 16, and depositing Ploy silicon on the surface of the gate oxide layer 10 to form a gate electrode 5 structure, as shown in fig. 7;
step 008, isolating the gate electrode 5 structure from the ohmic contact region 6 by depositing a passivation layer, as shown with reference to fig. 8;
step 009, forming an ohmic contact window by etching the passivation layer, and forming a good ohmic contact layer 7 by alloying deposited metal and high temperature annealing, as shown in fig. 9;
step 010, forming a source metal 8 by depositing an electrode metal on the front surface, as shown with reference to fig. 9;
step 011, thinning the substrate by a thinning process on the back surface, and reducing the on-resistance; a metal is deposited, laser annealed to form a drain ohmic contact layer 2, and an electrode metal is deposited to form a drain contact electrode 1, as shown with reference to fig. 10.
Further defined, the N-type heavily doped substrate 3 in step 001 is a 4H-SiC substrate with a doping concentration of 1e19cm -2 The thickness is 360um, the thickness of the buffer layer is 1um, the doping concentration is 1e18cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The thickness and doping concentration of the drift layer were determined to be 10um,8e15cm -2 。
Further limiting, in the step 002, the P-Well region 13 is doped with P type, and a layer of SiO of 20-50 nm is formed on the surface of the drift layer before implantation 2 The film cushion layer prevents the surface of the SiC drift layer from being damaged by high-energy ion implantation. The energy of each implantation of the P-Well region is 100-600 Kev, and the implantation dosage is 1e 12-1 e14 cm -2 The implantation times are 3-5 times, the P-Well region is implanted for 4 times, and the implantation energy and the implantation dose are respectively as follows: 560Kev 1e14 cm -2 ，390Kev 1e13cm -2 ，280Kev 5e12cm -2 ，120Kev1e12cm -2 。
Further limiting, in step 003, the carrier extension layer CSL-1 is doped with P type, and the N type doping concentration of the drift layer 4 is compensated by the N type doping concentration of the drift layer 4, so that the N type doping concentration of the drift layer 4 is reduced, the carrier extension layer CSL-2 is doped with N type, so that the N type doping concentration of the carrier extension layer CSL-2 12 is increased, and a layer of SiO of 20-50 nm is formed on the surface of the drift layer 4 before injection 2 The film cushion layer prevents the surface of the SiC drift layer from being damaged by high-energy ion implantation. In this case, the number of injection times of CSL-1 is 2, and the energy and the dose of injection are respectively: 700Kev 4e11cm -2 , 600Kev 3e11cm -2 The injected P-type ions and the N-type doping of the drift layer are mutually compensated to obtain the CSL-1 region with the N-type doping concentration of 1e 15-3 e15cm -2 The method comprises the steps of carrying out a first treatment on the surface of the The injection times of CSL-2 are 3 times, and the energy and the dose of the injection are respectively as follows: 700Kev 8e11cm -2 , 600Kev 7e11cm -2 ，500Kev 6e11cm -2 So that the N-type doping concentration of the CSL-2 region is increased to 7e 16-8 e16cm -2 。
Further, in step 004, the source region 14 is doped with N-type, and the number of times of implantation is 3 in this case, and the implantation energy and dose are respectively: 280Kev 1e15cm -2 , 160Kev 9e14cm -2 ，80Kev 8e14cm -2 。
Further defined, in step 005, the ohmic contact region 6 is doped with P-type material, and the number of times of implantation is 3 in this case, and the implantation energy and dose are respectively: 350Kev 1e15cm -2 , 220Kev 9e14cm -2 ，100Kev 8e14cm -2 。
Further limiting, in step 6, the shielding layer 9 is doped with P-type, and in this case, the number of implantation times is 3, and the implantation energy and the implantation dose are respectively: 260Kev 1e15cm -2 , 160Kev 9e14cm -2 ，80Kev 8e14cm -2 The method comprises the steps of carrying out a first treatment on the surface of the And after the ion implantation is finished, activating annealing is required, in this case, a high-temperature vacuum annealing furnace is adopted, the annealing temperature is 1700 ℃, and the annealing time is 30min.
Further limiting that the temperature of the gate oxide growth in the step 7 is 1350 ℃, the thickness of the grown gate oxide is 60nm, the grown gate oxide structure is subjected to NO annealing treatment, the interface state of the gate oxide growth is reduced, the on mobility is improved, and the annealing temperature and the annealing time are 1250 ℃ and 1H respectively.
Further defined, the passivation layer is formed by LPCVD and grown to a thickness of 0.6um. The deposited ohmic contact metal is Ni, and the alloying condition is 960 ℃ for 5min; the electrode metal deposited on the front surface is Al, and the thickness is 4-5 um; thinning the substrate to 180-200 mu m; the ohmic contact metal deposited on the back surface is Ni, and alloying is carried out by adopting a laser local annealing mode.
Further limited, the back contact electrode metal is Ti/Ni/Ag, the thickness is 1.5um, and the back contact electrode is formed by adopting a sputtering process.
In summary, the method for manufacturing the silicon carbide MOS power device with high short-circuit robustness has the advantages that carrier extension layers of two areas are provided, namely CSL-1 and CSL-2, the doping concentration of the CSL-2 area close to one side of a channel is higher than that of the CSL-1, and the short-circuit robustness is greatly improved under the conditions of improving the current passing capability and reducing the on-resistance; the invention has obvious case effect and simple manufacturing process, and has wide prospect in the manufacture and application of novel silicon carbide MOS.
For the purposes of this disclosure, the following points are also described:
(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A structure manufacturing method for improving the short-circuit robustness of a SIC power device is characterized by comprising the following steps:
step 001, providing an N-type heavily doped substrate (3), and forming an N-type buffer layer (17) on the front surface; forming a metal electrode layer on the back surface of the drift layer (4) covered with the N-type buffer layer (17) and of the N-type lightly doped type;
002, P-type doping is carried out on the surface of the drift layer (4) through a photoetching mask to form a P-Well region (13);
step 003, after determining the P-Well region (13), carrying out twice light doping through a secondary mask, and forming buried doping under the P-Well region (13) to form a carrier extension layer CSL-1 (11) and a carrier extension layer CSL-2 (12);
step 004, N-type heavily doping is carried out on the surface of the P-Well region (13) through a photoetching mask to form a source region (14);
step 005, carrying out P-type heavy doping on the surface of the P-Well region (13) through a photoetching mask to form an ohmic contact region (6);
step 006, forming a groove structure in the center of the P-Well region (13) by photoetching mask and dry etching, and implanting P-type ions into the bottom of the groove by ion implantation to carry out P-type heavy doping; forming a shielding layer (9);
step 007, forming a gate oxide layer (10) on the surface of the groove through a dry-oxygen thermal oxidation process, forming a channel at the interface between the gate oxide layer (10) and the P-Well region (13), and depositing Ploy silicon on the surface of the gate oxide layer (10) to form a gate electrode (5) structure;
step 008, isolating the gate electrode (5) structure from the ohmic contact region (6) by depositing a passivation layer;
step 009, forming an ohmic contact window by etching the passivation layer, and forming a good source ohmic contact layer (7) by alloying deposited metal and high-temperature annealing;
step 010, forming source metal (8) on the front side by depositing electrode metal;
step 011, thinning the substrate by a thinning process on the back surface in sequence; depositing metal to form a back drain ohmic contact layer (2); and depositing electrode metal on the back surface to form a drain contact electrode (1).
2. The method for manufacturing a structure for improving the short-circuit robustness of a SIC power device according to claim 1, wherein the substrate (3) of the N-type heavy doping type in the step 001 is a 4H-SiC substrate, and the doping concentration is 1e19cm -2 。
3. The method for manufacturing a structure for improving short circuit robustness of a SIC power device according to claim 1, wherein in the step 003, the carrier extension layer CSL-1 (11) is doped with P type, the N type doping concentration of the drift layer (4) is reduced by compensating the N type doping concentration of the drift layer (4), the carrier extension layer CSL-2 (12) is doped with N type, the N type doping concentration of the carrier extension layer CSL-2 (12) is increased, and a layer of SiO of 20-50 nm is formed on the surface of the drift layer (4) before injection 2 The film cushion layer prevents the surface of the SiC drift layer from being damaged by high-energy ion implantation.
4. The method for manufacturing the structure for improving the short circuit robustness of the SIC power device according to claim 1, wherein the source region (14) is doped with N type in the step 004.
5. The method for manufacturing the structure for improving the short circuit robustness of the SIC power device according to claim 1, wherein the Europe contact area (6) is doped with P type in the step 005.
6. The method for manufacturing the structure for improving the short-circuit robustness of the SIC power device according to claim 1, wherein the shielding layer (9) in the step 6 is doped with P type; and after the ion implantation is finished, activating annealing is required, in this case, a high-temperature vacuum annealing furnace is adopted, the annealing temperature is 1650-1750 ℃, and the annealing time is 10-30 min.
7. The method for manufacturing the structure for improving the short circuit robustness of the SiC power device according to claim 1, wherein in the step 7, the temperature of the gate oxide growth is 1250-1350 ℃, the thickness of the grown gate oxide structure is 50-60 nm, the grown gate oxide structure is subjected to NO annealing treatment, the interface state of the gate oxide growth is reduced, the on mobility is improved, and the annealing temperature and the annealing time are 1250 ℃ and 1H respectively.
8. The structure for improving the short circuit robustness of the SIC power device, which is prepared by the structure manufacturing method for improving the short circuit robustness of the SIC power device, is characterized by sequentially comprising a drain contact electrode (1), a drain ohmic contact layer (2), a substrate (3), an N-type buffer layer (17), a drift layer (4) and a P-Well region (13) from bottom to top;
a carrier expansion layer CSL-1 (11) and a carrier expansion layer CSL-2 (12) which are connected with the drift layer (4) are arranged in the P-Well region (13);
an ohmic contact region (6) connected with the carrier expansion layer CSL-2 (12) is arranged at the end part of the P-Well region (13);
a source region (14) connected with the ohmic contact region (6) is arranged at the top of the P-Well region (13);
the top surface of the source region (14) is provided with a channel (16) which extends downwards into the drift layer (4);
a shielding layer (9) and a gate oxide layer (10) are arranged in the channel (16); a wrapped gate electrode (5) is arranged in the gate oxide layer (10);
the top surface of the gate oxide layer (10) is provided with a gate passivation layer (15) extending upwards;
the ohmic contact region (6), the source region (14) and the top surface of the gate passivation layer (15) are covered by a source metal (8).
9. The structure for improving the short circuit robustness of the SIC power device according to claim 8, wherein the carrier extension layer CSL-1 (11) is located in the middle of the carrier extension layer CSL-2 (12).
10. The structure for improving the short circuit robustness of the SIC power device according to claim 8, wherein the N-type doping concentration of the carrier extension layer CSL-2 (12) is 5e 16-8 e16cm -2 ；
The concentration of the carrier extension layer CSL-1 (11) is 1e 15-5 e15cm -2 。
CN202311405648.2A 2023-10-27 2023-10-27 Structure for improving short circuit robustness of SIC power device and manufacturing method Pending CN117316983A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118431270A (en) * 2024-07-01 2024-08-02 深圳市港祥辉电子有限公司 Field-stop gallium oxide IGBT device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118431270A (en) * 2024-07-01 2024-08-02 深圳市港祥辉电子有限公司 Field-stop gallium oxide IGBT device and preparation method thereof

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