JPH1098188A - Insulated gate semiconductor device - Google Patents

Insulated gate semiconductor device

Info

Publication number
JPH1098188A
JPH1098188A JP8331321A JP33132196A JPH1098188A JP H1098188 A JPH1098188 A JP H1098188A JP 8331321 A JP8331321 A JP 8331321A JP 33132196 A JP33132196 A JP 33132196A JP H1098188 A JPH1098188 A JP H1098188A
Authority
JP
Japan
Prior art keywords
semiconductor
layer
conductivity type
trench
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8331321A
Other languages
Japanese (ja)
Inventor
Katsunori Asano
Yoshitaka Sugawara
勝則 浅野
良孝 菅原
Original Assignee
Hitachi Ltd
Kansai Electric Power Co Inc:The
株式会社日立製作所
関西電力株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP20399296 priority Critical
Priority to JP8-203992 priority
Application filed by Hitachi Ltd, Kansai Electric Power Co Inc:The, 株式会社日立製作所, 関西電力株式会社 filed Critical Hitachi Ltd
Priority to JP8331321A priority patent/JPH1098188A/en
Priority claimed from PCT/JP1997/004538 external-priority patent/WO1998026458A1/en
Publication of JPH1098188A publication Critical patent/JPH1098188A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

PROBLEM TO BE SOLVED: To relax an electric field intensity of an insulation material layer at the lower part of a trench-type insulating gate layer and to improve voltage- resistance and reliability by providing at the lower part of the trench-type insulation gate, the first semiconductor area of the second conduction type formed in a semiconductor substrate, that is, a semiconductor area for relaxing electric field. SOLUTION: A trench-type insulating gate electrode 14, with a substrate, in a broad sense, comprising a substrate 3, a drift layer 2, and a body layer 4 etched anisotropically, forms a trench 69 penetrating the body layer 4 of p-conductive type with its bottom part reaching the drift layer 2 of n<-> - conductivity type. At its bottom, an electric field-relaxing semiconductor area 1 of p-conductive type is formed, then after a gate insulating film 9 is formed on the inside surface of the trench 69, polysilicon is deposited to fill the trench 69 with it for forming a gate area 64. At the lower part of the trench-type insulation gate electrode 14, most of the applied voltage is shared with the electric field relaxing semiconductor area 1 and the drift layer 2 of n<-> - conductivity type, the electric field intensity of the insulating material layer 9 is relaxed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、スイッチング素子
として用いられる絶縁ゲート半導体装置に関するもので
ある。
[0001] The present invention relates to an insulated gate semiconductor device used as a switching element.

【0002】[0002]

【従来の技術】従来から、高速スイッチング特性に優
れ、かつ高入力インピーダンスをもつので入力損失が小
さい電力用縦型半導体装置として、MOSFETや絶縁ゲート
バイポーラトランジスタ(以下IGBTと記す)が知ら
れている。両トランジスタとも低損失化を図るためにそ
れぞれの半導体装置に内在する接合型電界効果トランジ
スタ(以下JFETと記す)の抵抗を削減するために、図1
1や図12に示すように、凹部29にゲート14を形成
するトレンチ型絶縁ゲート構造の半導体装置が製作され
ている。
2. Description of the Related Art Conventionally, MOSFETs and insulated gate bipolar transistors (hereinafter, referred to as IGBTs) have been known as power type vertical semiconductor devices which are excellent in high-speed switching characteristics and have a high input impedance and a small input loss. . To reduce the resistance of the junction field effect transistor (hereinafter referred to as JFET) in each semiconductor device in order to reduce the loss of both transistors, FIG.
As shown in FIG. 1 and FIG. 12, a semiconductor device having a trench type insulated gate structure in which a gate 14 is formed in a recess 29 is manufactured.

【0003】[0003]

【発明が解決しようとする課題】図11及び図12の従
来のトレンチ型絶縁ゲート構造の半導体装置において、
第1の導電型(n)をもつ半導体基板としてのn-導電型
のドリフト層2のキャリア濃度が大きい場合には、ゲー
ト電位をソース電位(図12ではエミッタ電位)以下に
してチャネルが形成されないようにしている。この場
合、ドレイン-ソース間(図12ではコレクタ−エミッ
タ間)に正極性の高電圧を印加すると、第1の導電型を
もつ半導体基板上の一部もしくは全面に設けられ第1の
導電型(n)と反対の第2の導電型(p)をもち、n-
電型のドリフト層2との間に接合を形成する半導体層と
してのp導電型のボディ層4とn-導電型のドリフト層2
の接合から空乏層が拡がる。ところが、ゲート14の直
下ではn-導電型のドリフト層2のキャリア濃度が大きく
導電率が高いので、その層の抵抗が小さくなる。その結
果n-導電型のドリフト層2での電圧分担が小さくなり、
凹部29の内表面に形成された絶縁物層9の底部に高電
圧が加わることになる。このため、トレンチ型絶縁ゲー
ト下部における絶縁物層9内の底部電界強度が高くな
り、耐圧はこの絶縁物層9の絶縁破壊により制限され、
装置の高耐圧化が困難であった。また、絶縁物層9内の
電界強度が高くなると絶縁物層9の劣化につながるた
め、高信頼度を得ることが困難であった。
SUMMARY OF THE INVENTION In the conventional semiconductor device having a trench-type insulated gate structure shown in FIGS.
When the carrier concentration of the n conductivity type drift layer 2 as the semiconductor substrate having the first conductivity type (n) is high, the gate potential is set to be lower than the source potential (the emitter potential in FIG. 12) and no channel is formed. Like that. In this case, when a positive high voltage is applied between the drain and the source (between the collector and the emitter in FIG. 12), the first conductive type is provided on a part or the whole surface of the semiconductor substrate having the first conductive type ( a p-type body layer 4 serving as a semiconductor layer having a second conductivity type (p) opposite to n) and forming a junction with the n conductivity type drift layer 2, and an n conductivity type drift Layer 2
The depletion layer expands from the junction. However, just below the gate 14, the carrier concentration of the n conductivity type drift layer 2 is high and the conductivity is high, so that the resistance of the layer is small. As a result, the voltage sharing in the n - conductivity type drift layer 2 is reduced,
A high voltage is applied to the bottom of the insulator layer 9 formed on the inner surface of the recess 29. For this reason, the electric field strength at the bottom of the insulator layer 9 below the trench-type insulated gate is increased, and the breakdown voltage is limited by the dielectric breakdown of the insulator layer 9.
It was difficult to increase the breakdown voltage of the device. Further, if the electric field strength in the insulator layer 9 is increased, the insulator layer 9 is deteriorated, so that it has been difficult to obtain high reliability.

【0004】[0004]

【課題を解決するための手段】本発明は、トレンチ型絶
縁ゲート層の下部の電界強度を緩和し、高耐圧及び高信
頼度の絶縁ゲート半導体装置を提供することを目的とし
ている。本発明では、上記課題を解決するために、トレ
ンチ型絶縁ゲート半導体装置のトレンチ型絶縁ゲートの
下部に、半導体基板内に形成された第2の導電型の第1
の半導体領域すなわち電界緩和のための半導体領域を設
けた。これにより、ドレイン−ソース間(あるいはコレ
クターエミッタ間)に正極性の電圧を印加した場合、た
とえば図1〜図10でドリフト層が第1の導電型である
と、第2の導電型のボディ層と第1の導電型のドリフト
層に空乏層が拡がる。一方、トレンチ型絶縁ゲート電極
の下部では、電界緩和のための半導体領域と第1の導電
型ドリフト層との接合から、ドレイン−ソース間(ある
いはコレクターエミッタ間)電圧に応じて空乏層が拡が
り、印加電圧の大部分が上記電界緩和半導体領域と第1
の導電型のドリフト層により分担されるようになる。こ
の結果、ゲートの絶縁物層底部の電圧分担が小さくなり
その絶縁物層の電界強度が緩和され、半導体装置の高耐
圧化あるいは高信頼化が達成できる。本発明で用いるト
レンチの語は溝以外に各種の形の孔、凹所を包含する概
念である。
SUMMARY OF THE INVENTION An object of the present invention is to provide an insulated gate semiconductor device having a high breakdown voltage and a high reliability by relaxing the electric field intensity below a trench type insulated gate layer. According to the present invention, in order to solve the above-mentioned problems, a first conductive type first semiconductor formed in a semiconductor substrate is provided below a trench type insulated gate of a trench type insulated gate semiconductor device.
, Ie, a semiconductor region for electric field relaxation. Thus, when a positive voltage is applied between the drain and the source (or between the collector and the emitter), for example, if the drift layer is of the first conductivity type in FIGS. As a result, the depletion layer spreads to the first conductivity type drift layer. On the other hand, under the trench-type insulated gate electrode, a depletion layer expands from a junction between the semiconductor region for electric field relaxation and the first conductivity type drift layer in accordance with a drain-source (or collector-emitter) voltage, Most of the applied voltage is equal to the electric field relaxation semiconductor region and the first electric field.
Of the conductive type. As a result, the voltage distribution at the bottom of the insulator layer of the gate is reduced, the electric field strength of the insulator layer is reduced, and a higher breakdown voltage or higher reliability of the semiconductor device can be achieved. The term "trench" used in the present invention is a concept that includes various types of holes and recesses in addition to grooves.

【0005】本発明の他のものでは、トレンチ型絶縁ゲ
ートの底部の絶縁物層の厚さを側面の絶縁物層の厚さよ
り大幅に厚くしている。これにより、高耐圧化あるいは
高信頼性が達成できる。また、この場合、前記電界緩和
のための半導体領域を設ければ、さらに高い耐圧あるい
は高信頼性が達成される。
In another embodiment of the present invention, the thickness of the insulating layer at the bottom of the trench-type insulated gate is much larger than the thickness of the insulating layer on the side. Thereby, high breakdown voltage or high reliability can be achieved. In this case, if a semiconductor region for relaxing the electric field is provided, higher withstand voltage or higher reliability can be achieved.

【0006】[0006]

【発明の実施の形態】本発明の絶縁ゲート半導体装置は
以下の実施形態をもつものである。すなわち第1の導電
型をもつ半導体基板上に、第1の導電型と反対の第2の
導電型をもち、前記半導体基板との間に接合を形成する
第2の導電型の半導体層を設け、さらに前記半導体層を
貫通して前記半導体基板の一部までうがった凹部を設け
る。前記凹部の底部において前記半導体基板内に第2の
導電型の第1の半導体領域を形成している。さらに前記
凹部内表面に絶縁層を形成し、その絶縁層によって前記
半導体基板及び前記第2の導電型の半導体層から絶縁し
たゲートの少なくとも一部を前記凹部内に設ける。さら
に前記半導体層の中で前記絶縁層に囲まれた前記ゲート
の周囲部の領域において、前記ゲートの周囲部の前記第
2の導電型の半導体層の表面から所定の深さまで第1の
導電型の第2の半導体領域を形成する。さらに前記第2
の導電型の半導体層及び前記第2の半導体領域の上に第
1の電極をこれらと導電的に設け、さらに前記半導体基
板の他の部分に第2の電極を設けている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An insulated gate semiconductor device according to the present invention has the following embodiments. That is, a semiconductor layer of a second conductivity type having a second conductivity type opposite to the first conductivity type and forming a junction with the semiconductor substrate is provided on a semiconductor substrate having a first conductivity type. Further, a recess penetrating the semiconductor layer to a part of the semiconductor substrate is provided. A first semiconductor region of a second conductivity type is formed in the semiconductor substrate at the bottom of the recess. Further, an insulating layer is formed on the inner surface of the recess, and at least a part of a gate insulated from the semiconductor substrate and the semiconductor layer of the second conductivity type by the insulating layer is provided in the recess. Further, in a region around the gate surrounded by the insulating layer in the semiconductor layer, the first conductivity type is extended to a predetermined depth from a surface of the second conductivity type semiconductor layer around the gate. Is formed. Further, the second
A first electrode is conductively provided on the conductive semiconductor layer and the second semiconductor region, and a second electrode is provided on another portion of the semiconductor substrate.

【0007】また、前記半導体基板は、より高い導電率
をもつ半導体層の上に同じ導電型でそれより低い導電率
の導電体層を設けている。さらに、前記第2の半導体領
域は前記半導体基板のうち前記第2の導電型の半導体層
と接合を形成している部分よりも導電率が高くなされて
いる。さらに、前記基板の前記接合をもつ面とは反対側
の面に第2の導電型の層を設けている。さらに、半導体
基板内に第3の導電型の第2の半導体領域を前記凹部か
ら隔離して設けている。さらに、前記基板の前記接合を
もつ面とは反対側の面に第2の導電型の層を設け、かつ
半導体基板内に第3の導電型の第2の半導体領域を前記
凹部から隔離して設けている。さらに、第2の電極を半
導体基板の上であって前記第1の電極から所定の距離を
隔てた位置に設けている。さらに、半導体基板内に形成
される第2の導電型の第1の半導体領域を、前記凹部の
底部及び底部につながる側部に設けている。
In the semiconductor substrate, a conductor layer of the same conductivity type and a lower conductivity is provided on a semiconductor layer having a higher conductivity. Further, the second semiconductor region has a higher conductivity than a portion of the semiconductor substrate that forms a junction with the second conductivity type semiconductor layer. Further, a second conductivity type layer is provided on a surface of the substrate opposite to the surface having the junction. Further, a second semiconductor region of a third conductivity type is provided in the semiconductor substrate so as to be isolated from the recess. Further, a layer of the second conductivity type is provided on the surface of the substrate opposite to the surface having the junction, and the second semiconductor region of the third conductivity type is separated from the recess in the semiconductor substrate. Provided. Further, a second electrode is provided on the semiconductor substrate at a position separated from the first electrode by a predetermined distance. Further, a first semiconductor region of the second conductivity type formed in the semiconductor substrate is provided on a bottom portion of the concave portion and a side portion connected to the bottom portion.

【0008】本発明の他の絶縁ゲート半導体装置は以下
の実施形態をもつものである。すなわち第1の導電型を
もつ半導体基板上に、第1の導電型と反対の第2の導電
型をもち、前記半導体基板との間に接合を形成する第2
の導電型の半導体層を設け、さらに前記半導体層を貫通
して前記半導体基板の一部までうがった凹部を設ける。
前記凹部内表面に底部の厚さが側面の厚さより厚い絶縁
層を形成し、その絶縁層によって前記半導体基板及び前
記第2の導電型の半導体層から絶縁したゲートの少なく
とも一部を前記凹部内に設ける。さらに前記半導体層の
中で前記絶縁層に囲まれた前記ゲートの周囲部の領域に
おいて、前記ゲートの周囲部の前記第2の導電型の半導
体層の表面から所定の深さまで第1の導電型の第2の半
導体領域を形成する。さらに前記第2の導電型の半導体
層及び前記第2の半導体領域の上に第1の電極をこれら
と導電的に設け、さらに前記半導体基板の他の部分に第
2の電極を設けている。さらに、前記基板の前記接合を
もつ面とは反対側の面に第2の導電型の層を設けてい
る。さらに、前記凹部の内表面に形成した絶縁層は、前
記凹部の底部絶縁層の厚さが前記凹部の側面の厚さの約
5ないし約20倍である。さらに、前記凹部の底部に形
成した絶縁層の厚さは約0.5ないし約2ミクロンであ
る。本発明において、上記の約5、約20、約0.5、
約2などは2割程度の誤差範囲を含むものと解すべきで
ある。
[0008] Another insulated gate semiconductor device of the present invention has the following embodiments. That is, a second substrate having a second conductivity type opposite to the first conductivity type on a semiconductor substrate having the first conductivity type and forming a bond with the semiconductor substrate.
And a concave portion penetrating the semiconductor layer to a part of the semiconductor substrate is provided.
An insulating layer having a bottom portion thicker than a side surface thickness is formed on the inner surface of the recess, and at least a part of a gate insulated from the semiconductor substrate and the second conductive type semiconductor layer by the insulating layer is formed in the recess. To be provided. Further, in a region around the gate surrounded by the insulating layer in the semiconductor layer, the first conductivity type is extended to a predetermined depth from a surface of the second conductivity type semiconductor layer around the gate. Is formed. Further, a first electrode is provided on the semiconductor layer of the second conductivity type and the second semiconductor region in a conductive manner, and a second electrode is provided on another portion of the semiconductor substrate. Further, a second conductivity type layer is provided on a surface of the substrate opposite to the surface having the junction. Further, in the insulating layer formed on the inner surface of the recess, the thickness of the bottom insulating layer of the recess is about 5 to about 20 times the thickness of the side face of the recess. Further, the thickness of the insulating layer formed at the bottom of the recess is about 0.5 to about 2 microns. In the present invention, the above-mentioned about 5, about 20, about 0.5,
It should be understood that about 2 or the like includes an error range of about 20%.

【0009】[0009]

【実施例】図1ないし図10を参照して、本発明の実施
例を説明する。 <<実施例1>>図1は、本発明の実施例1である耐圧25
00V級nチャネルSiC(炭化珪素)MOSFETの単位セ
グメントの断面図である。この実施例では、セグメント
幅は5μm、奥行きは1mmである。その他の構造諸元
は以下のとおりである。n-導電型のドリフト層2はn+
電型のドレイン層3の上に設け、厚さは約20μmであ
る。n+導電型のドレイン層3は厚さ約300μm、p導
電型のボディ層4の厚さは4μm、n+導電型のソース領
域5およびp導電型の電界緩和半導体領域1の接合深さ
は各0.5μm、凹部すなわちトレンチ69の深さは6
μm、トレンチ幅は3μm、トレンチ69内に設けたS
iO2(酸化珪素)等の絶縁物層9の厚さはトレンチ6
9底部及びトレンチ69側面で0.1μmである。本実
施例では、トレンチ型絶縁ゲート電極14は紙面奥行方
面に長いストライプ状である。なおトレンチの平面形状
は、例えばこの実施例のように紙面奥行方向に長い長溝
状のものの他に、例えば直径3μmの円形孔状や正方形
のものなどでもよい。トレンチの配置は、例えば5μm
ピッチで等間隔に配列する。なお円形のトレンチの場合
は縦横に格子状に又は千鳥状に配列すればよい。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. << Embodiment 1 >> FIG. 1 shows a first embodiment of the present invention.
It is sectional drawing of the unit segment of 00V class n channel SiC (silicon carbide) MOSFET. In this embodiment, the segment width is 5 μm and the depth is 1 mm. Other structural specifications are as follows. The n conductivity type drift layer 2 is provided on the n + conductivity type drain layer 3 and has a thickness of about 20 μm. The drain layer 3 of the n + conductivity type has a thickness of about 300 μm, the thickness of the body layer 4 of the p conductivity type is 4 μm, and the junction depth of the source region 5 of the n + conductivity type and the electric field relaxation semiconductor region 1 of the p conductivity type is 0.5 μm each, the depth of the recess or trench 69 is 6
μm, the trench width is 3 μm, and the S
The thickness of the insulator layer 9 such as iO 2 (silicon oxide) is
9 is 0.1 μm at the bottom and the side of the trench 69. In this embodiment, the trench-type insulated gate electrode 14 has a long stripe shape in the depth direction of the drawing. The planar shape of the trench may be, for example, a circular groove having a diameter of 3 μm or a square in addition to a long groove having a long length in the depth direction of the paper as in this embodiment. The arrangement of the trench is, for example, 5 μm
They are arranged at equal pitches. In the case of circular trenches, they may be arranged vertically and horizontally in a lattice or in a staggered manner.

【0010】本実施例の製作方法の具体例は、次のとお
りである。最初にドレイン領域として機能する1018
ら1020atm/cm3濃度の、たとえば、1019at
m/cm3の濃度のn+形SiC(炭化珪素)基板3を用
意する。この基板3の一表面上に1015から1016at
m/cm3濃度、例えば約5×1015atm/cm3濃度
のSiCのn-導電型のドリフト層2を気相成長法等によ
り形成する。次にそのドリフト層2の上に1016atm
/cm3程度のSiCのp導電型のボディ層4を気相成
長法等により形成する。そして、ソース層として、選択
的に1018atm/cm3程度の濃度のn+導電型の領域
5を窒素のイオン打ち込み等により形成する。(窒素に
かえてりん等でも可能。)
A specific example of the manufacturing method according to the present embodiment is as follows. First, a concentration of 10 18 to 10 20 atm / cm 3 , for example, 10 19 at, which functions as a drain region
An n + -type SiC (silicon carbide) substrate 3 having a concentration of m / cm 3 is prepared. 10 15 to 10 16 at on one surface of the substrate 3
An n - conductivity type drift layer 2 of SiC having a concentration of m / cm 3 , for example, about 5 × 10 15 atm / cm 3 is formed by a vapor phase growth method or the like. Next, 10 16 atm is applied on the drift layer 2.
A p-type body layer 4 of SiC of about / cm 3 is formed by a vapor phase growth method or the like. Then, as the source layer, an n + conductivity type region 5 having a concentration of about 10 18 atm / cm 3 is selectively formed by ion implantation of nitrogen or the like. (It is also possible to use phosphorus instead of nitrogen.)

【0011】次に、図1のように基板3、ドリフト層2
及びボディ層4からなる広義の基板を異方性エッチング
して、p導電型のボディ層4を貫通し底部がn-導電型の
ドリフト層2に達するトレンチ(溝)69を形成する。
その底に深さ0.5μm、1017atm/cm3程度のp
導電型の電界緩和半導体領域1をホウ素(又はアルミニ
ウム等でも可)のイオン打ち込み等により形成する。続
いて、トレンチ69の内表面にSiO2のゲート絶縁膜
9を形成した後、トレンチ69内にりんを高濃度に含ん
だゲート領域としてのポリシリコンを堆積しトレンチ6
9を埋め込んでゲート領域14を作る。トレンチ69の
寸法の1例は、深さ6μm、幅3μm、長さ1mmであ
る。ここに示した寸法は1例であって、必要に応じて他
の寸法も用いる。トレンチ69内のポリシリコンを残
し、それ以外の場所(基板表面等)の残りのポリシリコ
ンを除去することにより、トレンチ型絶縁ゲート電極1
4が形成される。最後に、アルミニウム(他にニッケル
等も用いうる)で表面にソース電極11、裏面にドレイ
ン電極10を形成し、絶縁ゲート半導体装置(MOSFET)を
完成する。このMOSFETのオン抵抗は、約30mΩ・cm
2であった。
Next, as shown in FIG. 1, the substrate 3, the drift layer 2
Then, a broadly defined substrate composed of the body layer 4 is anisotropically etched to form a trench (groove) 69 that penetrates the body layer 4 of the p-conductivity type and the bottom reaches the drift layer 2 of the n conductivity type.
0.5 μm deep and 10 17 atm / cm 3
The conductive type electric field relaxation semiconductor region 1 is formed by ion implantation of boron (or aluminum or the like). Subsequently, after a gate insulating film 9 of SiO 2 is formed on the inner surface of the trench 69, polysilicon as a gate region containing a high concentration of phosphorus is deposited in the trench 69 to form a trench 6.
9 is buried to form a gate region 14. An example of the dimensions of the trench 69 is 6 μm in depth, 3 μm in width, and 1 mm in length. The dimensions shown here are examples, and other dimensions may be used as needed. By leaving the polysilicon in the trench 69 and removing the remaining polysilicon in other places (such as the substrate surface), the trench-type insulated gate electrode 1 is removed.
4 are formed. Lastly, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the back surface using aluminum (in addition, nickel or the like may be used), thereby completing an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET is about 30 mΩ · cm
Was 2 .

【0012】本実施例はnチャネルSiC MOSFETであ
り、この装置ではドレイン電極10の電位がソース電極
11の電位より高く、かつゲート電極であるトレンチ型
絶縁ゲート電極14の電位がソース電極11の電位より
も高くなるようにゲート電圧を印加する。このゲート電
圧がしきい値電圧を超えた場合、トレンチ型絶縁ゲート
電極14の側面のp導電型のボディ層4の表面にn導電
型のチャネルが形成される。それにより電子がn+導電型
のソース領域5からそのチャネルを介してn-導電型のド
リフト層2、さらにn+導電型のドレイン層3に流れ込み
半導体装置がオンとなる。また、ゲート電極であるトレ
ンチ型絶縁ゲート電極14の電位がソース電極11の電
位以下になるようにゲート電圧を印加し、かつドレイン
電極10の電位がソース電極11の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡が
る。この空乏層により電界強度を緩和し、印加電圧に耐
える耐電圧性が生じる。
This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11 and the potential of the trench-type insulated gate electrode 14 as the gate electrode is the potential of the source electrode 11. The gate voltage is applied so as to be higher. When the gate voltage exceeds the threshold voltage, an n-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14. As a result, electrons flow from the source region 5 of the n + conductivity type to the drift layer 2 of the n conductivity type via the channel thereof and further to the drain layer 3 of the n + conductivity type, and the semiconductor device is turned on. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 becomes higher than the potential of the source electrode 11. When applied, the drift layer 2 of n - conductivity type and p
A depletion layer extends on both sides of the junction 24 of the conductive type body layer 4. The depletion layer alleviates the electric field strength and produces a withstand voltage that can withstand the applied voltage.

【0013】本実施例では、上記の接合24の両側に拡
がる空乏層以外に、トレンチ型絶縁ゲート電極14の下
部のp導電型の電界緩和半導体領域1とn-導電型のドリ
フト層2との接合からもドレイン−ソース間電圧に応じ
てそれぞれの層に空乏層が拡がり、印加電圧に耐える耐
電圧性が生じる。したがって、トレンチ型絶縁ゲート電
極14の下部では、印加電圧の大部分が上記電界緩和半
導体領域1とn-導電型のドリフト層2により分担され
る。このためにゲート底部における絶縁物層9の電圧分
担が小さくなり、その絶縁物層9の電界強度が緩和され
る。これにより、ゲート絶縁物層9の電界強度が緩和さ
れ耐電圧の向上を図ることができるとともに、ゲート絶
縁物層9の信頼性が向上する。
[0013] In this embodiment, in addition to the depletion layer extending on both sides of the bonding 24, the trench type insulated at the bottom of the p conductivity type of the gate electrode 14 field relaxation semiconductor region 1 and the n - conductivity type drift layer 2 of A depletion layer extends from the junction to each layer in accordance with the drain-source voltage, and a withstand voltage that withstands the applied voltage is generated. Therefore, below the trench-type insulated gate electrode 14, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2. For this reason, the voltage distribution of the insulator layer 9 at the bottom of the gate is reduced, and the electric field strength of the insulator layer 9 is reduced. Thereby, the electric field strength of the gate insulating layer 9 is reduced, the withstand voltage can be improved, and the reliability of the gate insulating layer 9 is improved.

【0014】計算による予測では、図11のような従来
のトレンチ型絶縁ゲートMOSFETの場合には、トレンチ型
絶縁ゲート電極14とソース電極11を短絡し、ソース
電極11を0Vとしドレイン電極10に+2000Vを
印加した場合、トレンチ型絶縁ゲート底部のSi02
縁物層9の電界強度は、Si02の破壊電界強度である
6〜10MV/cmに近い値となり、半導体装置の耐圧はS
iO2絶縁膜の耐圧で決まり2000Vであった。これ
に対して、本実施例のMOSFETのようにトレンチ型絶縁ゲ
ート14の下部に電界緩和半導体領域1を形成したもの
では、トレンチ型絶縁ゲート底部側端部のSi02絶縁
物層9の電界強度は、従来のものに比べて15〜30%
減少する。その結果、半導体装置の耐圧は2300Vか
ら2600Vに向上した。従来のようにトレンチ型絶縁
ゲート14の下部に電界緩和半導体領域1を形成しなか
ったものでは、ドレイン電極10に印加した電圧はn-
電型のドリフト層2とトレンチ型絶縁ゲート14の底部
の絶縁物層9により分担され、絶縁物層9の電圧分担が
大きくなり、それに応じて電界強度も大きくなり、絶縁
物層の耐圧で半導体装置の耐圧も決まっていた。しか
し、本実施例のようにトレンチ型絶縁ゲート14の下部
に電界緩和半導体領域1を形成すると、電界緩和半導体
領域1、n-導電型のドリフト層2およびトレンチ型絶縁
ゲート底部絶縁物層9により電圧が分担される。特に電
界緩和半導体領域1とn-導電型のドリフト層2の接合近
傍でドレイン−ソース間印加電圧の大部分を分担する。
それにより、トレンチ型絶縁ゲート14の底部の絶縁物
層9の電圧分担が小さくなり、それに応じてその層9の
電界強度も小さくなる。耐圧が高い素子の場合には、ト
レンチ型絶縁ゲート14の底部の絶縁物層9の電界強度
が特に高くなるので、トレンチ型絶縁ゲート14の下部
に電界緩和半導体領域1を形成した効果は顕著になる。
According to calculations, in the case of a conventional trench-type insulated gate MOSFET as shown in FIG. 11, the trench-type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0 V, and the drain electrode 10 is set to +2000 V. Is applied, the electric field strength of the SiO 2 insulator layer 9 at the bottom of the trench-type insulated gate becomes a value close to the breakdown electric field strength of SiO 2 of 6 to 10 MV / cm, and the breakdown voltage of the semiconductor device is S
It was determined by the withstand voltage of the iO 2 insulating film and was 2000 V. On the other hand, in the case where the electric field relaxation semiconductor region 1 is formed under the trench type insulated gate 14 like the MOSFET of the present embodiment, the electric field strength of the SiO 2 insulator layer 9 at the bottom end of the trench type insulated gate is reduced. Is 15-30% of the conventional one
Decrease. As a result, the breakdown voltage of the semiconductor device was improved from 2300 V to 2600 V. In the case where the electric field relaxation semiconductor region 1 is not formed below the trench-type insulated gate 14 as in the related art, the voltage applied to the drain electrode 10 is equal to the n conductivity type drift layer 2 and the bottom of the trench-type insulated gate 14. The voltage is shared by the insulating layer 9, the voltage sharing of the insulating layer 9 is increased, the electric field strength is correspondingly increased, and the withstand voltage of the insulating layer determines the withstand voltage of the semiconductor device. However, when the electric field relaxation semiconductor region 1 is formed below the trench type insulated gate 14 as in the present embodiment, the electric field relaxation semiconductor region 1, the n conductivity type drift layer 2 and the trench type insulated gate bottom insulator layer 9 form Voltage sharing. In particular, most of the drain-source applied voltage is shared in the vicinity of the junction between the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2.
Thereby, the voltage distribution of the insulator layer 9 at the bottom of the trench-type insulated gate 14 is reduced, and the electric field strength of the layer 9 is correspondingly reduced. In the case of an element having a high withstand voltage, the electric field intensity of the insulator layer 9 at the bottom of the trench-type insulated gate 14 becomes particularly high, so that the effect of forming the electric-field relaxation semiconductor region 1 under the trench-type insulated gate 14 is remarkable. Become.

【0015】<<実施例2>>図2は、本発明の実施例2の
nチャネルSiC IGBTのセグメントの断面図であ
る。その構造は実施例1のn+導電型のドレイン層3の代
わりにp導電型のコレクタ層6を形成したものである。
実施例2の構造諸元および製作方法は、実施例1のSi
C−n+導電型基板の代わりにSiC−p+導電型基板を用
いる点が異なるだけであり、後の製作工程は実施例1の
場合と同様である。なお、p+導電型基板の不純物濃度
は、1018〜1019atm/cm3である。
Embodiment 2 FIG. 2 is a sectional view of a segment of an n-channel SiC IGBT according to Embodiment 2 of the present invention. The structure is such that a p-type collector layer 6 is formed instead of the n + -type drain layer 3 of the first embodiment.
The structural specifications and manufacturing method of the second embodiment are the same as those of the first embodiment.
The only difference is that a SiC-p + conductivity type substrate is used instead of the Cn + conductivity type substrate, and the subsequent manufacturing process is the same as that of the first embodiment. The impurity concentration of the p + conductivity type substrate is 10 18 to 10 19 atm / cm 3 .

【0016】本実施例のnチャネルIGBTの動作にお
いて、先ずコレクタ電極12の電位がエミッタ電極13
の電位より高く、かつゲート電極であるトレンチ型絶縁
ゲート電極14の電位がエミッタ電極13の電位よりも
高くなるようにゲート電圧を印加する。このゲート電圧
がしきい値電圧を超えると、トレンチ型絶縁ゲート電極
14の側面のp導電型のボディ層4の表面にn導電型の
チャネルが形成され、n+導電型のエミッタ領域7からそ
のチャネルを介して電子がn-導電型のドリフト層2に流
れ込む。これによってp導電型のコレクタ層6からはn-
導電型のドリフト層2に正孔が注入されオンとなる。こ
の時、n-導電型のドリフト層2で電導率変調が起こるた
め、MOSFETでは非常に高かったオン抵抗が、IGBTで
は大幅に低くなる。本実施例の場合、200A/cm2
の電流でオン電圧は1.5Vであり、オン抵抗は7.5m
Ω・cm2であった。また、ゲート電極であるトレンチ
型絶縁ゲート電極14の電位がエミッタ電極13の電位
以下になるようにゲート電圧を印加し、かつコレクタ電
極12の電位がエミッタ電極13の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡がっ
て電界強度を緩和し、印加電圧に耐える耐電圧性が生じ
る。本実施例では、この空乏層で電圧を分担する以外
に、トレンチ型絶縁ゲート電極14の下部でも、コレク
タ−エミッタ間電圧に応じて電界緩和半導体領域1とn-
導電型のドリフト層2との接合からそれぞれの層に空乏
層が拡がって耐電圧性が生じる。したがってトレンチ型
絶縁ゲート電極14の下部では、印加電圧の大部分が上
記電界緩和半導体領域1とn-導電型のドリフト層2によ
り分担される。それ故、ゲート絶縁物層9の電圧分担が
小さくなり絶縁物層9の電界強度が緩和される。これに
より、ゲート絶縁物層9の信頼性が向上する。また、ゲ
ート絶縁物層9の電界強度が緩和され耐圧の向上を図る
ことが可能である。本実施例の場合においても、前述の
MOSFETの場合と同様にトレンチ型絶縁ゲート14の底部
側面部の絶縁物層9の電界強度は、電界緩和半導体領域
1を形成しない従来の構造のIGBTに比べ、15〜3
0%程度緩和される。したがって、本実施例において
も、ゲート絶縁物層9の電界強度が緩和されたことによ
り耐圧の向上を図れるとともにゲート絶縁物層9の信頼
性が向上する。例えば実施例によれば耐圧が2300V
から2600Vに改善できた。
In the operation of the n-channel IGBT of this embodiment, first, the potential of the collector electrode 12
And a gate voltage is applied such that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is higher than the potential of the emitter electrode 13. When the gate voltage exceeds the threshold voltage, an n-conductivity-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14, and n + -conductivity-type emitter region 7 is formed. Electrons flow into the n conductivity type drift layer 2 through the channel. As a result, from the p-conductivity type collector layer 6, n
Holes are injected into the conductive type drift layer 2 to be turned on. At this time, since conductivity modulation occurs in the n conductivity type drift layer 2, the ON resistance, which was very high in the MOSFET, is greatly reduced in the IGBT. In the case of the present embodiment, 200 A / cm 2
The ON voltage is 1.5 V and the ON resistance is 7.5 m
Ω · cm 2 . Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 becomes higher than the potential of the emitter electrode 13. When applied, the drift layer 2 of n - conductivity type and p
The depletion layer spreads on both sides of the junction 24 of the conductive type body layer 4 to reduce the electric field intensity, and a withstand voltage to withstand the applied voltage is generated. In the present embodiment, in addition to sharing the voltage with the depletion layer, the electric field relaxation semiconductor region 1 and n are also formed below the trench-type insulated gate electrode 14 according to the collector-emitter voltage.
From the junction with the conductive type drift layer 2, a depletion layer spreads in each layer, and a withstand voltage is generated. Therefore, below the trench-type insulated gate electrode 14, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2. Therefore, the voltage distribution of the gate insulator layer 9 is reduced, and the electric field strength of the insulator layer 9 is reduced. Thereby, the reliability of the gate insulator layer 9 is improved. Further, the electric field strength of the gate insulator layer 9 is reduced, and the withstand voltage can be improved. Also in the case of this embodiment, the aforementioned
As in the case of the MOSFET, the electric field strength of the insulator layer 9 on the bottom side surface of the trench-type insulated gate 14 is 15 to 3 times that of the IGBT having the conventional structure in which the electric field relaxation semiconductor region 1 is not formed.
It is relaxed by about 0%. Therefore, also in this embodiment, since the electric field strength of the gate insulating layer 9 is reduced, the withstand voltage can be improved, and the reliability of the gate insulating layer 9 can be improved. For example, according to the embodiment, the withstand voltage is 2300 V
To 2600V.

【0017】<<実施例3>>図3は、本発明の実施例3で
ある耐圧2500V級nチャネルSiC(炭化珪素)MO
SFETの単位セグメントの断面図である。この実施例で
は、セグメント幅は5μm、奥行きは1mmである。そ
の他の構造諸元は以下のとおりである。n-導電型のドリ
フト層2はn+導電型のドレイン層3の上に設け、厚さは
約20μmである。n+導電型のドレイン層3は厚さ約3
00μm、p導電型のボディ層4の厚さは4μm、n+
電型のソース領域5およびp導電型の電界緩和半導体領
域1の接合深さは各0.5μm、凹部すなわちトレンチ
69の深さは6μm、トレンチ幅は3μm、トレンチ6
9内に設けたSiO2(酸化珪素)等の絶縁物層9の厚
さはトレンチ69底部で0.5μmトレンチ69側面で
0.1μmである。本実施例では、トレンチ型絶縁ゲー
ト電極14は紙面奥行方面に長いストライプ状である。
なおトレンチの平面形状は、例えばこの実施例のように
紙面奥行方向に長い長溝状のものの他に、例えば直径3
μmの円形孔状や正方形のものなどでもよい。トレンチ
の配置は、例えば5μmピッチで等間隔に配列する。な
お円形のトレンチの場合は縦横に格子状に又は千鳥状に
配列すればよい。
<< Embodiment 3 >> FIG. 3 shows an n-channel SiC (silicon carbide) MO having a withstand voltage of 2500 V class according to Embodiment 3 of the present invention.
FIG. 3 is a sectional view of a unit segment of the SFET. In this embodiment, the segment width is 5 μm and the depth is 1 mm. Other structural specifications are as follows. The n conductivity type drift layer 2 is provided on the n + conductivity type drain layer 3 and has a thickness of about 20 μm. The n + conductivity type drain layer 3 has a thickness of about 3
00 μm, the thickness of the body layer 4 of the p-conductivity type is 4 μm, the junction depth of the source region 5 of the n + conductivity type and the electric field relaxation semiconductor region 1 of the p-conductivity type are each 0.5 μm, and the depth of the recess or trench 69. 6 μm, trench width 3 μm, trench 6
The thickness of the insulator layer 9 such as SiO 2 (silicon oxide) provided in the trench 9 is 0.5 μm at the bottom of the trench 69 and 0.1 μm at the side surface of the trench 69. In this embodiment, the trench-type insulated gate electrode 14 has a long stripe shape in the depth direction of the drawing.
The planar shape of the trench may be, for example, a long groove extending in the depth direction of the paper as in this embodiment, or a diameter of 3 for example.
It may have a circular hole shape of μm or a square shape. The trenches are arranged at equal intervals, for example, at a pitch of 5 μm. In the case of circular trenches, they may be arranged vertically and horizontally in a lattice or in a staggered manner.

【0018】本実施例の製作方法の具体例は、次のとお
りである。最初にドレイン領域として機能する1018
ら1020atm/cm3濃度の、たとえば、1019at
m/cm3の濃度のn+形SiC(炭化珪素)基板3を用
意する。この基板3の一表面上に1015から1016at
m/cm3濃度、例えば約5×1015atm/cm3濃度
のSiCのn-導電型のドリフト層2を気相成長法等によ
り形成する。次にそのドリフト層2の上に1016atm
/cm3程度のSiCのp導電型のボディ層4を気相成
長法等により形成する。そして、ソース層として、選択
的に1018atm/cm3程度の濃度のn+導電型の領域
5を窒素のイオン打ち込み等により形成する。(窒素に
かえてりん等でも可能。)
A specific example of the manufacturing method according to the present embodiment is as follows. First, a concentration of 10 18 to 10 20 atm / cm 3 , for example, 10 19 at, which functions as a drain region
An n + -type SiC (silicon carbide) substrate 3 having a concentration of m / cm 3 is prepared. 10 15 to 10 16 at on one surface of the substrate 3
An n - conductivity type drift layer 2 of SiC having a concentration of m / cm 3 , for example, about 5 × 10 15 atm / cm 3 is formed by a vapor phase growth method or the like. Next, 10 16 atm is applied on the drift layer 2.
A p-type body layer 4 of SiC of about / cm 3 is formed by a vapor phase growth method or the like. Then, as the source layer, an n + conductivity type region 5 having a concentration of about 10 18 atm / cm 3 is selectively formed by ion implantation of nitrogen or the like. (It is also possible to use phosphorus instead of nitrogen.)

【0019】次に、図3のように基板3、ドリフト層2
及びボディ層4からなる広義の基板を異方性エッチング
して、p導電型のボディ層4を貫通し底部がn-導電型の
ドリフト層2に達するトレンチ(溝)69を形成する。
その底に深さ0.5μm、1017atm/cm3程度のp
導電型の電界緩和半導体領域1をホウ素(又はアルミニ
ウム等でも可)のイオン打ち込み等により形成する。続
いて、トレンチ69の内表面にSiO2のゲート絶縁膜
9を形成した後、トレンチ69内にりんを高濃度に含ん
だゲート領域としてのポリシリコンを堆積しトレンチ6
9を埋め込んでゲート領域14を作る。トレンチ69の
寸法の1例は、深さ6μm、幅3μm、長さ1mmであ
る。ここに示した寸法は1例であって、必要に応じて他
の寸法も用いる。トレンチ69内のポリシリコンを残
し、それ以外の場所(基板表面等)の残りのポリシリコ
ンを除去することにより、トレンチ型絶縁ゲート電極1
4が形成される。最後に、アルミニウム(他にニッケル
等も用いうる)で表面にソース電極11、裏面にドレイ
ン電極10を形成し、絶縁ゲート半導体装置(MOSFET)を
完成する。このMOSFETのオン抵抗は、約30mΩ・cm
2であった。
Next, as shown in FIG. 3, the substrate 3, the drift layer 2
Then, a broadly defined substrate composed of the body layer 4 is anisotropically etched to form a trench (groove) 69 that penetrates the body layer 4 of the p-conductivity type and the bottom reaches the drift layer 2 of the n conductivity type.
0.5 μm deep and 10 17 atm / cm 3
The conductive type electric field relaxation semiconductor region 1 is formed by ion implantation of boron (or aluminum or the like). Subsequently, after a gate insulating film 9 of SiO 2 is formed on the inner surface of the trench 69, polysilicon as a gate region containing a high concentration of phosphorus is deposited in the trench 69 to form a trench 6.
9 is buried to form a gate region 14. An example of the dimensions of the trench 69 is 6 μm in depth, 3 μm in width, and 1 mm in length. The dimensions shown here are examples, and other dimensions may be used as needed. By leaving the polysilicon in the trench 69 and removing the remaining polysilicon in other places (such as the substrate surface), the trench-type insulated gate electrode 1 is removed.
4 are formed. Lastly, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the back surface using aluminum (in addition, nickel or the like may be used), thereby completing an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET is about 30 mΩ · cm
Was 2 .

【0020】本実施例はnチャネルSiC MOSFETであ
り、この装置ではドレイン電極10の電位がソース電極
11の電位より高く、かつゲート電極であるトレンチ型
絶縁ゲート電極14の電位がソース電極11の電位より
も高くなるようにゲート電圧を印加する。このゲート電
圧がしきい値電圧を超えた場合、トレンチ型絶縁ゲート
電極14の側面のp導電型のボディ層4の表面にn導電
型のチャネルが形成される。それにより電子がn+導電型
のソース領域5からそのチャネルを介してn-導電型のド
リフト層2、さらにn+導電型のドレイン層3に流れ込み
半導体装置がオンとなる。また、ゲート電極であるトレ
ンチ型絶縁ゲート電極14の電位がソース電極11の電
位以下になるようにゲート電圧を印加し、かつドレイン
電極10の電位がソース電極11の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡が
る。この空乏層により電界強度を緩和し、印加電圧に耐
える耐電圧性が生じる。
This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11, and the potential of the trench-type insulated gate electrode 14 as the gate electrode is the potential of the source electrode 11. The gate voltage is applied so as to be higher. When the gate voltage exceeds the threshold voltage, an n-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14. As a result, electrons flow from the source region 5 of the n + conductivity type to the drift layer 2 of the n conductivity type via the channel thereof and further to the drain layer 3 of the n + conductivity type, and the semiconductor device is turned on. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 becomes higher than the potential of the source electrode 11. When applied, the drift layer 2 of n - conductivity type and p
A depletion layer extends on both sides of the junction 24 of the conductive type body layer 4. The depletion layer alleviates the electric field strength and produces a withstand voltage that can withstand the applied voltage.

【0021】本実施例では、上記の接合24の両側に拡
がる空乏層以外に、トレンチ型絶縁ゲート電極14の下
部のp導電型の電界緩和半導体領域1とn-導電型のドリ
フト層2との接合からもドレイン−ソース間電圧に応じ
てそれぞれの層に空乏層が拡がり、印加電圧に耐える耐
電圧性が生じる。したがって、トレンチ型絶縁ゲート電
極14の下部では、印加電圧の大部分が上記電界緩和半
導体領域1とn-導電型のドリフト層2により分担され
る。このためにゲート底部における絶縁物層9の電圧分
担が小さくなり、その絶縁物層9の電界強度が緩和され
る。これにより、ゲート絶縁物層9の電界強度が緩和さ
れ耐電圧の向上を図ることができるとともに、ゲート絶
縁物層9の信頼性が向上する。
[0021] In this embodiment, in addition to the depletion layer extending on both sides of the bonding 24, the trench type insulated at the bottom of the p conductivity type of the gate electrode 14 field relaxation semiconductor region 1 and the n - conductivity type drift layer 2 of A depletion layer extends from the junction to each layer in accordance with the drain-source voltage, and a withstand voltage that withstands the applied voltage is generated. Therefore, below the trench-type insulated gate electrode 14, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2. For this reason, the voltage distribution of the insulator layer 9 at the bottom of the gate is reduced, and the electric field strength of the insulator layer 9 is reduced. Thereby, the electric field strength of the gate insulating layer 9 is reduced, the withstand voltage can be improved, and the reliability of the gate insulating layer 9 is improved.

【0022】計算による予測では、図11のような従来
のトレンチ型絶縁ゲートMOSFETの場合には、トレンチ型
絶縁ゲート電極14とソース電極11を短絡し、ソース
電極11を0Vとしドレイン電極10に+2000Vを
印加した場合、トレンチ型絶縁ゲート底部のSi02
縁物層9の電界強度は、Si02の破壊電界強度である
6〜10MV/cmに近い値となった。これに対して、本実
施例のMOSFETのようにトレンチ型絶縁ゲート14の下部
に電界緩和半導体領域1を形成し絶縁物層9の底部の厚
みを側面の厚みより厚い0.5μmとした本実施例の場
合では、トレンチ型絶縁ゲート底部側端部のSi02
縁物層9の電界強度は、従来のものに比べて45〜65
%減少する。その結果、半導体装置の耐圧は2900V
から3250Vに向上した。従来のようにトレンチ型絶
縁ゲート14の下部に電界緩和半導体領域1を形成しな
かったものでは、ドレイン電極10に印加した電圧はn-
導電型のドリフト層2とトレンチ型絶縁ゲート14の底
部の絶縁物層9により分担され、絶縁物層9の電圧分担
が大きくなり、それに応じて電界強度も大きくなってい
た。しかし、本実施例のようにトレンチ型絶縁ゲート1
4の下部に電界緩和半導体領域1を形成すると、電界緩
和半導体領域1、n-導電型のドリフト層2およびトレン
チ型絶縁ゲート底部絶縁物層9により電圧が分担され
る。特に電界緩和半導体領域1とn-導電型のドリフト層
2の接合近傍でドレイン−ソース間印加電圧の大部分を
分担する。それにより、トレンチ型絶縁ゲート14の底
部の絶縁物層9の電圧分担が小さくなり、それに応じて
その層9の電界強度も小さくなる。耐圧が高い素子の場
合には、トレンチ型絶縁ゲート14の底部の絶縁物層9
の電界強度が特に高くなるので、トレンチ型絶縁ゲート
14の下部に電界緩和半導体領域1を形成した効果は顕
著になる。
According to calculations, in the case of the conventional trench-type insulated gate MOSFET as shown in FIG. 11, the trench-type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0 V, and the drain electrode 10 is set to +2000 V. Was applied, the electric field strength of the SiO 2 insulator layer 9 at the bottom of the trench-type insulated gate was close to 6 to 10 MV / cm, which is the breakdown electric field strength of SiO 2 . On the other hand, as in the MOSFET of the present embodiment, the electric field relaxation semiconductor region 1 is formed below the trench-type insulated gate 14, and the thickness of the bottom of the insulator layer 9 is set to 0.5 μm which is larger than the thickness of the side surface. In the case of the example, the electric field strength of the SiO 2 insulator layer 9 at the bottom end of the trench-type insulated gate is 45 to 65 compared with the conventional one.
%Decrease. As a result, the withstand voltage of the semiconductor device is 2900 V
To 3250V. In the case where the electric field relaxation semiconductor region 1 is not formed below the trench type insulated gate 14 as in the related art, the voltage applied to the drain electrode 10 is n
The conductive type drift layer 2 and the insulating layer 9 at the bottom of the trench type insulating gate 14 share the voltage, and the voltage sharing of the insulating layer 9 increases, and the electric field intensity increases accordingly. However, as in this embodiment, the trench type insulated gate 1
When the electric field relaxation semiconductor region 1 is formed below the semiconductor substrate 4, a voltage is shared by the electric field relaxation semiconductor region 1, the n conductivity type drift layer 2 and the trench type insulating gate bottom insulator layer 9. In particular, most of the drain-source applied voltage is shared in the vicinity of the junction between the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2. Thereby, the voltage distribution of the insulator layer 9 at the bottom of the trench-type insulated gate 14 is reduced, and the electric field strength of the layer 9 is correspondingly reduced. In the case of an element having a high withstand voltage, the insulator layer 9 at the bottom of the trench-type insulated gate 14 is used.
Is particularly high, the effect of forming the electric field relaxation semiconductor region 1 under the trench-type insulated gate 14 becomes remarkable.

【0023】<<実施例4>>図4は、本発明の実施例4の
nチャネルSiC IGBTのセグメントの断面図であ
る。その構造は実施例1のn+導電型のドレイン層3の代
わりにp導電型のコレクタ層6を形成したものである。
実施例2の構造諸元および製作方法は、実施例1のSi
C−n+導電型基板の代わりにSiC−p+導電型基板を用
いる点が異なるだけであり、後の製作工程は実施例1の
場合と同様である。なお、p+導電型基板の不純物濃度
は、1018〜1019atm/cm3である。
Fourth Embodiment FIG. 4 is a sectional view of a segment of an n-channel SiC IGBT according to a fourth embodiment of the present invention. The structure is such that a p-type collector layer 6 is formed instead of the n + -type drain layer 3 of the first embodiment.
The structural specifications and manufacturing method of the second embodiment are the same as those of the first embodiment.
The only difference is that a SiC-p + conductivity type substrate is used instead of the Cn + conductivity type substrate, and the subsequent manufacturing process is the same as that of the first embodiment. The impurity concentration of the p + conductivity type substrate is 10 18 to 10 19 atm / cm 3 .

【0024】本実施例のnチャネルIGBTの動作にお
いて、先ずコレクタ電極12の電位がエミッタ電極13
の電位より高く、かつゲート電極であるトレンチ型絶縁
ゲート電極14の電位がエミッタ電極13の電位よりも
高くなるようにゲート電圧を印加する。このゲート電圧
がしきい値電圧を超えると、トレンチ型絶縁ゲート電極
14の側面のp導電型のボディ層4の表面にn導電型の
チャネルが形成され、n+導電型のエミッタ領域7からそ
のチャネルを介して電子がn-導電型のドリフト層2に流
れ込む。これによってp導電型のコレクタ層6からはn-
導電型のドリフト層2に正孔が注入されオンとなる。こ
の時、n-導電型のドリフト層2で電導率変調が起こるた
め、MOSFETでは非常に高かったオン抵抗が、IGBTで
は大幅に低くなる。本実施例の場合、200A/cm2
の電流でオン電圧は1.5Vであり、オン抵抗は7.5m
Ω・cm2であった。また、ゲート電極であるトレンチ
型絶縁ゲート電極14の電位がエミッタ電極13の電位
以下になるようにゲート電圧を印加し、かつコレクタ電
極12の電位がエミッタ電極13の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡がっ
て電界強度を緩和し、印加電圧に耐える耐電圧性が生じ
る。本実施例では、この空乏層で電圧を分担する以外
に、トレンチ型絶縁ゲート電極14の下部でも、コレク
タ−エミッタ間電圧に応じて電界緩和半導体領域1とn-
導電型のドリフト層2との接合からそれぞれの層に空乏
層が拡がって耐電圧性が生じる。したがってトレンチ型
絶縁ゲート電極14の下部では、印加電圧の大部分が上
記電界緩和半導体領域1とn-導電型のドリフト層2によ
り分担される。それ故、ゲート絶縁物層9の電圧分担が
小さくなり絶縁物層9の電界強度が緩和される。これに
より、ゲート絶縁物層9の信頼性が向上する。また、ゲ
ート絶縁物層9の電界強度が緩和され耐圧の向上を図る
ことが可能である。本実施例の場合においても、前述の
MOSFETの場合と同様にトレンチ型絶縁ゲート14の底部
側面部の絶縁物層9の電界強度は、電界緩和半導体領域
1を形成しない従来の構造のIGBTに比べ、45〜6
5%程度緩和される。したがって、本実施例において
も、ゲート絶縁物層9の電界強度が緩和されたことによ
り耐圧の向上を図れるとともにゲート絶縁物層9の信頼
性が向上する。例えば実施例によれば耐圧が2900V
から3250Vに改善できた。
In the operation of the n-channel IGBT of this embodiment, first, the potential of the collector electrode 12
And a gate voltage is applied such that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is higher than the potential of the emitter electrode 13. When the gate voltage exceeds the threshold voltage, an n-conductivity-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14, and n + -conductivity-type emitter region 7 is formed. Electrons flow into the n conductivity type drift layer 2 through the channel. As a result, from the p-conductivity type collector layer 6, n
Holes are injected into the conductive type drift layer 2 to be turned on. At this time, since conductivity modulation occurs in the n conductivity type drift layer 2, the ON resistance, which was very high in the MOSFET, is greatly reduced in the IGBT. In the case of the present embodiment, 200 A / cm 2
The ON voltage is 1.5 V and the ON resistance is 7.5 m
Ω · cm 2 . Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 becomes higher than the potential of the emitter electrode 13. When applied, the drift layer 2 of n - conductivity type and p
The depletion layer spreads on both sides of the junction 24 of the conductive type body layer 4 to reduce the electric field intensity, and a withstand voltage to withstand the applied voltage is generated. In the present embodiment, in addition to sharing the voltage with the depletion layer, the electric field relaxation semiconductor region 1 and n are also formed below the trench-type insulated gate electrode 14 according to the collector-emitter voltage.
From the junction with the conductive type drift layer 2, a depletion layer spreads in each layer, and a withstand voltage is generated. Therefore, below the trench-type insulated gate electrode 14, most of the applied voltage is shared by the electric field relaxation semiconductor region 1 and the n conductivity type drift layer 2. Therefore, the voltage distribution of the gate insulator layer 9 is reduced, and the electric field strength of the insulator layer 9 is reduced. Thereby, the reliability of the gate insulator layer 9 is improved. Further, the electric field strength of the gate insulator layer 9 is reduced, and the withstand voltage can be improved. Also in the case of this embodiment, the aforementioned
As in the case of the MOSFET, the electric field strength of the insulator layer 9 on the bottom side surface of the trench-type insulated gate 14 is 45 to 6 compared with the IGBT having the conventional structure in which the electric field relaxation semiconductor region 1 is not formed.
It is reduced by about 5%. Therefore, also in this embodiment, since the electric field strength of the gate insulating layer 9 is reduced, the withstand voltage can be improved, and the reliability of the gate insulating layer 9 can be improved. For example, according to the embodiment, the withstand voltage is 2900 V
To 3250V.

【0025】<<実施例5>>図5は本発明の実施例5のn
チャネルSiC MOSFETの単位セグメントの断面図であ
る。実施例5は、実施例3のn導電型チャネルSiC
MOSFETに第2の導電型(p)の第3の半導体領域として
の第2電界緩和半導体領域8を設けた構造である。この
電界緩和半導体領域8は、0.5μm厚であり、表面不
純物濃度が1017atm/cm3程度の、n-導電型のド
リフト層2と反対のp導電型を示す領域である。製作方
法は、n-導電型のドリフト層2を形成するところまでは
実施例3のMOSFETと同様である。実施例3の製法との主
な違いは、n-導電型のドリフト層2の形成後、選択的に
ホウ素(またはアルミニウム等でも可)をイオン打ち込
み等で注入し、第2電界緩和半導体領域8を形成する点
である。その後の製作工程は実施例3の場合と全く同様
であるから記載を省略する。
<< Embodiment 5 >> FIG. 5 shows n of Embodiment 5 of the present invention.
It is sectional drawing of the unit segment of a channel SiC MOSFET. In the fifth embodiment, the n-conductivity type channel SiC of the third embodiment is used.
This is a structure in which the MOSFET is provided with a second electric field relaxation semiconductor region 8 as a third semiconductor region of the second conductivity type (p). This electric field relaxation semiconductor region 8 is a region having a thickness of 0.5 μm and a surface impurity concentration of about 10 17 atm / cm 3 , and showing a p conductivity type opposite to the n conductivity type drift layer 2. The fabrication method is the same as that of the MOSFET of the third embodiment up to the point where the drift layer 2 of the n conductivity type is formed. The main difference from the manufacturing method of the third embodiment is that after the n conductivity type drift layer 2 is formed, boron (or aluminum or the like) is selectively implanted by ion implantation or the like to form the second electric field relaxation semiconductor region 8. Is the point that forms Subsequent manufacturing steps are exactly the same as in the case of the third embodiment, and a description thereof will be omitted.

【0026】実施例3のMOSFETでは、トレンチ型絶縁ゲ
ート14の底部の側端部における絶縁物層9の電界強度
が大きくなり、耐圧はその部分の電界強度で決まってい
た。それに対して、本実施例のように第2電界緩和半導
体領域8を形成したものでは、空乏層が第2電界緩和半
導体領域8とn-導電型のドリフト層2の接合部から拡が
り、トレンチ型絶縁ゲート14の下部の電界緩和半導体
領域1とn-導電型のドリフト層2の接合部から拡がる空
乏層と連なる。そしてその空乏層はn-導電型のドリフト
層2中をドレイン電極10側へ拡がる。その結果、ドレ
イン−ソース電極間に印加された電圧が、前述の連なっ
た空乏層によっても分担される。このため、絶縁物層9
の電圧分担がさらに小さくなり、電界強度がさらに緩和
される。本実施例においては、従来のものに比べて約5
5%〜80%の電界強度が緩和される。したがって、実
施例5の半導体装置は従来のものに比べて約55%以上
耐圧が向上し、例えば、耐圧は3100Vから3600
V程度に改善できる。上記の電界強度の緩和により上記
絶縁物層9の信頼性向上がさらに図れる。実験例とし
て、3000Vの電圧印加試験を実施したところ従来の
ものに比べて2倍以上の寿命が得られた。
In the MOSFET of the third embodiment, the electric field strength of the insulating layer 9 at the side edge at the bottom of the trench-type insulated gate 14 was increased, and the breakdown voltage was determined by the electric field strength at that portion. On the other hand, in the case where the second electric field relaxation semiconductor region 8 is formed as in the present embodiment, the depletion layer extends from the junction between the second electric field relaxation semiconductor region 8 and the n conductivity type drift layer 2, and the trench type is formed. The depletion layer extends from the junction between the electric field relaxation semiconductor region 1 under the insulating gate 14 and the n conductivity type drift layer 2. Then, the depletion layer spreads in the n conductivity type drift layer 2 toward the drain electrode 10. As a result, the voltage applied between the drain and source electrodes is also shared by the above-described connected depletion layers. Therefore, the insulator layer 9
Is further reduced, and the electric field intensity is further reduced. In this embodiment, about 5 times as compared with the conventional one.
The electric field intensity of 5% to 80% is reduced. Therefore, the withstand voltage of the semiconductor device of the fifth embodiment is improved by about 55% or more as compared with the conventional device. For example, the withstand voltage is 3100 V to 3600 V.
V can be improved. By relaxing the electric field intensity, the reliability of the insulating layer 9 can be further improved. As a test example, when a voltage application test of 3000 V was performed, the life was more than twice as long as that of the conventional one.

【0027】<<実施例6>>図6は本発明の実施例6のn
チャネルSiC IGBTのセグメントの断面図であ
る。実施例6はnチャネルSiC IGBTに第2電界
緩和半導体領域8を設けた構造を有する。この構造は実
施例3のn+導電型のドレイン層3の代わりにp+導電型の
コレクタ層6が形成されたものである。実施例6の構造
諸元および製作方法では、実施例5のSiC−n導電型
基板の代わりにSiC−p導電型基板を用い、ドレイン
層を若干低濃度にするとともに、絶縁物層9の厚さや膜
質の改善をはかっている。その他の製作工程は、実施例
3の場合と同様である。なお、p+導電型基板の不純物
濃度は、1018〜1019atm/cm3である。この実
施例の場合も実施例5の場合と同様に、第2電界緩和半
導体領域8を形成することによる効果があり、絶縁物層
9の電界強度が緩和される。本実施例においては、従来
のものに比べて約65%〜130%の電界強度が緩和さ
れる。したがって、この半導体装置では約25%以上耐
圧向上を図ることができ、耐圧は3300Vから460
0V程度に改善できた。上記の電界強度の緩和により上
記絶縁物層9の信頼性向上も図れる。
<< Embodiment 6 >> FIG. 6 is a view showing n of Embodiment 6 of the present invention.
FIG. 4 is a sectional view of a segment of a channel SiC IGBT. The sixth embodiment has a structure in which a second electric field relaxation semiconductor region 8 is provided in an n-channel SiC IGBT. In this structure, a p + -type collector layer 6 is formed instead of the n + -type drain layer 3 of the third embodiment. In the structural specifications and manufacturing method of the sixth embodiment, a SiC-p conductivity type substrate is used instead of the SiC-n conductivity type substrate of the fifth embodiment, the drain layer is slightly reduced in concentration, and the thickness of the insulator layer 9 is reduced. Improving pod film quality. Other manufacturing steps are the same as those in the third embodiment. The impurity concentration of the p + conductivity type substrate is 10 18 to 10 19 atm / cm 3 . In the case of this embodiment, similarly to the case of the fifth embodiment, there is an effect by forming the second electric field relaxation semiconductor region 8, and the electric field strength of the insulator layer 9 is reduced. In this embodiment, the electric field intensity of about 65% to 130% is reduced as compared with the conventional one. Therefore, in this semiconductor device, the withstand voltage can be improved by about 25% or more, and the withstand voltage is from 3300 V to 460.
It was improved to about 0V. By relaxing the electric field intensity, the reliability of the insulating layer 9 can be improved.

【0028】<<実施例7>>図7は本発明の実施例7のn
チャネルSiC MOSFETの単位セグメントの断面図であ
る。実施例7では、ドレイン電極19を実施例1〜4の
ドレイン層3の面ではなくてボディ層4が設けられるド
リフト層2の面に設けている。このような構成のものを
横型の絶縁ゲート半導体装置と称している。実施例7で
は前記各実施例で設けていたp導電型のボディ層4の代
わりに、一定の領域をもつたとえばストライプ状のp導
電型のボディ領域40を設ける。ドリフト層2の上でボ
ディ領域40から一定距離離れたところにn+導電型のド
レイン領域33を設ける。そしてドレイン領域33の上
にドレイン電極19を設ける。
<< Embodiment 7 >> FIG. 7 shows n of Embodiment 7 of the present invention.
It is sectional drawing of the unit segment of a channel SiC MOSFET. In the seventh embodiment, the drain electrode 19 is provided not on the surface of the drain layer 3 of the first to fourth embodiments but on the surface of the drift layer 2 on which the body layer 4 is provided. Such a configuration is called a horizontal insulated gate semiconductor device. In the seventh embodiment, a body region 40 of, for example, a striped p-conductivity type having a certain region is provided instead of the p-conductivity type body layer 4 provided in each of the above embodiments. An n + conductivity type drain region 33 is provided on the drift layer 2 at a predetermined distance from the body region 40. Then, the drain electrode 19 is provided on the drain region 33.

【0029】ドレイン電極19は絶縁ゲート電極14か
ら所定の距離を隔てて絶縁ゲート電極14に並行して設
けるのが望ましい。ドレイン電極19とボディ領域40
との間には1個又はそれ以上のp導電型のターミネーシ
ョン領域15をボディ領域40に実質的に並行して設け
ている。ターミネーション領域15は、ボディ領域40
の端部の電界集中を緩和するためのものである。上記の
各点以外の構造は図1のものと同じである。横型の絶縁
ゲート半導体装置では、ソース端子とドレイン端子が同
じ方向に設けられているので、ハイブリッドIC等に組
み込んで用いる場合の配線作業が簡単になる。またドレ
イン電極19が個々の半導体装置に設けられているので
接続の自由度が増す。実施例7に示したドレイン領域及
びドレイン電極19の構成は、図5に示す実施例5の構
成に対しても同様に適用可能である。また図2の実施例
2、図4の実施例4及び図6の実施例6において、コレ
クタ層6に相当するp+導電型のコレクタ領域をボディ層
4上の面に設け、そのコレクタ領域にコレクタ電極を設
けることにより、図7の構成を実施例2、4及び6の装
置にも同様に適用可能である。
The drain electrode 19 is desirably provided in parallel with the insulated gate electrode 14 at a predetermined distance from the insulated gate electrode 14. Drain electrode 19 and body region 40
One or more termination regions 15 of p conductivity type are provided substantially parallel to the body region 40. The termination region 15 is provided in the body region 40.
Is intended to alleviate the electric field concentration at the end portions of the. Structures other than those described above are the same as those in FIG. In the horizontal insulated gate semiconductor device, since the source terminal and the drain terminal are provided in the same direction, the wiring operation when the semiconductor device is incorporated in a hybrid IC or the like is simplified. Further, since the drain electrode 19 is provided in each semiconductor device, the degree of freedom of connection increases. The configuration of the drain region and the drain electrode 19 shown in the seventh embodiment can be similarly applied to the configuration of the fifth embodiment shown in FIG. In the second embodiment shown in FIG. 2, the fourth embodiment shown in FIG. 4, and the sixth embodiment shown in FIG. 6, a collector region of p + conductivity type corresponding to the collector layer 6 is provided on the surface of the body layer 4, and the collector region is formed. By providing the collector electrode, the configuration of FIG. 7 can be similarly applied to the devices of the second, fourth, and sixth embodiments.

【0030】<<実施例8>>図8は、本発明の実施例8の
nチャネルSiC MOSFETのセグメントの断面図であ
る。実施例8の構造は大略実施例3と同じであるが、電
界緩和半導体領域の断面形状と製作工程において実施例
3と異なる。実施例8では、トレンチ69を形成した
後、電界緩和半導体領域1Aを形成する際、ホウ素等の
イオン打ち込み量を実施例3より多くする。これによ
り、トレンチ底部の両端部においてn-導電型のドリフト
層2内の横方向のホウ素の拡散がより顕著に進行し、図
8に示すように電界緩和半導体領域1Aが深さ方向と同
程度まで両側にふくらんだ形状となる。その結果トレン
チ型絶縁ゲート14の底部側端部における絶縁物層9の
電界強度がより緩和され、より高い耐圧を実現できる。
その理由は、電界緩和半導体領域1Aのふくらんだ広い
領域で、電圧が分担されるためである。たとえば実施例
3の半導体装置の耐圧2900〜3250Vに比べ、図
8に示す実施例8の耐圧は3200Vから3500Vと
増大し、更に信頼性も向上できた。一方、図8の構造の
場合、オン抵抗が若干増大するが実用的には全く問題に
ならない程度である。なお、本実施例の両脇にふくらん
だ形状の電界緩和半導体領域1Aは、実施例1から実施
例7にも同様に適用可能である。
<< Eighth Embodiment >> FIG. 8 is a sectional view of a segment of an n-channel SiC MOSFET according to an eighth embodiment of the present invention. The structure of the eighth embodiment is substantially the same as that of the third embodiment, but is different from the third embodiment in the cross-sectional shape and the manufacturing process of the electric field relaxation semiconductor region. In the eighth embodiment, when forming the electric field relaxation semiconductor region 1A after forming the trench 69, the ion implantation amount of boron or the like is set to be larger than that in the third embodiment. Thereby, the diffusion of boron in the lateral direction in the n -conductivity type drift layer 2 at both ends of the trench bottom portion progresses more remarkably, and as shown in FIG. Until the shape bulges on both sides. As a result, the electric field strength of the insulator layer 9 at the bottom end of the trench-type insulated gate 14 is further reduced, and a higher breakdown voltage can be realized.
The reason for this is that the voltage is shared in the swelled wide region of the electric field relaxation semiconductor region 1A. For example, the withstand voltage of the eighth embodiment shown in FIG. 8 is increased from 3200 V to 3500 V as compared with the withstand voltage of 2900 to 3250 V of the semiconductor device of the third embodiment, and the reliability is further improved. On the other hand, in the case of the structure shown in FIG. 8, the on-resistance slightly increases, but it is practically no problem. In addition, the electric field relaxation semiconductor region 1 </ b> A having a bulging shape on both sides of the present embodiment is similarly applicable to the first to seventh embodiments.

【0031】前記の実施例7に示したドレイン領域及び
ドレイン電極19の構成は、図8に示す実施例8の構成
に対しても同様に適用可能である。
The structure of the drain region and the drain electrode 19 shown in the seventh embodiment can be similarly applied to the structure of the eighth embodiment shown in FIG.

【0032】<<実施例9>>図9は、本発明の実施例9で
ある耐圧2500V級nチャネルSiC(炭化珪素)MO
SFETの単位セグメントの断面図である。この実施例はト
レンチ69側面の絶縁層9の厚さに対してトレンチ底部
のそれを約5ないし約20倍以上にして電圧の分担を改
良しようとする。この実施例では、セグメント幅は5μ
m、奥行きは1mmである。その他の構造諸元は以下の
とおりである。n-導電型のドリフト層2はn+導電型のド
レイン層3の上に設け、厚さは約20μmである。n+
電型のドレイン層3は、厚さ約300μm、p導電型の
ボディ層4の厚さは4μm、n+導電型のソース領域5の
接合深さは0.5μm、凹部すなわちトレンチ69の深
さは6μm、トレンチ幅は3μm、トレンチ69内に設
けたSiO2(酸化珪素)等の絶縁物層9の厚さはトレ
ンチ69底部で1μm、トレンチ69側面で0.1μm
である。本実施例では、トレンチ型絶縁ゲート電極14
は紙面奥行方面に長いストライプ状である。なおトレン
チの平面形状は、例えばこの実施例のように紙面奥行方
向に長い長溝状のものの他に、例えば直径3μmの円形
孔状や正方形のものなどでもよい。トレンチの配置は、
例えば5μmピッチで等間隔に配列する。なお円形のト
レンチの場合は縦横に格子状に又は千鳥状に配列すれば
よい。
<< Embodiment 9 >> FIG. 9 shows a ninth embodiment of the present invention, which is a 2500V class n-channel SiC (silicon carbide) MO.
FIG. 3 is a sectional view of a unit segment of the SFET. This embodiment seeks to improve voltage sharing by making the thickness at the bottom of the trench about 5 to about 20 times or more the thickness of the insulating layer 9 on the side of the trench 69. In this embodiment, the segment width is 5 μm.
m and depth are 1 mm. Other structural specifications are as follows. The n conductivity type drift layer 2 is provided on the n + conductivity type drain layer 3 and has a thickness of about 20 μm. The drain layer 3 of the n + conductivity type has a thickness of about 300 μm, the thickness of the body layer 4 of the p conductivity type is 4 μm, the junction depth of the source region 5 of the n + conductivity type is 0.5 μm, The depth is 6 μm, the trench width is 3 μm, and the thickness of the insulator layer 9 such as SiO 2 (silicon oxide) provided in the trench 69 is 1 μm at the bottom of the trench 69 and 0.1 μm at the side surface of the trench 69.
It is. In this embodiment, the trench-type insulated gate electrode 14
Is a long stripe shape in the depth direction of the paper. The planar shape of the trench may be, for example, a circular groove having a diameter of 3 μm or a square in addition to a long groove having a long length in the depth direction of the paper as in this embodiment. The arrangement of the trench
For example, they are arranged at equal intervals at a pitch of 5 μm. In the case of circular trenches, they may be arranged vertically and horizontally in a lattice or in a staggered manner.

【0033】本実施例の製作方法の具体例は、次のとお
りである。最初にドレイン領域として機能する1018
ら1020atm/cm3濃度の、たとえば、1019at
m/cm3の濃度のn+形SiC(炭化珪素)基板3を用
意する。この基板3の一表面上に1015から1016at
m/cm3濃度、例えば約5×1015atm/cm3濃度
のSiCのn-導電型のドリフト層2を気相成長法等によ
り形成する。次にそのドリフト層2の上に1016atm
/cm3程度のSiCのp導電型のボディ層4を気相成
長法等により形成する。そして、ソース層として、選択
的に1018atm/cm3程度の濃度のn+導電型の領域
5を窒素のイオン打ち込み等により形成する。(窒素に
かえてりん等でも可能。)
A specific example of the manufacturing method according to the present embodiment is as follows. First, a concentration of 10 18 to 10 20 atm / cm 3 , for example, 10 19 at, which functions as a drain region
An n + -type SiC (silicon carbide) substrate 3 having a concentration of m / cm 3 is prepared. 10 15 to 10 16 at on one surface of the substrate 3
An n - conductivity type drift layer 2 of SiC having a concentration of m / cm 3 , for example, about 5 × 10 15 atm / cm 3 is formed by a vapor phase growth method or the like. Next, 10 16 atm is applied on the drift layer 2.
A p-type body layer 4 of SiC of about / cm 3 is formed by a vapor phase growth method or the like. Then, as the source layer, an n + conductivity type region 5 having a concentration of about 10 18 atm / cm 3 is selectively formed by ion implantation of nitrogen or the like. (It is also possible to use phosphorus instead of nitrogen.)

【0034】次に、図9のように基板3、ドリフト層2
及びボディ層4からなる広義の基板を異方性エッチング
して、p導電型のボディ層4を貫通し底部がn-導電型の
ドリフト層2に達するトレンチ(溝)69を形成する。
続いて、トレンチ69の内表面にSiO2のゲート絶縁
膜9を形成し、さらに気相成長法により選択的にトレン
チ底部のSiO2ゲート絶縁膜9を厚くし、約1μmと
する。そしてトレンチ69内にりんを高濃度に含んだゲ
ート領域としてのポリシリコンを堆積しトレンチ69を
埋め込んでゲート領域14を作る。トレンチ69の寸法
の1例は、深さ6μm、幅3μm、長さ1mmである。
ここに示した寸法は1例であって、必要に応じて他の寸
法も用いる。トレンチ69内のポリシリコンを残し、そ
れ以外の場所(基板表面等)の残りのポリシリコンを除
去することにより、トレンチ型絶縁ゲート電極14が形
成される。最後に、アルミニウム(他にニッケル等も用
いうる)で表面にソース電極11、裏面にドレイン電極
10を形成し、絶縁ゲート半導体装置(MOSFET)を完成す
る。このMOSFETのオン抵抗は、約30mΩ・cm2であ
った。
Next, as shown in FIG. 9, the substrate 3, the drift layer 2
Then, a broadly defined substrate composed of the body layer 4 is anisotropically etched to form a trench (groove) 69 that penetrates the body layer 4 of the p-conductivity type and the bottom reaches the drift layer 2 of the n conductivity type.
Subsequently, a gate insulating film 9 of SiO 2 is formed on the inner surface of the trench 69, and the thickness of the SiO 2 gate insulating film 9 at the bottom of the trench is selectively increased to about 1 μm by a vapor phase growth method. Then, polysilicon as a gate region containing phosphorus at a high concentration is deposited in the trench 69 and the trench 69 is buried to form the gate region 14. An example of the dimensions of the trench 69 is 6 μm in depth, 3 μm in width, and 1 mm in length.
The dimensions shown here are examples, and other dimensions may be used as needed. The trench-type insulated gate electrode 14 is formed by leaving the polysilicon in the trench 69 and removing the remaining polysilicon in other places (such as the substrate surface). Lastly, the source electrode 11 is formed on the front surface and the drain electrode 10 is formed on the back surface using aluminum (in addition, nickel or the like may be used), thereby completing an insulated gate semiconductor device (MOSFET). The on-resistance of this MOSFET was about 30 mΩ · cm 2 .

【0035】本実施例はnチャネルSiC MOSFETであ
り、この装置ではドレイン電極10の電位がソース電極
11の電位より高く、かつゲート電極であるトレンチ型
絶縁ゲート電極14の電位がソース電極11の電位より
も高くなるようにゲート電圧を印加する。このゲート電
圧がしきい値電圧を超えた場合、トレンチ型絶縁ゲート
電極14の側面のp導電型のボディ層4の表面にn導電
型のチャネルが形成される。それにより電子がn+導電型
のソース領域5からそのチャネルを介してn-導電型のド
リフト層2、さらにn+導電型のドレイン層3に流れ込み
半導体装置がオンとなる。また、ゲート電極であるトレ
ンチ型絶縁ゲート電極14の電位がソース電極11の電
位以下になるようにゲート電圧を印加し、かつドレイン
電極10の電位がソース電極11の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡が
る。この空乏層により電界強度を緩和し、印加電圧に耐
える耐電圧性が生じる。
This embodiment is an n-channel SiC MOSFET. In this device, the potential of the drain electrode 10 is higher than the potential of the source electrode 11, and the potential of the trench-type insulated gate electrode 14 as the gate electrode is the potential of the source electrode 11. The gate voltage is applied so as to be higher. When the gate voltage exceeds the threshold voltage, an n-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14. As a result, electrons flow from the source region 5 of the n + conductivity type to the drift layer 2 of the n conductivity type via the channel thereof and further to the drain layer 3 of the n + conductivity type, and the semiconductor device is turned on. Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the source electrode 11, and the voltage is set so that the potential of the drain electrode 10 becomes higher than the potential of the source electrode 11. When applied, the drift layer 2 of n - conductivity type and p
A depletion layer extends on both sides of the junction 24 of the conductive type body layer 4. The depletion layer alleviates the electric field strength and produces a withstand voltage that can withstand the applied voltage.

【0036】本実施例では、絶縁物層9のトレンチ底部
の厚みを1μmとトレンチ側面部の厚みより数倍から1
0倍程度以上厚くすることにより、絶縁物層9の底部及
び底部側面端部の電界が緩和される。これにより、耐電
圧の向上を図ることができる。あるいは、ゲート絶縁物
層9の信頼性を向上できる。
In the present embodiment, the thickness of the insulating layer 9 at the bottom of the trench is 1 μm, which is several times larger than the thickness of the side of the trench by 1 to 1 μm.
By making the thickness about 0 times or more, the electric field at the bottom of the insulator layer 9 and the end of the bottom side surface is reduced. Thereby, the withstand voltage can be improved. Alternatively, the reliability of the gate insulator layer 9 can be improved.

【0037】計算による予測では、図11のような従来
のトレンチ型絶縁ゲートMOSFETの場合には、トレンチ型
絶縁ゲート電極14とソース電極11を短絡し、ソース
電極11を0Vとしドレイン電極10に+2000Vを
印加した場合、トレンチ型絶縁ゲート底部のSi02
縁物層9の電界強度は、Si02の破壊電界強度である
6〜10MV/cmを超える値となった。これに対して、本
実施例のMOSFETのように絶縁物層9の厚みを1μmとし
たものでは、トレンチ型絶縁ゲート底部側端部のSi0
2絶縁物層9の電界強度は、従来のものに比べて90%
程度減少する。絶縁物層の信頼性は、電界強度がその破
壊電界強度近くになると大幅に低下する。本実施例では
絶縁物層9の電界強度が大幅に小さくなったことから、
信頼性が大幅に向上した。その結果半導体装置の耐圧は
2900Vから3250Vに向上した。さらにn-ドリ
フト層を厚くすることにより、さらなる高耐圧化が可能
である。ドレイン電極10に印加した電圧はn-導電型の
ドリフト層2とトレンチ型絶縁ゲート14の底部の絶縁
物層9により分担され、絶縁物層9の電圧分担が大きく
なり、それに応じて電界強度も大きくなっていた。しか
し、本実施例のようにトレンチ型絶縁ゲート14の底部
の絶縁物の厚さを約1μm以上とすると、n-導電型のド
リフト層2およびトレンチ型絶縁ゲート底部絶縁物層9
により電圧が分担され、特に絶縁物層9の底部でドレイ
ン−ソース間印加電圧の大部分を分担する。しかし、絶
縁物層9の厚みを増した分だけその層9の電界強度も小
さくなる。耐圧が高い素子の場合には、トレンチ型絶縁
ゲート14の底部の絶縁物層9の電界強度が特に高くな
るので、絶縁物層9底部の厚みを増す効果は顕著にな
る。実施例9において、実施例5における第2電界緩和
半導体領域8に相当するものを設けると、実施例5と同
様の効果が得られる。実施例9において、実施例7にお
けるように、ドレイン電極19を絶縁ゲート電極14か
ら所定の距離を隔てて絶縁ゲート電極14に並行して設
けると、実施例7と同様の効果を得ることができる。
According to calculations, in the case of the conventional trench-type insulated gate MOSFET as shown in FIG. 11, the trench-type insulated gate electrode 14 and the source electrode 11 are short-circuited, the source electrode 11 is set to 0 V, and the drain electrode 10 is set to +2000 V. Was applied, the electric field strength of the SiO 2 insulator layer 9 at the bottom of the trench-type insulated gate exceeded 6 to 10 MV / cm, which is the breakdown electric field strength of SiO 2 . On the other hand, in the case where the thickness of the insulator layer 9 is 1 μm as in the MOSFET of this embodiment, the Si0 at the bottom-side end of the trench-type insulated gate is not used.
(2 ) The electric field strength of the insulating layer 9 is 90%
To a degree. The reliability of the insulator layer is greatly reduced when the electric field intensity approaches the breakdown electric field intensity. In the present embodiment, since the electric field strength of the insulator layer 9 is significantly reduced,
Significantly improved reliability. As a result, the breakdown voltage of the semiconductor device was improved from 2900 V to 3250 V. By further increasing the thickness of the n drift layer, a higher breakdown voltage can be achieved. The voltage applied to the drain electrode 10 is shared by the n conductivity type drift layer 2 and the insulator layer 9 at the bottom of the trench type insulated gate 14, and the voltage share of the insulator layer 9 increases, and the electric field strength correspondingly increases. It was getting bigger. However, if the thickness of the insulator at the bottom of the trench type insulated gate 14 is about 1 μm or more as in this embodiment, the n conductivity type drift layer 2 and the trench type insulated gate bottom insulator layer 9 are formed.
, And in particular, most of the applied voltage between the drain and the source at the bottom of the insulator layer 9. However, the electric field strength of the insulating layer 9 is reduced by the increase of the thickness of the insulating layer 9. In the case of an element having a high withstand voltage, the electric field strength of the insulating layer 9 at the bottom of the trench-type insulated gate 14 becomes particularly high, so that the effect of increasing the thickness of the bottom of the insulating layer 9 becomes remarkable. In the ninth embodiment, the same effect as that of the fifth embodiment can be obtained by providing a component corresponding to the second electric field relaxation semiconductor region 8 in the fifth embodiment. In the ninth embodiment, when the drain electrode 19 is provided in parallel with the insulated gate electrode 14 at a predetermined distance from the insulated gate electrode 14 as in the seventh embodiment, the same effect as in the seventh embodiment can be obtained. .

【0038】<<実施例10>>図10は、本発明の実施例
10のnチャネルSiC IGBTのセグメントの断面
図である。その構造は実施例9のn+導電型のドレイン層
3の代わりにp導電型のコレクタ層6を形成したもので
ある。実施例10の構造諸元および製作方法は、実施例
9のSiC−n+導電型基板の代わりにSiC−p+導電型
基板を用いる点が異なるだけであり、後の製作工程は実
施例9の場合と同様である。尚、p+導電型基板の不純物
濃度は、1018〜1019atm/cm3である。
Embodiment 10 FIG. 10 is a sectional view of a segment of an n-channel SiC IGBT according to Embodiment 10 of the present invention. The structure is such that a p-type collector layer 6 is formed in place of the n + -type drain layer 3 of the ninth embodiment. Structure specifications and fabrication method of Example 10 is the point of using the SiC-p + conductivity type substrate instead of SiC-n + conductivity type substrate of Example 9 differs only after the manufacturing process Example 9 Is the same as The impurity concentration of the p + conductivity type substrate is 10 18 to 10 19 atm / cm 3 .

【0039】本実施例のnチャネルIGBTの動作にお
いて、先ずコレクタ電極12の電位がエミッタ電極13
の電位より高く、かつゲート電極であるトレンチ型絶縁
ゲート電極14の電位がエミッタ電極13の電位よりも
高くなるようにゲート電圧を印加する。このゲート電圧
がしきい値電圧を超えると、トレンチ型絶縁ゲート電極
14の側面のp導電型のボディ層4の表面にn導電型の
チャネルが形成され、n+導電型のエミッタ領域7からそ
のチャネルを介して電子がn-導電型のドリフト層2に流
れ込む。これによってp導電型のコレクタ層6からはn-
導電型のドリフト層2に正孔が注入されオンとなる。こ
の時、n-導電型のドリフト層2で電導率変調が起こるた
め、MOSFETでは非常に高かったオン抵抗が、IGBTで
は大幅に低くなる。本実施例の場合、200A/cm2
の電流でオン電圧は1.5Vであり、オン抵抗は7.5m
Ω・cm2であった。また、ゲート電極であるトレンチ
型絶縁ゲート電極14の電位がエミッタ電極13の電位
以下になるようにゲート電圧を印加し、かつコレクタ電
極12の電位がエミッタ電極13の電位より高くなるよ
うに電圧を印加した場合、n-導電型のドリフト層2とp
導電型のボディ層4の接合24の両側に空乏層が拡がっ
て電界強度を緩和し、印加電圧に耐える耐電圧性が生じ
る。
In the operation of the n-channel IGBT of this embodiment, first, the potential of the collector electrode 12
And a gate voltage is applied such that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is higher than the potential of the emitter electrode 13. When the gate voltage exceeds the threshold voltage, an n-conductivity-type channel is formed on the surface of p-type body layer 4 on the side surface of trench-type insulated gate electrode 14, and n + -conductivity-type emitter region 7 is formed. Electrons flow into the n conductivity type drift layer 2 through the channel. As a result, from the p-conductivity type collector layer 6, n
Holes are injected into the conductive type drift layer 2 to be turned on. At this time, since conductivity modulation occurs in the n conductivity type drift layer 2, the ON resistance, which was very high in the MOSFET, is greatly reduced in the IGBT. In the case of the present embodiment, 200 A / cm 2
The ON voltage is 1.5 V and the ON resistance is 7.5 m
Ω · cm 2 . Further, a gate voltage is applied so that the potential of the trench-type insulated gate electrode 14 serving as the gate electrode is equal to or lower than the potential of the emitter electrode 13, and the voltage is set so that the potential of the collector electrode 12 becomes higher than the potential of the emitter electrode 13. When applied, the drift layer 2 of n - conductivity type and p
The depletion layer spreads on both sides of the junction 24 of the conductive type body layer 4 to reduce the electric field intensity, and a withstand voltage to withstand the applied voltage is generated.

【0040】本実施例では、トレンチ型絶縁ゲート電極
14の下部では、印加電圧の大部分が絶縁物層9の底部
により分担されるが、絶縁物層9の底部を厚くすること
によりその底部及び底部側面端部の電界強度が緩和され
る。これにより、ゲート絶縁物層9の信頼性が大幅に向
上する。また、ゲート絶縁物層9の電界強度が緩和され
るため耐圧の向上を図ることが可能である。本実施例の
場合においても、前述のMOSFETの場合と同様にトレンチ
型絶縁ゲート14の底部側面部の絶縁物層9の電界強度
は、絶縁物層9を大幅に厚くしない従来の構造のIGB
Tに比べ、90%程度緩和される。したがって、本実施
例においても、ゲート絶縁物層9の電界強度が緩和され
たことにより耐圧の向上を図れるとともにゲート絶縁物
層9の信頼性が大幅に向上する。例えば実施例によれば
耐圧が2900Vから3250Vに改善できた。
In the present embodiment, most of the applied voltage is shared by the bottom of the insulator layer 9 below the trench-type insulated gate electrode 14, but by increasing the bottom of the insulator layer 9, the bottom and the bottom of the insulator layer 9 are thickened. The electric field intensity at the bottom side edge is reduced. Thereby, the reliability of the gate insulator layer 9 is greatly improved. In addition, since the electric field strength of the gate insulator layer 9 is reduced, the withstand voltage can be improved. Also in the case of the present embodiment, the electric field strength of the insulator layer 9 on the bottom side surface of the trench-type insulated gate 14 is the same as that of the MOSFET described above, and the IGB of the conventional structure which does not greatly increase the thickness of the insulator layer 9 is obtained.
It is relaxed by about 90% compared to T. Therefore, also in the present embodiment, since the electric field strength of the gate insulating layer 9 is reduced, the withstand voltage can be improved, and the reliability of the gate insulating layer 9 can be greatly improved. For example, according to the embodiment, the withstand voltage was improved from 2900 V to 3250 V.

【0041】実施例10において、実施例6における第
2電界緩和半導体領域8に相当するものを設けると、実
施例6と同様の効果が得られる。実施例10において、
実施例7におけるように、コレクタ電極12を絶縁ゲー
ト電極14から所定の距離を隔てて絶縁ゲート電極14
に並行して設けると、実施例7と同様の効果を得ること
ができる。
In the tenth embodiment, the same effect as that of the sixth embodiment can be obtained by providing a structure corresponding to the second electric field relaxation semiconductor region 8 in the sixth embodiment. In Example 10,
As in the seventh embodiment, the collector electrode 12 is separated from the insulated gate electrode 14 by a predetermined distance.
, The same effect as in the seventh embodiment can be obtained.

【0042】以上、実施例1ないし10について本発明
を説明したが、本発明はこれらの実施例に限定されるも
のではなく、トレンチ型MOSサイリスタ、トレンチ型静
電誘導トランジスタ、サイリスタ及びIEGT(Injecti
on Enhanced Insulated GateBipolar Transistor)等に
も適用でき、各種の変形や応用ができるものである。ま
た絶縁物層9はSiO2以外にTa25(酸化タンタ
ル)、Si34(窒化珪素)やAlN(窒化アルミニウ
ム)といった他の絶縁物でもよい。さらに、本発明の実
施例ではゲートはトレンチを埋め込んだ構造にしてある
が、必ずしもその必要はなく、SiO2絶縁物層9を介
してトレンチ69の内壁の一部に薄膜状に形成してもか
まわない。
Although the present invention has been described with reference to the first to tenth embodiments, the present invention is not limited to these embodiments, but includes a trench type MOS thyristor, a trench type static induction transistor, a thyristor, and an IEGT (Injector).
on Enhanced Insulated Gate Bipolar Transistor), etc., and can be modified and applied in various ways. Further, the insulator layer 9 may be other insulators such as Ta 2 O 5 (tantalum oxide), Si 3 N 4 (silicon nitride), and AlN (aluminum nitride) other than SiO 2 . Further, in the embodiment of the present invention, the gate has a structure in which the trench is buried. However, it is not always necessary. The gate may be formed in a thin film on a part of the inner wall of the trench 69 via the SiO 2 insulator layer 9. I don't care.

【0043】[0043]

【発明の効果】本発明の絶縁ゲート半導体装置では、ト
レンチ型絶縁ゲートの底部に第2の導電型をもつ第1の
半導体領域を形成したことにより、従来のトレンチ型絶
縁ゲート構造の半導体装置では高電界であったトレンチ
型絶縁ゲートの底部の絶縁物層の電界強度が緩和され
た。その結果半導体装置では耐圧を従来のものに比べて
15〜30%程度向上できた。上記の電界強度の緩和に
よりその絶縁物層の信頼性が向上する。本発明の絶縁ゲ
ート半導体装置では、トレンチ型絶縁ゲートの底部に第
2の導電型をもつ第1の半導体領域を形成し、トレンチ
型絶縁ゲートの底部の絶縁物層の厚さを側面部の厚さよ
り厚くしたことにより、従来のトレンチ型絶縁ゲート構
造の半導体装置では高電界であったトレンチ型絶縁ゲー
トの底部の絶縁物層の電界強度がさらに、緩和された。
その結果半導体装置では耐圧を従来のものに比べて45
〜65%程度向上できた。上記の電界強度の緩和により
その絶縁物層の信頼性が向上する。
According to the insulated gate semiconductor device of the present invention, the first semiconductor region having the second conductivity type is formed at the bottom of the trench type insulated gate. The electric field intensity of the insulator layer at the bottom of the trench-type insulated gate, which had a high electric field, was reduced. As a result, the breakdown voltage of the semiconductor device was improved by about 15 to 30% as compared with the conventional device. By relaxing the electric field strength, the reliability of the insulator layer is improved. In the insulated gate semiconductor device of the present invention, the first semiconductor region having the second conductivity type is formed at the bottom of the trench-type insulated gate, and the thickness of the insulator layer at the bottom of the trench-type insulated gate is changed to the thickness of the side portion. By increasing the thickness, the electric field strength of the insulator layer at the bottom of the trench insulated gate, which was high in the conventional semiconductor device having the trench insulated gate structure, was further reduced.
As a result, the withstand voltage of the semiconductor device is 45 times that of the conventional device.
Up to about 65% could be improved. By relaxing the electric field strength, the reliability of the insulator layer is improved.

【0044】また、本発明の絶縁ゲート半導体装置の半
導体基板を、より高い導電率をもつ基板の上に同じ導電
型でそれより低い導電率の層を設けた構造とすることに
より、第2の電極と半導体基板との接触抵抗を小さくす
ることができる。このより低い導電率の層を形成したこ
とにより半導体装置の耐圧を高くすることができる。
Further, the semiconductor substrate of the insulated gate semiconductor device of the present invention has a structure in which a layer having the same conductivity type and a lower conductivity is provided on a substrate having a higher conductivity. The contact resistance between the electrode and the semiconductor substrate can be reduced. By forming the lower conductivity layer, the breakdown voltage of the semiconductor device can be increased.

【0045】さらに、本発明の絶縁ゲート半導体装置の
第2の半導体領域の導電率を、半導体基板内で第2の導
電型をもち半導体基板との間に接合を形成する第2の導
電型の半導体層と接合を形成している層の導電率よりも
高くすることにより、第1の電極と第2の半導体領域と
の接触抵抗を小さくすることができ、半導体装置のオン
抵抗を低減できる。
Further, the conductivity of the second semiconductor region of the insulated gate semiconductor device of the present invention is determined by the second conductivity type having the second conductivity type in the semiconductor substrate and forming a junction with the semiconductor substrate. By setting the conductivity higher than the conductivity of the layer forming the junction with the semiconductor layer, the contact resistance between the first electrode and the second semiconductor region can be reduced, and the on-resistance of the semiconductor device can be reduced.

【0046】また、半導体基板の前記接合をもつ面とは
反対側の面に第2の導電型の半導体層を設けた絶縁ゲー
ト半導体装置において、トレンチ型ゲート底部に第2の
導電型の第1の半導体領域を形成することにより、従来
のトレンチ型絶縁ゲート構造の半導体装置では、高電界
であったトレンチ型絶縁ゲートの底部の絶縁物層の電界
強度が緩和された。その結果半導体装置では耐圧を従来
のものに比べて15〜30%程度向上できる。上記の電
界強度の緩和により絶縁物層の信頼性が向上する。ま
た、半導体基板の前記接合をもつ面とは反対側の面に第
2の導電型の半導体層を設けた絶縁ゲート半導体装置に
おいて、トレンチ型ゲート底部に第2の導電型の第1の
半導体領域を形成し、トレンチ型絶縁ゲートの底部の絶
縁物層の厚さを側面部の厚さより厚くしたことにより、
従来のトレンチ型絶縁ゲート構造の半導体装置では、高
電界であったトレンチ型絶縁ゲートの底部の絶縁物層の
電界強度が緩和された。その結果半導体装置では耐圧を
従来のものに比べて45〜65%程度向上できる。上記
の電界強度の緩和により絶縁物層の信頼性が向上する。
Further, in the insulated gate semiconductor device having a semiconductor layer of the second conductivity type provided on the surface of the semiconductor substrate opposite to the surface having the junction, the first portion of the second conductivity type is formed at the bottom of the trench gate. In the semiconductor device having the conventional trench-type insulated gate structure, the electric field strength of the insulator layer at the bottom of the trench-type insulated gate was reduced in the conventional semiconductor device having the trench-type insulated gate structure. As a result, the breakdown voltage of the semiconductor device can be improved by about 15 to 30% as compared with the conventional device. The reliability of the insulator layer is improved by the above-mentioned relaxation of the electric field strength. Further, in the insulated gate semiconductor device provided with a semiconductor layer of a second conductivity type on a surface of the semiconductor substrate opposite to the surface having the junction, a first semiconductor region of a second conductivity type is formed at the bottom of the trench gate. By making the thickness of the insulator layer at the bottom of the trench type insulated gate thicker than the thickness of the side surface,
In a conventional semiconductor device having a trench-type insulated gate structure, the electric field strength of the insulator layer at the bottom of the trench-type insulated gate, which was high in electric field, was reduced. As a result, the breakdown voltage of the semiconductor device can be improved by about 45 to 65% as compared with the conventional device. The reliability of the insulator layer is improved by the above-mentioned relaxation of the electric field strength.

【0047】さらに、本発明の絶縁ゲート半導体装置の
半導体基板内に第2の導電型の第3の半導体領域を選択
的に設けることにより、第2の導電型の第1の半導体領
域だけを設けた場合よりさらに絶縁ゲート半導体装置の
トレンチゲートの底部の絶縁物層側端部の電界強度を緩
和することができた。それにより半導体装置の耐圧を従
来のものに比べて55〜130%程度向上できた。上記
の電界強度の緩和により絶縁物層の信頼性がさらに向上
する。さらに、第2の電極を第1の電極と同じ方向に設
けた横型の半導体装置では、上述の高耐圧化あるいは信
頼性の向上が図れるうえに、個々の半導体装置が同じ方
向に第2の電極を有するので接続の自由度が増し、高集
積化が可能となる。さらに、第2の導電型の第1の電界
緩和半導体領域をトレンチの底部及び底部につながる側
部にも形成することにより、トレンチ型絶縁ゲートの底
部側端部の電界強度をさらに緩和することができ、耐圧
の向上を図ることができる。また、絶縁物層の電界強度
緩和により、絶縁物層の信頼性の向上を図ることができ
る。また、絶縁物層の底部の厚さを側面より大幅に厚く
することにより、絶縁物層の底部及び底部と側面との境
界部の電界を大幅に緩和することができ、耐圧の向上を
図ることができる。また、絶縁物層の電界強度の緩和に
より、絶縁物層の信頼性の大幅な向上を図ることができ
る。さらに、第2の導電型の第1の半導体領域を形成す
ることにより、さらなる高耐圧化又は信頼性の向上がは
かれる。
Further, by selectively providing the third semiconductor region of the second conductivity type in the semiconductor substrate of the insulated gate semiconductor device of the present invention, only the first semiconductor region of the second conductivity type is provided. In this case, the electric field strength at the end of the bottom of the trench gate of the insulated gate semiconductor device on the side of the insulator layer could be further reduced. Thereby, the breakdown voltage of the semiconductor device can be improved by about 55 to 130% as compared with the conventional device. By relaxing the electric field strength, the reliability of the insulator layer is further improved. Further, in a lateral semiconductor device in which the second electrode is provided in the same direction as the first electrode, not only the above-described high withstand voltage or improvement in reliability can be achieved, but also each semiconductor device has the second electrode in the same direction as the first electrode. , The degree of freedom of connection is increased, and high integration is possible. Furthermore, by forming the first electric field relaxation semiconductor region of the second conductivity type also at the bottom of the trench and at the side portion connected to the bottom, the electric field strength at the bottom end of the trench insulated gate can be further reduced. It is possible to improve the withstand voltage. In addition, the reliability of the insulator layer can be improved by relaxing the electric field strength of the insulator layer. In addition, by making the thickness of the bottom of the insulator layer significantly larger than that of the side surface, the electric field at the bottom of the insulator layer and the boundary between the bottom and the side surface can be greatly reduced, and the withstand voltage can be improved. Can be. In addition, the reliability of the insulator layer can be significantly improved by relaxing the electric field strength of the insulator layer. Further, by forming the first semiconductor region of the second conductivity type, higher withstand voltage or higher reliability can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1の絶縁ゲート半導体装置の断
面図
FIG. 1 is a sectional view of an insulated gate semiconductor device according to a first embodiment of the present invention.

【図2】本発明の実施例2の絶縁ゲート半導体装置の断
面図
FIG. 2 is a sectional view of an insulated gate semiconductor device according to a second embodiment of the present invention.

【図3】本発明の実施例3の絶縁ゲート半導体装置の断
面図
FIG. 3 is a sectional view of an insulated gate semiconductor device according to a third embodiment of the present invention;

【図4】本発明の実施例4の絶縁ゲート半導体装置の断
面図
FIG. 4 is a sectional view of an insulated gate semiconductor device according to a fourth embodiment of the present invention.

【図5】本発明の実施例5の絶縁ゲート半導体装置の断
面図
FIG. 5 is a sectional view of an insulated gate semiconductor device according to a fifth embodiment of the present invention.

【図6】本発明の実施例6の絶縁ゲート半導体装置の断
面図
FIG. 6 is a sectional view of an insulated gate semiconductor device according to a sixth embodiment of the present invention.

【図7】本発明の実施例7の絶縁ゲート半導体装置の断
面図
FIG. 7 is a sectional view of an insulated gate semiconductor device according to a seventh embodiment of the present invention.

【図8】本発明の実施例8の絶縁ゲート半導体装置の断
面図
FIG. 8 is a sectional view of an insulated gate semiconductor device according to an eighth embodiment of the present invention.

【図9】本発明の実施例9の絶縁ゲート半導体装置の断
面図
FIG. 9 is a sectional view of an insulated gate semiconductor device according to a ninth embodiment of the present invention.

【図10】本発明の実施例10の絶縁ゲート半導体装置
の断面図
FIG. 10 is a sectional view of an insulated gate semiconductor device according to a tenth embodiment of the present invention.

【図11】従来のMOSFETの絶縁ゲート半導体装置の断面
FIG. 11 is a sectional view of a conventional MOSFET insulated gate semiconductor device.

【図12】従来のIGBTの絶縁ゲート半導体装置の断
面図
FIG. 12 is a cross-sectional view of a conventional IGBT insulated gate semiconductor device.

【符号の説明】[Explanation of symbols]

1、1A:電界緩和半導体領域 2:n-導電型のドリフト層 3:n+導電型のドレイン層 4:p導電型のボディ層 5:n+導電型のソース領域 6:p導電型のコレクタ層 7:n+導電型のエミッタ領域 8:第2電界緩和半導体領域 9:トレンチ型絶縁ゲート絶縁物層 10:ドレイン電極 11:ソース電極 12:コレクタ電極 13:エミッタ電極 14:トレンチ型絶縁ゲート電極 15:ターミネーション領域 19:ドレイン電極 24:n-導電型のドリフト層とp導電型のボディ層との
接合部 33:ドレイン領域 40:ボディ領域 69:トレンチ
1, 1A: electric field relaxation semiconductor region 2: n conductivity type drift layer 3: n + conductivity type drain layer 4: p conductivity type body layer 5: n + conductivity type source region 6: p conductivity type collector Layer 7: n + conductivity type emitter region 8: Second electric field relaxation semiconductor region 9: Trench type insulated gate insulator layer 10: Drain electrode 11: Source electrode 12: Collector electrode 13: Emitter electrode 14: Trench type insulated gate electrode 15: termination region 19: drain electrode 24: junction between n - conductivity type drift layer and p-conductivity type body layer 33: drain region 40: body region 69: trench

Claims (12)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 第1の導電型をもつ半導体基板、前記半
    導体基板上に設けられ、第1の導電型と反対の第2の導
    電型をもち、半導体基板との間に接合を形成する第2の
    導電型の半導体層、 前記の半導体層を貫通して前記半導体基板の一部までう
    がった少なくとも一つの凹部、 前記凹部の底部において前記半導体基板内に形成された
    第2の導電型の第1の半導体領域、 前記凹部の内表面に形成した絶縁層、 前記絶縁層によって前記基板及び前記半導体層と絶縁さ
    れて少なくとも一部が前記凹部内に設けられたゲート、 前記半導体層の中で前記絶縁層に囲まれた前記ゲートの
    周囲部の領域において前記第2の導電型の半導体層の表
    面から所定の深さまで形成された第1の導電型の第2の
    半導体領域、 前記第2の導電型の半導体層及び前記第2の半導体領域
    の上にこれらと導電的に設けた第1の電極、及び前記半
    導体基板の他の部分に設けた第2の電極、 を備えたことを特徴とする絶縁ゲート半導体装置。
    1. A semiconductor substrate having a first conductivity type, a semiconductor substrate provided on the semiconductor substrate, having a second conductivity type opposite to the first conductivity type, and forming a junction with the semiconductor substrate. A semiconductor layer of a second conductivity type, at least one recess penetrating the semiconductor layer to a part of the semiconductor substrate, and a second conductivity type second layer formed in the semiconductor substrate at a bottom of the recess. A semiconductor region, an insulating layer formed on an inner surface of the concave portion, a gate insulated from the substrate and the semiconductor layer by the insulating layer, at least a part of which is provided in the concave portion; A first conductive type second semiconductor region formed to a predetermined depth from a surface of the second conductive type semiconductor layer in a region around the gate surrounded by an insulating layer; Semiconductor layer and the second An insulated gate semiconductor device comprising: a first electrode provided on a semiconductor region and conductively provided with the first electrode; and a second electrode provided on another portion of the semiconductor substrate.
  2. 【請求項2】 前記半導体基板は、より高い導電率を持
    つ半導体層の上に形成した同じ導電型でそれより低い導
    電率の半導体層を有することを特徴とする請求項1記載
    の絶縁ゲート半導体装置。
    2. The insulated gate semiconductor according to claim 1, wherein the semiconductor substrate has a semiconductor layer of the same conductivity type and lower conductivity formed on the semiconductor layer having higher conductivity. apparatus.
  3. 【請求項3】 前記第2の半導体領域は前記半導体基板
    のうち前記第2の導電型の半導体層と接合を形成してい
    る部分よりも導電率が高いことを特徴とする請求項1記
    載の絶縁ゲート半導体装置。
    3. The semiconductor device according to claim 1, wherein said second semiconductor region has a higher conductivity than a portion of said semiconductor substrate which forms a junction with said second conductivity type semiconductor layer. Insulated gate semiconductor device.
  4. 【請求項4】 前記基板の前記接合をもつ面とは反対側
    の面に第2の導電型の層を設けたことを特徴とする請求
    項1記載の絶縁ゲート半導体装置。
    4. The insulated gate semiconductor device according to claim 1, wherein a layer of a second conductivity type is provided on a surface of said substrate opposite to a surface having said junction.
  5. 【請求項5】 半導体基板内に第2の導電型の第3の半
    導体領域を前記凹部から隔離して設けたことを特徴とす
    る請求項1記載の絶縁ゲート半導体装置。
    5. The insulated gate semiconductor device according to claim 1, wherein a third semiconductor region of a second conductivity type is provided in the semiconductor substrate so as to be separated from the recess.
  6. 【請求項6】 前記基板の前記接合をもつ面とは反対側
    の面に第2の導電型の層を設け、かつ半導体基板内に第
    2の導電型の領域を前記凹部から隔離して設けたことを
    特徴とする請求項4記載の絶縁ゲート半導体装置。
    6. A second conductivity type layer is provided on a surface of the substrate opposite to the surface having the junction, and a second conductivity type region is provided in the semiconductor substrate so as to be isolated from the recess. The insulated gate semiconductor device according to claim 4, wherein
  7. 【請求項7】 前記第2の電極が、前記半導体基板の上
    であって前記第1の電極から所定の距離を隔てた位置に
    設けられたことを特徴とする請求項1記載の絶縁ゲート
    半導体装置。
    7. The insulated gate semiconductor according to claim 1, wherein the second electrode is provided on the semiconductor substrate at a position separated from the first electrode by a predetermined distance. apparatus.
  8. 【請求項8】 前記半導体基板内に形成される第2の導
    電型の第1の半導体領域を、前記凹部の底部及び底部に
    つながる側部に設けたことを特徴とする請求項1記載の
    絶縁ゲート半導体装置。
    8. The insulation according to claim 1, wherein a first semiconductor region of the second conductivity type formed in the semiconductor substrate is provided on a bottom portion of the concave portion and a side portion connected to the bottom portion. Gate semiconductor device.
  9. 【請求項9】 第1の導電型をもつ半導体基板、 前記半導体基板上に設けられ、第1の導電型と反対の第
    2の導電型をもち、半導体基板との間に接合を形成する
    第2の導電型の半導体層、 前記の半導体層を貫通して前記半導体基板の一部までう
    がった少なくとも一つの凹部、 前記凹部の内表面に形成され、前記凹部の底部におい
    て、前記凹部の側面より厚さが大きい絶縁層、 前記絶縁層によって前記基板及び前記半導体層と絶縁さ
    れて少なくとも一部が前記凹部内に設けられたゲート、 前記半導体層の中で前記絶縁層に囲まれた前記ゲートの
    周囲部の領域において前記第2の導電型の半導体層の表
    面から所定の深さまで形成された第1の導電型の第2の
    半導体領域、 前記第2の導電型の半導体層及び前記第2の半導体領域
    の上にこれらと導電的に設けた第1の電極、及び前記半
    導体基板の他の部分に設けた第2の電極、 を備えたことを特徴とする絶縁ゲート半導体装置。
    9. A semiconductor substrate having a first conductivity type, a semiconductor substrate provided on the semiconductor substrate, having a second conductivity type opposite to the first conductivity type, and forming a bond with the semiconductor substrate. A semiconductor layer of conductivity type 2, at least one recess penetrating through the semiconductor layer to a part of the semiconductor substrate, formed on an inner surface of the recess, and at a bottom of the recess, from a side surface of the recess. An insulating layer having a large thickness, a gate insulated from the substrate and the semiconductor layer by the insulating layer and at least a part of which is provided in the concave portion; and a gate surrounded by the insulating layer in the semiconductor layer. A first conductive type second semiconductor region formed to a predetermined depth from a surface of the second conductive type semiconductor layer in a peripheral region, the second conductive type semiconductor layer, and the second conductive type semiconductor layer; Conduct these with the semiconductor area An insulated gate semiconductor device comprising: a first electrode electrically provided; and a second electrode provided on another portion of the semiconductor substrate.
  10. 【請求項10】 前記基板の前記接合をもつ面とは反対
    側の面に第2の導電型の層を設けたことを特徴とする請
    求項9記載の絶縁ゲート半導体装置。
    10. The insulated gate semiconductor device according to claim 9, wherein a second conductivity type layer is provided on a surface of said substrate opposite to a surface having said junction.
  11. 【請求項11】 前記凹部の内表面に形成した絶縁層
    は、前記凹部の底部の絶縁層の厚さが前記凹部の側面の
    厚さの約5ないし約20倍である請求項9又は10記載
    の絶縁ゲート半導体装置。
    11. The insulating layer formed on the inner surface of the recess, wherein the thickness of the insulating layer at the bottom of the recess is about 5 to about 20 times the thickness of the side surface of the recess. Insulated gate semiconductor device.
  12. 【請求項12】 前記凹部の底部に形成した絶縁層の厚
    さは約0.5ないし約2ミクロンであることを特徴とす
    る請求項9又は10記載の絶縁ゲート半導体装置。
    12. The insulated gate semiconductor device according to claim 9, wherein the thickness of the insulating layer formed at the bottom of the recess is about 0.5 to about 2 microns.
JP8331321A 1996-08-01 1996-12-11 Insulated gate semiconductor device Pending JPH1098188A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP20399296 1996-08-01
JP8-203992 1996-08-01
JP8331321A JPH1098188A (en) 1996-08-01 1996-12-11 Insulated gate semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8331321A JPH1098188A (en) 1996-08-01 1996-12-11 Insulated gate semiconductor device
PCT/JP1997/004538 WO1998026458A1 (en) 1996-12-11 1997-12-10 Insulated gate semiconductor device
EP97947874A EP0893830A4 (en) 1996-12-11 1997-12-10

Publications (1)

Publication Number Publication Date
JPH1098188A true JPH1098188A (en) 1998-04-14

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ID=26514225

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