JP2612040B2 - MOS-FET using β-SiC and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS-FET using β-SiC and a method of manufacturing the same, and particularly to a MOS-FET usable at a high temperature and a method of manufacturing the same.

[Related Art] In recent years, with the technical development of semiconductor devices, semiconductor devices such as ICs and LSIs have been used in various devices. MOS is one of the basic elements of such a semiconductor device.
・ FET (Metal Oxide Semiconductor ・ Field Effect Tra)
nsistor) and plays a very important role in various ICs and LSIs.

Here, a device structure and a manufacturing method of a conventional MOS-FET will be described with reference to FIG.

Various structures such as a vertical type and a horizontal type are conceivable as the element structure of the MOS-FET, and a horizontal type structure as shown in the figure is widely used as a basic element of IC and LSI.

Such a MOS-FET is an N-type or P-type Si substrate 30
Has a source region 32 and a drain region 34 of another conductivity type (P-type or N-type) on its upper surface. A region sandwiched between the source region 32 and the drain region 34 is a channel region 30a, and an oxide layer 36 as an electrical insulator is formed on the upper surfaces of the source region 32, the drain region 34, and the channel region 30a. Have been.

Further, a source electrode 38 is connected to the source region 32, and a drain electrode 40 is connected to the drain region 34. Further, a gate electrode 42 is formed above the channel region 30a via the oxide layer 36.

Then, by supplying a predetermined voltage to the gate electrode 42, the current flowing between the source region 32 and the drain region 34 is controlled.

On the other hand, such a MOS FET using a conventional Si semiconductor has been manufactured by the following method.

In other words, the semiconductor device is large enough to manufacture a semiconductor device first.
A single crystal of Si (silicon) is prepared and mixed with impurities such as boron and phosphorus to obtain a P-type or N-type. The production of the Si single crystal can be performed by a known method such as a pulling method or a floating method.

Next, an oxide layer (SiO ₂ ) 36 is formed on the upper surface of the substrate 30 made of the Si single crystal thus obtained. And this oxide layer
A portion of 36 is covered with a mask 44, and impurities are ion-implanted from above to form a source region 32 and a drain region 34 having a conductivity type different from that of the substrate 30 at a predetermined portion not covered by the mask 44. The upper part of the substrate 30 in the middle between the source region 32 and the drain region 34 thus formed becomes the channel region 30a.

Here, the source region is thus formed by ion implantation.
When the drain region 34 and the drain region 34 are formed, amorphization occurs in this portion. Therefore, recrystallization is performed by the thermal annealing treatment. This thermal annealing treatment is usually performed at a temperature of about 800 ° C.

Thereafter, part of the oxide layer 36 above the source region 32 and the drain region 34 is removed by etching or the like. And
A source electrode 38 and a drain electrode 40 connected to the source region 32 and the drain region 34 are formed through the removed portions. Further, the source electrode 38 and the drain electrode 40
A gate electrode 42 is formed in a portion corresponding to an upper part of the channel region 30a corresponding to the middle of the above.

A MOS-FET using a conventional Si substrate has been manufactured by such a method.

As described above, MOS / FETs made of Si semiconductors are widely used in various devices. For example, also in automobiles, semiconductor devices having many MOS FETs are used for various control circuits and the like.

However, engines, transmissions, and the like have not been used in spite of the expectation that their performance will be improved if semiconductor devices are installed around them and control is performed.
This is because these locations are hot, and conventional semiconductor devices usually use Si semiconductors. That is, the normal operating temperature range of ICs and LSIs using Si semiconductors has an upper limit of about 120 ° C., and cannot be used at higher temperatures. This is due to the physical property value of the Si semiconductor, which has a band gap (energy gap of the forbidden band) of 1.1 eV. Therefore, it is impossible to manufacture ICs and LSIs that can be used at high temperatures using Si semiconductors. Therefore, to develop a semiconductor device that can be used at a high temperature, it is necessary to use a semiconductor having a wide band gap other than a Si semiconductor.

On the other hand, the band gap of β-SiC (silicon carbide) semiconductor is 2.2 eV, which is wider than 1.1 eV of Si semiconductor. And β-SiC
Is a stable substance that has characteristics such as being hardly decomposed even at high temperatures and having low reactivity with other substances. Therefore, it is considered that ICs and LSIs using a β-SiC semiconductor can be used up to a high temperature of about 500 ° C., and β-SiC is considered to be suitable as a material for a semiconductor device that can operate at a high temperature.

However, it is extremely difficult to produce a single crystal of β-SiC, and in particular, a single crystal large enough to produce a semiconductor device cannot be obtained. Therefore, it has been difficult to manufacture a transistor or the like using a β-SiC semiconductor. However, recently, a single crystal of a β-SiC semiconductor has been obtained by a chemical vapor deposition method such that a semiconductor device can be manufactured. This is to grow a single crystal of β-SiC on a Si substrate at a temperature of about 1300 ° C. using hydrogen gas as a carrier gas and silane and propane gas as reaction gases. About this, for example, `` S.
Nishino et al “Epitaxial growth and electrical Cha
racteriatics of cubic SiC on silicon J.Appl.Phys.6
1 (10) .15 1987 P4889 ”.

Also, a prototype of a β-SiC MOS-FET using a β-SiC single crystal obtained by such a method is described in, for example, “Y. Kondo, e.
t.al “Experimental 3C-SiC MOSFET”, IEEE ELECTCTRON
DEVICE LETTERS.VOL.EDL-7.1986 P404 ".

The fields of application of semiconductor devices that can be used at high temperatures include not only the above-mentioned surroundings of engines in automobiles, but also around jet engines of aircraft, around reactors of nuclear reactors, and in the space industry such as artificial satellites. There are many industrial fields.

[Problem to be Solved by the Invention] As described above, there is a proposal for a MOS-FET using a β-SiC semiconductor. However, at the present stage, the development of a single element such as a MOS / FET as a basic element of an IC or an LSI has only been considered, and an M-type using β-SiC having sufficient characteristics has been studied.
OS / FET has not been manufactured yet. This is similar to the difficulty of producing a single crystal of β-SiC as described above,
This is because the processing is very difficult.

In other words, ICs and LSIs using a β-SiC semiconductor are considered to have the most appropriate structure as shown in FIG. 7 similar to the conventional example, but the β-SiC semiconductor has such a structure. Is difficult for the following reasons.

First, when a β-SiC semiconductor is used, source and drain regions having sufficient characteristics cannot be manufactured by using an ion implantation method. That is, when ions are implanted into a single crystal by ion implantation, the single crystal becomes amorphous. Therefore, in the case of a Si semiconductor, recrystallization is performed by thermal annealing as described above. In the case of Si, recrystallization can be performed at a temperature of about 800 ° C., so that thermal annealing can be performed without any trouble. However, in the case of a β-SiC single crystal, the temperature for recrystallization is usually as high as 1500 ° C. or higher. Therefore, when performing thermal annealing of the ion-implanted layer, it is necessary to set the temperature to this level. However, the softening point of the oxide film that electrically insulates the gate electrode is about 1400 ° C., and even for β-SiC single crystal, the temperature for thermal annealing must be performed at about 1300 ° C. or less. For this reason, thermal annealing becomes insufficient,
Recrystallization could not be performed sufficiently.

Even if thermal annealing is performed at a temperature of 1500 ° C. or more by taking measures to prevent the oxide film from rising in temperature, since Si atoms evaporate from the region that has been made amorphous by ion implantation, the desired source and drain regions can be obtained. Could not be formed.

As described above, an ion implantation method cannot be used as a method for forming the source and drain regions. Therefore, the source and drain regions must be formed by another method. As a method of forming the source and drain regions, besides ion implantation, (1) a method of forming by diffusion,
(2) A formation method by epitaxial growth is known.

Considering these, first, the formation method by diffusion cuts the already formed bond between Si and C,
There is a need for a step in which impurities are interrupted in the meantime, and then the broken bonds are recombined. That is, in the formation method by diffusion, it is necessary to perform recrystallization as in the case of ion implantation, and a temperature equivalent to that in the case of ion implantation is required. Therefore, as in the case of the ion implantation method,
The formation method by diffusion cannot be used for forming the source and drain regions in the β-SiC single crystal.

Next, the epitaxial method basically does not include a step of breaking the bond between Si and C. And a good PN junction at a temperature of about 1300 ° C (source and drain regions to the substrate)
Can be formed. Therefore, it is considered that a method of manufacturing a PN junction by an epitaxial method can be adopted. However, in the epitaxial method, since a PN junction is formed uniformly on a substrate provided in an epitaxial apparatus, it is impossible to manufacture a MOS-FET having a structure as shown in FIG.

Further, even if other means are used in addition to the epitaxial growth method, it is extremely difficult to manufacture a MOS-FET having a structure as shown in FIG. Therefore, β-SiC is
Although the material is very suitable for MOS-FETs, it cannot be used to produce MOS-FETs having sufficient characteristics, and such MOS-FETs are not known.

The present invention has been made to solve the above-described problems, and has as its object to provide a MOS-FET using β-SiC having sufficient characteristics even at a high temperature and a method of manufacturing the same. And

[Means for Solving the Problems] A MOS-FET using β-SiC according to the present invention comprises, as shown in FIG. 1 (F), a substrate made of a semiconductor and a substrate bonded to the substrate. In a MOS-FET having a source region and a drain region made of semiconductors of different conductivity types, a substrate 10 is formed of P-type β-SiC, and an N-type β layer having a source region 12 a and a drain region 12 b laminated on the substrate 10. -It is characterized by being formed by SiC.

That is, in the present invention, a P-type β-SiC single crystal is used as the substrate 10. Therefore, the source region 12
a, the drain region 12b can be formed of an N-type β-SiC layer, and these regions can have low resistance. Therefore, MOS-FET
As a result, sufficient characteristics can be exhibited. P-type β-Si
C generally has high resistance and cannot obtain sufficient characteristics.

The impurity concentration of the substrate using P-type β-SiC is 1 × 1
It is desirable to set it to 0 ¹⁸ / cm ³ or less. This is because if the impurity concentration is higher than this, the withstand voltage of the MOS / FET will decrease significantly,
This is because the sufficient function cannot be exhibited.

Further, in the present invention, an N-type β-SiC
The source region 12a and the drain region 12b made of are laminated. Therefore, the source region 12a and the drain region 12b can be formed by epitaxial growth. Therefore, the crystal structure of N-type β-SiC in the source region 12a and the drain region 12b can be made sufficiently good, and the operation characteristics as an element can be made good.

Furthermore, N other than the source region 12a and the drain region 12b
The type β-SiC layer can be removed by reactive ion etching, and a MOS-FET with excellent characteristics can be obtained. Note that the thickness of the N-type β-SiC layer is desirably 1 micrometer or less. This is because if the step in the gate portion is 1 micrometer or more, there are problems in terms of fabrication and reliability of the MOS-FET.

Next, as shown in FIGS. 1 (A) to 1 (F), a method for manufacturing a MOS-FET using β-SiC according to the present invention is shown in FIG. Forming a type β-SiC layer 12;
Regions other than the source and drain regions of the layer 12 are removed by reactive ion etching using gas plasma to form a source region 12a and a drain region 12b made of an N-type β-SiC layer with the channel region of the substrate interposed therebetween. And forming an oxide layer 16 on the upper surfaces of the source region 12a, the drain region 12b, and the channel region 10a, and a part of the portion of the oxide layer 16 located on the source region 12a and the drain region 12b. Removing and forming an electrode connection portion 24; a source electrode 18 connected to the source region 12a via the electrode connection portion 24; a drain electrode 20 connected to the drain region 12b via the electrode connection portion 24; and a channel region. Forming a gate electrode 22 provided on the upper portion 10a with the oxide layer 16 interposed therebetween.

Thus, according to the present invention, the source region 12a and the drain region 12b are formed on the substrate 10 of P-type β-SiC single crystal by N-type β-SiC.
-It is formed by epitaxially growing the SiC layer 12. Therefore, N-type β-
The SiC layer 12 can be formed uniformly.

The N-type β-SiC single crystal epitaxially grown on the P-type β-SiC single crystal substrate 10 has an impurity concentration of 1%.
× 10 ¹⁷ / cm ³ 〜1 × 10 ²⁰ / cm ³
The thickness should be less than micrometer. In addition, as the epitaxial growth method, a chemical vapor deposition method, an MBE method, or the like can be appropriately employed. Further, although the impurity concentration of the N-type β-SiC layer 12 does not need to be uniform in the layer, the surface concentration is required to obtain ohmic contact with the source electrode 18 and the drain electrode 20 and to reduce the operating resistance of the element. On the side, it is good to be at least 1 × 10 ¹⁷ / cm ³ or more.

Then, for the N-type β-SiC layer 12 laminated,
A predetermined portion is removed by reactive ion etching using gas plasma. That is, the N-type β-SiC layer other than the source region 12a and the drain region 12b is removed by reactive ion etching using gas plasma. Therefore, extremely high-precision processing, that is, a step of 1 μm or less can be accurately formed. And this makes it very difficult to process β-SiC
However, complicated patterns can be effectively produced.

It should be noted that so-called chemical etching, such as etching with chlorine gas at a temperature of 1000 ° C. or more, may be used as the etching, but cannot be applied because the processing accuracy cannot be sufficiently high.

It is preferable to remove the P-type β-SiC substrate 10 of about several thousand angstroms below the removed N-type β-SiC film 12 by reactive ion etching.

After this etching process, an oxide layer 16 having an appropriate thickness is formed. This may be performed, for example, by performing the process at a temperature of 1000 ° C. or more in an oxygen atmosphere. Also, the source region 12
a, a connection part 24 for connecting the source electrode 18 and the drain electrode 20 to a part of the oxide layer corresponding to the upper part of the drain region 12b.
The connection portion 24 may be formed by removing the oxide layer 16 by chemical etching or the like.

Further, the source electrode 18 connected to the source region 12a and the drain electrode 20 connected to the drain region 12b, and the gate electrode 22 are formed at a portion sandwiched between the two electrodes. Examples of the electrode material include polysilicon, platinum, and tungsten. , Aluminum or the like can be used, and this electrode can be formed by a vacuum evaporation method, a sputtering method, or the like. Further, the molding of each electrode may be performed by photolithography and an appropriate etching process.

If it is necessary to perform an appropriate thermal annealing process after the fabrication of the MOS / FET, this may be performed.

[Operation] Next, the operation of the MOS-FET using the prepared β-SiC will be described.

Since the operation of the MOS FET differs depending on the configuration of the electronic circuit used, the most general configuration is here, that is, the source electrode 18 and the substrate 10 as shown in FIG. The operation in the case where is given will be described.

When the potential of the gate electrode 22 is on the minus side of a predetermined threshold voltage, the channel region 10a below the gate electrode 22 remains P-type and the N-type drain region 12b
Since a positive potential is applied to the drain region 12b side and the reverse bias is applied to the P-type channel region 10a and the P-type channel region 10a, no drain current flows from the channel region 10a to the source region 12a. Similarly, since a reverse bias is applied between the drain region 12b and the P-type substrate 10 therebelow, no drain current flows.

On the other hand, the potential of the gate electrode 22 is changed to the plus side, and when the potential exceeds the threshold voltage, the β-SiC
An N-type inversion layer is formed in the layer. Therefore, the drain region
12b, the channel region 10a and the source region 12a are all connected by an N-type layer. As a result, the drain current flows to the source region 12a through the channel region 10a.

Thus, the drain current is controlled by the applied gate voltage. Therefore, M using β-SiC according to the present invention
In the OS-FET, the same transistor characteristics as those of the MOS-FET using a Si semiconductor can be obtained. And β-Si
C can exhibit high temperature properties.

[Effects of the Invention] As described above, a MOS transistor using β-SiC according to the present invention
According to the FET, when the gate voltage is equal to or lower than the threshold value, the drain current is reversely biased between the N-type drain region 12b and the P-type substrate 10 and can be effectively prevented. In particular, in the present invention, since the junction between the P-type substrate 10 and the N-type drain region 12b is formed by epitaxial growth, the crystallinity is good and the leakage current at the time of reverse bias is suppressed to a very small value. be able to. Therefore, the drain current can be effectively prevented.

Further, in the present invention, β-SiC is used. Therefore, the transistor is stable even at a high temperature, and good transistor characteristics can be maintained.

Example An example of the present invention will be described below. Substrate 10
The P-type β-SiC single crystal was formed on the Si substrate by a chemical vapor deposition method by a heteroepitaxial growth method. The outline of the crystal growth is as follows. First, a 3-inch Si substrate was placed on a carbon susceptor heated by high-frequency induction heating to about 1320 ° C., and in this state, 12 hydrogen / min, 5 cc silane, 3 cc propane, and 0.05 cc / min were used. Diborane gas was flowed into a quartz reaction tube provided with a carbon susceptor, and a P-type β-SiC single crystal was grown at a growth rate of 1.5 to 3.0 micrometers per hour for 3 hours.
As a result, a P-type β-SiC single crystal having a layer thickness of about 9 μm and an impurity concentration of 1 × 10 ¹⁶ / cm ^-3 to 1 × 10 ¹⁷ / cm ^-3 formed on the Si substrate is obtained. Then, using this P-type β-SiC single crystal as the substrate 10, a MOS • FET was manufactured.

First, an N-type β-SiC single crystal layer 12 was epitaxially grown on the P-type β-SiC substrate 10 by a chemical vapor deposition method to a thickness of about 2,000 Å to 5,000 Å (FIG. 1B). The crystal growth was performed at a growth temperature of about 1320 ° C. for about 20 minutes by flowing 121 hydrogen / min, 5 cc silane, and 3 cc propane gas per minute. Especially when no impurities are added, β
-The transmission type of the SiC layer is N-type. N-type β-SiC grown
The impurity concentration of the layer 12 is 1 × 10 ¹⁷ / cm ^{-3 to} 1.5 × 10 ¹⁷ / cm ^-3
It is.

Next, on the N-type β-SiC layer 12, an aluminum film serving as a mask at the time of reactive ion etching is formed to a thickness of about 5000 angstroms by a vacuum deposition method, and the source region 12a, The aluminum film other than the region on the drain region 12b was removed with phosphoric acid. Source area after resist removal
12a, the source region 12a is formed by plasma formed by discharging under a condition of a pressure of 4 Pa using a gas obtained by mixing 17% of carbon with CF ₄ (carbon tetrafluoride) gas using the aluminum film remaining on the drain 12b as a mask. N other than the drain region 12b
Β-SiC layer 12 and thousands of angstroms of P-type β-SiC
The single crystal substrate 10 was removed by etching. After etching, the resist and the aluminum film were removed, washed with diluted hydrofluoric acid, washed with pure water, and dried (FIG. 1C).

Next, an oxidation treatment was performed at 1100 ° C. for 2 hours in a wet oxygen atmosphere to form an oxide layer 16 of about 500 angstroms on the surface of the β-SiC single crystal (FIG. 1D). Source region using resist formed by photolithography as a mask
A portion of the oxide film 16 on the drain 12a and the drain 12b was removed by etching with hydrofluoric acid to form a connection portion 24 (FIG. 1E).

After removing the resist, an aluminum film having a thickness of about 1 micrometer was formed by a vacuum evaporation method. Further, a part of the aluminum film was removed by etching with phosphoric acid using a resist formed by photolithography as a mask, thereby forming a source electrode 18, a gate electrode 22, and a drain electrode 20. After the removal of the resist, annealing was performed at 450 ° C. for 20 minutes in a nitrogen atmosphere to produce a MOS-FET using β-SiC (FIG. 1F).

Also, N-type β-Si formed by etching and oxidation
The junction end face between the C layer 12 and the P-type substrate 10 can have such a flatness that electrolytic concentration does not occur by appropriately selecting the conditions of the reactive ion etching.

Further, defects generated in the crystal at the time of etching can be suppressed to such an extent that they can be removed when forming the oxide layer 16 of about several hundred angstroms. Therefore, N-type β-
The drain leak current flowing through the joint end face between the SiC layer 12 and the P-type substrate 10 can be made sufficiently small.

In this example, aluminum was used for each of the electrodes 18, 20, and 22. However, this was used for the sake of simplicity of the experiment, and the temperature was higher when polysilicon, silicide, or a refractory metal electrode was used. It goes without saying that it is advantageous when used.

Next, a MOS transistor using the β-SiC thus fabricated
An operation example of the FET will be described with reference to FIG. In this operation example, the source electrode 18 is grounded, and the drain electrode 20
In FIG. 2, the values of the drain voltage and the drain current with respect to the gate voltage when a voltage within the range of 0 to 5 V and -1 to 8 V are applied to the gate electrode 22 are observed by a curve tracer.

FIG. 3 shows typical characteristics of the fabricated MOS-FET at room temperature. It is clear from the figure that the dressing current changes depending on the gate voltage. When the gate voltage is equal to or lower than zero volt, almost no drain current is observed.
Therefore, MOS / FET with good characteristics without drain leakage current
It is understood that has been made. In addition, the same element
The characteristics at 400 ° C. are shown in FIG. Drain current can be seen when the gate voltage is less than zero volts, but 400 ° C
It is clear that the drain current shows a change depending on the gate voltage even at the temperature of, and the lateral type MOS with different conduction types of the source, drain, substrate and channel region
-For the first time, FET operation at 400 ° C was confirmed for FET.

For reference, the characteristics of a conventional MOS-FET using a Si semiconductor at room temperature and 400 ° C. by the same measurement method are shown in FIGS.
Shown in the figure. At room temperature, the transistor exhibits extremely good transistor characteristics, but at 400 ° C., the dressing leakage current is extremely large, and it is clear that the transistor does not function.

It should be noted that an example of a comparison between the embodiment of the present invention and the conventional example is represented as follows by numerical values.

(A) Example of the present invention Conditions Drain area 250 μm × 320 μm b, 400 ° C., Vd = 4 V, leakage current about 300 μA, 0.38 A / cm ² (B) Conventional example Condition Drain area 11 μm × 20 μm b, 400 ° C., Vd = 4 V, leakage current of about 4 mA, 1,800 A / cm ² or more, the superiority of the present invention is understood.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing an embodiment of a MOS-FET using β-SiC according to the present invention and a manufacturing method thereof. FIG. 2 is a circuit configuration at the time of measuring transistor characteristics of the MOS-FET according to the embodiment. FIG. 3, FIG. 3 is a characteristic diagram showing the transistor characteristics of the MOSFET in the embodiment at room temperature, FIG. 4 is a characteristic diagram showing the transistor characteristics of the MOSFET in the embodiment at 400 ° C., and FIG. FIG. 6 is an explanatory view showing a structure and a manufacturing method of a MOS-FET using a Si semiconductor of FIG. 6, FIG. 6 is a characteristic diagram showing transistor characteristics of the conventional MOS-FET at room temperature, and FIG. FIG. 4 is a characteristic diagram showing transistor characteristics of a FET at 400 ° C. 10 ... Substrate 12 ... N-type β-SiC layer 10a ... Channel region 12a ... Source region 12b ... Drain region 16 ... Oxide layer 18 ... Source electrode 20 ... Drain electrode 22 ... Gate electrode

Claims (2)

(57) [Claims] In a MOS-FET having a substrate made of a semiconductor and a source region and a drain region made of a semiconductor having a conductivity type different from that of a substrate bonded to the substrate, the substrate is formed of P-type β-SiC. And an N-type β in which a source region and a drain region are stacked on a substrate.
-A MOS-FET using β-SiC, which is formed by SiC. 2. A step of forming an N-type β-SiC layer by epitaxial growth on a substrate made of P-type β-SiC, and applying gas plasma to a region other than a region serving as a source and a drain of the N-type β-SiC layer. It is removed by the reactive ion etching used, and N is sandwiched across the channel region of the substrate.
Forming a source region and a drain region comprising a type β-SiC layer; forming an oxide layer on the upper surface of the source region, the drain region and the channel region; and forming an oxide layer on the source region and the drain region of the oxide layer. Removing a part of the located portion to form an electrode connection; a source electrode connected to the source region via the electrode connection; a drain electrode connected to the drain region via the electrode connection; and a channel region. Forming a gate electrode provided on top of the oxide layer via an oxide layer; and a method for manufacturing a MOS-FET using β-SiC.