JPH039534A - Field effect transistor using silicon carbide - Google Patents
Field effect transistor using silicon carbideInfo
- Publication number
- JPH039534A JPH039534A JP14561889A JP14561889A JPH039534A JP H039534 A JPH039534 A JP H039534A JP 14561889 A JP14561889 A JP 14561889A JP 14561889 A JP14561889 A JP 14561889A JP H039534 A JPH039534 A JP H039534A
- Authority
- JP
- Japan
- Prior art keywords
- silicon carbide
- field effect
- schottky junction
- metal
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 36
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 238000005468 ion implantation Methods 0.000 abstract description 7
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 19
- 239000013078 crystal Substances 0.000 description 17
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 13
- 108091006146 Channels Proteins 0.000 description 11
- 239000012535 impurity Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、炭化珪素を用いた電界効果トランジスタに関
し、さらに詳しくはソース領域および／またはドレイン
領域として炭化珪素と金属またはその化合物とのショッ
トキー接合を存する電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor using silicon carbide, and more particularly to a field effect transistor using silicon carbide as a source region and/or drain region. The present invention relates to a field effect transistor including a junction.
（従来の技術）
炭化珪素（ＳｉＣ）は広い禁制帯幅（２，２〜３．３ｅ
Ｖ）を有する半導体材料であって、熱的、化学的、おお
よび機械的に極めて安定であり、放射線）■傷にも強い
という優れた特徴を持っている。また、炭化珪素中にお
ける電子の飽和移動速度は、珪素（Ｓｉ）などの他の半
導体材料に比べて大きい。一般に、珪素のような従来の
半導体材料を用いた半導体装置は、特に高温、高出力駆
動、放射線照射。(Prior art) Silicon carbide (SiC) has a wide forbidden band width (2.2 to 3.3 e
V) It is a semiconductor material that is extremely stable thermally, chemically, and mechanically, and has the excellent characteristics of being resistant to radiation damage. Furthermore, the saturation transfer speed of electrons in silicon carbide is higher than that of other semiconductor materials such as silicon (Si). In general, semiconductor devices using conventional semiconductor materials such as silicon are susceptible to high temperatures, high power operation, and radiation exposure, especially.
高周波動作などの苛酷な条件下では使用が困難である。It is difficult to use under harsh conditions such as high frequency operation.
従って、炭化珪素を用いた半導体装置は。Therefore, semiconductor devices using silicon carbide.
このような苛酷な条件下でも使用し得る半導体装置とし
て広範な分野での利用が期待されている。As a semiconductor device that can be used even under such severe conditions, it is expected to be used in a wide range of fields.
しかしながら、大きな面積を有し、かつ高品質の炭化珪
素単結晶を、生産性を考慮した工業的規模で安定に供給
し得る結晶成長技術は確立されていない。それゆえ、炭
化珪素は、上述のような多くの利点および可能性を有す
る半導体材料であるにもかかわらず、それを用いた半導
体装置の実用化が阻まれている。However, no crystal growth technology has been established that can stably supply silicon carbide single crystals having a large area and high quality on an industrial scale in consideration of productivity. Therefore, although silicon carbide is a semiconductor material that has many advantages and possibilities as described above, the practical application of semiconductor devices using it has been hindered.
この問題点を解決するために、安価で入手の容易な珪素
単結晶基板上に、大きな面積を有する良質の炭化珪素単
結晶を、化学的気相成長法（ＣＶＤ法）で形成する方法
が提案されている（特開昭５９−２０３７９９号）。こ
の方法では、炭化珪素単結晶を気相成長させる際に適当
な不純物を添加すれば、得られた炭化珪素単結晶の伝導
型や不純物濃度を制御することができる。それゆえ、こ
の方法で得られた炭化珪素単結晶を用いて各種の半導体
装置が開発されている。これらのなかには、炭化珪素半
導体をチャネル形成層に用いた間Ｓ構造の反転型電界効
果トランジスタのような半導体装置も含まれている。To solve this problem, a method has been proposed in which a high-quality silicon carbide single crystal with a large area is formed by chemical vapor deposition (CVD) on an inexpensive and easily available silicon single crystal substrate. (Japanese Unexamined Patent Publication No. 59-203799). In this method, by adding an appropriate impurity when growing a silicon carbide single crystal in a vapor phase, the conductivity type and impurity concentration of the obtained silicon carbide single crystal can be controlled. Therefore, various semiconductor devices have been developed using silicon carbide single crystals obtained by this method. These include semiconductor devices such as inverted field effect transistors with an S structure using a silicon carbide semiconductor for a channel forming layer.
一般に、 ＭＯ５反転型電界効果トランジスタにおいて
は、半導体基板またはその上に形成された半ス領域およ
びドレイン領域を設けなければならない。つまり、Ｐ型
のチャネル形成層を用いたｎチャネル反転型の場合には
、該ｐ型チャネル形成層にｎ型のソース領域およびドレ
イン領域を形成する必要があり、逆にｎ型のチャネル形
成層を用いたｐ−チャネル反転型の場合には、該ｎ型チ
ャネル形成層にｐ型のソース領域およびドレイン領域を
形成する必要がある。このような電界効果トランジスタ
が良好な素子特性を示すためには、そのソース領域およ
びドレイン領域が２次のような２つの条件を満足する必
要がある。第１に、リーク電流を低減させるために、ソ
ース領域およびドレイン領域とチャネル形成層とのｐｎ
接合が良好な特性を有さなければならない。第２に、ト
ランジスタのオン抵抗を低下させるために、ソース領域
およびドレイン領域自体の抵抗、ならびにこれらの領域
と配線用金属との間の接触抵抗が充分に小さくなければ
ならない。Generally, MO5 inverted field effect transistors must have a half region and a drain region formed in or on a semiconductor substrate. In other words, in the case of an n-channel inversion type using a P-type channel forming layer, it is necessary to form an n-type source region and a drain region in the p-type channel forming layer; In the case of a p-channel inversion type using , it is necessary to form a p-type source region and a p-type drain region in the n-type channel forming layer. In order for such a field effect transistor to exhibit good device characteristics, its source region and drain region must satisfy two conditions such as quadraticity. First, in order to reduce leakage current, the pn
The bond must have good properties. Second, in order to reduce the on-resistance of the transistor, the resistance of the source and drain regions themselves and the contact resistance between these regions and the wiring metal must be sufficiently small.
（発明が解決しようとする課題）
通常、チャネル形成層にソース領域およびドレイン領域
を形成するには、不純物熱拡散法またはイオン注入法が
用いられている。チャネル形成層が珪素からなる半導体
装置の場合、これらの方法は、いずれも有用であり、す
でにデバイスプロセス技術として確立されている。これ
に対し、チャネル形成層が炭化珪素からなる半導体装置
の場合には、以下の理由から、これらの方法は適当では
ない。まず、不純物熱拡散法では、炭化珪素中における
不純物の拡散係数が小さいので、 １，６００″Ｃ以上
の高い拡散温度が必要である。従って、不純物濃度を制
御することが困難であり、しかも用いた半導体基板やチ
ャネル形成層が劣化するおそれがある。他方、イ・オン
注入法の場合には、炭化珪素中に注入された不純物は、
比較的安定に存在しており、そのイオン化の割合が小さ
い。従って。(Problems to be Solved by the Invention) Generally, an impurity thermal diffusion method or an ion implantation method is used to form a source region and a drain region in a channel forming layer. In the case of a semiconductor device in which the channel forming layer is made of silicon, all of these methods are useful and have already been established as device process techniques. On the other hand, in the case of a semiconductor device in which the channel forming layer is made of silicon carbide, these methods are not suitable for the following reasons. First, in the impurity thermal diffusion method, the diffusion coefficient of impurities in silicon carbide is small, so a high diffusion temperature of 1,600"C or more is required. Therefore, it is difficult to control the impurity concentration, and it is difficult to use. On the other hand, in the case of ion implantation, impurities implanted into silicon carbide may deteriorate.
It exists relatively stably, and its ionization rate is small. Therefore.
チャネル形成層に設けたソース領域およびドレイン領域
の抵抗が充分に低下しない。また、イオン注入法では、
充分良好な特性を有するｐｎ接合が得られない。それゆ
え、現在開発されている炭化珪素を用いたＭＯ５型電界
効果トランジスタは、リーク電流が大きいことやオン抵
抗が大きいことが問題となり実用化されるまでには至っ
ていない。The resistance of the source region and drain region provided in the channel forming layer is not sufficiently reduced. In addition, in the ion implantation method,
A pn junction with sufficiently good characteristics cannot be obtained. Therefore, currently developed MO5 field effect transistors using silicon carbide have problems such as large leakage current and large on-resistance, and have not been put into practical use.
本発明は上記従来の問題点を解決するものであり、その
目的とするところは、リーク電流およびオン抵抗が大幅
に低減され、良好な素子特性を有する炭化珪素を用いた
電界効果トランジスタを提供することにある。The present invention solves the above-mentioned conventional problems, and its purpose is to provide a field effect transistor using silicon carbide, which has significantly reduced leakage current and on-resistance, and has good device characteristics. There is a particular thing.
（課題を解決するための手段および作用）本発明は、炭
化珪素からなるチャネル形成層に形成されたソース領域
およびドレイン領域を有する電界効果トランジスタであ
って、該ソース領域およびドレイン領域の少なくとも一
方が、該チャネル形成層を構成する炭化珪素と、金属ま
たはその化合物とのショットキー接合で形成されており
そのことにより上記目的が達成される。(Means and effects for solving the problems) The present invention provides a field effect transistor having a source region and a drain region formed in a channel forming layer made of silicon carbide, wherein at least one of the source region and the drain region is formed in a channel forming layer made of silicon carbide. The channel forming layer is formed by a Schottky junction between silicon carbide and a metal or a compound thereof, thereby achieving the above object.
電界効果トランジスタのリーク電流を低減するためには
、ｐｎ接合だけでなく、ｐｎ接合と同様に整流特性を示
すショットキー接合を用いることができる。ショットキ
ー接合は、炭化珪素半導体の成長層表面に金属薄膜を蒸
着法などにより形成するか、あるいは該金Ｂ薄膜をさら
に該炭化珪素半導体層と反応させて該金属の化合物から
なる薄膜を形成することにより、容易に得られる。この
場合、イオン注入法などとは異なり、炭化珪素半導体層
自体が変化しないので、上記のショットキ−接合は、イ
オン注入によるｐｎ接合に比べて良好な整流特性を有す
る。また、ショットキー接合を形成するための金属は、
一般に、その抵抗率が半導体に比べてはるかに小さく、
シかも配線材料の金属との接触抵抗が充分に小さい。従
って、ショットキー接合を用いれば、トランジスタのオ
ン抵抗を充分に低下させることができる。In order to reduce the leakage current of a field effect transistor, it is possible to use not only a pn junction but also a Schottky junction that exhibits rectifying characteristics similar to a pn junction. A Schottky junction is formed by forming a metal thin film on the surface of a silicon carbide semiconductor growth layer by a vapor deposition method, or by further reacting the gold B thin film with the silicon carbide semiconductor layer to form a thin film made of a compound of the metal. can be easily obtained. In this case, unlike the ion implantation method, the silicon carbide semiconductor layer itself does not change, so the Schottky junction has better rectification characteristics than a pn junction formed by ion implantation. In addition, the metal for forming the Schottky junction is
In general, its resistivity is much lower than that of semiconductors,
Moreover, the contact resistance between the wiring material and the metal is sufficiently small. Therefore, by using a Schottky junction, the on-resistance of a transistor can be sufficiently reduced.
ショットキー接合を形成するための金属またはその化合
物は、炭化珪素とショットキー接合を形成し得るもので
あればよく、白金（ｐｔ）や金（Ａｕ）などの金属また
はその化合物（例えば、該金属と珪素や炭素とを含む化
合物）が挙げられる。The metal or its compound for forming a Schottky junction may be any metal as long as it can form a Schottky junction with silicon carbide, and metals such as platinum (PT) and gold (Au) or their compounds (for example, the metal and silicon and carbon).
（実施例） 以下に２本発明の実施例について説明する。(Example) Two embodiments of the present invention will be described below.
第１図（ａ）は９本発明の炭化珪素半導体装置の一例で
あるｐ−チャネル反転型のＭＯＳ電界効果トランジスタ
（ＭＯＳＦＥＴ）を示す。このＭＯＳＦＥＴは以下のよ
うにして作製された。FIG. 1(a) shows a p-channel inversion type MOS field effect transistor (MOSFET) which is an example of the silicon carbide semiconductor device of the present invention. This MOSFET was manufactured as follows.
まず、第１図（ｂ）に示すように、 ＣＶＤ法により。First, as shown in FIG. 1(b), by the CVD method.
Ｓｉ単結晶基板１上にβ−５ｉＣ単結晶層２（層厚約１
０μｍ）を成長させて、チャネル形成層とした。A β-5iC single crystal layer 2 (layer thickness approximately 1
0 μm) was grown to form a channel forming layer.
原料ガスとしては、シラン（ＳｉＨｍ）ガスとプロパン
（Ｃ：ＩＨｌｌ）ガスとを用いた。気相成長の間に不純
物のドープは行わなかったが、得られたβ−５ｉＣ単結
晶Ｎ２のキャリア濃度は２ ＸＩＯｌｂｃｍ−３であり
。Silane (SiHm) gas and propane (C:IHll) gas were used as raw material gases. Although no impurity doping was performed during the vapor phase growth, the carrier concentration of the obtained β-5iC single crystal N2 was 2XIOlbcm-3.
伝導型はｎ型であった。The conductivity type was n-type.
続いて、 ＣＶＤ法またはプラズマＣＶＤ法によりβ−
５ｉＣ単結晶層２上にＳｉＯ□膜を形成した。次いで、
ホトリソグラフィーを用いて、 ５ｉＯｚ膜の素子形成
領域に対応する部分をエツチングにより開口し、フィー
ルド絶縁膜３とした（第１図（Ｃ））。なお、エツチン
グにはフッ化水素（ＩＩＦ）溶液を用いた。そして、酸
素雰囲気下、約１，１００°Ｃにて３時間の熱酸化を行
うことにより、β−５ｉＣ単結晶層２上に熱酸化膜１１
（膜厚的５０μｍ）を形成した後。Subsequently, β-
A SiO□ film was formed on the 5iC single crystal layer 2. Then,
Using photolithography, a portion of the 5iOz film corresponding to the element formation region was etched to form a field insulating film 3 (FIG. 1(C)). Note that a hydrogen fluoride (IIF) solution was used for etching. Then, by performing thermal oxidation for 3 hours at approximately 1,100°C in an oxygen atmosphere, a thermal oxide film 11 is formed on the β-5iC single crystal layer 2.
(film thickness: 50 μm).
さらにＣＶＤ法により、熱酸化膜１１上に、リン（Ｐ）
をドープした多結晶Ｓｉ膜１２ （膜厚的５００ ｎｍ
）を形成した。Furthermore, by CVD method, phosphorus (P) is added on the thermal oxide film 11.
Polycrystalline Si film 12 doped with
) was formed.
次いで、第１図（ｄ）に示すように、ホトリソグラフィ
ーを用いて、ゲート形成用レジストパターン１３（長さ
５μｍ）を形成した後、ソース領域とドレイン領域とに
対応する部分の熱酸化膜１１および多結晶Ｓｉ膜１２を
エツチングにより開口してゲート絶縁膜４およびゲート
電極５を形成した。さらに。Next, as shown in FIG. 1(d), a resist pattern 13 for gate formation (5 μm in length) is formed using photolithography, and then a thermal oxide film 11 is formed in the portions corresponding to the source and drain regions. Then, polycrystalline Si film 12 was opened by etching to form gate insulating film 4 and gate electrode 5. moreover.
反応性イオンエツチングを用いて、露出したβＳｉＣ単
結晶層２の表面部分を２００ ｎｍだけエツチングした
後１表面全体に白金（ｐｔ）を電子ビーム蒸着すること
により、Ｐｔ薄膜１４（膜厚１１００ｎ ）を形成した
（第１図（ｄ））。そして、窒素雰囲気中、約２００°
Ｃにて２０分間の熱アニール処理を行うことにより、
ＳｉＣとｐｔとを反応させて、シリサイド膜６および７
を形成した（第１図（ｅ））。これらのシリサイド膜６
および７は、β−５ｉＣ単結晶層２を構成するｎ型Ｓｉ
Ｃとショットキー接合を形成し、それぞれソース領域８
およびドレイン領域９を与える。After etching the exposed surface portion of the βSiC single crystal layer 2 by 200 nm using reactive ion etching, a Pt thin film 14 (thickness: 1100 nm) is formed by electron beam evaporation of platinum (PT) over the entire surface. (Fig. 1(d)). Then, in a nitrogen atmosphere, about 200°
By performing thermal annealing treatment at C for 20 minutes,
Silicide films 6 and 7 are formed by reacting SiC and PT.
was formed (Fig. 1(e)). These silicide films 6
and 7 are n-type Si constituting the β-5iC single crystal layer 2.
form a Schottky junction with C, and source regions 8 and 8, respectively.
and drain region 9.
次いで、ゲート電極５の上方に形成されたＰｔ薄膜１２
はレジストパターン１３と共に除去し、フィールド絶縁
膜３およびゲート絶縁膜４の表面上に形成されたＰｔ薄
膜１２はエツチングにより除去した。Next, a Pt thin film 12 formed above the gate electrode 5
was removed together with the resist pattern 13, and the Pt thin film 12 formed on the surfaces of the field insulating film 3 and gate insulating film 4 was removed by etching.
なお、エツチングには王水を用いた。最後に、配線材料
としてアルミニウム（ＡＩ）を真空蒸着した後、ホトリ
ソグラフィーを用いて、配線電極ＩＯを形成することに
より、第１図（ａ）に示すようなｐチャネル反転型ＭＯ
ＳＦＥＴを得た。Note that aqua regia was used for etching. Finally, after vacuum-depositing aluminum (AI) as a wiring material, a wiring electrode IO is formed using photolithography to form a p-channel inverted MO as shown in FIG. 1(a).
I got SFET.
比較のために、 Ｓｉ単結晶基板上にｎ型β−３ｉＣ単
結晶層を成長させてチャネル形成層とし、該チャネル形
成層に例えばホウ素（Ｂ）をイオン注入することに・よ
り、ｎ型のソース領域およびトレイン領域を設けた従来
のｐ−チャネル反転型ＭＯ５ＦＩＥＴを作製した。For comparison, an n-type β-3iC single-crystal layer was grown on a Si single-crystal substrate to serve as a channel-forming layer, and boron (B), for example, was ion-implanted into the channel-forming layer. A conventional p-channel inverted MO5FIET with a source region and a train region was fabricated.
このようにして得られた本実施例のＭＯ５Ｉ’［ＥＴお
よび従来のＭＯＳＦＥＴを、トランジスタ特性（ドレイ
ン電流−ドレイン電圧特性）について調べた。その結果
をそれぞれ第２図および第３図に示す。この図から明ら
かなように９本実施例のＭＯＳＦＥＴでは。The transistor characteristics (drain current-drain voltage characteristics) of the thus obtained MO5I'[ET of this example and the conventional MOSFET were investigated. The results are shown in FIGS. 2 and 3, respectively. As is clear from this figure, in the MOSFET of the 9th embodiment.
ソース領域およびドレイン領域が、チャネル形成層を構
成する炭化珪素と、白金のシリサイドとのショットキー
接合で形成されているので、従来のＭＯＳＦＥＴに比べ
てリーク電流が大幅に低減され、ドレイン電流の良好な
飽和を示すトランジスタ特性が得られた。例えば、オフ
時（ゲート電圧がＯＶ）におけるリーク電流を比較する
と、ドレイン電圧が一５■の場合、従来のＭＯＳＦＥＴ
では２０μ八であったのに対し１本実施例のＭＯＳＦＥ
Ｔでは０．１μ八であった。また、オン時（ゲート電圧
が一５Ｖ）におけるＭＯＳＦＥＴの内部抵抗、すなわち
オン抵抗を比較すると、従来のＭＯＳＦＥＴでは２にΩ
であったのに対し１本実施例のＭＯＳＦＥＴでは４００
Ωであり、オン抵抗が大幅に低下していることがわかっ
た。Since the source region and drain region are formed by a Schottky junction between silicon carbide that constitutes the channel forming layer and platinum silicide, leakage current is significantly reduced compared to conventional MOSFETs, and drain current is improved. Transistor characteristics showing saturation were obtained. For example, when comparing the leakage current when off (gate voltage is OV), when the drain voltage is 15μ, the conventional MOSFET
In this case, the MOSFE of this embodiment was 20 μ8.
In T, it was 0.1μ8. Also, when comparing the internal resistance of the MOSFET when it is on (gate voltage - 5V), that is, the on-resistance, it is found that the conventional MOSFET has a resistance of 2 Ω.
On the other hand, in the MOSFET of this example, it was 400
It was found that the on-resistance was significantly reduced.
なお１本実施例では、ｎ型ＳｉＣを用いたｐ−チャネル
反転型ＭＯＳＦＥＴの作製を例示したが１本発明はｐ型
ＳｉＣおよびそれとショットキー接合を形成する金属ま
たはその化合物を用いたｎ−チャネル反転型ＭＯＳＦＥ
Ｔにも適用することができる。In this example, the fabrication of a p-channel inverted MOSFET using n-type SiC was exemplified, but the present invention is directed to an n-channel MOSFET using p-type SiC and a metal or a compound thereof that forms a Schottky junction with it. Inverted type MOSFE
It can also be applied to T.
（発明の効果）
本発明によれば、ソース領域および／またはドレイン領
域として、チャネル形成層を構成する炭化珪素と金属ま
たはその化合物とのショットキー接合を用いているため
、リーク電流およびオン抵抗が大幅に低減され、良好な
素子特性を有する炭化珪素を用いた電界効果トランジス
タが得られる。(Effects of the Invention) According to the present invention, since a Schottky junction between silicon carbide constituting the channel forming layer and a metal or a compound thereof is used as the source region and/or drain region, leakage current and on-resistance are reduced. A field effect transistor using silicon carbide can be obtained which has a significantly reduced amount of heat and good device characteristics.
このような電界効果トランジスタは、珪素のような他の
半導体材料を用いた電界効果トランジスタは、珪素のよ
うな他の半導体材料を用いた電界効果トランジスタでは
使用が困難な条件下（例えば。Such field effect transistors can be used under conditions that make field effect transistors using other semiconductor materials such as silicon difficult to use (e.g.
高温、高出力駆動、高周波動作、放射線照射など）にお
いても使用が可能な電界効果トランジスタとして有用で
ある。It is useful as a field effect transistor that can be used even at high temperatures, high output drive, high frequency operation, radiation irradiation, etc.
−（−図ＩＬＩ旧創燻悦班
第１図（ａ）〜（ｅ）は本発明の一実施例であるｐ−チ
ャネル反転型ＭＯＳ電界効果トランジスタの製造工程を
説明するための断面図、第２図は該電界効果トランジス
タのドレイン電流−ドレイン電圧特性を示すグラフ、第
３図はイオン注入法を用いて作製された従来のｐ−チャ
ネル反転型ＭＯＳ電界効果トランジスタのドレイン電流
−ドレイン電圧特性を示すグラフである。-(-Figure ILI Old Soukouetsu Group Figures 1 (a) to (e) are cross-sectional views for explaining the manufacturing process of a p-channel inversion type MOS field effect transistor, which is an embodiment of the present invention. Figure 2 is a graph showing the drain current-drain voltage characteristics of the field effect transistor, and Figure 3 is a graph showing the drain current-drain voltage characteristics of a conventional p-channel inversion type MOS field effect transistor manufactured using the ion implantation method. This is a graph showing.
■・・・Ｓｉ単結晶基板、２・・・β−３ｉＣ単結晶層
、３・・・フィールド絶縁膜、４・・・ゲート絶縁膜、
５・・・ゲート電極、６，７・・・シリサイド膜、８・
・・ソース領域、９・・・ドレイン領域、１０・・・配
線電極、 １１・・・熱酸化膜、１２・・・多結晶Ｓｉ
膜、 １３・・・レジストパターン。■...Si single crystal substrate, 2...β-3iC single crystal layer, 3...Field insulating film, 4...Gate insulating film,
5... Gate electrode, 6,7... Silicide film, 8.
... Source region, 9... Drain region, 10... Wiring electrode, 11... Thermal oxide film, 12... Polycrystalline Si
Film, 13...Resist pattern.
１４・・・ＰＬ薄膜。14...PL thin film.
以 上Below Up
Claims (1)
ス領域およびドレイン領域を有する電界効果トランジス
タであって、 該ソース領域およびドレイン領域の少なくとも一方が、
該チャネル形成層を構成する炭化珪素と、金属またはそ
の化合物とのショットキー接合で形成される、電界効果
トランジスタ。[Scope of Claims] 1. A field effect transistor having a source region and a drain region formed in a channel forming layer made of silicon carbide, wherein at least one of the source region and the drain region comprises:
A field effect transistor formed by a Schottky junction between silicon carbide constituting the channel forming layer and a metal or a compound thereof.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14561889A JPH0770726B2 (en) | 1989-06-07 | 1989-06-07 | Field effect transistor using silicon carbide |
| US07/759,933 US5216264A (en) | 1989-06-07 | 1991-09-16 | Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14561889A JPH0770726B2 (en) | 1989-06-07 | 1989-06-07 | Field effect transistor using silicon carbide |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH039534A true JPH039534A (en) | 1991-01-17 |
| JPH0770726B2 JPH0770726B2 (en) | 1995-07-31 |
Family
ID=15389193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14561889A Expired - Fee Related JPH0770726B2 (en) | 1989-06-07 | 1989-06-07 | Field effect transistor using silicon carbide |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770726B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459107A (en) * | 1992-06-05 | 1995-10-17 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
| US5612260A (en) * | 1992-06-05 | 1997-03-18 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
| JP2006024880A (en) * | 2004-06-09 | 2006-01-26 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2006303532A (en) * | 2000-07-11 | 2006-11-02 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
-
1989
- 1989-06-07 JP JP14561889A patent/JPH0770726B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459107A (en) * | 1992-06-05 | 1995-10-17 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
| US5612260A (en) * | 1992-06-05 | 1997-03-18 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
| US5629531A (en) * | 1992-06-05 | 1997-05-13 | Cree Research, Inc. | Method of obtaining high quality silicon dioxide passivation on silicon carbide and resulting passivated structures |
| JP2006303532A (en) * | 2000-07-11 | 2006-11-02 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP2006024880A (en) * | 2004-06-09 | 2006-01-26 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0770726B2 (en) | 1995-07-31 |
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