CN104576766A - SiC MOS capacitor of Al2O3/LaAlO3/SiO2 stacking gate medium layer and manufacturing method - Google Patents
SiC MOS capacitor of Al2O3/LaAlO3/SiO2 stacking gate medium layer and manufacturing method Download PDFInfo
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- CN104576766A CN104576766A CN201510007165.6A CN201510007165A CN104576766A CN 104576766 A CN104576766 A CN 104576766A CN 201510007165 A CN201510007165 A CN 201510007165A CN 104576766 A CN104576766 A CN 104576766A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title abstract 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 title abstract 5
- 239000003990 capacitor Substances 0.000 title abstract 5
- 229910052681 coesite Inorganic materials 0.000 title abstract 5
- 229910052593 corundum Inorganic materials 0.000 title abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 title abstract 5
- 239000000377 silicon dioxide Substances 0.000 title abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 title abstract 5
- 229910052682 stishovite Inorganic materials 0.000 title abstract 5
- 229910052905 tridymite Inorganic materials 0.000 title abstract 5
- 229910001845 yogo sapphire Inorganic materials 0.000 title abstract 5
- 229910002244 LaAlO3 Inorganic materials 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000007704 transition Effects 0.000 claims abstract description 18
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 51
- 238000000137 annealing Methods 0.000 claims description 34
- 230000006835 compression Effects 0.000 claims description 26
- 238000007906 compression Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 13
- 238000001816 cooling Methods 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 239000003595 mist Substances 0.000 claims description 6
- 238000003949 trap density measurement Methods 0.000 abstract description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 120
- 239000008367 deionised water Substances 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000009835 boiling Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005527 interface trap Effects 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000004506 ultrasonic cleaning Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- BVKZGUZCCUSVTD-UHFFFAOYSA-L Carbonate Chemical compound [O-]C([O-])=O BVKZGUZCCUSVTD-UHFFFAOYSA-L 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a SiC MOS capacitor of an Al2O3/LaAlO3/SiO2 stacking gate medium layer and a manufacturing method. According to the capacitor, a SiC substrate is a heavy-doped SiC substrate layer, and a light-doped SiC epitaxial layer is arranged on the SiC substrate layer. The stacking gate medium layer comprises a lower SiO2 transition layer, an LaAlO3 layer and an Al2O3 covering layer. The lower SiO2 transition layer is arranged on the SiC epitaxial layer, the LaAlO3 layer is arranged on the lower SiO2 transition layer and provided with the Al2O3 covering layer, and a positive electrode and a negative electrode are connected with the surface of the Al2O3 covering layer and the back surface of the SiC substrate respectively. According to the SiC MOS capacitor of the stacking gate medium layer, the interface state density and boundary trap density are lowered, the MOS channel mobility is increased, gate leakage current is reduced, the voltage endurance capability of the medium layer is improved, and the quality and reliability of the SiC MOS capacitor are improved.
Description
Technical field
The present invention relates to a kind of SiC mos capacitance and manufacture method thereof, particularly relate to a kind of Al
2o
3/ LaAlO
3/ SiO
2the SiC mos capacitance of stacking gate dielectric layer and manufacture method thereof.
Background technology
Along with the development of microelectric technique and power electronic technology, the performance requirement that practical application works under the conditions such as high temperature, high power, high frequency to device is more and more higher, the first generation semi-conducting material of Si representative and be that the second generation semi-conducting material application in these areas of representative occurs bottleneck with GaAs.Carborundum (SiC) material, as one of the Typical Representative of third generation semiconductor material with wide forbidden band, its energy gap is large, critical breakdown electric field is high, and there is the performances such as high heat conductance, high electron saturation velocities and high Flouride-resistani acid phesphatase, become one of primary semiconducting material manufacturing high temperature, high power, high frequency and Flouride-resistani acid phesphatase device, therefore one of current research focus becoming microelectronics technology for aspects such as SiC material, device and techniques.
SiC material can by the method high-quality SiO of direct growth on sic substrates of thermal oxidation
2dielectric layer, therefore, SiO
2/ SiC MOS device becomes the Main way of current SiC device Study and appliance, such as SiC MOSFET, IGBT etc.But, SiO
2there is following shortcoming in/SiC MOS device: first at present, and surface of SiC forms SiO by dry-oxygen oxidation compared with Si material
2suitable slow of speed, add process costs, simultaneously SiO
2thickness can not grow too thick.Secondly, a large amount of C bunches that stay after SiC thermal oxidation can increase oxide layer and interface trap, make SiO
2the interface trap density of/SiC is usually than SiO
2interface trap density height 1-2 order of magnitude of/Si, high interface trap density can reduce the mobility of charge carrier greatly, causes conducting resistance to increase, and power loss increases.At present, industry scientific research scholar is by adopting surface of SiC nitrogenize preliminary treatment, nitrogen oxides, the technological process control such as N source or H source annealing in process, SiO
2the interface quality of/SiC and overall permanence have had certain lifting, but and SiO
2/ Si interface quality is compared to appoint no small gap.
In addition, for SiO
2/ SiC MOS device, according to Gauss theorem (k
siCe
siC=k
oxidee
oxide), when SiC (k=9.6-10) reaches its critical breakdown electric field (-3MV/cm), SiO
2(k=3.9) electric field in dielectric layer will reach 7.4-7.7MV/cm, and so high electric field will seriously reduce the reliability of oxide layer.Therefore, high-g value is adopted to replace SiO
2as gate dielectric layer, research hafnium is particularly important at the application and research of SiC MOS device.Current Al
2o
3, HfO
2, AlN and ZrO
2had certain research Deng hafnium at SiCMOS, but high K medium directly replaces SiO
2make the interface state density of medium and SiC substrate comparatively large, oxide traps density and leakage current are also larger.
Summary of the invention
The object of the invention is to the object of the invention is to the deficiency for above-mentioned prior art, provide a kind of Al
2o
3/ LaAlO
3/ SiO
2the SiC mos capacitance of stacking gate dielectric layer and manufacture method thereof, to reduce interface state density and bound trap density, increase MOS channel mobility, reduce gate leak current, and improve the voltage endurance capability of dielectric layer further, improve the quality of SiC mos capacitance and strengthen its reliability.
For achieving the above object, the invention provides a kind of Al
2o
3/ LaAlO
3/ SiO
2the SiC mos capacitance of stacking gate dielectric layer, the SiC mos capacitance of described stacking dielectric layer comprises: SiC substrate, SiC epitaxial layer, stacking gate dielectric layer and positive and negative electrode;
Described SiC substrate is provided with SiC epitaxial layer;
Described stacking gate dielectric layer comprises lower floor SiO
2transition zone, LaAlO
3layer and Al
2o
3cover layer; Described SiC epitaxial layer is provided with lower floor SiO
2transition zone, described lower floor SiO
2transition zone is provided with described LaAlO
3layer, described LaAlO
3layer is provided with Al
2o
3cover layer;
Described positive and negative electrode respectively with Al
2o
3tectal surface is connected with the back side of SiC substrate.
Described SiC substrate is heavily doped SiC substrate layer, and described SiC epitaxial layer is lightly doped SiC epitaxial layer
Further, described SiC epitaxial layer thickness is 5-100 μm, and doping content is 1 × 10
15-5 × 10
16cm
-3.
Further, described lower floor SiO
2the thickness of transition zone is 1-30nm.
Further, described LaAlO
3the thickness of layer is 5nm-100nm.
Further, described Al
2o
3tectal thickness is 1-30nm.
For achieving the above object, the invention provides a kind of Al
2o
3/ LaAlO
3/ SiO
2the manufacture method of the SiC mos capacitance of stacking gate dielectric layer, is characterized in that, described method comprises:
Step 1, growth thickness is 5-100 μm of lightly doped SiC epitaxial layer on sic substrates, and doping content is 1 × 10
15-5 × 10
16cm
-3
Step 2, carries out clean by the upper SiC epitaxial layer of SiC substrate, is then under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 1nm-30nm
2transition zone;
Step 3, by grown SiO
2transition zone in Ar compression ring border short annealing process and in Ar compression ring border cooling processing;
Step 4, utilizes the method for atomic layer deposition (ALD), the lower floor SiO after annealing and cooling processing
2on transition zone, deposit a layer thickness is the LaAlO of 5nm-100nm
3layer;
Step 5, utilizes the method for atomic layer deposition, at LaAlO
3on layer, deposit a layer thickness is the Al of 1-30nm
2o
3cover layer;
Step 6, utilizes the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of described SiC substrate as negative electrode, then at N
2short annealing process in compression ring border.
Further, in described step 3, short annealing in Ar compression ring border, is specially, and annealing temperature is 1000 ± 5 DEG C, and annealing time is 5min, anneals in Ar compression ring border.
Further, cool in Ar compression ring border in described step 3, be specially, cool in Ar compression ring border according to the speed of 5 DEG C/min.
Further, in described step 4, deposit a layer thickness is the LaAlO of 5nm-100nm
3layer, being specially deposition temperature is 200 DEG C-400 DEG C, and deposition time is 20min-6h, and deposit a layer thickness is the LaAlO of 5nm-100nm
3layer.
Further, in described step 5, deposit a layer thickness is the Al of 1-30nm
2o
3cover layer, being specially deposition temperature is 200 DEG C-400 DEG C, and deposition time is 5min-2h, and deposit a layer thickness is the Al of 1-30nm
2o
3cover layer.
Tool of the present invention has the following advantages:
1, the gate dielectric material LaAlO of the present invention's employing
3, its dielectric constant high (k-25), crystallization temperature is high, Heat stability is good, thus adds the critical breakdown electric field of gate medium, improves the breakdown characteristics of electric capacity, improves device reliability.
2, the lower floor SiO of the present invention's employing
2transition zone adds the barrier height of gate medium and SiC substrate, greatly can reduce electronics in SiC substrate through gate medium tunnelling to the probability of gate electrode, thus reduce gate leak current, improve reliability.Meanwhile, this SiO of nitriding process growth is adopted
2transition zone, reduces interface state density and the bound trap density of gate medium and SiC, adds channel mobility, improve device performance.
3, the Al of the present invention's employing
2o
3cover layer reduces the probability of the trapped electron tunnelling in High k gate medium to gate electrode, and, this Al
2o
3cover layer to also reduce in gate electrode electron tunneling to the probability in SiC substrate.Meanwhile, Al
2o
3cover layer can avoid LaAlO
3because moisture absorption and exposure form hydrocarbon and the carbonate of low-k in atmosphere respectively, thus reduce gate leak current, improve the q&r of mos capacitance.
Accompanying drawing explanation
Fig. 1 is Al of the present invention
2o
3/ LaAlO
3/ SiO
2the structural representation of the SiC mos capacitance of stacking gate dielectric layer;
Fig. 2 is Al of the present invention
2o
3/ LaAlO
3/ SiO
2the manufacturing flow chart of the SiC mos capacitance of stacking gate dielectric layer.
Fig. 3 is Al of the present invention
2o
3/ LaAlO
3/ SiO
2the flow chart of the manufacture method of the SiC mos capacitance of stacking gate dielectric layer.
Embodiment
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Fig. 1 is Al of the present invention
2o
3/ LaAlO
3/ SiO
2the schematic diagram of the SiC mos capacitance of stacking gate dielectric layer, as shown in the figure, the present invention includes: SiC substrate 1, SiC epitaxial layer 10, stacking gate dielectric layer 2 and positive and negative electrode 3.
SiC substrate 1 is provided with SiC epitaxial layer 10;
Stacking gate dielectric layer 2 comprises lower floor SiO
2transition zone 21, LaAlO
3layer 22 and Al
2o
3cover layer 23; SiC epitaxial layer 10 is provided with lower floor SiO
2transition zone 21, lower floor SiO
2transition zone 21 is provided with LaAlO
3layer 22, LaAlO
3layer 22 is provided with Al
2o
3cover layer 23;
Positive electrode 31, negative electrode 32 respectively with Al
2o
3the surface of cover layer 23 is connected with the back side of SiC substrate 1.
Concrete, SiC substrate layer is attached most importance to doped SIC substrate layer, and SiC epitaxial layer is the SiC epitaxial layer of gently mixing.
Concrete, SiC epitaxial layer thickness is 5-100 μm, and doping content is 1 × 10
15-5 × 10
16cm
-3.Lower floor SiO
2the thickness of transition zone is 1-30nm, LaAlO
3the thickness of layer is 5nm-100nm, Al
2o
3tectal thickness is 1-30nm.
By lower floor SiO
2transition zone, LaAlO
3layer and Al
2o
3the gate dielectric layer of cover layer composition is a stacking gate dielectric layer, to reduce interface state density and bound trap density, increases MOS channel mobility, reduces gate leak current, and improve the voltage endurance capability of dielectric layer further, improve the q&r of MOS.
Fig. 3 is Al of the present invention
2o
3/ LaAlO
3/ SiO
2the flow chart of the manufacture method of the SiC mos capacitance of stacking gate dielectric layer, as shown in the figure, the present invention includes following steps:
Step 1, growth thickness is 5-100 μm of lightly doped SiC epitaxial layer on sic substrates, and doping content is 1 × 10
15-5 × 10
16cm
-3
Step 2, carries out clean by the upper SiC epitaxial layer of SiC substrate, is then under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 1nm-30nm
2transition zone;
Step 3, by grown lower floor SiO
2transition zone in Ar compression ring border short annealing process and in Ar compression ring border cooling processing;
Step 4, utilizes the method for atomic layer deposition (ALD), the lower floor SiO after annealing and cooling processing
2on transition zone, deposit a layer thickness is the LaAlO of 5nm-100nm
3layer;
Step 5, utilizes the method for atomic layer deposition, at LaAlO
3on layer, deposit a layer thickness is the Al of 1-30nm
2o
3cover layer;
Step 6, utilizes the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of described SiC substrate as negative electrode, then at N
2short annealing process in compression ring border.
Al of the present invention
2o
3/ LaAlO
3/ SiO
2the exemplifying embodiment 1 of the manufacture method of the SiC mos capacitance of stacking gate dielectric layer comprises the steps:
Step 101, N-type heavy doping SiC substrate grows the lightly doped SiC epitaxial layer of N-type.
Be 380 μm by thickness, doping content is 5 × 10
18cm
-3n-type SiC substrate be placed in SiC epitaxial furnace, under temperature 1570 DEG C of conditions, growth a layer thickness be 8 μm, doping content is 3 × 10
15cm
-3n-type SiC epitaxial layer.
Step 102, carries out preliminary treatment to grown N-type SiC epitaxial layer.
102.1, with deionized water, ultrasonic cleaning is carried out to N-type SiC epitaxial layer;
102.2, be that 80% sulfuric acid prolongs sheet to epitaxial loayer and cleans by concentration, after boiling 10min, soak 30min;
102.3, with washed with de-ionized water SiC epitaxial layer number time;
102.4, be the H of 5:1:1 by ratio
2o, H
2o
2and the mixed liquor of hydrochloric acid composition, be soak 5min in the mixed liquor of 80 DEG C in temperature by SiC epitaxial wafer, with the cleaning of HF (hydrofluoric acid) solution, then with washed with de-ionized water number time, finally dry with infrared lamp.
Step 103, SiC epitaxial layer grows nitrogenize SiO
2transition zone.
Pretreated N-type SiC epitaxial wafer is placed in oxidation furnace, is under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 6nm
2transition zone;
Step 104, to grown SiO
2transition zone carries out annealing and cooling processing
104.1, will SiO be grown
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, and annealing temperature is 1000 ± 5 DEG C, and annealing time is 5min;
104.2, by annealing after grown SiO
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, cooldown rate 5 DEG C/min;
Step 105, deposit LaAlO
3layer.
Annealing and cooling processing after grown SiO
2the SiC epitaxial wafer of transition zone adopts the LaAlO that method deposit one deck 15nm of atomic layer deposition is thick
3layer, deposition temperature is 300 DEG C, and deposition time is 1h.
Step 106, deposit Al
2o
3cover layer.
Adopt the method for atomic layer deposition at gate medium LaAlO
3the Al that on layer, deposit one deck 4nm is thick
2o
3, deposition temperature is 300 DEG C, and deposition time is 15min;
Step 107, splash-proofing sputtering metal Ni electrode and annealing in process.
107.1, utilize the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of SiC substrate as negative electrode;
107.1, the SiC mos capacitance after splash-proofing sputtering metal Ni electrode is placed in the N that temperature is 400 ± 5 DEG C
2anneal in compression ring border 5min, completes the making of whole SiC mos capacitance.
Al of the present invention
2o
3/ LaAlO
3/ SiO
2the exemplifying embodiment 2 of the manufacture method of the SiC mos capacitance of stacking gate dielectric layer comprises the steps:
Step 201, N-type heavy doping SiC substrate grows the lightly doped SiC epitaxial layer of N-type.
Be 380 μm by thickness, doping content is 8 × 10
18cm
-3n-type SiC substrate be placed in SiC epitaxial furnace, under temperature 1570 DEG C of conditions, growth a layer thickness be 12 μm, doping content is 1 × 10
16cm
-3n-type SiC epitaxial layer.
Step 202, carries out preliminary treatment to grown N-type SiC epitaxial layer.
202.1, with deionized water, ultrasonic cleaning is carried out to N-type SiC epitaxial layer;
202.2, be that 80% sulfuric acid prolongs sheet to epitaxial loayer and cleans by concentration, after boiling 10min, soak 30min;
202.3, with washed with de-ionized water SiC epitaxial layer number time;
202.4, be the H of 5:1:1 by ratio
2o, H
2o
2and the mixed liquor of hydrochloric acid composition, be soak 5min in the mixed liquor of 80 DEG C in temperature by SiC epitaxial wafer, with the cleaning of HF (hydrofluoric acid) solution, then with washed with de-ionized water number time, finally dry with infrared lamp.
Step 203, SiC epitaxial layer grows nitrogenize SiO
2transition zone.
Pretreated N-type SiC epitaxial wafer is placed in oxidation furnace, is under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 8nm
2transition zone;
Step 204, to grown SiO
2transition zone carries out annealing and cooling processing.
204.1, will SiO be grown
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, and annealing temperature is 1000 ± 5 DEG C, and annealing time is 5min;
204.2, by annealing after grown SiO
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, cooldown rate 5 DEG C/min;
Step 205, deposit LaAlO
3layer.
Annealing and cooling processing after grown SiO
2the SiC epitaxial wafer of transition zone adopts the LaAlO that method deposit one deck 30nm of atomic layer deposition is thick
3layer, deposition temperature is 250 DEG C, and deposition time is 140min.
Step 206, deposit Al
2o
3cover layer.
Adopt the method for atomic layer deposition at LaAlO
3the Al that on layer, deposit one deck 8nm is thick
2o
3, deposition temperature is 250 DEG C, and deposition time is 40min;
Step 207, splash-proofing sputtering metal Ni electrode and annealing in process.
207.1, utilize the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of SiC substrate as negative electrode;
207.1, the SiC mos capacitance after splash-proofing sputtering metal Ni electrode is placed in the N that temperature is 400 ± 5 DEG C
2anneal in compression ring border 5min, completes the making of whole SiC mos capacitance.
Al of the present invention
2o
3/ LaAlO
3/ SiO
2the exemplifying embodiment 3 of the manufacture method of the SiC mos capacitance of stacking gate dielectric layer comprises the steps:
Step 301, N-type heavy doping SiC substrate grows the lightly doped SiC epitaxial layer of N-type
Be 380 μm by thickness, doping content is 1 × 10
19cm
-3n-type SiC substrate be placed in SiC epitaxial furnace, under temperature 1570 DEG C of conditions, growth a layer thickness be 30 μm, doping content is 2 × 10
15cm
-3n-type SiC epitaxial layer.
Step 302, carries out preliminary treatment to grown N-type SiC epitaxial layer.
302.1, with deionized water, ultrasonic cleaning is carried out to N-type SiC epitaxial layer;
302.2, be that 80% sulfuric acid prolongs sheet to epitaxial loayer and cleans by concentration, after boiling 10min, soak 30min;
302.3, with washed with de-ionized water SiC epitaxial layer number time;
302.4, be the H of 5:1:1 by ratio
2o, H
2o
2and the mixed liquor of hydrochloric acid composition, be soak 5min in the mixed liquor of 80 DEG C in temperature by SiC epitaxial wafer, with the cleaning of HF (hydrofluoric acid) solution, then with washed with de-ionized water number time, finally dry with infrared lamp.
Step 303, SiC epitaxial layer grows nitrogenize SiO
2transition zone.
Pretreated N-type SiC epitaxial wafer is placed in oxidation furnace, is under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 20nm
2transition zone;
Step 304, to grown SiO
2transition zone carries out annealing and cooling processing.
104.1, will SiO be grown
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, and annealing temperature is 1000 ± 5 DEG C, and annealing time is 5min;
104.2, by annealing after grown SiO
2the SiC epitaxial wafer of transition zone is placed in Ar compression ring border and anneals, cooldown rate 5 DEG C/min;
Step 305, deposit LaAlO
3layer.
Annealing and cooling processing after grown SiO
2the SiC epitaxial wafer of transition zone adopts the LaAlO that method deposit one deck 50nm of atomic layer deposition is thick
3layer, deposition temperature is 320 DEG C, and deposition time is 3h.
Step 306, deposit Al
2o
3cover layer.
Adopt the method for atomic layer deposition at gate medium LaAlO
3the Al that on layer, deposit one deck 10nm is thick
2o
3, deposition temperature is 320 DEG C, and deposition time is 45min;
Step 307, splash-proofing sputtering metal Ni electrode and annealing in process.
307.1, utilize the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of SiC substrate as negative electrode;
307.1, the SiC mos capacitance after splash-proofing sputtering metal Ni electrode is placed in the N that temperature is 400 ± 5 DEG C
2anneal in compression ring border 5min, completes the making of whole SiC mos capacitance.
Tool of the present invention has the following advantages:
1, the gate dielectric material LaAlO of the present invention's employing
3, its dielectric constant high (k-25), crystallization temperature is high, Heat stability is good, thus adds the critical breakdown electric field of gate medium, improves the breakdown characteristics of electric capacity, improves device reliability.
2, the lower floor SiO of the present invention's employing
2transition zone adds the barrier height of gate medium and SiC substrate, greatly can reduce electronics in SiC substrate through gate medium tunnelling to the probability of gate electrode, thus reduce gate leak current, improve reliability.Meanwhile, this SiO of nitriding process growth is adopted
2transition zone, reduces interface state density and the bound trap density of gate medium and SiC, adds channel mobility, improve device performance.
3, the Al of the present invention's employing
2o
3cover layer reduces the probability of the trapped electron tunnelling in High k gate medium to gate electrode, and, this Al
2o
3cover layer to also reduce in gate electrode electron tunneling to the probability in SiC substrate.Meanwhile, Al
2o
3cover layer can avoid LaAlO
3because moisture absorption and exposure form hydrocarbon and the carbonate of low-k in atmosphere respectively, thus reduce gate leak current, improve the q&r of mos capacitance.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. an Al
2o
3/ LaAlO
3/ SiO
2the SiC mos capacitance of stacking gate dielectric layer, is characterized in that, the SiC mos capacitance of described stacking dielectric layer comprises: SiC substrate, SiC epitaxial layer, stacking gate dielectric layer and positive and negative electrode;
Described SiC substrate is provided with SiC epitaxial layer;
Described stacking gate dielectric layer comprises lower floor SiO
2transition zone, LaAlO
3layer and Al
2o
3cover layer; Described SiC epitaxial layer is provided with lower floor SiO
2transition zone, described lower floor SiO
2transition zone is provided with described LaAlO
3layer, described LaAlO
3layer is provided with Al
2o
3cover layer;
Described positive and negative electrode respectively with Al
2o
3tectal surface is connected with the back side of SiC substrate.
Described SiC substrate is heavily doped SiC substrate layer, and described SiC epitaxial layer is lightly doped SiC epitaxial layer
2. the SiC mos capacitance of stacking gate dielectric layer according to claim 1, is characterized in that, described SiC epitaxial layer thickness is 5-100 μm, and doping content is 1 × 10
15-5 × 10
16cm
-3.
3. the SiC mos capacitance of stacking gate dielectric layer according to claim 1, is characterized in that, described lower floor SiO
2the thickness of transition zone is 1-30nm.
4. the SiC mos capacitance of stacking gate dielectric layer according to claim 1, is characterized in that, described LaAlO
3the thickness of layer is 5nm-100nm.
5. the SiC mos capacitance of stacking gate dielectric layer according to claim 1, is characterized in that, described Al
2o
3tectal thickness is 1-30nm.
6. an Al
2o
3/ LaAlO
3/ SiO
2the manufacture method of the SiC mos capacitance of stacking gate dielectric layer, is characterized in that, described method comprises:
Step 1, growth thickness is 5-100 μm of lightly doped SiC epitaxial layer on sic substrates, and doping content is 1 × 10
15-5 × 10
16cm
-3
Step 2, carries out clean by the upper SiC epitaxial layer of SiC substrate, is then under the condition of 1175 ± 5 DEG C in temperature, 10%N
2o:90%N
2mist in growth thickness be the lower floor nitrogenize SiO of 1nm-30nm
2transition zone;
Step 3, by grown SiO
2transition zone in Ar compression ring border short annealing process and in Ar compression ring border cooling processing;
Step 4, utilizes the method for atomic layer deposition (ALD), the lower floor SiO after annealing and cooling processing
2on transition zone, deposit a layer thickness is the LaAlO of 5nm-100nm
3layer;
Step 5, utilizes the method for atomic layer deposition, at LaAlO
3on layer, deposit a layer thickness is the Al of 1-30nm
2o
3cover layer;
Step 6, utilizes the method for magnetron sputtering at Al
2o
3cover surface splash-proofing sputtering metal Ni as positive electrode, at the back spatter W metal of described SiC substrate as negative electrode, then at N
2short annealing process in compression ring border.
7. method according to claim 6, is characterized in that, in described step 3, short annealing in Ar compression ring border, is specially, and annealing temperature is 1000 ± 5 DEG C, and annealing time is 5min, anneals in Ar compression ring border.
8. method according to claim 6, is characterized in that, cools, be specially in described step 3 in Ar compression ring border, cools in Ar compression ring border according to the speed of 5 DEG C/min.
9. method according to claim 6, is characterized in that, in described step 4, deposit a layer thickness is the LaAlO of 5nm-100nm
3layer, being specially deposition temperature is 200 DEG C-400 DEG C, and deposition time is 20min-6h, and deposit a layer thickness is the LaAlO of 5nm-100nm
3layer.
10. method according to claim 6, is characterized in that, in described step 5, deposit a layer thickness is the Al of 1-30nm
2o
3cover layer, being specially deposition temperature is 200 DEG C-400 DEG C, and deposition time is 5min-2h, and deposit a layer thickness is the Al of 1-30nm
2o
3cover layer.
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