CN101807576A - Nanocrystalline floating gate nonvolatile memory and manufacturing method thereof - Google Patents

Abstract

The invention discloses a nanocrystalline floating gate nonvolatile memory with a multi-value storage function and a manufacturing method thereof. The packet memory includes: a silicon substrate; heavily doped source and drain conductive regions on a silicon substrate; covered by SiO on the carrier channel between the source and drain conduction regions₂The material medium and the high-k material medium form a composite tunneling layer from bottom to top; a first nanocrystal floating gate layer covered on the composite tunneling layer; a barrier layer medium covered on the first nanocrystal floating gate layer and used as a double-layer intercrystalline barrier layer; a second nanocrystalline floating gate layer covering the barrier layer medium; a high-k material or SiO coated on the second nanocrystal floating gate layer₂A control gate dielectric layer of material; and a gate material layer overlying the control gate dielectric layer. The invention improves the integration density of the floating gate nonvolatile memory, comprehensively improves the storage performance: the programming/erasing speed and endurance are improved, the data retention characteristic is improved, and the programming/erasing voltage and the operation power consumption are reduced.

Description

Nano-crystal floating gate nonvolatile memory and preparation method thereof

Technical field

The present invention relates to microelectronics technology, relate in particular to a kind of nano-crystal floating gate nonvolatile memory and preparation method thereof with many-valued memory function.

Background technology

The floating gate structure memory is to be used and universally recognized main flow type of memory by a large amount of at present, is a kind of crucial semiconductor components and devices, is widely used in electronics and computer industry.Traditional floating gate structure memory is because the selection of himself structure and material causes quick write/erase operation of requirement and long-time high stability to store afoul limitation, and along with technology node dwindle this contradiction not be improved significantly, limited the development of floating-gate memory.

Along with characteristic size enters into nanoscale, how to adapt to the development of technology, improving the storage data when reducing memory cell size writes, reads, wipes and keep performance, become the key issue that present floating-gate memory development faces, this just requires on material or structure traditional floating-gate memory further to be improved.

Based on SONOS (Poly-Si/SiO ₂/ Si ₃N ₄/ SiO ₂/ Si) structure nonvolatile storage and the nonvolatile storage that puts forward with nanocrystalline floating gate structure, utilize nano-crystalline granule as charge storage media, each nano-crystalline granule is with crystal grain insulation on every side and only store a small amount of several electrons, thereby realized discrete charge storage, reduced the harmfulness that the defective on the tunneling medium layer causes the fatal discharge channel that forms, only may cause that the electric charge on the local nano-crystalline granule leaks, thereby the retention performance that has guaranteed electric charge is more stable.

The selection of nano-crystalline granule material plays vital decisive action to the memory property of nanocrystalline floating gate structure memory.Have that the nonvolatile storage of nanocrystalline floating gate structure is potential to provide higher integration density, lower write/erase voltage, write/erase speed, higher tolerance, stronger data retention characteristics and multidigit storage capacity faster for application memory equipment a future.

Mos field effect transistor (the Metal Oxide Semiconductor Field Effect Transistor of the employing silicon nanocrystal floating gate structure of at room temperature working was proposed from 1996, MOSFET) since the memory, the nanocrystalline floating gate structure nonvolatile storage has caused extensive studies interest, and has done number of research projects on the one hand at this.

In order further to improve the integration density of existing traditional floating gate structure memory, and improve memory performance simultaneously, structural design and material to floating gate structure memory with many-valued memory function are selected, and having begun to become numerous is the direction and the emphasis of the research of purpose to improve the memory combination property and to improve the semiconductor storage unit integrated level.And in recent years,, begun to cause that industry pays close attention in a large number based on the many-valued storage organization of nanocrystalline floating gate memory.

Application number provides a kind of memory and manufacture method thereof with quantum dot for 02130478.5 Chinese invention patent, and its tunnel layer adopts silica, aluminium oxide, silicon oxynitride, tantalum oxide, hafnium oxide, zirconia, STO (SrTiO ₃); Floating boom adopts quanta point material, comprises silicon, silicon nitride, metal; The forming process of quantum dot is to deposit template layer earlier, and then oxidation forms foraminous die plate, deposit quanta point material, etching and planarization.

Application number provides a kind of employing HfO for U.S.'s patent of invention of 20060125027 ₂Nanocrystalline nonvolatile storage as floating boom forms the silicate that contains Hf by cosputtering Hf, Si, then at Ar/O ₂Middle short annealing forms HfO ₂Nanocrystalline, the tunnelling medium adopts SiO ₂, Si ₃N ₄, HfO ₂, ZrO ₂, Al ₂O ₃, La ₂O ₃

Application number adopts Si, Ge and metallic nanocrystalline floating gate for U.S.'s patent of invention of 20060166452 and application number provide a kind of non-volatile nano-crystal memory and manufacture method thereof for 2006080999 world inventions patent, adopts SiO ₂, HfO ₂, La ₂O ₃, Al ₂O ₃The tunnelling medium adopts SiON _xThe control gate medium, wherein the content of N reduces from the nano-crystal floating gate to the control gate gradually.

Application number provides a kind of quantum dot memory based on longitudinal double barrier resonant tunneling structure for 200410091126.0 Chinese invention patent, adopt SiGe quantum dot floating gate layer, double barrier resonant tunneling layer, by S-K growth pattern self-organizing growth SiGe quantum dot, alternating growth SiGe and Si form the double potential barrier of multilayer hetero-structure and wear layer then.

Adopt said method to utilize high K medium and nanocrystalline material to make floating gate structure non-volatile memory and generally can obtain nano-crystalline granule, nanocrystalline material is used as floating gate layer, and the method that wherein prepares nano-crystalline granule comprises that template, composite material annealing method, multilayer annealing, oxidation add etching, S-K self-organizing growth method etc.; High k material is used as dielectric layer; Single dielectric material or multilayered medium material are used as tunneling medium layer.

But utilize the method for preparing nano-crystal memory not possess many-valued memory function, and generally all exist complex manufacturing technology, cost of manufacture height, make efficiency low, perhaps nano-crystalline granule is bigger, perhaps technology controlling and process difficulty in the manufacturing process, perhaps shortcoming such as feasibility difference and traditional cmos process poor compatibility.

Summary of the invention

(1) technical problem that will solve

In view of this, one object of the present invention is to provide a kind of nano-crystal floating gate nonvolatile memory with many-valued memory function, makes integration density double under the prerequisite that does not change cellar area.This structure has the brilliant floating gate layer of double-layer nanometer, by changing program voltage and programming time, electric charge is stored in respectively in the different floating gate layers, thereby causes the change of threshold voltage, has many-valued memory function; Program/erase (P/E) voltage of composite tunnel layer structure that adopts the low high k of k/ to pile up simultaneously to reduce floating gate structure non-volatile memory, reduce the operating time and the operation power consumption of floating gate structure non-volatile memory, memory properties such as program/erase (P/E) speed of raising floating gate structure non-volatile memory, data retention characteristics (retention), program/erase (P/E) tolerance, program/erase efficient and data retention characteristics in the compromise simultaneously consideration floating gate structure non-volatile memory are to adapt to the needs that the semiconductor storage unit size is dwindled.

Another object of the present invention is to provide a kind of making to have the method for the nano-crystal floating gate nonvolatile memory of many-valued memory function, based on traditional CMOS technology, to simplify manufacture craft, reduces cost of manufacture, improves make efficiency, improves compatible.

(2) technical scheme

For reaching an above-mentioned purpose, the invention provides a kind of nano-crystal floating gate nonvolatile memory with many-valued memory function, this memory comprises:

Silicon substrate 1;

Source conduction region 9 and leakage conduction region 10 at silicon substrate 1 upper heavy doping;

Leak in the source cover on the carrier channels between the conduction region, by SiO ₂The composite tunnel layer that material medium 2 and high k material medium 3 constitute from bottom to top;

The first nano-crystal floating gate layer 4 that on composite tunnel layer, covers;

The barrier layer medium 5 that on the first nano-crystal floating gate layer 4, covers as double-layer nanometer intergranular barrier layer;

The second nano-crystal floating gate layer 6 that on barrier layer medium 5, covers;

On the second nano-crystal floating gate layer 6, cover by high k material or SiO ₂The control gate dielectric layer 7 that material constitutes; And

The gate material layer 8 that on control gate dielectric layer 7, covers.

In the such scheme, the described first nano-crystal floating gate layer 4, barrier layer medium 5 and the second nano-crystal floating gate layer 6 form the capture layer of this memory in the stacked structure of certain thickness ratio combination.

In the such scheme, the material selection metallic nano crystal of the described first nano-crystal floating gate layer 4 and the second nano-crystal floating gate layer 6, metallic nano crystal material are any one in W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag metal; Nanocrystalline diameter is 1nm to 10nm, and density is 1 * 10 ¹¹Cm ^-2To 1 * 10 ¹³Cm ^-2

In the such scheme, described barrier layer medium 5 is formed by high k material, comprises HfO ₂, Al ₂O ₃, ZrO ₂, Ta ₂O ₅, LaAlO ₃, any one or a few the combination among HfAlO, HfLaON and the HfTaON; The thickness of described barrier layer medium 5 is 3nm to 5nm.

For reaching above-mentioned another purpose, the invention provides a kind of method with nano-crystal floating gate nonvolatile memory of many-valued memory function, this method comprises:

A, on silicon substrate growth one deck SiO ₂The tunnelling medium of material;

B, at SiO ₂The tunnelling medium of growth one floor height k material on the tunnelling medium of material;

C, on the tunnelling medium of high k material the growing metal film, form the nano-crystal floating gate layer behind the high annealing;

The barrier layer of D, the high k material of on the nano-crystal floating gate layer, growing;

E, on high k material barrier layer regrowth layer of metal film, form second layer nano-crystal floating gate behind the high annealing;

F, on the nano-crystal floating gate layer deposition high k material or SiO ₂The control gate dielectric layer of material;

G, on the control gate dielectric layer gate material layer of deposit spathic silicon material or metal material;

H, photoetching form grid line bar figure in the resist on gate material layer;

I, be mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO with grid line bar figure ₂Material medium/high k material medium composite tunnel layer forms the grid pile structure;

J, photoetching, ion inject, and form the source conduction region and leak conduction region in the silicon substrate of grid line bar both sides;

K, growth dielectric, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode, and encapsulation.

In the such scheme, SiO grows described in the steps A ₂The method of the tunnelling medium of material is: thermal oxidation, ald ALD, chemical vapor deposition CVD; Described SiO ₂The thickness of the tunnelling medium of material is 1nm to 5nm.

In the such scheme, the method for the tunnelling medium of the high k material of growth described in the step B is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering.The thickness of the tunnelling medium of described high k material is 2nm to 10nm.

In the such scheme, the SiO described in steps A and the step B ₂The tunnelling medium of the tunnelling medium of material/high k material is combined into described composite tunnel layer in the certain thickness ratio, and the gross thickness of described composite tunnel layer is 3nm to 15nm.

In the such scheme, the method for the floating gate layer of growing nano-crystal described in the step C is: adopt sputter or evaporation plated film on the composite tunnel dielectric layer, then the thin-film material that forms is carried out the high temperature rapid thermal treatment, make the thin-film material crystallization, form nano-crystalline granule.

In the such scheme, the method on the barrier layer of the high k material of growth described in the step D is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering.The thickness of the tunnelling medium of described high k material is 3nm to 5nm.

In the such scheme, the method of the second layer of growth described in step e nano-crystal floating gate layer is: adopt sputter or evaporation plated film on high K dielectric barrier, then the thin-film material that forms is carried out the high temperature rapid thermal treatment, make the thin-film material crystallization, form nano-crystalline granule.

In the such scheme, high k material of deposition or SiO described in the step F ₂The method of the control gate dielectric layer of material is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering; The high k material or the SiO of described deposition ₂The thickness of the control gate dielectric layer of material is 10nm to 30nm.

In the such scheme, the method for the gate material layer of material of deposit spathic silicon described in the step G or metal material is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering; The thickness of the polycrystalline silicon material of described deposition or the gate material layer of metal material is at least 100nm.

In the such scheme, be lithographically optical lithography or electron beam lithography described in the step H, the width of the grid line bar figure that forms after the photoetching is the long 20nm to 2000nm of being of grid.

In the such scheme, the concrete processing step of described optical lithography comprises: be the AZ5214 negativity optics resist of 1.5 μ at gate material layer surface applied one layer thickness, to baking before coated AZ5214 negativity optics resist employing hot plate is under 100 ℃ 100 seconds, the then exposure of adopting mask aligner to utilize photomask to be undertaken by designed gate figure 30 seconds to optics resist AZ5214, toasted 70 seconds down at 115 ℃ with hot plate then, follow general exposing to the sun, direct naked the exposing to the sun 60 seconds without photomask used the special-purpose developer solution 1Microposit of AZ5214 351:5H at last ₂O or 1AZ400K:4H ₂O at room temperature developed 50 seconds, only stayed AZ5214 optics resist above grid heap to be formed, adopted deionized water photographic fixing at room temperature 30 seconds at last, finishes and form grid line bar figure in AZ5214 negativity optics resist; Adopting the width of the AZ5214 negativity optics resist grid line bar of optical lithography formation is 500nm to 2000nm.

In the such scheme, the concrete processing step of described electron beam lithography comprises: be the SAL601 negative electronic erosion-resisting agent of 500nm at grid material surface applied one layer thickness, coated SAL601 negative electronic erosion-resisting agent was dried by the fire 2 minutes before hot plate is under 105 ℃, then adopt the e-beam direct write lithography system to expose by gate figure, then the SAL601 negative electronic erosion-resisting agent after the exposure was dried by the fire 2 minutes with hot plate back under 105 ℃, then adopt MF CD-26 developer solution at room temperature to develop 1 to 10 minute, adopt deionized water photographic fixing at room temperature 30 seconds again, finish and in the SAL601 negative electronic erosion-resisting agent, form grid line bar figure; Adopting the width of the SAL601 negative electronic erosion-resisting agent grid line bar of electron beam lithography formation is 20nm to 500nm.

In the such scheme, described step I comprises: the AZ5214 negativity optics resist that covers on the grid surface or SAL601 negative electronic erosion-resisting agent grid line bar figure as mask, are adopted high density inductively coupled plasma ICP lithographic method or reactive ion etching RIE method etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO successively ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer removes photoresist again, forms the grid pile structure; The described method of removing photoresist is that wet method is removed photoresist, and adopts dense H ₂SO ₄+ H ₂O ₂Boiling glue removes photoresist.

In the such scheme, described step J comprises: be the AZ9912 positivity optics resist of 1.5 μ m at surface applied one layer thickness, baking is 100 seconds before adopting hot plate under 100 ℃, the source, the drain region that adopt lay photoetching mask plate to be sequestered in grid line bar both sides on mask aligner expose, at room temperature developed 50 seconds with the special-purpose developer solution of AZ9912 then, with deionized water photographic fixing at room temperature 30 seconds, finish formation source, drain region figure in AZ9912 positivity optics resist at last; In the silicon substrate of formed source, drain region, inject P again ³¹⁺Ion, the injection energy is 50keV, implantation dosage is 1 * 10 ¹⁸Cm ^-2, again at dense H ₂SO ₄+ H ₂O ₂In boil glue and remove photoresist; Then under 1100 ℃ of temperature at N ₂Short annealing is 10 seconds in the atmosphere, thereby forms the source conduction region and leak conduction region in the silicon substrate of grid line bar both sides.

In the such scheme, the dielectric of growing described in the step K, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode and comprise:

At first, at surface deposition one deck dielectric, material comprises: SiO ₂, phosphorosilicate glass PSG or boron-phosphorosilicate glass BPSG; Coating one layer thickness is the AZ9912 positivity optics resist of 1.5 μ m on this insulating medium layer then, adopt hot plate 100 ℃ down before baking 100 seconds, the employing lay photoetching mask plate is sheltered and is exposed on mask aligner; Next the special-purpose developer solution with AZ9912 positivity optics resist at room temperature developed 50 seconds; With deionized water photographic fixing at room temperature 30 seconds, finish above source, leakage, grid and form contact hole graph at last;

Next step utilizes AZ9912 positivity optics resist figure as mask, adopts buffered hydrofluoric acid solution HF+NH ₄F+H ₂O corrodes insulating medium layer at normal temperatures;

Again next step, as metal electrode material, the thickness of described Al-1%Si film is 1 μ m to evaporation one layer thickness less than the Al-1%Si film of AZ9912 positivity optics resist thickness on the AZ9912 positivity optics resist of the source of exposing, leakage, grid material surface and not removal;

Then, adopt the ultrasonic metal electrode material of peeling off AZ9912 positivity optics resist and going up evaporation side of acetone;

At last, carry out annealing in process formation source, leakage, gate electrode to peeling off the remaining metal electrode material in back; Describedly be to peeling off the condition that the remaining metal electrode material in back carries out annealing in process: under 400 ℃ of temperature at N ₂Annealing in process is 5 minutes in the atmosphere; Then under 400 ℃ of temperature at N ₂/ H ₂Annealing is 20 minutes in the mist; At last under 400 ℃ of temperature at N ₂Annealing is 5 minutes in the atmosphere.

(3) beneficial effect

From technique scheme as can be seen, the present invention has following beneficial effect:

(1) this nano-crystal floating gate nonvolatile memory with many-valued memory function provided by the invention and preparation method thereof is produced on the body silicon substrate, does not need expensive backing material, has both saved cost, helps heat radiation simultaneously again.

(2) this nano-crystal floating gate nonvolatile memory provided by the invention and preparation method thereof with many-valued memory function, its structure and manufacture craft are very simple, and SiO successively grows on silicon substrate ₂The tunnelling dielectric film of material, the tunnelling dielectric film of high k material, SiO ₂The tunnelling dielectric film of material, nano-crystalline granule, high k material or SiO ₂Behind the control gate dielectric film of material, polysilicon or the metal gate material film, utilize photoetching, etching, source to leak the nano-crystal floating gate nonvolatile memory that technologies such as ion injection, annealing can be prepared multi-medium composite tunnel layer of the present invention.

(3) owing to adopted nanocrystalline/high K barrier layer/nanocrystalline composite capture layer structure of piling up, device has many-valued memory function, thereby makes integration density double under the constant situation of area; Simultaneously, the use of hafnium and nanocrystalline material can also optimize storage memory property, particularly performance index such as memory window, program/erase (P/E) speed, program/erase (P/E) operating voltage, operating time, operation power consumption, data retention characteristics, program/erase (P/E) tolerance can obtain comprehensive raising.

(4) various nano-crystal floating gate materials, dielectric layer material, grid material all can adopt these conventional method preparations of magnetron sputtering, electron beam evaporation or chemical vapor deposition (CVD), so the complete process process of the preparation technology of material requested and making memory is all compatible fully with traditional cmos process.

(5) adopt the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function provided by the invention, manufacture craft is simple, and make efficiency stability high and technology is high, and cost of manufacture is low, helps promotion and application of the present invention.

Description of drawings

Fig. 1 is the structural representation with nano-crystal floating gate nonvolatile memory of many-valued memory function provided by the invention;

Fig. 2 is the realization flow figure of the overall technological scheme of the manufacture method of the nano-crystal floating gate nonvolatile memory with many-valued memory function provided by the invention;

Fig. 3-1 is deposition one deck SiO on silicon substrate ₂The schematic diagram of the tunnelling medium of material;

Fig. 3-2 is at SiO ₂The schematic diagram of the tunnelling medium of deposition one floor height k material on the tunnelling medium of material;

Fig. 3-3 is the schematic diagram of one deck nano-crystalline granule as floating gate layer of growing on the tunnelling medium of high k material;

Fig. 3-4 is the schematic diagram on growth one deck high K medium barrier layer on ground floor is nanocrystalline;

Fig. 3-5 is the schematic diagram of regrowth one deck nano-crystalline granule floating boom on the high K medium barrier layer;

Fig. 3-6 is the schematic diagram of deposition one deck control gate dielectric layer on the nano-crystal floating gate layer;

Fig. 3-7 is the schematic diagram of deposition one deck gate material layer on the control gate dielectric layer;

Fig. 3-8 be grid material surface applied one deck negative resist and before the schematic diagram that dries by the fire;

Fig. 3-9 is the schematic diagram that coated negative resist is exposed, development and photographic fixing form grid line bar figure;

Fig. 3-10 is mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO for utilizing the negative resist figure ₂Material medium/high k material medium/SiO ₂The schematic diagram of material medium composite tunnel layer;

Fig. 3-11 forms the schematic diagram of grid pile structure for removing photoresist;

Fig. 3-12 for substrate surface coating one deck positivity optics resist of finishing above-mentioned steps and before the schematic diagram that dries by the fire;

Fig. 3-13 is for carrying out the schematic diagram that optical exposure, development and photographic fixing form source, drain region figure to coated positivity optics resist;

Fig. 3-14 is the schematic diagram that the silicon substrate ion of formed source, drain region is injected formation source, leakage conduction region;

The schematic diagram of Fig. 3-15 for removing photoresist and carrying out short annealing;

Fig. 3-16 is the schematic diagram of the body structure surface deposit one deck dielectric after finishing above step;

Fig. 3-17 be on insulating medium layer coating one deck positivity optics resist and before the schematic diagram that dries by the fire;

Fig. 3-18 is the schematic diagram that coated positivity optics resist is exposed, development and photographic fixing form contact hole graph above source, leakage, grid;

Fig. 3-19 for utilize positivity optics resist figure as mask at normal temperatures the etching insulating layer film expose the schematic diagram of source, leakage, grid material;

Fig. 3-20 is for evaporating the schematic diagram of one deck Al-1%Si film as metal electrode material on the positivity optics resist of the source of exposing, leakage, grid material surface and not removal;

Fig. 3-21 is the metal electrode material of peeling off positivity optics resist and going up evaporation side, and carries out the schematic diagram that annealing in process forms source, leakage, gate electrode to peeling off the remaining metal electrode material in back.

Fig. 4-1 for adopt bigger direct impulse with device programming to " 00 " state;

Fig. 4-2 for adopt bidirectional pulse (higher forward voltage and lower negative voltage) with device programming to " 10 " state;

Fig. 4-3 for adopt less direct impulse with device programming to " 01 " state;

Fig. 4-4 is erased to device " 11 " state for adopting negative-going pulse.

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

As shown in Figure 1, Fig. 1 is the structural representation with nano-crystal floating gate nonvolatile memory of many-valued memory function provided by the invention, and the nano-crystal floating gate nonvolatile memory of this multi-medium composite tunnel layer comprises: the SiO that covers on the carrier channels between the conduction region is leaked in the source conduction region 9 of silicon substrate 1, silicon substrate upper heavy doping and leakage conduction region 10, source ₂Material medium 2/ high k material medium 3 composite tunnel layers, nano-crystal floating gate layer 4, as the hafnium medium 5 on double-layer nanometer intergranular barrier layer, the high k material or the SiO that cover on nano-crystal floating gate layer 6, the nano-crystal floating gate layer ₂The gate material layer 8 that covers on control of material gate dielectric layer 7 and the control gate dielectric layer.

Silicon substrate 1, SiO ₂Material medium 2/ high k material medium 3 composite tunnel layers, nano-crystal floating gate layer 4, nanocrystalline high K medium barrier layer 5, nano-crystal floating gate layer 6, control gate dielectric layer 7, gate material layer 8 constitute the grid pile structure, and source conduction region 8 and leakage conduction region 9 are arranged in the silicon substrate 1 of grid pile structure both sides.

Wherein, silicon substrate 1 is the p type, is used to support whole nano-crystal floating gate nonvolatile memory with many-valued memory function.

Described SiO ₂Material medium 2/ high k material medium 3 composite tunnel layers are ground floor SiO ₂The tunnelling medium 2 of material, the tunnelling medium 3 of the second floor height k material combine described SiO in the certain thickness ratio ₂The gross thickness of material medium/high k material medium composite tunnel layer is 3nm to 15nm.

Ground floor SiO in the described composite tunnel layer ₂The tunnelling medium 2 of material is by SiO ₂Material forms, this SiO ₂The thickness of tunneling medium layer is 1nm to 5nm.

The tunnelling medium 3 of the second floor height k material in the described composite tunnel layer is formed by high k material, comprises HfO ₂, Al ₂O ₃, ZrO ₂, Ta ₂O ₅, La ₂O ₃, any one or a few the combination among HfAlO, HfLaON and the HfTaON; The thickness of the tunneling medium layer of described high k material is 2nm to 10nm.

The brilliant floating boom 4 of described double-layer nanometer and 6 layers are as charge storage media, its material selection metallic nano crystal.Described metallic nano crystal material is any one in W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag metal; Described nanocrystalline diameter is 1nm to 10nm, and density is 1 * 10 ¹¹Cm ^-2To 1 * 10 ¹³Cm ^-2

The barrier layer medium 5 of described double-layer nanometer intergranular is formed by high k material, comprises HfO ₂, Al ₂O ₃, ZrO ₂, Ta ₂O ₅, La ₂O ₃, any one or a few the combination among HfAlO, HfLaON and the HfTaON; The thickness on the barrier layer of described high k material is 3nm to 5nm.

Described control gate dielectric layer 7 is formed by high k material, comprises HfO ₂, Al ₂O ₃, ZrO ₂, Ta ₂O ₅, La ₂O ₃, among HfAlO, HfLaON, the HfTaON any one; Perhaps by SiO ₂Material forms; The thickness of described control gate dielectric layer is 10nm to 30nm.。

Described gate material layer 8 adopts polysilicon gate or metal gate, and described metal gate material comprises TaN, IrO ₂Or metal silicide; The thickness of the gate material layer of described polycrystalline silicon material or metal material is at least 100nm.

Structural representation based on the nano-crystal floating gate nonvolatile memory of multi-medium composite tunnel layer shown in Figure 1, Fig. 2 shows the realization flow figure of overall technological scheme that the present invention makes the nano-crystal floating gate nonvolatile memory of multi-medium composite tunnel layer, and this method may further comprise the steps:

Step 201: growth one deck SiO on silicon substrate ₂The tunnelling medium of material;

Step 202: at SiO ₂The tunnelling medium of growth one floor height k material on the tunnelling medium of material;

Step 203: growing nano-crystal floating gate layer on the tunnelling medium of high k material;

Step 204: growth high K medium barrier layer on ground floor nano-crystal floating gate layer;

Step 205: regrowth one deck nano-crystalline granule on the high K medium barrier layer;

Step 206: high k material of deposition or SiO on the nano-crystal floating gate layer ₂The control gate dielectric layer of material;

Step 207: the gate material layer of deposit spathic silicon material or metal material on the control gate dielectric layer;

Step 208: photoetching forms grid line bar figure in the resist on gate material layer;

Step 209: with the grid line bar figure on the resist is mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer forms the grid pile structure;

Step 210: photoetching, ion inject, and form the source conduction region and leak conduction region in the silicon substrate of grid line bar both sides;

Step 211: growth dielectric, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode, and encapsulation.

With above-mentioned steps 201 described one deck SiO that on silicon substrate, grow ₂The technological process of the tunnelling medium correspondence of material is shown in Fig. 3-1, and Fig. 3-1 is growth one deck SiO on silicon substrate 301 ₂The schematic diagram of the tunnelling medium 302 of material.Silicon substrate described in the step 201 is a p type silicon substrate; Described growth SiO ₂The method of the tunnelling medium of material is thermal oxidation, ald ALD, chemical vapor deposition CVD, electron beam evaporation or magnetron sputtering; Described SiO ₂The thickness of the tunnelling medium of material is 1nm to 5nm.

Described with above-mentioned steps 202 at SiO ₂The technological process of the tunnelling medium correspondence of growth one floor height k material is shown in Fig. 3-2 on the tunnelling medium of material, and Fig. 3-2 is at SiO ₂The schematic diagram of the tunnelling medium 303 of growth one floor height k material on the tunnelling medium 302 of material.The method of the tunnelling medium of the high k material of growth described in the step 202 is for utilizing magnetron sputtering, electron beam evaporation, chemical vapor deposition CVD or atomic layer deposition ALD; The thickness of the tunnelling medium of described high k material is 1nm to 20nm.

With above-mentioned steps 203 described on the tunnelling medium of high k material regrowth one deck SiO ₂The technological process of the tunnelling medium correspondence of material is shown in Fig. 3-3, and Fig. 3-3 is regrowth one deck SiO on the tunnelling medium 303 of high k material ₂The schematic diagram of the tunnelling medium 304 of material.SiO grows described in the step 203 ₂The method of the tunnelling medium of material is ald ALD, chemical vapor deposition CVD, electron beam evaporation or magnetron sputtering; Described SiO ₂The thickness of the tunnelling medium of material is 1nm to 5nm.

With one deck SiO that on silicon substrate 301, grows described in above-mentioned steps 201,202 and 203 ₂The tunnelling medium 302 of material is again at SiO ₂The tunnelling medium 303 of growth one floor height k material, regrowth one deck SiO on the tunnelling medium 303 of high k material again on the tunnelling medium 302 of material ₂The purpose of the tunnelling medium 304 of material is to form composite tunnel layer, the floating gate layer that is used to isolate silicon substrate and is used as charge storage layer, memory property indexs such as the write/erase speed of comprehensive simultaneously raising memory, write/erase voltage, retention time, stability, integration density.The ground floor SiO of described growth ₂The tunnelling medium of the tunnelling medium of material, the second floor height k material and the 3rd layer of SiO ₂The tunnelling medium of material is formed described composite tunnel layer in the certain thickness ratio, described SiO ₂Material medium/high k material medium/SiO ₂The gross thickness of material medium composite tunnel layer is 3nm to 30nm.

Described with above-mentioned steps 204 at SiO ₂On the tunnelling medium of material the technological process of growth one deck nano-crystal floating gate layer correspondence as shown in Figure 3-4, Fig. 3-4 is at SiO ₂The schematic diagram of growth one deck nano-crystalline granule 305 on the tunnelling medium 304 of material.Described in the step 204 at SiO ₂The purpose of growth one deck nano-crystalline granule is as charge storage media on the tunnelling medium of material; The method of described formation nano-crystalline granule is: the method for utilizing sputter or evaporation is at SiO ₂Material medium superficial growth one deck 1 according to the hot properties of different thin-film materials, corresponding different temperature short annealing 5 seconds to 90 seconds, makes thin-film material at SiO to metal, compound or silicon, the germanium film of 10nm thickness again ₂The dielectric surface crystallization, thus nano-crystalline granule formed as floating gate layer.

With the described technological processes that deposition one deck control gate dielectric layer is corresponding on the nano-crystal floating gate layer of above-mentioned steps 205 shown in Fig. 3-5, Fig. 3-5 be the schematic diagram that deposits one deck control gate dielectric layer 306 on nano-crystalline granule 305.The method that deposits the control gate dielectric layer described in the step 205 on the nano-crystal floating gate layer is: utilize chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering; The high k material or the SiO of described deposition ₂The thickness of control of material gate dielectric layer is 10nm to 50nm.

Described the corresponding technological process of deposition one deck gate material layer is shown in Fig. 3-6 on the control gate dielectric layer with above-mentioned steps 206, and Fig. 3-6 be the schematic diagram that deposits one deck gate material layer 307 on control gate dielectric layer 306.The method that deposits grid material described in the step 206 on the control gate dielectric layer is: use methods such as chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering at control gate dielectric film superficial growth one deck polysilicon or metallic film; The thickness of described film is at least 100nm.

Photoetching described in the above-mentioned steps 207 forms grid line bar figure and can further include in the resist on gate material layer: grid material surface applied one deck resist and before baking, to coated resist expose, development and photographic fixing formation grid line bar figure

With above-mentioned grid material surface applied one deck resist and before the corresponding technological process of baking shown in Fig. 3-7, Fig. 3-7 is the schematic diagram that dries by the fire before also at grid material 307 surface applied one deck resists 308.Described resist 308 is: AZ5214 negativity optics resist or SAL601 negative electronic erosion-resisting agent, and the thickness of described AZ5214 negativity optics resist is 1.5 μ m, corresponding preceding baking condition is: adopt hot plate to toast 100 seconds down at 100 ℃; The thickness of described SAL601 negative electronic erosion-resisting agent is 500nm, and corresponding preceding baking condition is: adopt hot plate to toast 2 minutes under 105 ℃ of temperature.

With above-mentioned to coated resist expose, development and photographic fixing form the corresponding technological process of gate figure shown in Fig. 3-8, Fig. 3-8 is the schematic diagram that coated resist 308 is exposed, development and photographic fixing form grid line bar figure 309.The line thickness of the grid structure that forms after the photoetching is the long 20nm to 2000nm of being of grid.

Described coated AZ5214 negativity optics resist 308 is exposed, develop and the concrete processing step of photographic fixing formation grid line bar figure 309 comprises: to AZ5214 negativity optics resist 308 utilize photomask with mask aligner by designed grid line bar graph exposure 30 seconds, toasted 70 seconds down at 115 ℃ with hot plate then, follow general exposing to the sun (i.e. direct naked the exposing to the sun without photomask) 60 seconds, use the special-purpose developer solution of AZ5214 (1Microposit 351:5H2O or 1AZ400K:4H2O) at room temperature to develop at last 50 seconds, only above grid heap to be formed, stay AZ5214 optics resist, adopt deionized water photographic fixing at room temperature 30 seconds at last, finish and in AZ5214 optics resist, form grid line bar figure.Adopting the width of the AZ5214 optics resist grid line bar figure of optical lithography formation is 500nm to 2000nm.

Described coated SAL601 negativity electron sensitive resist 308 is exposed, the concrete processing step that development and photographic fixing form grid line bar figure 309 comprises: adopt the e-beam direct write lithography systems to expose by designed grid line bar figure to SAL601 negative electronic erosion-resisting agent 308, then the SAL601 negative electronic erosion-resisting agent after the exposure was dried by the fire 2 minutes with hot plate back under 105 ℃, then adopt MF CD-26 developer solution at room temperature to develop 1 to 10 minute, adopt deionized water photographic fixing at room temperature 30 seconds at last, finish and in the SAL601 electronic corrosion-resistant, form grid line bar figure.Adopting the width of the SAL601 electronic corrosion-resistant grid line bar figure of electron beam lithography formation is 20nm to 500nm.

Be mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO with grid line bar figure described in the above-mentioned steps 208 ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer forms the grid pile structure and can further include: utilizes the resist figure to be mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer, removing photoresist forms the grid pile structure.

Be mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO with the above-mentioned resist figure that utilizes ₂Material medium/high k material medium/SiO ₂The technological process of material medium composite tunnel layer correspondence is shown in Fig. 3-9, and Fig. 3-9 is mask etching gate material layer 307, control gate dielectric layer 306, nano-crystal floating gate layer 305, SiO for utilizing resist figure 309 ₂Material medium 304/ high k material medium 303/SiO ₂The schematic diagram of material medium 302 composite tunnel layers.Among Fig. 3-9,310,311,312,313,314,315 are respectively the ground floor SiO after being etched ₂The tunnelling medium of the tunnelling medium of material, the second floor height k material, the 3rd layer of SiO ₂The tunnelling medium of material, nano-crystal floating gate layer, control gate dielectric layer, gate material layer.The described resist figure that utilizes is mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO ₂Material medium/high k material medium/SiO ₂The technical process that the material medium composite tunnel layer forms the grid pile structure comprises: the AZ5214 optics resist that covers on the grid surface or SAL601 electronic corrosion-resistant grid line bar figure as mask, are adopted high density inductively coupled plasma ICP lithographic method or reactive ion etching RIE method etch polysilicon or metal gate material layer, high k material or SiO successively ₂Control of material gate dielectric layer, nano-crystal floating gate layer, SiO ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer.

Form the corresponding technological process of grid pile structure shown in Fig. 3-10 with above-mentioned removing photoresist, Fig. 3-10 is for removing the schematic diagram that resist 309 forms the grid pile structure.Described method of removing photoresist is: wet method is removed photoresist, and adopts dense H ₂SO ₄+ H ₂O ₂Boiling glue removes photoresist.

Photoetching described in the above-mentioned steps 209, ion are injected, and form the source conduction region and leak conduction region can further include in the silicon substrate of grid line bar both sides: surface applied one deck AZ9912 positivity optics resist and before dry by the fire; Coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing form source, drain region figure; Silicon substrate ion to source, drain region injects the formation source, leaks conduction region; Remove photoresist, and short annealing.

The technological process corresponding with above-mentioned coating one deck AZ9912 positivity optics resist and preceding baking is shown in Fig. 3-11, and Fig. 3-11 is the schematic diagram of coating one deck AZ9912 positivity optics resist 316 and preceding baking.The thickness of described coated AZ9912 positivity optics resist 316 is 1.5 μ m; The condition of baking is before described: baking is 100 seconds before adopting hot plate under 100 ℃.

Coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing form the corresponding technological process in source, drain region figure shown in Fig. 3-12 with above-mentioned, Fig. 3-12 is for carrying out the schematic diagram that optical exposure, development and photographic fixing form source, drain region figure to coated AZ9912 positivity optics resist.Among Fig. 3-12,317 are the AZ9912 positivity optics resist after the exposure, and 318,319 are respectively source, the drain region figure that exposure forms.The described method that coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing is: adopt lay photoetching mask plate to shelter by the designed source in grid line bar both sides, drain region figure on mask aligner and expose, special-purpose developer solution with AZ9912 at room temperature developed 50 seconds then, with deionized water photographic fixing at room temperature 30 seconds, finish formation source, drain region figure in AZ9912 positivity optics resist at last.

Inject the formation source with above-mentioned silicon substrate ion to formed source, drain region, leak the corresponding technological process of conduction region shown in Fig. 3-13, Fig. 3-13 is the schematic diagram that the silicon substrate ion of formed source, drain region is injected formation source, leakage conduction region.Among Fig. 3-13,320,321 are respectively ion injects formed source, leakage.The described actual conditions that the silicon substrate ion of formed source, drain region is injected is: the silicon substrate to formed source, drain region injects P ³¹⁺Ion, the injection energy is 50keV, implantation dosage is 1 * 10 ¹⁸Cm ^-2

With above-mentioned remove photoresist and technological process that short annealing is corresponding shown in Fig. 3-14, Fig. 3-14 is for removing the schematic diagram of resist 317 and short annealing.Described method of removing photoresist is: wet method is removed photoresist, and promptly adopts dense H ₂SO ₄+ H ₂O ₂Boil glue; The purpose of described short annealing is activator impurity, reduces defective, thus in the silicon substrate of grid line bar both sides the formation source, leak conduction region; The actual conditions of described short annealing is: at N ₂Short annealing 10 seconds under 1100 ℃ of temperature in the atmosphere.

Grow described in the above-mentioned steps 210 dielectric, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode, and encapsulation can further include:

Deposit one deck dielectric;

On insulating medium layer coating one deck AZ9912 positivity optics resist and before dry by the fire;

Coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing, above source, leakage, gate region, form contact hole graph;

Utilize AZ9912 positivity optics resist figure to corrode the dielectric film at normal temperatures and expose source, leakage, grid material as mask;

Evaporation one deck Al-1%Si film is as metal electrode material on the AZ9912 positivity optics resist of the source of exposing, leakage, grid material surface and not removal;

Peel off the metal electrode material of AZ9912 positivity optics resist and last evaporation side thereof, and carry out annealing in process formation source, leakage, gate electrode peeling off the remaining metal electrode material in back.

The technological process corresponding with above-mentioned deposit one deck insulating medium layer is shown in Fig. 3-15, and Fig. 3-15 is the schematic diagram of deposit one deck insulating medium layer 322.Described dielectric material comprises SiO ₂, phosphorosilicate glass PSG, boron-phosphorosilicate glass BPSG etc.; The deposition process of described dielectric is chemical vapor deposition CVD, electron beam evaporation or magnetron sputtering.

With above-mentioned coating one deck AZ9912 positivity optics resist on the dielectric and before the corresponding technological process of baking shown in Fig. 3-16, Fig. 3-16 is coating AZ9912 positivity optics resist 323 and the preceding schematic diagrames that dry by the fire.The thickness of described AZ9912 positivity optics resist is 1.5 μ m, and the condition of baking was before coated AZ9912 positivity optics resist was carried out: baking is 100 seconds before adopting hot plate under 100 ℃.

With above-mentioned coated AZ9912 positivity optics resist is being carried out optical exposure, development, photographic fixing, the technological process that forms the contact hole graph correspondence above source, leakage, grid is shown in Fig. 3-17, and Fig. 3-17 is the schematic diagram that coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing.Among Fig. 3-17, be respectively the contact hole graph that above grid, source, leakage, forms in 324,325,326.The described actual conditions that coated AZ9912 positivity optics resist is carried out optical exposure, development and photographic fixing is: adopt lay photoetching mask plate to shelter on mask aligner and expose, special-purpose developer solution with AZ9912 at room temperature developed 50 seconds then, with deionized water photographic fixing at room temperature 30 seconds, finish above source, leakage, grid and form contact hole graph at last.

Corrode the dielectric film with the above-mentioned AZ9912 of utilization positivity optics resist figure at normal temperatures as mask and expose the corresponding technological process in source, leakage, grid material shown in Fig. 3-18, Fig. 3-18 is for to utilize AZ9912 positivity optics resist figure to corrode the schematic diagram of dielectric film at normal temperatures as mask.Among Fig. 3-18,327 are the dielectric layer film after being corroded, and 328,329,330 are respectively grid, source, the leakage material that exposes behind the corrosion dielectric layer film.The method of described corrosion dielectric film is: utilize AZ9912 positivity optics resist figure as mask, adopt buffered hydrofluoric acid solution (HF+NH ₄F+H ₂O) etching insulating layer film at normal temperatures.

With above-mentioned on the source of exposing, leakage, grid material surface and the AZ9912 positivity optics resist do not removed evaporation one deck Al-1%Si film as the corresponding technological process of metal electrode material shown in Fig. 3-19, Fig. 3-19 for evaporation one deck Al-1%Si film 331 on the source of exposing, leakage, grid material surface and the AZ9912 positivity optics resist do not removed as the schematic diagram of metal electrode material.The thickness of described Al-1%Si film is 1 μ m, and this thickness should be less than the thickness of AZ9912 positivity optics resist.

With the above-mentioned metal electrode material of peeling off AZ9912 positivity optics resist and going up evaporation side, and carrying out technological process that annealing in process forms source, leakage, gate electrode correspondence shown in Fig. 3-20 to peeling off the remaining metal electrode material in back, Fig. 3-20 is for peeling off and to remaining metal electrode being carried out the schematic diagram of annealing in process.Among Fig. 3-20,332,333,334 are respectively grid, source, the drain electrode of peeling off back formation.The described method of peeling off is: the metal electrode material that adopts the acetone ultrasonic AZ9912 of peeling off positivity optics resist and last evaporation side thereof; The actual conditions of described annealing in process is: under 400 ℃ at N ₂Annealing in process is 5 minutes in the atmosphere; Then under 400 ℃ at N ₂/ H ₂Annealing is 20 minutes in the mist; At last under 400 ℃ at N ₂Annealing is 5 minutes in the atmosphere.

Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (19)

1. the nano-crystal floating gate nonvolatile memory with many-valued memory function is characterized in that, this memory comprises:

Silicon substrate (1);

Source conduction region (9) and leakage conduction region (10) at silicon substrate (1) upper heavy doping;

Leak in the source cover on the carrier channels between the conduction region, by SiO ₂The composite tunnel layer that material medium (2) and high k material medium (3) constitute from bottom to top;

The first nano-crystal floating gate layer (4) that on composite tunnel layer, covers;

Go up the barrier layer medium (5) that covers as double-layer nanometer intergranular barrier layer at the first nano-crystal floating gate layer (4);

Go up the second nano-crystal floating gate layer (6) that covers at barrier layer medium (5);

The second nano-crystal floating gate layer (6) go up to cover by high k material or SiO ₂The control gate dielectric layer (7) that material constitutes; And

Go up the gate material layer (8) that covers at control gate dielectric layer (7).

2. the nano-crystal floating gate nonvolatile memory with many-valued memory function according to claim 1, it is characterized in that the described first nano-crystal floating gate layer (4), barrier layer medium (5) and the second nano-crystal floating gate layer (6) form the capture layer of this memory in the stacked structure of certain thickness ratio combination.

3. the nano-crystal floating gate nonvolatile memory with many-valued memory function according to claim 1, it is characterized in that, the material selection metallic nano crystal of the described first nano-crystal floating gate layer (4) and the second nano-crystal floating gate layer (6), the metallic nano crystal material is any one in W, Al, Ni, Co, Cr, Pt, Ru, Sn, Ti, Au and the Ag metal; Nanocrystalline diameter is 1nm to 10nm, and density is 1 * 10 ¹¹Cm ^-2To 1 * 10 ¹³Cm ^-2

4. the nano-crystal floating gate nonvolatile memory with many-valued memory function according to claim 1 is characterized in that, described barrier layer medium (5) is formed by high k material, comprises HfO ₂, Al ₂O ₃, ZrO ₂, Ta ₂O ₅, LaAlO ₃, any one or a few the combination among HfAlO, HfLaON and the HfTaON; The thickness of described barrier layer medium (5) is 3nm to 5nm.

5. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function is characterized in that, this method comprises:

A, on silicon substrate growth one deck SiO ₂The tunnelling medium of material;

B, at SiO ₂The tunnelling medium of growth one floor height k material on the tunnelling medium of material;

C, on the tunnelling medium of high k material the growing metal film, form the nano-crystal floating gate layer behind the high annealing;

The barrier layer of D, the high k material of on the nano-crystal floating gate layer, growing;

E, on high k material barrier layer regrowth layer of metal film, form second layer nano-crystal floating gate behind the high annealing;

F, on the nano-crystal floating gate layer deposition high k material or SiO ₂The control gate dielectric layer of material;

G, on the control gate dielectric layer gate material layer of deposit spathic silicon material or metal material;

H, photoetching form grid line bar figure in the resist on gate material layer;

I, be barrier layer, nano-crystal floating gate layer, SiO between mask etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, nano-crystal floating gate with grid line bar figure ₂Material medium/high k material medium composite tunnel layer forms the grid pile structure;

J, photoetching, ion inject, and form the source conduction region and leak conduction region in the silicon substrate of grid line bar both sides;

K, growth dielectric, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode, and encapsulation.

6. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5 is characterized in that SiO grows described in the steps A ₂The method of the tunnelling medium of material is: thermal oxidation, ald ALD, chemical vapor deposition CVD; Described SiO ₂The thickness of the tunnelling medium of material is 1nm to 5nm.

7. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that the method for the tunnelling medium of the high k material of growth described in the step B is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering.The thickness of the tunnelling medium of described high k material is 2nm to 10nm.

8. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5 is characterized in that, the SiO described in steps A and the step B ₂The tunnelling medium of the tunnelling medium of material/high k material is combined into described composite tunnel layer in the certain thickness ratio, and the gross thickness of described composite tunnel layer is 3nm to 15nm.

9. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that, the method of the floating gate layer of growing nano-crystal described in the step C is: adopt sputter or evaporation plated film on the composite tunnel dielectric layer, then the thin-film material that forms is carried out the high temperature rapid thermal treatment, make the thin-film material crystallization, form nano-crystalline granule.

10. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that the method on the barrier layer of the high k material of growth described in the step D is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering.The thickness of the tunnelling medium of described high k material is 3nm to 5nm.

11. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that, the method of the second layer of growth described in step e nano-crystal floating gate layer is: adopt sputter or evaporation plated film on high K dielectric barrier, then the thin-film material that forms is carried out the high temperature rapid thermal treatment, make the thin-film material crystallization, form nano-crystalline granule.

12. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5 is characterized in that, high k material of deposition or SiO described in the step F ₂The method of the control gate dielectric layer of material is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering; The high k material or the SiO of described deposition ₂The thickness of the control gate dielectric layer of material is 10nm to 30nm.

13. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that the method for the gate material layer of material of deposit spathic silicon described in the step G or metal material is: chemical vapor deposition CVD, ald ALD, electron beam evaporation or magnetron sputtering; The thickness of the polycrystalline silicon material of described deposition or the gate material layer of metal material is at least 100nm.

14. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that, be lithographically optical lithography or electron beam lithography described in the step H, the width of the grid line bar figure that forms after the photoetching is the long 20nm to 2000nm of being of grid.

15. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 14 is characterized in that, the concrete processing step of described optical lithography comprises:

At gate material layer surface applied one layer thickness is the AZ5214 negativity optics resist of 1.5 μ m, to baking before coated AZ5214 negativity optics resist employing hot plate is under 100 ℃ 100 seconds, the then exposure of adopting mask aligner to utilize photomask to be undertaken by designed gate figure 30 seconds to optics resist AZ5214, toasted 70 seconds down at 115 ℃ with hot plate then, follow general exposing to the sun, direct naked the exposing to the sun 60 seconds without photomask used the special-purpose developer solution 1Microposit of AZ5214 351:5H at last ₂0 or 1AZ400K:4H ₂O at room temperature developed 50 seconds, only stayed AZ5214 optics resist above grid heap to be formed, adopted deionized water photographic fixing at room temperature 30 seconds at last, finishes and form grid line bar figure in AZ5214 negativity optics resist; Adopting the width of the AZ5214 negativity optics resist grid line bar of optical lithography formation is 500nm to 2000nm.

16. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 14 is characterized in that, the concrete processing step of described electron beam lithography comprises:

At grid material surface applied one layer thickness is the SAL601 negative electronic erosion-resisting agent of 500nm, coated SAL601 negative electronic erosion-resisting agent was dried by the fire 2 minutes before hot plate is under 105 ℃, then adopt the e-beam direct write lithography system to expose by gate figure, then the SAL601 negative electronic erosion-resisting agent after the exposure was dried by the fire 2 minutes with hot plate back under 105 ℃, then adopt MF CD-26 developer solution at room temperature to develop 1 to 10 minute, adopt deionized water photographic fixing at room temperature 30 seconds again, finish and in the SAL601 negative electronic erosion-resisting agent, form grid line bar figure; Adopting the width of the SAL601 negative electronic erosion-resisting agent grid line bar of electron beam lithography formation is 20nm to 500nm.

17. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5 is characterized in that, described step I comprises:

The AZ5214 negativity optics resist that covers on the grid surface or SAL601 negative electronic erosion-resisting agent grid line bar figure as mask, are adopted high density inductively coupled plasma ICP lithographic method or reactive ion etching RIE method etching gate material layer, control gate dielectric layer, nano-crystal floating gate layer, SiO successively ₂Material medium/high k material medium/SiO ₂The material medium composite tunnel layer removes photoresist again, forms the grid pile structure; The described method of removing photoresist is that wet method is removed photoresist, and adopts dense H ₂SO ₄+ H ₂O ₂Boiling glue removes photoresist.

18. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5 is characterized in that, described step J comprises:

At surface applied one layer thickness is the AZ9912 positivity optics resist of 1.5 μ m, baking is 100 seconds before adopting hot plate under 100 ℃, the source, the drain region that adopt lay photoetching mask plate to be sequestered in grid line bar both sides on mask aligner expose, at room temperature developed 50 seconds with the special-purpose developer solution of AZ9912 then, with deionized water photographic fixing at room temperature 30 seconds, finish formation source, drain region figure in AZ9912 positivity optics resist at last; In the silicon substrate of formed source, drain region, inject P again ³¹⁺Ion, the injection energy is 50keV, implantation dosage is 1 * 10 ¹⁸Cm ^-2, again at dense H ₂SO ₄+ H ₂O ₂In boil glue and remove photoresist; Then under 1100 ℃ of temperature at N ₂Short annealing is 10 seconds in the atmosphere, thereby forms the source conduction region and leak conduction region in the silicon substrate of grid line bar both sides.

19. the manufacture method with nano-crystal floating gate nonvolatile memory of many-valued memory function according to claim 5, it is characterized in that, grow described in the step K dielectric, photoetching, burn into evaporated metal, peel off, anneal, form source electrode, drain electrode and gate electrode and comprise:

At first, at surface deposition one deck dielectric, material comprises: SiO ₂, phosphorosilicate glass PSG or boron-phosphorosilicate glass BPSG; Coating one layer thickness is the AZ9912 positivity optics resist of 1.5 μ m on this insulating medium layer then, adopt hot plate 100 ℃ down before baking 100 seconds, the employing lay photoetching mask plate is sheltered and is exposed on mask aligner; Next the special-purpose developer solution with AZ9912 positivity optics resist at room temperature developed 50 seconds; With deionized water photographic fixing at room temperature 30 seconds, finish above source, leakage, grid and form contact hole graph at last;

Next step utilizes AZ9912 positivity optics resist figure as mask, adopts buffered hydrofluoric acid solution HF+NH ₄F+H ₂O corrodes insulating medium layer at normal temperatures;

Again next step, as metal electrode material, the thickness of described Al-1%Si film is 1 μ m to evaporation one layer thickness less than the Al-1%Si film of AZ9912 positivity optics resist thickness on the AZ9912 positivity optics resist of the source of exposing, leakage, grid material surface and not removal;

Then, adopt the ultrasonic metal electrode material of peeling off AZ9912 positivity optics resist and going up evaporation side of acetone;

At last, carry out annealing in process formation source, leakage, gate electrode to peeling off the remaining metal electrode material in back; Describedly be to peeling off the condition that the remaining metal electrode material in back carries out annealing in process: under 400 ℃ of temperature at N ₂Annealing in process is 5 minutes in the atmosphere; Then under 400 ℃ of temperature at N ₂/ H ₂Annealing is 20 minutes in the mist; At last under 400 ℃ of temperature at N ₂Annealing is 5 minutes in the atmosphere.

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