CN102655167A - Charge-trapping type gate stack and storage unit - Google Patents
Charge-trapping type gate stack and storage unit Download PDFInfo
- Publication number
- CN102655167A CN102655167A CN2011100500916A CN201110050091A CN102655167A CN 102655167 A CN102655167 A CN 102655167A CN 2011100500916 A CN2011100500916 A CN 2011100500916A CN 201110050091 A CN201110050091 A CN 201110050091A CN 102655167 A CN102655167 A CN 102655167A
- Authority
- CN
- China
- Prior art keywords
- sublayer
- layer
- charge
- storage medium
- charge trap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a charge-trapping type gate stack and a storage unit. The gate stack is formed by stacking a tunneling layer, a storage layer and a blocking layer from bottom to top, wherein the storage layer is formed by stacking at least three medium sub-layers including at least two storage medium sub-layers and at least one modulation medium sub-layer sandwiched between the storage medium sub-layers, and the modulation medium sub-layer is used for changing the charge distribution in the storage layer so as to reduce charges close to the blocking layer and gather the charges in the storage layer. According to the invention, through effectively controlling the charge distribution in the storage layer, the data retention property of the storage layer of the gate stack for the charge constraint capacity can be improved, and high-reliability operation for a device can be realized. In addition, through introducing a modulation structure of the storage layer, device performances such as the programming efficiency, the operation voltage of a charge-trapping type nonvolatile memory device are optimized.
Description
Technical field
The present invention relates to microelectronic industry memory technology field, relate in particular to a kind of charge trap-type grid storehouse and memory cell.
Background technology
Present microelectronic product mainly is divided into logical device and memory device two big classes, and all need use memory device in nearly all now electronic product, thereby memory device occupies important status at microelectronic.Memory device generally can be divided into volatile storage and nonvolatile memory.The main feature of non-volatility memorizer is under situation about not powering up, also can keep canned data for a long time.The characteristics of its existing read-only memory (ROM) have very high access speed again, and are easy to wipe and rewrite, and power consumption is less.Along with the needs to big capacity, low-power consumption storage such as multimedia application, mobile communication; Non-volatility memorizer; Flash memory (Flash) particularly, the market share of shared semiconductor device becomes increasing, also more and more becomes a kind of considerable type of memory.
Traditional Flash memory is the silica-based nonvolatile memory that adopts the polysilicon membrane FGS floating gate structure, and a defective on the device tunneling medium layer (generally being oxide layer) promptly can form fatal discharge channel.The charge trap-type memory utilizes electric charge localization characteristic stored in the capture layer; Realize discrete charge storage; Defective on the tunneling medium layer only can cause local electric charge to leak; Make electric charge keep more stable like this, this structure and logic process are compatible fully simultaneously, replace conventional FGS floating gate structure with inevitable.
Fig. 1 is the structural representation of prior art charge trap-type memory of the present invention.Fig. 2 is the band structure sketch map of charge trap-type memory shown in Figure 1.For charge trap-type memory shown in Figure 1, the optimization of device performances such as its programming efficiency, memory window, operating voltage and data retention characteristics becomes the focus of people's research gradually.In realizing process of the present invention, the inventor recognizes that prior art charge trap-type grid storehouse has following defective: accumulation layer is relatively poor to the constraint ability of electric charge, causes the data retention characteristics of memory cell not good.
Summary of the invention
The technical problem that (one) will solve
For addressing the aforementioned drawbacks, the invention provides a kind of charge trap-type grid storehouse and memory cell, to improve the constraint ability of grid storehouse accumulation layer, strengthen the data retention characteristics of memory cell to electric charge.
(2) technical scheme
According to an aspect of the present invention, a kind of charge trap-type grid storehouse is provided.This grid storehouse is piled up from bottom to top by tunnel layer, accumulation layer and barrier layer and forms; Wherein, This accumulation layer is piled up by at least three layers of medium sublayer and is formed, at least three layers of medium sublayer comprise two-layer at least storage medium sublayer and at least one deck be sandwiched in and can be with the modulated media sublayer between the storage medium sublayer, can be used for changing the CHARGE DISTRIBUTION of accumulation layer with the modulated media sublayer; To reduce electric charge, make charge concentration in accumulation layer near the barrier layer.
Preferably, in the charge trap-type grid storehouse of the present invention, the storage medium sublayer is by high defect concentration low energy gap width dielectric material or dark conduction level dielectric material preparation; Can be with of the dielectric material preparation of modulated media sublayer by the broad stopband width; The forbidden band of storage medium sub-layer material falls into can be with the forbidden band of modulated media sublayer.
Preferably, in the charge trap-type grid storehouse of the present invention, formation can be at least a in the following material with the broad stopband width dielectric material of modulated media sublayer: SiON or Al
2O
3
Preferably, in the charge trap-type grid storehouse of the present invention, can with the thickness of modulated media sublayer 0.5-5nm.
Preferably, in the charge trap-type grid storehouse of the present invention, the high defect concentration low energy gap width dielectric material that forms the storage medium sublayer is at least a in the following material: Si
3N
4Or HfO
2Dark conduction level dielectric material is a kind of in the following material: silicon nanocrystal or metallic nano crystal.
Preferably, in the charge trap-type grid storehouse of the present invention, accumulation layer comprises three layers of medium sublayer, upwards is followed successively by the storage medium sublayer, can be with modulated media sublayer and storage medium sublayer from tunnel layer.
Preferably, in the charge trap-type grid storehouse of the present invention, the storage medium sublayer is that thickness is the HfO of 5nm
2The sublayer can be that thickness is the Al of 2nm with the modulated media sublayer
2O
3The sublayer.
Preferably, in the charge trap-type grid storehouse of the present invention, accumulation layer comprises five layers of medium sublayer, upwards is followed successively by the storage medium sublayer, can be with the modulated media sublayer, the storage medium sublayer, can be with modulated media sublayer and storage medium sublayer from tunnel layer.
Preferably, in the charge trap-type grid storehouse of the present invention, the SiO of broad stopband width dielectric material is adopted on tunnel layer and barrier layer
2Or Al
2O
3
According to another aspect of the present invention, a kind of charge trap-type memory cell is provided.This memory cell comprises: be formed at source electrode, the drain electrode of substrate both sides, and be formed at grid storehouse, the gate electrode of top, substrate middle part; The grid storehouse is the grid storehouse of preceding text.
(3) beneficial effect
Among the present invention,, can improve the data retention characteristics of grid storehouse accumulation layer, realize the high reliability operation of device the constraint ability of electric charge through the CHARGE DISTRIBUTION in effective control store layer.In addition, the present invention can be with modulated structure through introducing accumulation layer, realizes the optimization of device performances such as charge trap-type non-volatile memory device programming efficiency, operating voltage.Simultaneously, the preparation technology of charge trap-type grid storehouse of the present invention and conventional silicon planar CMOS process compatible are beneficial to extensive use.
Description of drawings
Fig. 1 is the structural representation of prior art charge trap-type memory of the present invention;
Fig. 2 is the band structure sketch map of charge trap-type memory shown in Figure 1;
Fig. 3 is the structural representation of embodiment of the invention charge trap-type memory cell;
Fig. 4 is the band structure sketch map of charge trap-type memory shown in Figure 3;
The structural representation of Fig. 5 another embodiment of the present invention charge trap-type memory cell;
Fig. 6 is the band structure sketch map of charge trap-type memory shown in Figure 5;
Fig. 7 can be with modulated charge to capture type memory cell and conventional store layer structure operation voltage and memory window test result comparison diagram for accumulation layer in the specific embodiment of the invention;
Fig. 8 can be with modulated charge to capture the type memory cell for accumulation layer in the specific embodiment of the invention and conventional store layer structure programmed, efficiency of erasing test result comparison diagram;
Fig. 9 can be with modulated charge for accumulation layer in the specific embodiment of the invention and capture data maintenance The performance test results comparison diagram under type memory cell and the conventional store layer structure room temperature.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, to further explain of the present invention.
In an exemplary embodiment of the present invention, a kind of charge trap-type grid storehouse is provided.This grid storehouse comprises from bottom to top: tunnel layer, accumulation layer and barrier layer.Wherein, This accumulation layer is piled up by at least three layers of medium sublayer and is formed; At least three layers of medium sublayer comprises two-layer at least storage medium sublayer and be sandwiched in can be with the modulated media sublayer between the storage medium sublayer, can be used for changing the CHARGE DISTRIBUTION of accumulation layer with the modulated media sublayer.Wherein, the CHARGE DISTRIBUTION in the above-mentioned change accumulation layer mainly refers to: make electric charge mainly be limited in the accumulation layer, near the electric charge minimizing on barrier layer, thereby effectively reduce the leakage current when programming.
Preferably, the storage medium sublayer is by the dielectric material preparation of the dielectric material or the dark conduction level of high defect concentration low energy gap width; Can be with of the dielectric material preparation of modulated media sublayer by the broad stopband width; The forbidden band of storage medium sub-layer material falls into can be with the forbidden band of modulated media sublayer.
In the present embodiment,, can improve the data retention characteristics of grid storehouse, realize the high reliability operation of device the constraint ability of electric charge through the CHARGE DISTRIBUTION in effective control store layer.
In the present invention preferably in the embodiment charge trap-type grid storehouse, formation can be at least a in the following material with the material of the broad stopband width of modulated media sublayer: SiON or Al
2O
3, its thickness is 0.5-5nm.The dielectric material that constitutes the high defect concentration low energy gap width of storage medium sublayer is a kind of in the following material: Si
3N
4Or HfO
2The dielectric material of dark conduction level is a kind of in the following material: silicon nanocrystal or metallic nano crystal.
For the grid storehouse of present embodiment, its manufacturing approach defines the gate patterns zone again for forming material requested successively earlier.Its technology that relates to comprises thermal oxidation; But the technology of chemical vapor deposition method, sputtering technology, atomic layer deposition technology, thermal evaporation technology, pulsed laser deposition technology, electron beam evaporation process or other implementation structure is like conventional methods such as photoetching, etching, flattening surface, annealing.
According to another aspect of the present invention, a kind of charge trap-type memory cell also is provided.This memory cell comprises: be formed at source electrode, the drain electrode of substrate both sides, and be formed at grid storehouse, the gate electrode of top, substrate middle part; The grid storehouse is above-mentioned grid storehouse.Because this grid storehouse strengthens the also corresponding raising of the data retention characteristics of this memory cell to the constraint ability of electric charge.
For the charge trap-type memory cell of present embodiment, can adopt modes such as electric field auxiliary (Fowler-Nordheim is called for short FN) tunnelling, channel hot electron injection (CHE) programming to realize programming operation.Can adopt that the FN grid are wiped, the band-to-band-tunneling hot hole injects modes such as (BBTH) and realizes erase operation.Reading of information can be accomplished through read forward or back read operation.
Below will be elaborated to the present invention, it should be noted that the concrete technical characterictic in following examples only is used to understand the present invention, not constitute restriction protection range of the present invention with certain embodiments.
Fig. 3 is the structural representation of embodiment of the invention charge trap-type memory cell.Fig. 4 is the band structure sketch map of charge trap-type memory shown in Figure 3.In the present embodiment, the grid stack architecture is mainly piled up from bottom to top by tunnel layer, accumulation layer and barrier layer and forms.Wherein broad stopband width dielectric material such as SiO are adopted in tunnel layer and barrier layer
2, Al
2O
3, or other has the material of similarity.Each thickness of thin layer can be according to the different adjustment of material therefor.Accumulation layer is piled up by three layers of dielectric material and is formed, and wherein mainly plays the dielectric material such as the Si of the high defect concentration low energy gap width of can adopting of memory action
3N
4, HfO
2Deng, also can adopt the material such as the formations such as silicon nanocrystal, metallic nano crystal of dark conduction level, its thickness can be according to the different adjustment of material therefor.For the CHARGE DISTRIBUTION in the optimal Storage layer, the material of insertion one deck broad stopband such as SiON, Al in the low energy gap storage medium
2O
3, or other has the material of similarity, and the forbidden band of arrowband material is dropped in the forbidden band of broadband material fully.The wide-band gap material thickness of thin layer that inserts small gap material is about 0.5-5nm, and position close tunnel layer or near the barrier layer is positioned at the situation of small gap material central authorities for wide-band gap material shown in Fig. 3.
Specifically, for charge trap-type memory cell as shown in Figure 3, its substrate is p type Si; Tunnel layer is SiO
2, form by thermal oxidation method.Small gap material and elastic braid material are respectively HfO in the accumulation layer stacked structure
2And Al
2O
3, the Al of insertion
2O
3Thickness of thin layer is 2nm, is positioned at HfO
2Storage medium central authorities, HfO up and down
2Layer thickness is 5nm.The barrier layer is by Al
2O
3Material constitutes, and thickness is 10nm.Accumulation layer and barrier layer form by atomic layer deposition technology.Electrode material is Al, is prepared by electron beam evaporation method.
The structural representation of Fig. 5 another embodiment of the present invention charge trap-type memory cell.Fig. 6 is the band structure sketch map of charge trap-type memory shown in Figure 5.As shown in Figure 6, in the present embodiment charge trap-type memory cell, its grid stack architecture mainly is made up of tunnel layer, accumulation layer and barrier layer.Wherein broad stopband width dielectric material such as SiO are adopted in tunnel layer and barrier layer
2, Al
2O
3, or other has the material of similarity.Each thickness of thin layer can be according to the different adjustment of material therefor.Accumulation layer is piled up by multilayered medium material and is formed, and wherein mainly plays the dielectric material such as the Si of the high defect concentration low energy gap width of can adopting of memory action
3N
4, HfO
2Deng, also can adopt the material such as the formations such as silicon nanocrystal, metallic nano crystal of dark conduction level, its thickness can be according to the different adjustment of material therefor.For the CHARGE DISTRIBUTION in the optimal Storage layer, the material of insertion multilayer broad stopband such as SiON, Al in the low energy gap storage medium
2O
3, or other has the material of similarity, and the forbidden band of arrowband material is dropped in the forbidden band of broadband material fully, is illustrated in figure 5 as the situation of inserting two-layer wide-band gap material.The wide-band gap material thickness of thin layer that inserts small gap material is about 0.5-5nm, and position close tunnel layer or near the barrier layer is the situation of branch small gap material such as two-layer wide-band gap material shown in the figure.
Can in specific embodiment, also prepare traditional individual layer accumulation layer capacitance structure with the optimization function of modulated structure to device performance in order to contrast accumulation layer, as shown in Figure 1, accumulation layer is 10nm HfO
2It is identical that material, other structure, material and preparation technology and accumulation layer can be with modulated charge to capture type capacitance stores structure.
Fig. 7 can be with modulated charge to capture type memory cell and conventional store layer structure operation voltage and memory window test result comparison diagram for accumulation layer in the specific embodiment of the invention.Based on identical scanning voltage scope, has bigger memory window through the structure that can be with modulation to optimize.
Fig. 8 can be with modulated charge to capture the type memory cell for accumulation layer in the specific embodiment of the invention and conventional store layer structure programmed, efficiency of erasing test result comparison diagram.Can be with structure programming, the efficiency of erasing modulated after optimizing to have through accumulation layer significantly improves.
Fig. 9 can be with modulated charge for accumulation layer in the specific embodiment of the invention and capture data maintenance The performance test results comparison diagram under type memory cell and the conventional store layer structure room temperature.Can be with the structure after modulation is optimized to have good data maintenance performance through accumulation layer, can be used for high reliability operation.
From the above, in an embodiment of the present invention, can be with modulated structure, realize the optimization of device performances such as charge trap-type non-volatile memory device programming efficiency, operating voltage through introducing accumulation layer.Simultaneously; This prioritization scheme can improve data retention characteristics through the CHARGE DISTRIBUTION in effective control store layer, realizes the high reliability operation while of device; Charge trap-type splitting bar memory fabrication technology of the present invention and conventional silicon planar CMOS process compatible are beneficial to extensive use.
Above-described specific embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely specific embodiment of the present invention; Be not limited to the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. charge trap-type grid storehouse; It is characterized in that; This grid storehouse is piled up from bottom to top by tunnel layer, accumulation layer and barrier layer and forms, and wherein, this accumulation layer is piled up by at least three layers of medium sublayer and formed; Said at least three layers of medium sublayer comprise two-layer at least storage medium sublayer and at least one deck be sandwiched in and can be with the modulated media sublayer between the said storage medium sublayer; The said CHARGE DISTRIBUTION that can be used for changing accumulation layer with the modulated media sublayer to reduce the electric charge near the barrier layer, makes charge concentration in accumulation layer.
2. charge trap-type grid storehouse according to claim 1 is characterized in that:
Said storage medium sublayer is by high defect concentration low energy gap width dielectric material or dark conduction level dielectric material preparation;
Said can the preparation with the dielectric material of modulated media sublayer by the broad stopband width;
The forbidden band of said storage medium sub-layer material fall into said can be with the forbidden band of modulated media sublayer.
3. charge trap-type grid storehouse according to claim 2 is characterized in that: forming said can be at least a in the following material with the broad stopband width dielectric material of modulated media sublayer: SiON or Al
2O
3
4. charge trap-type grid storehouse according to claim 3 is characterized in that: said can be 0.5-5nm with the thickness of modulated media sublayer.
5. charge trap-type grid storehouse according to claim 3 is characterized in that: the said high defect concentration low energy gap width dielectric material that forms said storage medium sublayer is at least a in the following material: Si
3N
4Or HfO
2Said dark conduction level dielectric material is a kind of in the following material: silicon nanocrystal or metallic nano crystal.
6. charge trap-type grid storehouse according to claim 5 is characterized in that: said accumulation layer comprises three layers of medium sublayer, upwards is followed successively by the storage medium sublayer, can be with modulated media sublayer and storage medium sublayer from tunnel layer.
7. charge trap-type grid storehouse according to claim 5 is characterized in that: said storage medium sublayer is that thickness is the HfO of 5nm
2The sublayer, said can be that thickness is the Al of 2nm with the modulated media sublayer
2O
3The sublayer.
8. charge trap-type grid storehouse according to claim 5; It is characterized in that: said accumulation layer comprises five layers of medium sublayer, upwards is followed successively by the storage medium sublayer, can be with the modulated media sublayer, the storage medium sublayer, can be with modulated media sublayer and storage medium sublayer from tunnel layer.
9. according to each described charge trap-type grid storehouse among the claim 1-8, it is characterized in that: the SiO of broad stopband width dielectric material is adopted on said tunnel layer and barrier layer
2Or Al
2O
3
10. a charge trap-type memory cell is characterized in that, this memory cell comprises: be formed at source electrode, the drain electrode of substrate both sides, and be formed at grid storehouse, the gate electrode of top, substrate middle part; Said grid storehouse is like each described grid storehouse among the claim 1-9.
11. charge trap-type memory cell according to claim 10 is characterized in that, said memory cell:
Adopt electric field to assist FN tunnelling mode or channel hot electron injection mode to carry out programming operation;
Adopt FN grid erase mode, band-to-band-tunneling hot hole injection mode to carry out erase operation;
Adopt read forward or back read operation to carry out reading of information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100500916A CN102655167A (en) | 2011-03-02 | 2011-03-02 | Charge-trapping type gate stack and storage unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100500916A CN102655167A (en) | 2011-03-02 | 2011-03-02 | Charge-trapping type gate stack and storage unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102655167A true CN102655167A (en) | 2012-09-05 |
Family
ID=46730762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100500916A Pending CN102655167A (en) | 2011-03-02 | 2011-03-02 | Charge-trapping type gate stack and storage unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102655167A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761989A (en) * | 2014-01-03 | 2014-04-30 | 南京大学 | Method for measuring local charge distribution in SONOS (silicon oxide nitride oxide semiconductor) storage by utilizing single charge technology |
| CN110783343A (en) * | 2019-11-05 | 2020-02-11 | 中国科学院微电子研究所 | Improved charge trapping memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050093054A1 (en) * | 2003-11-05 | 2005-05-05 | Jung Jin H. | Non-volatile memory devices and methods of fabricating the same |
| CN101101926A (en) * | 2007-07-10 | 2008-01-09 | 清华大学 | Non-volatile memory part for multi-digit storage and its making method |
| CN101807576A (en) * | 2009-02-13 | 2010-08-18 | 中国科学院微电子研究所 | Nano-crystal floating gate nonvolatile memory and manufacturing method thereof |
| CN101924109A (en) * | 2009-06-11 | 2010-12-22 | 上海华虹Nec电子有限公司 | Structure and method for improving data storage capability of silicon oxide nitride oxide semiconductor (SONOS) flash memory |
-
2011
- 2011-03-02 CN CN2011100500916A patent/CN102655167A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050093054A1 (en) * | 2003-11-05 | 2005-05-05 | Jung Jin H. | Non-volatile memory devices and methods of fabricating the same |
| CN101101926A (en) * | 2007-07-10 | 2008-01-09 | 清华大学 | Non-volatile memory part for multi-digit storage and its making method |
| CN101807576A (en) * | 2009-02-13 | 2010-08-18 | 中国科学院微电子研究所 | Nano-crystal floating gate nonvolatile memory and manufacturing method thereof |
| CN101924109A (en) * | 2009-06-11 | 2010-12-22 | 上海华虹Nec电子有限公司 | Structure and method for improving data storage capability of silicon oxide nitride oxide semiconductor (SONOS) flash memory |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761989A (en) * | 2014-01-03 | 2014-04-30 | 南京大学 | Method for measuring local charge distribution in SONOS (silicon oxide nitride oxide semiconductor) storage by utilizing single charge technology |
| CN103761989B (en) * | 2014-01-03 | 2016-01-20 | 南京大学 | Single charging techniques is utilized to measure the method for local hole distribution in SONOS storer |
| CN110783343A (en) * | 2019-11-05 | 2020-02-11 | 中国科学院微电子研究所 | Improved charge trapping memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI373846B (en) | Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells | |
| JP4374037B2 (en) | Nonvolatile semiconductor memory and manufacturing method thereof | |
| TWI305947B (en) | A novel low power non-volatile memory and gate stack | |
| JP4314259B2 (en) | Nonvolatile semiconductor memory | |
| EP1253646A1 (en) | Insulating barrier | |
| JP4372174B2 (en) | Nonvolatile semiconductor memory and manufacturing method thereof | |
| KR20050043135A (en) | Non volatile memory and fabrication method thereof | |
| CN102339833B (en) | High-reliability split-gate nonvolatile memory structure with high-speed low-voltage operation function | |
| CN101807576A (en) | Nano-crystal floating gate nonvolatile memory and manufacturing method thereof | |
| JP2005328029A (en) | Nonvolatile semiconductor storage element and method for manufacturing the same | |
| CN102655167A (en) | Charge-trapping type gate stack and storage unit | |
| US8659071B2 (en) | Method and structure to improve the erasing speed operation of SONOS memory device having a graded silicon nitride layer | |
| CN102456746B (en) | Nonvolatile semiconductor memory cell, device and preparation method thereof | |
| CN102201453B (en) | Memory unit and nonvolatile memory device and foming method thereof | |
| CN101383378A (en) | Non-volatile memory of multi-layered nano-crystal floating gate structure | |
| JP4492930B2 (en) | Charge storage memory and manufacturing method thereof | |
| US20070090448A1 (en) | Systems and methods for memory structure comprising embedded flash memory | |
| CN101330008A (en) | Method for making metal nanocrystalline non-volatility memory | |
| US20090108329A1 (en) | Non-volatile semiconductor device and method of fabricating the same | |
| JP2009076764A (en) | Nonvolatile semiconductor memory, method of writing to the same, and method of erasing the same | |
| CN102315223A (en) | High-performance plane floating gate flash memory device structure and making method thereof | |
| US20100044775A1 (en) | Semiconductor memory device and semiconductor device | |
| CN102117810A (en) | Charge trapping type nonvolatile memory and manufacturing method thereof | |
| CN112490248B (en) | Ferroelectric floating gate memory cell string and preparation method thereof | |
| CN102983138A (en) | Charge trapping type non-volatilization memorizer and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120905 |