JP2009076764A - Nonvolatile semiconductor memory, method of writing to the same, and method of erasing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To balance speed-up of "writing and erasing" and improvement of "charge retention characteristics and read-out characteristics". <P>SOLUTION: A nonvolatile semiconductor memory has a memory cell 1 having: a silicon substrate 10; source region and drain region 14a and 14b provided away from the silicon substrate; a first barrier layer 21 provided on the silicon substrate between the source region and the drain region; a first quantum well layer 22 in which a first energy level group including at least one energy level quantized is formed in a conduction band; a second barrier layer 23; a second quantum well layer 24 in which a second energy level group including at least one energy level which is different from the energy level of the first energy level group and which is quantized is formed in the conduction band, and in which there is an energy level EC2 larger than any one energy level EC1 in the first energy level group in the second energy level group; a third barrier layer 25; and a control electrode 26. The second quantum well layer is capable of storing electrons. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory, a writing method thereof, and an erasing method thereof.

  Generally, a flash memory, which is one of nonvolatile semiconductor memories, is a nonvolatile memory that does not require an electrical holding operation (holding power supply) for storage, and can easily write a program or the like even after the product is completed. Therefore, it is widely used in a wide variety of electronic devices. The next generation and later flash memories are required to be further miniaturized and operated at a low voltage.

  The tunnel layer in the next generation or later flash memory has a larger current flowing in order to perform high-speed writing or erasing at the time of “writing or erasing”, and leaking at the time of “charge holding” or “data reading”. It is desired that the current (leakage current) is smaller.

  However, generally, when the speed of writing and erasing is increased, the retention characteristics tend to be deteriorated. Usually, since the height of the tunnel barrier is fixed, “acceleration of writing and erasing” can be realized by making the barrier low and thin, but at that time, “charge retention characteristics and read characteristics” deteriorate. Conversely, increasing the barrier thickness and thickness improves the “charge retention characteristics and read characteristics”, but slows the “write and erase” speed. Thus, it is difficult to achieve both “acceleration of writing and erasing” and “improvement of charge holding characteristics and reading characteristics”.

  As a solution to this problem, a proposal has been made to raise the electron barrier by accumulating electrons in the tunnel layer (see, for example, Non-Patent Document 1). In this case, a Coulomb blockade is used, and the feature is that electrons are accumulated in Si dots.

Further, it has been proposed to use a single quantum well structure in order to increase the speed of “writing and erasing” (see, for example, Patent Document 1).
R.Ohba et.al., Technical Digest of Electron Device Meeting 2005 P853 JP 2001-244352 A

  When the technology disclosed in Non-Patent Document 1 described above is used, it is necessary to increase the energy level in the quantum dot in order to satisfy the performance required in the next generation or later flash memory. Dots will be used. However, if a too small quantum dot is used, the energy for accumulating charges increases, so it becomes difficult to maintain the Coulomb blockade above room temperature. That is, the mechanism of Non-Patent Document 1 cannot operate at room temperature or higher when miniaturization progresses.

  Further, when the technique disclosed in Patent Document 1 is used, sufficient charge holding cannot be performed in the charge holding state and the reading state. This is because the resonance state of the single quantum well lowers the effective barrier, and the effective barrier when the retained electrons escape to the channel side is also low. That is, the speed of “writing and erasing” is increased, and the characteristics of “charge retention” and “data reading” are deteriorated.

  As described above, according to the conventional technique, it is impossible to achieve both the speeding up of “writing and erasing” and the improvement of “charge holding characteristics and reading characteristics”.

  The present invention has been made in consideration of the above-described circumstances, and is a nonvolatile semiconductor memory that can achieve both high-speed “writing and erasing” and “charge retention characteristics and reading characteristics”, and writing thereof It is an object to provide a method and an erasing method thereof.

  A nonvolatile semiconductor memory according to a first aspect of the present invention includes a silicon substrate, a source region and a drain region that are provided apart from the silicon substrate, and the silicon substrate between the source region and the drain region. And a first quantum well provided on the first barrier layer, wherein a first energy level group including at least one energy level quantized in a conduction band is formed. A layer, a second barrier layer provided on the first quantum well layer, a quantization provided on the second barrier layer and different from the energy levels of the first energy level group in a conduction band A second energy level group including at least one energy level is formed, and one of the energy levels E of the first energy level group among the second energy level groups. A second quantum well layer having an energy level EC2 greater than 1, a third barrier layer provided on the second quantum well layer, and a control electrode provided on the third barrier layer. The second quantum well layer is capable of storing electrons.

  A non-volatile semiconductor memory writing method according to a second aspect of the present invention is the non-volatile semiconductor memory writing method according to the first aspect, in which the energy level in the first energy level group and the first Data is written by applying, to the control electrode, a positive voltage that causes resonance with the energy level in the two energy level group.

  The non-volatile semiconductor memory erasing method according to the third aspect of the present invention is the non-volatile semiconductor memory erasing method according to the first aspect, wherein the energy level in the first energy level group and the first Data is erased by applying, to the control electrode, a negative voltage that causes resonance with an energy level in the two energy level group.

  A non-volatile semiconductor memory erase method according to a fourth aspect of the present invention is the non-volatile semiconductor memory erase method according to the first aspect, wherein the first quantum well layer is quantized in the valence band. Data is erased by applying a negative voltage that causes resonance between the energy level and the quantized energy level in the valence band of the second quantum well layer to the control electrode. .

  According to the present invention, it is possible to achieve both speeding up of “writing and erasing” and improvement of “charge holding characteristics and reading characteristics”.

  Since the nonvolatile semiconductor memory of each embodiment of the present invention is a charge storage type memory, an outline of the charge storage type memory will be first described before describing the embodiment of the present invention.

  The charge storage type memory of each embodiment of the present invention has at least one memory cell 1, and a cross section of the memory cell 1 is shown in FIG. The memory cell 1 has a source region 14 a and a drain region 14 b that are formed apart from the silicon semiconductor substrate 10. A channel region 12 is formed between the source region 14a and the drain region 14b. On the channel region 12, a gate 20 for controlling the memory operation is provided. The gate 20 is formed on the silicon substrate 10 with a first barrier layer 21, a first quantum well layer 22, a second barrier layer 23, a charge storage layer 24 serving as a second quantum well layer, and a block layer 25 serving as a third barrier layer. , And the control electrode 26 in this order. Here, the first barrier layer 21, the first quantum well layer 22, and the second barrier layer 23 form a first quantum well. The second barrier layer 23, the second quantum well layer (charge storage layer) 24, and the third barrier layer (block layer) 25 form a second quantum well. Thus, the gate 20 has a triple barrier and a double well structure. The energy band of the gate 20 is shown in FIGS. 2 (a) and 2 (b). 2A is an energy band diagram in a non-resonant state, and FIG. 2B is an energy band diagram in a resonant state.

(Resonant state and non-resonant state)
Next, the resonance state and non-resonance state of the charge storage type memory will be described.

  First, let us consider a case where the gate has a single barrier as shown in FIG. A well having a continuous energy level (continuous state) exists beyond the single barrier. It can be understood that this state is continuous because the well width is wide and the quantum level interval is narrowed. Considering the level spread at the memory operating temperature, if there is no energy level difference of 0.25 eV or more, it is regarded as a continuous state. This well having a continuous state is called a classical well in order to distinguish it from a quantum well. This energy width, 0.25 eV, can be converted into a well width (layer thickness of the well layer). If the well width is 1.2 nm or less, the well is considered to be quantized. I can do it.

Further, unlike each embodiment of the present invention, FIG. 3B shows an energy band diagram in the case where the gate has a single quantum well structure. The gate shown in FIG. 3B is drawn as a classical well that forms a continuous state with a quantum well having one quantum level inside the well (the barrier on the right side of the classical well is considered to be infinitely far away. Is a stacked structure. In this case, the quantum level in the quantum well and the state in the classical well overlap with each other in the wave function, resulting in a resonance state. In other words, electrons with energy higher than the quantum level pass through a continuous state. This is indicated by the arrow 200 in FIG. The applied voltage dependence of the tunnel current of the memory cell having the gate having the energy band shown in FIGS. 3A and 3B is shown in graphs g _a and g _b in FIG. 4, respectively. As can be seen from the graphs g _a and g _b , the case of having a single quantum well structure (graph g _b ) is lower than the case of having a single barrier structure (graph g _a ). It can be seen that the leakage current decreases with voltage, but rather increases beyond the quantum level.

In contrast, an energy band diagram in the case where the gate has a double quantum well structure as in each embodiment of the present invention is shown in FIG. the applied voltage dependence of the tunnel current shown in graph g _c in FIG. When the quantum levels inside the first and second quantum well layers are different, the probability that the leakage current reaches the second quantum well layer is almost zero. That is, electrons do not reach the second quantum well layer. This state is referred to as a non-resonance state. In order to realize this non-resonant state, it is important that the second well is quantized. In the case where the second well is a classical well having a continuous energy band as disclosed in JP-A-2001-244352 ( For example, the case shown in FIG. 3B cannot be realized.

In contrast, as in the embodiments of the present invention, if the gate has a double quantum well structure, the non-resonant state, as can be seen from the graph g _c in FIG. 4, the applied voltage is low It can be seen that the leakage current extremely decreases in the voltage region. It is a feature of each embodiment of the present invention that in this non-resonant state, charge is held or the memory is read out. If reading is performed using a non-resonant state, it is possible to avoid the loss of electric charge due to a leakage current at the time of reading, and thus data retention is ensured even after reading.

  In addition, as in the embodiments of the present invention, as a characteristic of leakage current when the gate has a double quantum well structure, a specific applied voltage (hereinafter referred to as resonance voltage in this specification) is used. A resonance occurs, and at a voltage higher than the resonance voltage, a unique phenomenon is observed in which the leakage current rather decreases by an order of magnitude. A voltage higher than the resonance voltage can be regarded as a non-resonant state, so that the effective barrier is increased. This feature is a characteristic that appears as a result of using a double quantum well structure. In the memory cell to which a voltage higher than the resonance voltage is applied, the phenomenon that writing and erasing are remarkably delayed appears as a characteristic of the memory cell in each embodiment of the present invention. In the conventional structure shown in FIGS. 3A and 3B, such a phenomenon is not observed.

  When the gate has a double quantum well structure, as shown in FIG. 2B, a voltage is applied to the gate to shift the energy level, and the first and second quantum well layers 22, 24 When the internal quantum levels can be matched, the quantum levels resonate, and the probability that the leak current reaches the second quantum well layer 24 is approximately 1. This state is called an on-resonance state. The quantum level may have a width depending on the temperature, and when the p-type silicon substrate 10 is used, the energy band is bent according to the doping amount of the channel 12. When these are evaluated to the maximum, deviations of about 0.15 eV to 0.25 eV depending on the operating temperature and about 0.15 eV to 0.25 eV depending on the channel dope amount occur. Therefore, the first and second quantum wells 22 and 24 need to have an energy level difference of at least 0.3 eV to 0.5 eV. When a resonance state is generated, if electrons cannot be accumulated in the second quantum well layer 24, the electrons are reflected in the reverse direction and returned with probability 1. On the other hand, if a mechanism capable of accumulating electrons in the second quantum well layer 24 can be added as in the embodiments of the present invention, electrons are injected into the second quantum well layer 24 at a high density. Therefore, charge injection can be performed at a very high speed. The addition of a mechanism capable of storing electrons in the second quantum well layer 24 is also a feature of each embodiment of the present invention.

As a mechanism capable of accumulating electrons, the following devices are necessary. The second quantum well layer 24 must have many electron trap sites in the film plane and be quantized in the layer thickness direction. And it is preferable that it is not quantized in the in-plane direction. If there are a large number of electron trap sites in the film surface through the state spreading in the plane, electrons can be transferred to the trap site. With the configuration of the second quantum well shown below, the density of trap sites in each embodiment of the present invention can be ensured to be 1 × 10 ¹² cm ⁻² or more, more preferably 1 × 10 ¹³ , in terms of surface density. cm ⁻² or more can be secured. That is, the second quantum well layer is a quantum well with an increased trap site density. On the other hand, in a normal quantum well that does not increase the trap site density, the trap site density is an order of magnitude smaller than 10% of the increased trap site density. It can be said that it hardly happens.

  In the resonance state, the probability of being in each quantum well of the first quantum well layer and the second quantum well layer is the same, but since the density of trap sites is significantly different, most electrons are trapped in the second quantum well layer. Is done. When electrons are transferred to the trap site in the second quantum well layer, electrons are vacated at the resonance level in the second quantum well layer, and thus supply occurs from the first quantum well layer. In this way, electrons are accumulated from the next to the trap sites in the second quantum well layer. As a result, most of the electrons are accumulated on the side with many trap sites (second quantum well layer).

  When the voltage is turned off after writing, electrons cannot stay at the quantum level in the first quantum well layer and escape to the channel side.

(1) As a material of the second quantum well layer, when an expensive substance is added to the high dielectric oxide film, an electron storage site is created by adding an expensive substance into the high dielectric oxide film. It becomes possible. FIG. 5 shows the trap level when Ru is added to SrTiO ₃ . When Ru is added to SrTiO ₃ , two of the localized d orbitals of Ru are filled with electrons, and one is left empty. That is, a level caused by Ru appears in the band gap of SrTiO ₃ . This level can store electrons. As the amount of introduced Ru increases, this level forms a band and becomes metallized. Until metallization, it acts as a local charge accumulation level. This level can be introduced at a very high density, so that a spatially discrete charge storage layer can be formed. If Ru is introduced to the extent that it is metallized, a band having a width around the Ru level is formed. In addition to Ru, Tc, Re, Os, Rh, Ir, Pd, Pt, Co, Ni, W, Mo, Cr, Mn, or Fe can be used. It shall be called.

(2) As a material of the second quantum well layer, when both a high-valence substance and N are added to a high-dielectric oxide film, a high-dielectric oxide film is used, and an expensive-number substance is added to the electron. By creating a storage site and adding an electron accepting substance such as N, it is possible to deepen the energy level of the electron storage site. FIG. 6 shows trap levels in which Ru and N are introduced into SrTiO ₃ . When Ru and N are introduced into SrTiO ₃ , 1.5 of Ru's localized d orbitals are filled with electrons, and 1.5 is left empty. The introduction of N increases the state of the sky and lowers the level. As an electron acceptor, effective substances include nitrogen, carbon, boron, Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu are conceivable, and these substances will be referred to herein as the second group.

(3) When a metal such as TiN is used as the material of the second quantum well layer A metal thin film such as TiN is used. If it is a metal, the problem of insufficient charge accumulation does not occur. However, with metal, if the barrier is deteriorated, the charge may be lost. However, in the double quantum well structure in each embodiment of the present invention, if the quantum levels in the layer thickness direction do not match, no resonance current is generated, so it can be said that the structure is resistant to barrier degradation. This is because even if one barrier is deteriorated, resonance does not occur unless it interacts with the quantum level in the well.

In addition, a metal charge storage layer is formed in contact with an oxide such as SiO ₂ , Al ₂ O ₃ , HfO ₂ , HfSiON, LaAlO _3, etc., so that the metal state is maintained even when it is highly resistant to oxidation or oxidized. Must be metal. Therefore, metal nitride (TiN, TaN, WN, etc.), metal carbide (TaC, WC, etc.), oxide metal (SrRuO ₃ etc.), Pt, Ru, Ir, etc. are suitable as the metal material.

Similar to the floating gate electrode, polysilicon doped with phosphorus can also be used as the charge storage metal. Further, silicon-rich SiN into which a large amount of Si is introduced also generates metal band energy within the SiN gap. This metal state can be used as a charge storage layer. The SiN film becomes an insulating film when Si and N are introduced at a ratio of Si ₃ N ₄ . At this time, the ratio of the element is Si amount / N amount = 0.75. As Si is increased, Si dangling bonds increase and a film capable of trapping electrons is obtained. When the element ratio is Si amount / N amount ≧ 0.95, the SiN film is in a metal state (that is, a state in which an energy band having dispersion in the gap is formed), and a sufficient charge can be accumulated.

(4) When a SiN film is used as the material of the second quantum well layer It is also possible to use a SiN film used as a trap film. However, the above-described metallic SiN film containing a large amount of Si is preferable in order to solve the problem of shortage of accumulated charge, which has been a problem in the past.

  As can be seen from the above description, a basic structure is a double stack of wells quantized in the layer thickness direction. The first quantum well layer does not accumulate charges. The first quantum well layer plays a role as a launch pad for injecting electrons using quantum levels generated in the layer thickness direction. The second quantum well layer plays a role of accepting and accumulating electrons through quantum level resonance. Here, as shown in FIG. 7, the second quantum well layer may have a multiple quantum well structure in which quantum wells having the same energy level and the same layer thickness are stacked in multiple layers. In this case, since the energy level of the multiple quantum well portion has a width, the energy range that can resonate with the first quantum well layer is widened. By using this feature, it is possible to give a width to the applied voltage necessary for resonance, thereby improving the controllability and enabling higher-speed writing.

(First embodiment)
Next, the non-volatile semiconductor memory according to the first embodiment of the present invention will be described. The nonvolatile semiconductor memory according to the present embodiment is a charge storage type memory and includes at least one memory cell. A cross section of the memory cell is shown in FIG. As already described, the memory cell 1 has n-type source and drain regions 14a and 14b formed on the p-type silicon substrate 10 so as to be separated from each other. A channel region 12 is formed between the source region 14a and the drain region 14b. On the channel region 12, a gate 20 for controlling the memory operation is provided. The gate 20 is formed on the silicon substrate 10 with a first barrier layer 21, a first quantum well layer 22, a second barrier layer 23, a charge storage layer 24 serving as a second quantum well layer, and a third barrier layer. The block layer 25 and the control electrode 26 are stacked in this order. Here, the first barrier layer 21, the first quantum well layer 22, and the second barrier layer 23 form a first quantum well. The second barrier layer 23, the second quantum well layer (charge storage layer) 24, and the third barrier layer (block layer) 25 form a second quantum well. Thus, the gate 20 has a triple barrier and a double well structure. The energy band of the gate 20 is shown in FIGS. 2 (a) and 2 (b). 2A is an energy band diagram in a non-resonant state, and FIG. 2B is an energy band diagram in a resonant state.

  First, the first quantum well formed by the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 of the present embodiment will be described. Both ends of the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 are formed on the channel region 10 so as to extend over the source region 14a and the drain region 14b, respectively. The first and second barrier layers 21 and 23 constituting this laminated film are preferably formed of a silicon oxide film having a low dielectric constant. This is because in such a stacked gate, a large voltage is distributed to a layer having a low dielectric constant. In addition, the first quantum well layer 22 is preferably formed of a material having a deep well and good controllability. In the present embodiment, the first quantum well layer 22 is formed of silicon.

In order to reduce the interaction with the adjacent memory cell, it is necessary that the SiO ₂ equivalent layer thickness (EOT (Equivalent Oxide Thickness)) is 10 nm or less in the entire gate stack structure. Under the conditions, it is desirable that the thickness of the first and second barrier layers 21 and 23 occupy about half of EOT. This is because most of the voltage is to be distributed to the first and second barrier layers 21 and 23.

In the first embodiment, the SiO ₂ layer thickness of the first quantum well layer 22,1.0nm made of Si of thickness of the first barrier layer 21,0.5nm made of SiO ₂ of thickness of 2.5nm The second barrier layer 23 is used. At this time, the quantum well layer 22 is quantized, and a quantum level appears at a position of 1.5 eV on the conduction band side as shown in FIG. In addition, a quantum level appears at a position of 3.0 eV on the valence band side.

In this embodiment, as an example of a method for forming the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23, first, a SiO ₂ thermal oxide film having a layer thickness of 2.3 nm is formed. On top of this, Si is deposited by 1.1 nm. Here, when a thermal oxidation process is performed, a first barrier layer 21 made of SiO ₂ having a barrier width of 2.5 nm, a first quantum well layer 22 made of Si having a barrier width of 0.5 nm, and a barrier width of 1.0 nm. A laminated structure of the second barrier layer 23 made of SiO ₂ can be formed.

Next, the second quantum well layer (charge storage layer) 24 of this embodiment will be described.
Since the second quantum well layer 24 uses a high dielectric material, voltage distribution to the first and second barrier layers 21 and 23 is increased, so that operation at a lower voltage is possible. The effect of lowering the voltage is also to reduce the voltage applied to the third barrier layer (block layer) 25, so that it is possible to prevent electron injection from the electrode 26 side when erasing stored data. It becomes possible. That is, the electron injection on the electrode 26 side is suppressed. Further, when the distribution of the voltage applied to the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 increases, the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 becomes thinner. And, it becomes possible to keep the total voltage applied to the whole low.

When a predetermined voltage is applied to the control electrode 26, the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer (charge storage layer) 24 cause resonance, and the second Electrons reaching the quantum well layer 24 are trapped in the second quantum well layer 24. In the present embodiment, as the second quantum well layer (charge storage layer) 24, for example, an SrTiO ₃ film having a high dielectric constant of 300 and a thickness of 0.55 nm is used. In the present embodiment, as an example of a film formation method of the second quantum well layer (charge storage layer) 24, two targets (SrTiO ₃ target and SrRuO ₃ target) are used, and an atmosphere of oxygen / nitrogen / Ar mixed gas is used. Ru is introduced into the SrTiO ₃ film by simultaneous sputtering (Co-sputter). Here, nitrogen is introduced into the film by controlling the amount of nitrogen during film formation. After film formation, annealing is performed in a nitrogen / oxygen mixed atmosphere.

In this embodiment, the Ru amount introduced at the time of film formation is, for example, 8 × 10 ¹³ cm ⁻² in terms of surface density, and a large accumulated charge amount can be obtained. The amount of nitrogen introduced was approximately 9 × 10 ¹³ cm ⁻² . At this time, Ru forms a level in the SrTiO ₃ gap, and the level is clogged with about 50% of electrons. By introducing nitrogen in an amount almost equal to the amount of Ru, the state of one electron in the level is vacant, and there is a level drop of about 0.3 eV. As shown in FIG. 6, electrons can be packed in part or all of the remaining 50%. It is also possible to draw out some or all of the clogged electrons of about 50%. That is, when erasing data, it is easy to extract electrons excessively, or it is easy to inject holes, and the threshold voltage can be shifted to the minus side. With such a configuration, the threshold fluctuation can be increased by applying a voltage for a short time, which is advantageous for a storage operation and an erasing operation.

  In the conventional silicon nitride film, it is very difficult to trap holes or to remove electrons excessively, and thus a sufficient threshold fluctuation range cannot be secured. On the other hand, according to this embodiment, a large threshold fluctuation range due to excessive extraction of electrons (or excessive erasure by hole injection) can be secured, and high-speed erasure is possible. The same thing is possible even when metalized SiN into which a large amount of Si is introduced is used as the charge storage layer, but this case will be described in a third embodiment to be described later.

Furthermore, since the second quantum well layer (charge storage layer) 24 of this embodiment is made of SrTiO ₃ to which Ru and N are added, as shown in FIG. 9, the energy level of charge storage is very high. It exists in a deep position. Therefore, charge leakage is suppressed by orders of magnitude compared to the case where silicon nitride which is not metallized is used for the second quantum well layer. When the charge storage layer 24 is made of titanium oxide, as shown in FIG. 9, the barrier height (offset) ΔEc between the second barrier layer 23 and the second quantum well layer 24 is as very large as 3.5 eV, and the trap level If the substance added to the charge storage layer 24 is Ru, the position ΔEt is also very large at about 1.7 eV. When silicon nitride that is not metallized is used as the charge storage layer, ΔEc≈1.1 eV and ΔEt≈0.8 eV. Further, as in the present embodiment, nitrogen, carbon, boron, or low-valence substance (Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, By introducing Tb, Dy, Ho, Er, Tm, Yb, or Lu), the trap level ΔEt can be increased, so that the retention characteristics can be further improved.

  Although the trap level ΔEt varies depending on the additive material, the additive materials (Tc, Re, Ru, Os, Rh, Ir, Pd, Pt, Co, Ni, W, Mo, Cr, Mn) mentioned in this embodiment are used. , Fe), 0.5 eV or more can be secured. As in this embodiment, nitrogen, carbon, boron, or low-valent substance (Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy , Ho, Er, Tm, Yb, or Lu), the trap level ΔEt can be increased by about 0.3 eV.

  When Hf oxide or Zr oxide is used as the base material of the charge storage layer 24, ΔEc is about 2.0 eV, which is smaller than that of titanium oxide. However, the trap level becomes deeper than in the case of titanium oxide, and the trap level ΔEt can be secured to 1.5 eV. As described above, in the present embodiment, a material having a very deep trap level (the sum of the offset ΔEc and the trap level ΔEt shown in FIG. 9) is specified, and the ability to prevent the stored charge from escaping. Take advantage of great benefits. Further, as in this embodiment, nitrogen, carbon, boron, or low-valence substance (Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb , Dy, Ho, Er, Tm, Yb, or Lu), the trap level ΔEt can be increased, so that the retention characteristics can be further improved.

In addition, when the charge storage layer 24 contains Ti and Zr (or Hf), it is exactly the same if the band gap is generated according to the ratio. For example, Sr (Ti, Zr) O ₃ is a powerful base material, and an effective charge storage layer can be formed by replacing Ti or Zr with Ru.

In the present embodiment, an Al ₂ O ₃ film having a barrier width of 6 nm is used as the third barrier layer 25, and a TaN film is used as the control electrode 26.

Here, the operation of the memory cell according to the present embodiment will be described with reference to FIG. The quantum levels on the electron side in the first and second quantum well layers 22 and 24 are at positions of about 1.5 eV and 2.5 eV, respectively, with respect to the conduction band bottom of the p-type silicon substrate 10. Further, the quantum level on the hole side is at a position of 3.0 eV, 4.2 eV with respect to the top of the valence band of the p-type silicon substrate 10. Here, the barrier widths of the first and second barrier layers 21 and 23 made of SiO ₂ are 2.5 nm and 1.0 nm, respectively, and the well width of the first quantum well layer 22 made of Si is 0.5 nm, Ru Since the well width of the second quantum well layer 24 made of SrTiO ₃ to which is added is 0.55 and the barrier width of the third barrier layer 25 made of Al 2 O 3 is 6 nm, the EOT of the entire stacked structure of the gate 20 is 5 0.7 nm (= 2.5 + 0.5 / 3 + 1 + 0.55 / 25 + 6/3).

a) Addition of write <br/> + 5.7 V to the control electrode 26, the first and second barrier layers 21 and 23, respectively, 2.5V (= 5.7V × (2.5nm / 5. 7 nm)), 1.0 V (= 5.7 V × (1.0 nm / 5.7 nm)). At this time, the top of the valence band of the p-type Si substrate 10, the quantum level of the first quantum well layer 22, and the quantum level of the second quantum well layer 23 coincide, and electron resonance occurs. As a result, a writing operation can be performed.

  In the NAND flash memory, among the NAND cells connected in series and connected in series, except for the memory cells to be written, the channel is opened and the conductive state is opened. That is, by applying to the control electrode 26 a voltage that is equal to or higher than the maximum threshold voltage after writing and lower than the writing voltage, the MOS transistors of the memory cells other than the memory cell to be written are turned on. In that sense, it is necessary to increase the write voltage to some extent, but in this embodiment, as will be described later, the write voltage can be controlled fairly freely by changing the layer thickness.

b) When −6.8 V is applied to the erase control electrode 26, the first and second barrier layers 21 and 23 are 3.0 V (= 6.8 V × (2.5 nm / 5.7 nm)), 1 A voltage increase of 0.2 V (= 6.8 V × (1.0 nm / 5.7 nm)) occurs. At this time, the top of the valence band of the p-type Si substrate 10, the quantum level of the first quantum well layer 22, and the quantum level of the second quantum well layer 24 coincide with each other, and hole resonance occurs. As a result, holes flow, and an erasing operation by holes becomes possible.

c) In the read NAND flash memory, among the NAND cells connected in series and connected in series, except for the read memory cells, the channels are opened and in a conductive state. That is, by applying a voltage that is equal to or higher than the maximum threshold voltage after writing and is equal to or lower than the writing voltage to the control electrode 26, the MOS transistors of the memory cells other than the memory cell to be read are turned on. The memory cell to be read detects the state of stored data by measuring whether the memory cell is in a conductive state or a non-conductive state when a set voltage is applied.

d) It is possible to perform injection control (multi-leveling) using level increase by multi- level charge injection. When the quantum level of the charge storage layer shifts due to charge injection, resonance does not occur. This is caused by the electron correlation energy of electrons injected into the level. Apply a resonance voltage to the cell to be written. Then, electrons are injected at high speed. Due to the correlation energy of electrons, the quantum level in the second quantum well layer 24 rises according to the amount written. When electrons are sufficiently injected, the resonance state is deviated and the electron injection automatically ends. Here, when the injection amount is insufficient, the applied voltage may be increased. In this way, the amount of injected electrons can be accurately limited to a certain range. That is, it can be seen that when the first threshold value is determined, the distribution width of the first threshold value can be sufficiently narrowed. Next, by applying a resonant voltage, the second threshold value is determined, and the distribution width of the second threshold value can be sufficiently narrowed. It can be seen that by repeating the above, the memory cell can be easily multi-valued. Moreover, since the distribution width of each threshold is narrow, the voltage can be reduced.

  A condition for causing resonance of electrons and holes will be described with reference to FIGS.

  The energy level generated inside the quantum well is defined as follows. With reference to the bottom position of the conduction band of the Si substrate, the quantum level on the conduction band side in the first quantum well layer is denoted as EC1 (n) (n = 1, 2, 3,...). Similarly, the quantum level on the conduction band side in the second quantum well layer is denoted as EC2 (n) (n = 1, 2, 3,...). Here, C means a conduction band, and n is a quantum number (a positive integer). In addition, with reference to the top position of the valence band of the Si substrate, the quantum level on the valence band side in the first quantum well layer is denoted as EV1 (n) (n = 1, 2, 3,...). . Similarly, the quantum level on the valence band side in the second quantum well layer is denoted as EV2 (n) (n = 1, 2, 3,...). Here, V means a valence band, and n is a quantum number (a positive integer).

First, consider writing by electron resonance. The energy difference between the Fermi level of the p-type Si substrate (close to the top of the valence band because it is a p-type substrate) and the quantum level in the first quantum well layer 22 is approximately 1.0 eV + EC1 (1). Here, a numerical value of 1.0 eV means an energy difference between the Fermi level and the bottom of the Si conduction band. The energy difference between the quantum levels in the first quantum well layer 22 and the second quantum well layer 24 is approximately EC2 (1) −EC1 (1). When the ratio of these two values coincides with the ratio of the voltage drop in the first and second barrier layers 21 and 23, electron resonance occurs at that voltage. That is, the following relational expression [1.0 + EC1 (1)]: [EC2 (1) −EC1 (1)]
= Barrier width (EOT) of first barrier layer 21: Barrier width (EOT) of second barrier layer 23
When the above conditions are satisfied, the Fermi level, EC1 (1) in the first quantum well layer 22, and EC2 (1) in the second quantum well layer 24 all coincide, and an electron resonant tunneling occurs.

  However, since there is a heat distribution of electrons, the electrons on the substrate are allowed to distribute up to about 0.3 eV from the Fermi level of the p-type Si substrate. That is, the first term [1.0 + EC1 (1)] can be made somewhat small. For example, it can be seen that the first barrier layer 21 may be slightly thinner than the design value, or the second barrier layer 21 may be slightly thicker than the design value.

  Depending on the doping amount of the substrate, the Fermi level is near the top of the valence band. At this time, it has a distance of 1.12 eV from the bottom of the conduction band of the Si substrate. That is, the first term [1.0 + EC1 (1)] can be made somewhat larger. For example, it can be seen that the first barrier layer 21 may be slightly thicker than the design value, or the second barrier layer 23 may be slightly thinner than the design value.

The above contents can be summarized as follows. Here, EC1 and EC2 are the quantum levels inside the first quantum well layer 22 and the second quantum well layer 24, respectively, which are levels that coincide when the voltage is changed.
[0.7 eV + EC1] / [EC2-EC1] ≦ [barrier width of the first barrier layer] / [barrier width of the second barrier layer] ≦ [1.12 eV + EC1] / [EC2-EC1]

  It can be seen that the energy level may be changed, but the barrier width may be changed for this equation to hold.

Next, let us consider erasing by hole resonance. Since the energy difference between the top of the valence electrons of the Si substrate and the quantum level in the first quantum well layer 22 is expressed as EV1 (1), the quantum in the first quantum well layer 22 and the second quantum well layer 24 The energy difference between the levels is EV2 (1) −EV1 (1). If the ratio of these two values matches the voltage drop ratio of the first and second barrier layers 21 and 23, hole resonance occurs at that voltage. That is, the following relational expression [EV1 (1)]: [EV2 (1) -EV1 (1)]
= Barrier width (EOT) of first barrier layer: Barrier width (EOT) of second barrier layer
If this is satisfied, resonance occurs. However, since there is a heat distribution of holes at the top of the Si substrate valence electrons, a maximum distribution of 0.3 eV is allowed. For example, the first term [EV1 (1)] can be made somewhat small. For example, it can be seen that the first barrier may be slightly thinner than the design, or the second barrier may be somewhat thicker than the design.

  Further, depending on the doping amount of the substrate, the Fermi level is higher than the top of the valence band. At this time, it has a maximum distance of about 0.2 eV from the top of the valence band of the Si substrate. That is, the first term [EV1 (1)] can be made somewhat larger. For example, it can be seen that the first barrier may be somewhat thicker than the design, or the second barrier may be slightly thinner than the design.

The above contents can be summarized as follows. Here, EV1 and EV2 are the quantum levels inside the first quantum well layer and the second quantum well layer, respectively, which are coincident levels when the voltage is changed.
[EV1-0.3 eV] / [EV2-EV1] ≦ [barrier width of the first barrier layer] / [barrier width of the second barrier layer] ≦ [0.2 eV + EV1] / [EV2-EV1]

  In order to satisfy this expression, it is understood that the energy level may be changed, but the barrier width may be changed.

  There is a case where it can be designed so that both writing by electron resonance and erasing by hole resonance can be realized. As described above, since electrons and holes in the channel have a thermal distribution, a design that allows a certain width is possible by using this distribution. In this embodiment, as described above, electron resonance writing at +5.7 V and hole resonance erasure at -6.8 V can be performed.

  By changing the physical layer thickness and dielectric constant of the first barrier layer and the second barrier layer, the voltage required for writing and erasing can be adjusted. This is because, as can be seen from the above conditions, only the EOT ratio of the first and second barrier layers is important for realizing writing or erasing by resonance. For example, in the first embodiment, EOT of the first barrier layer: EOT of the second barrier layer = 2.5: 1.0 = 1.25: 0.5 = 3.75: 1.5 Consider the third case. At this time, the total EOT changes to 5.7, 3.9, and 7.4 nm, respectively (see FIG. 8). In the first case (this embodiment), the write voltage is 5.7 V and the erase voltage is −6.8 V, and in the second case, the write voltage is 7.8 V and the erase voltage is −9.4 V. In this case, the write voltage is 4.9V and the erase voltage is −5.9V. If the thicknesses of the first and second barrier layers 21 and 23 are reduced, the total EOT is reduced and the voltage distributed to these barriers is reduced. Therefore, the applied voltage needs to be increased.

Further, even if the thickness and dielectric constant of the block layer 25 are changed, the total EOT of the stacked structure of the gate 20 can be changed, so that the voltage required for writing and erasing can be adjusted. For example, when the thickness of the block layer 25 made of Al ₂ O ₃ is 9 nm, the total EOT is increased by 1.0 nm as compared with the present embodiment (fourth case shown in FIG. 8). As the total EOT increases, the voltage distributed to the first barrier layer 21 and the second barrier layer 23 decreases, so the applied voltage applied to the control electrode 26 needs to be increased. Consider the fourth to sixth cases where EOT of the first barrier layer: EOT of the second barrier layer = 2.5: 1.0 = 1.25: 0.5 = 3.75: 1.5. At this time, the total EOT in the fourth to sixth cases changes to 6.7 nm, 4.9 nm, and 8.4 nm, respectively. The write voltage in the fourth case is 6.7 V and the erase voltage is -8.0 V, the write voltage in the fifth case is 9.8 V, the erase voltage is -11.8 V, and the write in the sixth case The voltage is 5.6 V and the erase voltage is −6.7.

In this way, by using writing by electron resonance and erasing by hole resonance according to the present embodiment, a high current density can be used as shown in FIG. 4, so that high-speed writing and high-speed erasing are possible. is there. In addition, when resonance does not occur (non-resonant state), the leakage current is extremely reduced, so that the characteristics of retaining written charges are superior to the conventional case. In addition, by using this non-resonant state, which has not existed in the past, excellent characteristics are exhibited in that the erased state is maintained. For example, 1.0 × 10 ⁻¹⁶ A / cm ² or less can be realized with a low electric field of 1 MV / cm or less.

Further, at the time of reading, by using a voltage in a non-resonant state, the reading operation can be performed without affecting the accumulation state. Conventionally, since this non-resonant state is not used, there is a possibility that the accumulation state may change during reading. However, if the non-resonance state is used as in this embodiment, there is no influence on the accumulation state. I can do it. That is, the leakage current at the time of reading (when a voltage higher than the threshold voltage and lower than the resonance voltage is applied) can be set to 1.0 × 10 ⁻⁹ A / cm ² or lower. In the conventional memory structure, this leakage current has a value that is about one to two digits larger, and there is a problem of how to suppress read leakage. However, it can be seen that read leakage can be sufficiently suppressed by using the double quantum well structure of the present embodiment.

  As described above, according to the nonvolatile semiconductor memory of this embodiment, it is possible to perform high-speed writing, high-speed erasing, improved retention characteristics, and stable reading. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

(First modification)
As a first modification of the first embodiment, erasing using electron resonance will be described.

In this modification, the thickness of the first barrier layer 21 made of SiO ₂ is 1 nm, the thickness of the first quantum well layer 22 made of Si is 0.82 nm, and the layer of the second barrier layer 23 made of SiO _{2 is used.} The thickness is 1 nm. At this time, as shown in FIG. 12, the portion of the first quantum well layer 22 made of Si is quantized, and a quantum level appears at a position of 0.55 eV on the conduction band side. On the valence band side, quantum levels appear at 1.1 eV and 4.3 eV.

Next, the second quantum well layer (charge storage layer) 24 of this modification will be described.
The second quantum well layer 247 is considered to be metallized by forming a band inside the band gap by using SrTiO ₃ doped with a large amount of Ru. The thickness of the second quantum well layer 24 was 0.6 nm. At this time, a level quantized in the layer thickness direction appears at -1.0 eV in the band gap and 2.1 eV above the conduction band. The state of −1.0 eV in the gap is quantized in the layer thickness direction, but is considered to be metallized in the in-plane direction. The energy difference from the level in the first quantum well layer 22 is 1.55 eV. Here, when +6.7 V is applied (first case shown in FIG. 12), the top of the valence band of the Si substrate, the quantum level of the first quantum well layer 22, and the quantum in the second quantum well layer 24 are applied. The levels match. That is, writing by electron resonance is realized. In addition, when −6.7 V is applied, the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer 24 (the level in the gap corresponding to −1.0 eV) match. . At this time, since the Si substrate has empty levels in a continuous state, electrons resonate and escape from the second quantum well layer 24 to the Si substrate. The quantum level on the valence band side of the second quantum well layer 24 appears at a position of 3.9 eV with respect to the top of the valence band of Si, and the quantum level in the first quantum well layer 22 is Since the top of the valence band of the Si substrate does not match, the hole resonance state does not appear.

  In the second quantum well layer (charge storage layer) 24 of this modification, it is considered that charges are stored in the gap. This state can be easily erased by causing electron resonance.

  In this way, by using writing by electron resonance and erasing by electron resonance according to the present modification, a high current density can be used as shown in FIG. 4, thereby performing high-speed writing and high-speed erasing. It becomes possible. In addition, when resonance does not occur (non-resonant state), the leakage current is extremely reduced, so that the characteristics of retaining written charges are superior to the conventional case. In addition, by using this non-resonant state, which has not existed in the past, it exhibits excellent characteristics in maintaining the erased state. Further, at the time of reading, by using a voltage in a non-resonant state, the reading operation can be performed without affecting the accumulation state. Conventionally, since this non-resonant state was not used, there was a risk that the accumulation state would change even at the time of reading. However, if the non-resonance state of this modification is used, the influence on the accumulation state can be completely eliminated.

The applied voltage can be adjusted by changing the thickness and dielectric constant of the first barrier layer 21, the second barrier layer 23, and the third barrier layer 25. For example, if the thickness of the third barrier layer 25 made of Al ₂ O ₃ is 9 nm, electron resonance writing at +8.2 V and electron resonance erasing at −8.2 V are performed. Also, for example, as in the second case shown in FIG. 12, if both the first and second barrier layers have a barrier width of 2 nm, electron resonance writing at +4.9 V and electrons at -4.9 V are performed. Resonance elimination.

  As described above, according to the nonvolatile semiconductor memory of this modification, it is possible to perform high-speed writing, high-speed erasing, improvement in retention characteristics, and reading stabilization. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

(Second modification)
As a second modification, a case where the second quantum well layer is a multiple quantum well will be described. The portion of the second quantum well layer 24 is not a single layer film of SrTiO ₃ doped with Ru and N, but a Ru, N-doped SrTiO ₃ film (0.55 nm) / Al ₂ O ₃ barrier film (3 nm) / Ru, N The structure is a doped SrTiO ₃ film (0.55 nm). At this time, quantum levels are generated in the Ru, N-doped SrTiO ₃ films (0.55 nm) on both sides. Since the interaction occurs via the Al ₂ O ₃ barrier film sandwiched therebetween, the level has a width of about 0.1 eV as shown in FIG. By giving such a width, it is possible to give a width to the voltage that causes resonance, thereby improving controllability and enabling higher-speed writing.

  In this modified example, similarly to the first embodiment, high-speed writing, high-speed erasing, improvement of holding characteristics, and reading stabilization can be performed. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

(Second Embodiment)
Next, a nonvolatile semiconductor memory according to a second embodiment of the present invention is described.
The non-volatile semiconductor memory of this embodiment has the same basic structure as the non-volatile semiconductor memory (charge storage type memory) of the first embodiment. The second embodiment is different from the first embodiment in that polysilicon doped with a large amount of phosphorus (P) is used as the second quantum well layer (charge storage layer) 24.

First, the quantum well is formed by the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 as in the first embodiment. In the second embodiment, the thickness of the first barrier layer 21 made of SiO ₂ is 2.82 nm, the thickness of the first quantum well layer 22 made of Si is 0.82 nm, and the second barrier layer made of SiO _{2 is used.} The layer thickness of 23 is 1.0 nm. At this time, as shown in FIG. 13, the portion of the first quantum well layer 22 made of Si is quantized, and a quantum level appears at a position of 0.55 eV on the conduction band side. On the valence band side, quantum levels appear at 1.1 eV and 4.3 eV.

Next, the second quantum well layer (charge storage layer) 24 of this embodiment will be described.
The second quantum well layer 24 is considered to be metallized near the bottom of the conduction band by employing Si doped with a large amount of phosphorus (P). The thickness was 1 nm. At this time, a level quantized in the layer thickness direction appears just above the conduction band (0.0 eV) and 1.1 eV. The energy difference from the level in the first quantum well layer 22 is 0.55 eV. Here, when a voltage of +2.8 V is applied to the control electrode 26, the top of the valence band of the Si substrate, the quantum level in the first quantum well layer 22, and the quantum level in the second quantum well layer 24 are changed. Match. That is, writing by electron resonance is realized. In addition, when −2.8 V is applied to the control electrode 26, the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer 24 (level corresponding to 0.0 eV) coincide. (First case shown in FIG. 13). At this time, since the Si substrate has empty levels in a continuous state, electrons resonate and escape from the second quantum well layer to the Si substrate. The quantum level on the valence band side of the second quantum well layer 24 appears at positions of 0.75 eV and 3.0 eV with respect to the top of the Si valence band, but the quantum level in the first quantum well layer 22 is not limited. Since the level does not coincide with the top of the valence band of the Si substrate, the resonance state of the hole does not appear.

  Since the second quantum well layer (charge storage layer) 24 of this embodiment is doped with a large amount of phosphorus, it is considered that charges are stored near the bottom of the conduction band. This state can be easily erased by causing electron resonance.

  In this way, by using writing by electron resonance and erasing by electron resonance according to the present embodiment, a high current density can be used as shown in FIG. 4, so that high-speed writing and high-speed erasing are possible. is there. In addition, when resonance does not occur (non-resonant state), the leakage current is extremely reduced, so that the characteristics of retaining written charges are superior to the conventional case. In addition, by using this non-resonant state, which has not existed in the past, it exhibits excellent characteristics in maintaining the erased state. Further, at the time of reading, by using a voltage in a non-resonant state, the reading operation can be performed without affecting the accumulation state. Conventionally, since this non-resonant state is not used, there is a possibility that the accumulation state may change during reading. However, if the non-resonance state of the present embodiment is used, the influence on the accumulation state can be completely eliminated.

  The voltage at which resonance occurs (resonance voltage) is preferably large to some extent. In the case of a NAND memory, a cell that is not selected needs to open a channel and be in a conductive state at the time of “reading” or “writing”, so that a value larger than the threshold voltage is applied to the control electrode. It will be. This is because the non-resonant state needs to be maintained at that stage, so that the threshold voltage is desired to be smaller than the resonant voltage.

Such a large resonance voltage can be realized by layer thickness design or material selection (dielectric constant change). For example, this can be realized by changing the thicknesses of the first barrier layer, the second barrier layer, and the third barrier layer. If the thicknesses of the first and second barrier layers 21 and 23 made of SiO ₂ are 1.13 nm and 0.4 nm, and the thickness of the third barrier layer 25 made of Al ₂ O ₃ is 12 nm, the entire laminated structure of the gates The EOT of 5.8 nm becomes electron resonance writing at +7.9 V and electron resonance erasing at -7.9 V (second case shown in FIG. 13).

  As described above, according to the nonvolatile semiconductor memory of this embodiment, it is possible to perform high-speed writing, high-speed erasing, improved retention characteristics, and stable reading. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

  In the present embodiment, polysilicon is used as the second quantum well layer. However, since this polysilicon is easy to form and has a generation enthalpy equivalent or larger, it is used for a tunnel film or a block film. Polysilicon does not take oxygen from the surroundings.

(Third embodiment)
Next, the non-volatile semiconductor memory according to the third embodiment will be explained.
The nonvolatile semiconductor memory of this embodiment has the same basic structure as the nonvolatile semiconductor memory (charge storage memory) of the first embodiment. The second embodiment is different from the first embodiment in that the second quantum well layer (charge storage layer) 24 is made of SiN metallized by introducing a large amount of Si.

First, the quantum well is formed by the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 in the same manner as in the first embodiment. In the third embodiment, the layer thickness of the first barrier layer 21 made of SiO ₂ is 3.15 nm, the layer thickness of the first quantum well layer 22 made of Si is 0.42 nm, and the second barrier layer made of SiO _{2 is used.} The layer thickness of 23 is 0.55 nm. At this time, as shown in FIG. 14, the portion of the first quantum well layer 22 made of Si is quantized, and a quantum level appears at a position of 2.15 eV on the conduction band side. On the valence band side, a quantum level appears at a position of 4.2 eV.

Next, the second quantum well layer (charge storage layer) 24 of this embodiment will be described.
The second quantum well layer 24 employs SiN metallized with a large amount of Si introduced therein, so that a metal state is generated in a portion that enters the 0.8 eV gap from the bottom of the conduction band. It is discrete until the ratio of Si amount to nitrogen amount (= Si amount / nitrogen amount) in SiN is up to 0.9. When the ratio is 0.9, the accumulation amount is small. If the ratio is 0.95 or more, the accumulated amount is sufficient. Although it is a metal, it is quantized in the thickness direction, so no major leaks occur unless resonance occurs. In the present embodiment, the ratio of the Si amount and the nitrogen amount in the second quantum well layer 24 is set to 0.95 or more. The thickness was 1.1 nm. At this time, it is considered that levels quantized in the layer thickness direction at 1.6 eV and 2.7 eV are expressed with respect to the Si conduction band. The energy difference from the level in the first quantum well layer 22 is 0.55 eV. Here, when +5.8 V is applied to the control electrode 26, the top of the valence band of the Si substrate 10, the quantum level of the first quantum well layer 22, and the quantum level in the second quantum well layer 24 coincide. . That is, writing by electron resonance is realized. Further, when −5.8 V is applied to the control electrode 26 (first case shown in FIG. 14), the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer 24 (1. The levels at 6 eV). At this time, since the Si substrate has empty levels in a continuous state, electrons resonate and escape from the second quantum well layer 24 to the Si substrate. Although the quantum level on the valence band side of the second quantum well layer 22 appears at a position of 3.3 eV with respect to the top of the valence band of the Si substrate 10, the quantum level in the first quantum well layer 22 is present. Since the position and the top of the valence band of the Si substrate 10 do not coincide with each other, the hole resonance state does not appear.

  Since the second quantum well layer (charge storage layer) 24 of the present embodiment introduces a large amount of Si, a metal state is generated inside the gap. This metal state is considered to form a quantum level at a position of 1.6 eV in the layer thickness direction. In this state, electrons are caused to resonate with the quantum levels in the first quantum well layer 22 so that electrons can easily flow from the charge storage layer 24 to the channel side. That is, it can be erased.

  As described above, by using writing by electron resonance and erasing by electron resonance according to the present embodiment, a high current density can be used as shown in FIG. 4, so that high-speed writing and high-speed erasing are possible. . In addition, when resonance does not occur (non-resonant state), the leakage current is extremely reduced, so that the characteristics of retaining written charges are superior to the conventional case. In addition, by using this non-resonant state, which has not existed in the past, it exhibits excellent characteristics in maintaining the erased state. Further, at the time of reading, by using a voltage in a non-resonant state, the reading operation can be performed without affecting the accumulation state. Conventionally, since this non-resonant state is not used, there is a possibility that the accumulation state may change during reading. However, if the non-resonance state is used as in this embodiment, there is no influence on the accumulation state. I can do it.

The applied voltage can be adjusted by changing the thickness and dielectric constant of the first barrier layer, the second barrier layer, and the third barrier layer. For example, when the third barrier layer is made of 10 nm Al ₂ O ₃ , electron resonance writing at +7.1 V and electron resonance erasing at −7.1 V are performed (second case shown in FIG. 14).

  In the present embodiment, a metalized SiN layer is used as the second quantum well layer 24. However, SiN that is not metalized but can accumulate charges can also be used. It is more preferable to use metalized SiN because more charges can be accumulated.

  As described above, according to the nonvolatile semiconductor memory of this embodiment, it is possible to perform high-speed writing, high-speed erasing, improved retention characteristics, and stable reading. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

(Fourth embodiment)
Next, a non-volatile semiconductor memory according to a fourth embodiment of the present invention is described.
The nonvolatile semiconductor memory of this embodiment has the same basic structure as that of the nonvolatile semiconductor memory (charge storage type memory) of the first embodiment. This embodiment is different from the first embodiment in that metal TiN is used as the second quantum well layer (charge storage layer) 24.

First, the quantum well is formed by the first barrier layer 21 / first quantum well layer 22 / second barrier layer 23 as in the first embodiment. In the present embodiment, the thickness of the first barrier layer made of SiO ₂ is 1.5 nm, the thickness of the first quantum well layer 22 made of Si is 0.7 nm, and the layer of the second barrier layer made of SiO ₂ The thickness is 1.0 nm. At this time, the portion of the quantum well layer 22 made of Si is quantized, and a quantum level appears at a position of 0.77 eV on the conduction band side as shown in FIG. Further, a quantum level appears at a position of 1.5 eV on the valence band side.

Next, the second quantum well layer (charge storage layer) 24 of this embodiment will be described.
The second quantum well layer 24 is considered to be metallized near the bottom of the conduction band by using metal TiN. The thickness of the second quantum well layer 24 was 1 nm. At this time, levels quantized in the layer thickness direction at −0.4 eV and 1.94 eV with respect to the bottom of the Si conduction band appear. The energy difference from the level in the first quantum well layer 22 is 1.17 eV. Here, when +5.5 V is applied to the control electrode 26, the top of the valence band of the Si substrate coincides with the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer 24. That is, writing by electron resonance is realized. In addition, when −5.5 V is applied to the control electrode 26, the quantum level in the first quantum well layer 22 and the quantum level in the second quantum well layer 24 (the level corresponding to −0.4 eV) match. (First case shown in FIG. 15). At this time, since the empty state exists in the Si substrate 10 in a continuous state, electrons resonate and escape from the second quantum well layer 24 to the Si substrate 19. The quantum level on the valence band side of the second quantum well layer 24 appears at a position of 3.5 eV with respect to the top of the valence band of the Si substrate 10, but the quantum level in the first quantum well layer 22. And the top of the valence band of the Si substrate 10 do not coincide with each other, so that the resonance state of the hole does not appear.

  Since the second quantum well layer (charge storage layer) 24 of the present embodiment is a metal, it is considered that charges are stored near the bottom of the conduction band. This state can be easily erased by causing electron resonance.

  Thus, by using writing by electron resonance and erasing by electron resonance as in this embodiment, a high current density can be used as shown in FIG. It is. In addition, when resonance does not occur (non-resonant state), the leakage current is extremely reduced, so that the characteristics of retaining written charges are superior to the conventional case. In addition, by using this non-resonant state, which has not existed in the past, it exhibits excellent characteristics in maintaining the erased state. Further, at the time of reading, by using a voltage in a non-resonant state, the reading operation can be performed without affecting the accumulation state. Conventionally, since this non-resonant state is not used, there is a possibility that the accumulation state may change even at the time of reading. However, if the non-resonance state is used as in this embodiment, there is no influence on the accumulation state. I can do it.

The applied voltage applied to the control electrode can be adjusted by changing the thickness and dielectric constant of the first barrier layer 21, the second barrier layer 23, and the third barrier layer. For example, when Al ₂ O ₃ having a thickness of 10 nm is used as the third barrier layer, electron resonance writing at +7.1 V and electron resonance erasing at −7.1 V are performed (the second case shown in FIG. 15). ).

  As described above, according to the nonvolatile semiconductor memory of this embodiment, it is possible to perform high-speed writing, high-speed erasing, improved retention characteristics, and stable reading. That is, it is possible to achieve both high speed of “writing and erasing” and improvement of “charge retention characteristics and reading characteristics”.

In this example, TiN was used as the metal for forming the second quantum well layer. However, if the metal is stable with respect to the surrounding oxide (SiO ₂ , Al ₂ O _3, etc.), the formation of the quantum well can be performed. Is possible. For example, a nitride metal, a carbide metal, or an oxide metal can be used as the second quantum well layer. In addition, since Pt, Ir, Ru, and the like are not easily oxidized, it is not necessary to take oxygen away from the surrounding oxide, and can be used as the second quantum well layer. That is, any metal having a small stabilization energy when oxidized can be used as the second quantum well layer.

As described above, the nonvolatile semiconductor memory (charge storage type memory) using the first to fourth embodiments described above can obtain the following effects.
1) Since the resonant tunneling effect is used in writing and erasing, it can be performed at high speed. In other words, at the time of resonant tunneling, electrons and holes tunnel with a high probability, thus effectively becoming a low barrier. FIG. 16A shows an image of writing and erasing by electron resonance. FIG. 16B shows an image of electronic writing and hole erasing.
2) Since the holding state is a non-resonant state, the characteristics are improved. In other words, at the time of non-resonant tunneling, the tunnel probability is extremely lowered, so that it effectively becomes a high barrier. In the holding state using the non-resonant state, the leakage current can be suppressed to 1.0 × 10 ⁻¹⁶ A / cm ² or less.
3) Since the reading operation can be performed in a non-resonant state, the charge transfer during reading can be completely prevented. In the read operation using the non-resonant state, the read leak current can be suppressed to 1.0 × 10 ⁻⁹ A / cm ² or less.
4) Switching by applied voltage and can cope with high temperature (strong to temperature). In the tunnel barrier improvement by means of charge trapping (Coulomb blockade), the smaller the size, the weaker the temperature. In the present invention, there is no problem even at a high temperature (100 ° C.).
5) Injection control (multi-level) using level increase by charge injection can be performed. When the quantum level of the charge storage layer shifts due to charge injection, resonance does not occur. Therefore, it is possible to obtain a threshold with a narrow distribution width. In addition, if a process in which electron injection is automatically stopped is used, it is possible to easily increase the number of memory cells. In addition, when multi-valued, the distribution width of each threshold is narrow, so that the voltage can be reduced.

  In the first to fourth embodiments, the memory cell formed on the silicon substrate has been described. However, the present invention is not limited to this structure. It is also possible to form the memory cell structure of this embodiment by forming a silicon layer on a substrate other than a silicon substrate, for example, a glass substrate.

  By utilizing this structure, it can be formed as a nonvolatile semiconductor memory in a control drive circuit of a display element such as a liquid crystal display element. In addition to the glass substrate, there is no particular limitation as long as it is a substrate that can withstand the process temperature during molding, such as a ceramic substrate, and a substrate that does not generate unnecessary gas during the process.

  In each embodiment of the present invention, writing / erasing is performed at a high speed by a large resonant tunneling current, and storage / reading is performed at a low leakage current by a nonresonant state. In order to realize this, a configuration having a double quantum well structure and capable of storing a sufficient charge in the second quantum well is required.

  In each of the above embodiments, the memory cell configured to trap electrons in the second quantum well is described. However, the memory cell configured to trap holes in the second quantum well can be considered by inverting the entire configuration. It becomes. More specifically, the substrate is n-type.

  The writing method is performed by applying to the control electrode a negative voltage that causes resonance between the energy level in the valence band of the first quantum well layer and the energy level in the valence band of the second quantum well layer. At this time, holes are injected from the channel into the second quantum well.

  The erasing method is performed by applying to the control electrode a positive voltage that causes resonance between the energy level in the valence band of the first quantum well layer and the energy level in the valence band of the second quantum well layer. At this time, holes are emitted from the second quantum well to the channel side.

  The second erasing method is performed by applying a positive voltage that causes resonance between the energy level in the conduction band of the first quantum well layer and the energy level in the conduction band of the second quantum well layer to the control electrode. . At this time, electrons are injected from the channel into the second quantum well.

  As described above, the nonvolatile semiconductor memory according to each embodiment described above is mounted on stationary and portable electronic devices (for example, personal computers, telephones, PDAs, televisions, navigation systems, recording / playback devices, etc.), Application software or programs can be stored and used.

  Furthermore, image data / sound in an imaging device (for example, a digital still camera or a digital video camera) can be accumulated. In addition, it is also possible to easily substitute the function of a memory or a hard disk drive (HDD) installed in a home appliance or a composite printer FAX apparatus that communicates via a network such as the Internet or a LAN network.

  Thus, like a memory or HDD in a conventional device, it is extremely useful for data storage and temporary storage. In addition, the electronic component circuit can be mounted as an internal memory or cache memory of a system LSI or in a memory-embedded system that uses a nonvolatile memory as a part of the electronic circuit. To be more advanced, it is also assumed that the system (circuit function or the like) is used as a rewritable system LSI that rewrites as necessary.

  In each of the embodiments described above, the MONOS type or FG type flash memory has been described as an example. However, a memory circuit in which the MONOS type or FG type flash memory is integrated and a logic circuit are mixedly mounted on the same chip. The present invention can be easily applied to a system LSI and the like, and is within the scope of the present invention. In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

Sectional drawing which shows the memory cell which concerns on each embodiment of this invention. FIG. 2 is an energy band diagram of a non-resonance state and an electron resonance state of the memory cell shown in FIG. 1. The figure which shows the energy band of a memory cell. The graph which shows the voltage dependence characteristic of the leakage current of each state shown in FIG. Diagram for explaining states that occur in the gap upon addition of Ru to the SrTiO _3. Diagram for explaining states that occur in the gap upon addition of Ru and N in SrTiO _3. The figure of explanation when the 2nd quantum well layer turns into a multiple quantum well. FIG. 3 is an energy band diagram of the memory cell according to the first embodiment. The figure explaining the barrier height (offset) (DELTA) Ec and trap level (DELTA) Et of a memory cell. The figure explaining a quantum level and a resonance state. The figure explaining a quantum level and a resonance state. The energy band figure of the memory cell which concerns on the 1st modification of 1st Embodiment. The energy band figure of the memory cell which concerns on 2nd Embodiment. The energy band figure of the memory cell concerning a 3rd embodiment. The energy band figure of the memory cell which concerns on 4th Embodiment. The figure explaining writing and erasing by electron resonance, and writing by electron resonance and erasing by Hall resonance.

Explanation of symbols

1 memory cell 10 Si substrate 12 channel region 14a source region 14b drain region 20 gate 21 first barrier layer 22 first quantum well layer 23 second barrier layer 24 second quantum well layer (charge storage layer)
25 3rd barrier layer (block layer)
26 Control electrode

Claims (13)

A silicon substrate;
A source region and a drain region that are spaced apart from each other on the silicon substrate;
A first barrier layer provided on the silicon substrate between the source region and the drain region;
A first quantum well layer provided on the first barrier layer and formed with a first energy level group including at least one energy level quantized in a conduction band;
A second barrier layer provided on the first quantum well layer;
A second energy level group provided on the second barrier layer and including at least one quantized energy level different from the energy level of the first energy level group in a conduction band; A second quantum well layer having an energy level EC2 larger than any energy level EC1 of the first energy level group among the second energy level group;
A third barrier layer provided on the second quantum well layer;
A control electrode provided on the third barrier layer;
A memory cell having
The non-volatile semiconductor memory, wherein the second quantum well layer can store electrons.   2. The nonvolatile semiconductor memory according to claim 1, wherein a thickness of each of the first quantum well layer and the second quantum well layer is 1.2 nm or less. EC2-EC1 ≧ 0.3eV
The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is a non-volatile semiconductor memory.   The second quantum well layer has a multiple quantum well structure, and each quantum well of the multiple quantum well structure has the same energy level and the same layer thickness. Non-volatile semiconductor memory.   The second quantum well layer is at least one selected from the first group consisting of Tc, Re, Ru, Os, Rh, Ir, Pd, Pt, Co, Ni, W, Mo, Cr, Mn, and Fe. 5. The nonvolatile semiconductor memory according to claim 1, further comprising an oxide dielectric film of Ti, Zr, or Hf to which an element is added.   The second quantum well layer includes at least one element selected from the first group and nitrogen, carbon, boron, Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ce, Pr, Ti, Zr or at least one element selected from the second group consisting of Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, 6. The nonvolatile semiconductor memory according to claim 5, further comprising an oxide dielectric film of Hf.   5. The method according to claim 1, wherein the second quantum well layer includes at least one selected from polysilicon, nitride metal, carbide metal, oxide metal, Pt, Ir, and Ru. A non-volatile semiconductor memory according to claim 1.   The nonvolatile semiconductor memory according to claim 1, wherein the second quantum well layer is a silicon nitride layer.   9. The nonvolatile semiconductor memory according to claim 8, wherein a ratio of the silicon amount and the nitrogen amount in the silicon nitride layer is larger than 0.95. The nonvolatile semiconductor memory according to claim 1, wherein a leakage current density when reading data from the memory cell is 1.0 × 10 ⁻⁹ A / cm ² or less. A method for writing into a nonvolatile semiconductor memory according to any one of claims 1 to 10,
Data is written by applying a positive voltage that causes resonance between an energy level in the first energy level group and an energy level in the second energy level group to the control electrode. How to write. A method for erasing a nonvolatile semiconductor memory according to any one of claims 1 to 10,
Data is erased by applying a negative voltage that causes resonance between an energy level in the first energy level group and an energy level in the second energy level group to the control electrode. How to erase. A method for erasing a nonvolatile semiconductor memory according to any one of claims 1 to 10,
The control electrode generates a negative voltage that causes resonance between a quantized energy level in the valence band of the first quantum well layer and a quantized energy level in the valence band of the second quantum well layer. An erasing method characterized in that data is erased by applying to the data.

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