KR101243861B1 - Operating method of charge trap flash memory device - Google Patents

Abstract

An operating method of performing an erase operation on a charge trapping flash memory device having a charge trap layer is disclosed. The disclosed operating method is characterized in that erase is performed by applying a complex pulse of a DC pulse and a DC perturbation pulse to the charge trapping flash memory device.

Description

Operating method of charge trap flash memory device

The present invention relates to a method of operating a charge trapping flash memory device, and more particularly, to promote charge stabilization and recombination of electrons and holes, thereby ensuring stability of an erased state. And a method of operating a charge trapping flash memory device.

Among the semiconductor memory devices, the nonvolatile memory device is a storage device in which stored data is not destroyed even when power supply is cut off.

The configuration of the memory cell, which is a basic component of the nonvolatile semiconductor memory device, depends on the field in which the nonvolatile semiconductor memory device is used.

A high-capacity nonvolatile semiconductor memory device widely used at present, and in the case of a NAND (not and) flash semiconductor memory device, the gate of the transistor includes a floating gate in which charge is stored, that is, data is stored. It has a structure in which a control gate (control gate) for controlling this is sequentially stacked.

In such a flash semiconductor memory device, the memory cell size is rapidly being reduced in order to meet the increasing demand for increasing memory capacity every year. In addition, in order to reduce the size of the cell, it is required to effectively reduce the height in the vertical direction of the floating gate.

As a means for storing charge in order to effectively reduce the height of the memory cell in the vertical direction, and to maintain the memory characteristic of the memory cell, for example, the retention characteristic, which is to keep the stored data intact for a long time. MEIOS (Metal-Oxide-Nitride-Oxide-Semiconductor) or MONOS (Metal-Oxide- Nitride-Oxide-Semiconductor) memory devices constructed using silicon nitride (Si ₃ N ₄ ) rather than floating gates A semiconductor memory device having a structure of -Oxide-Insulator-Oxide-Semiconductor) has been proposed, and active research is being conducted. Here, the difference is that SONOS uses silicon as the control gate material and MONOS uses metal as the control gate material.

SONOS and MONOS type memory devices use a charge trap layer such as silicon nitride (Si ₃ N ₄ ) instead of a floating gate as a means for storing charge. That is, the SONOS type or MONOS type memory device uses an oxide film to form a stack (a stack composed of a floating gate and insulating layers stacked above and below) between a substrate and a control gate in a memory cell configuration of a flash semiconductor memory device. In this case, a nitride (Nitride) and an oxide (Oxide) are replaced by a stacked laminate (ONO), and a charge using a characteristic in which a threshold voltage shifts as the charge is trapped in the nitride film. It is a charge trap flash (CTF) memory device.

For more information about SONOS memory devices, see Technical Digest of International Electron Device Meeting (IEDM 2002, December), pp. 927-930. Swift et al., "An Embedded 90nm SONOS Nonvolatile Memory Utilizing Hot Electron Programming and Uniform Tunnel Erase".

The basic structure of a SONOS type memory device is as follows. A first silicon oxide film (SiO ₂ ) is formed as a tunnel insulating film on the semiconductor substrate between the source and drain regions, that is, on the channel region so that both ends contact the source and drain regions. The first silicon oxide film is a film for tunneling charges. A silicon nitride film (Si ₃ N ₄ ) is formed on the first silicon oxide film as the electrolytic trap layer. The silicon nitride film is a material film in which data is substantially stored, and charges tunneling the first silicon oxide film are trapped. A second silicon oxide film is formed on the silicon nitride film as a blocking insulating film for blocking the charge from moving upward through the silicon nitride film. A gate electrode is formed on the second silicon oxide film.

However, the SONOS type memory device having such a general structure has low dielectric constants of silicon nitride and silicon oxide films, insufficient trap site density in the silicon nitride film, high operating voltage, and high data rate (program speed). The problem is that the charge retention time in the vertical and horizontal directions is not sufficient as desired.

Recently, when the aluminum oxide film (Al ₂ O ₃ ) having a larger dielectric constant than the silicon oxide film is used as the blocking insulating film, the fact that the program speed and retention characteristics are improved compared with the silicon oxide film is used. It has been reported.

For more information on this report, please see the Extended Abstract of 2002 International Conf. on Solid State Device and Materials, Nagoya, Japan, Sept. 2002, pp. 162-163, in "Novel Structure of SiO ₂ / SiN / High-k dielectric, Al ₂ O ₃ for SONOS type flash memory," published by C. Lee et al.

As described above, in a charge trapping flash (CTF) memory device having a charge trap layer instead of a floating gate, electrons are stored in the charge trap layer during programming, and holes are stored in the charge trap layer during erasing. holes) to remove electrons stored in the charge trap layer by hole-electron recombination.

However, when initially programmed into an unused charge trapping flash memory device, the injected electrons are trapped in the charge trap layer and localized, where the electrons are thermally stabilized as a deep trap and spread spatially. Goes. Since the threshold voltage of the device is changed while the electrons are stabilized and spread in space, it takes time until the threshold voltage Vth is fixed as localized electron thermalization proceeds.

Such time-dependent Vth fluctuations make it difficult to control the threshold voltage value distribution during programming by an incremental step pulse programming (ISPP) method.

As is well known, the ISPP method applies a program pulse voltage while gradually increasing the magnitude of an applied program pulse voltage, and subsequently, verifies a threshold voltage of a memory cell by applying a verifying voltage. Repeatedly, the threshold voltage of the memory cell reaches a desired value. Since a plurality of memory cells constituting the memory device has an initial threshold voltage distribution, an ISPP scheme is introduced to allow all memory cells to reach a desired threshold voltage in consideration of the threshold voltage distribution for each memory cell.

However, when the threshold voltage changes with time as described above, it is difficult to control the threshold voltage value distribution by the ISPP method, and it is not easy to program the memory cell within a desired threshold voltage value range.

On the other hand, upon erasing of the programmed information, the recombination of the injected holes and the electrons de-trapped by the localized electrons or the fields is made non-localized, and the holes left after the recombination and localization not completely removed Re-distribution of the former electrons can be made.

During such electron-hole recombination and charge rearrangement, since the threshold voltage value of the memory element is changed, the effective erase time is not the hole injection time but the sum of the recombination time and the rearrangement time. Should be considered.

For the lifetime distribution of electron-holes after optical pumping measured in silicon nitride made by LPCVD, see K. S. Seol et al., Phys. Rev. B 62, 1532 (2000).

According to this document, the recombination time of electron-holes is widely distributed from ns to ms. In the LESR measurement results, it is known that the recombination time is distributed to ˜10 ³ s.

The recombination time (tau) of the localized electrons and holes can be expressed by Equation (1).

τ = τ ₀ exp (2 R / R ₀ ) (τ ₀ = 10 ^-8 s)

Where R ₀ is the localization length of the electron or hole, where R ₀ (E) = [ h ² / m ( E _c -E )] ^1/2 or [ h ² / m ( E _v -E )] ^1/2 can be satisfied. R is the localized electron-space space distance.

As can be seen from Equation 1, the deep trap ( R ₀ ) decreases, the recombination time increases.

In the erase mode, the injected holes stabilize over time and settle to deep levels.

In the program mode or the erase mode, the variation of the threshold voltage value is large while the stabilization occurs and the charge spreads spatially. Further stabilization results in less threshold voltage fluctuations, but at the same time, charges are localized to deep levels, making them difficult to move.

Therefore, when the recombination time is long, electrons or holes stabilized over time and localized to a deep level cannot be moved, making it difficult to recombine with the opposite charge. In addition, when stabilization, the movement of electrons or holes is limited, the stabilization time is gradually longer.

In addition, the recombination time is long, and the charge is stabilized over time, so that sufficient hole-electron recombination does not occur, and if the electrons trapped by such incomplete recombination remain after erasing, the dispersion increases during programming. .

For example, in a state in which electron-holes are incompletely recombined in the erase mode and electrons are present together as well as holes, even if the electrons are injected with the same number of electrons as the holes remaining when the electron-holes are completely recombined, And holes are incompletely recombined, resulting in the presence of holes as well as electrons. Even if an additional number of electrons are injected therein, the electrons may still be incompletely recombined to bring the holes together. Since the remaining holes can be recombined with the electrons at any moment during the program of repeating the electron injection process and the verification process by the ISPP method, the threshold voltage value can be changed, thus increasing the dispersion of the threshold voltage value at the completion of the program. .

As described above, due to incomplete recombination, the possibility of coexistence with opposite charges causes a scatter during programming, and only when the electrons are removed cleanly in the erased state, it is possible to prevent such a spread during programming.

Due to such incomplete recombination, if the opposite charges coexist, even during high temperature storage (HTS), electron-hole recombination may proceed to cause a change in the threshold voltage value.

Therefore, as described above, when the stabilization time and the recombination time are prolonged, and incomplete recombination is performed, the stability of the erase state or the program state decreases, and the possibility of deterioration of the dispersion of threshold voltage values during program or erase This becomes large, and a change occurs in the threshold voltage value during high temperature storage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and improves the rate of charge stabilization and the recombination of electrons and holes, so that the opposite charge remains in the charge trap layer in the erased state. It is an object of the present invention to provide a method of operating a charge trapping flash memory device which can prevent the electronic device from being prevented and ensuring stability of an erased state.

In order to achieve the above object, the present invention provides an operation method of performing an erase operation on a charge trapping flash memory device having a charge trapping layer, the method comprising: The erase is performed by applying a complex pulse.

Preferably, the complex pulse has a form in which the DC perturbation pulse appears after the DC pulse, and the DC perturbation pulse has a DC level of opposite polarity to the DC pulse.

Preferably, the magnitude of the DC level of the DC perturbation pulse is smaller than the DC pulse.

The complex pulse may have a form in which a DC pulse and a DC perturbation pulse appear alternately a plurality of times.

The charge trapping flash memory device includes a substrate; A gate structure may be included on the substrate, and the gate structure may include a tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode.

In this case, the tunnel insulating film may be an oxide film, the charge trap layer may be a nitride film, the blocking insulating film may include a high dielectric material, and the gate electrode may be formed of a metal film.

The complex pulse is preferably input to the substrate at the time of erasing.

The DC perturbation pulse promotes recombination or rearrangement of charges.

A verification pulse may be applied after the complex pulse to verify an erased state.

According to the operation method of performing the erase operation on the charge trapping flash memory device having the charge trap layer according to the present invention as described above, since the DC perturbation pulse is applied in addition to the DC pulse contributing to the erase, The movement of charges in the trap layer is active, thereby greatly increasing the stabilization rate and recombination rate of the charges, and significantly lowering the possibility of incomplete recombination, thereby greatly reducing the possibility of coexistence with the opposite charges. Therefore, it is possible to secure the stability of the erase state, greatly reduce the possibility of dispersion deterioration of the threshold voltage value during erasing, and prevent the problem of changing the threshold voltage value during high temperature storage.

Hereinafter, a method of operating a charge trapping flash memory device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 schematically shows an example of a charge trap type flash memory device in which a program or erase operation may be performed by applying an operating method according to the present invention.

Referring to FIG. 1, a charge trapping memory device 10 according to an embodiment of the present invention includes a substrate 11 and a gate structure 20 formed on the substrate 11.

First and second impurity regions 13 and 15 doped with a predetermined conductive impurity may be formed in the substrate 11. One of the first and second impurity regions 13 and 15 may be used as a drain D and the other as a source S.

The gate structure 20 includes a tunnel insulating film 21 formed on the substrate 11, a charge trap layer 23 formed on the tunnel insulating film 21, and a blocking insulating film 25 formed on the charge trap layer 23. ). The gate electrode 27 may be formed on the blocking insulating layer 25. In FIG. 1, reference numeral 19 denotes a spacer.

The tunnel insulating layer 21 is a film for tunneling charge, and is formed on the substrate 11 to contact the first and second impurity regions 13 and 15. The tunneling insulating film 21 may be formed of, for example, SiO ₂ or an oxide made of various high-k oxides or a combination thereof as a tunneling oxide film.

Alternatively, the tunnel insulating film 21 may be formed of a silicon nitride film, for example, Si ₃ N ₄ . At this time, the silicon nitride film is preferably formed so that the impurity concentration is not high (that is, the impurity concentration is comparable to that of the silicon oxide film) and the interface property with silicon is excellent. In order to form such a high quality silicon nitride film, the silicon nitride film constituting the tunnel insulating film 21 may be formed using a special manufacturing method such as Jet Vapor Depositon.

When the silicon nitride film is formed by the above-mentioned special manufacturing method, it is possible to form a defect-less silicon nitride film (defect-less Si ₃ N ₄ ) which does not have a high impurity concentration as compared with the silicon oxide film and has excellent interface characteristics with silicon.

Alternatively, the tunnel insulating layer 21 may be formed of a double layer structure of a silicon nitride film and an oxide film.

As described above, the tunnel insulating layer 21 may be formed of a single layer structure of an oxide or nitride, or may be formed of a plurality of layers of materials having different energy band gaps.

The charge trap layer 23 is a region in which information is stored by the charge trap. The charge trap layer 23 may be formed to include any one of polysilicon, nitride, high-k dielectric having high dielectric constant, and nanodots.

For example, the charge trap layer 23 may be formed of a nitride such as Si ₃ N ₄ or a high-k oxide such as SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfSiON, HfON, or HfAlO.

In addition, the charge trap layer 23 may include a plurality of nanodots discontinuously disposed as a charge trap site. In this case, the nano-dots may be made in the form of a microcrystal (nanocrystal).

The blocking insulating layer 25 is for blocking charge from moving upward through the position where the charge trap layer 23 is formed, and may be formed of an oxide layer.

The blocking insulating layer 25 is formed of SiO ₂ , or a high-k material, such as Si ₃ N ₄ , Al ₂ O ₃ , HfO ₂ , Ta ₂ O _5, or ZrO, which is a material having a higher dielectric constant than the tunneling insulating film 21. ₂ can be formed. The blocking insulating film 25 may be formed in a multilayer structure. For example, the blocking insulating film 25 may be formed of two or more layers including an insulating layer made of a commonly used insulating material such as SiO ₂ and a high dielectric layer formed of a material having a higher dielectric constant than the tunneling insulating film 21. Can be configured.

The gate electrode 27 may be formed of a metal film. For example, the gate electrode 27 may be formed of aluminum (Al). In addition, the gate electrode 27 may be formed of a silicide material such as Ru, TaN metal, or NiSi, which is typically used as a gate electrode of a semiconductor memory device. .

By injecting electrons into the charge trapping flash memory device as described above, a program is performed such that the injected electrons are trapped at the trap site of the charge trap layer to have a threshold voltage of a program state, for example, 3V, or to the memory device. Holes may be injected to erase electrons by electron-hole recombination to perform an erase such that a threshold voltage of an erase state becomes a threshold voltage of, for example, 0V. As described above, memory cells of a flash memory device have two states, a program state and an erase state. An on state in which current flows to a drain connected to a bit line by a voltage provided to the gate electrode 27 when the threshold voltage of the flash memory cell is reduced and is read is called an erase state. The off state in which no current flows to the drain connected to the bit line by the voltage provided to the gate electrode 27 when the threshold voltage is increased is called a program state.

As described above, the charge trap for performing the program or erase operation of the present invention, such that the stabilization of charge (electrons and / or holes) during programming or erasing occurs quickly and to prevent incomplete recombination of electron-holes during erasing According to the type flash memory device operating method, a program or erase operation is performed by applying a voltage in the form of a complex pulse of a DC pulse and a perturbation pulse. The perturbation pulse may be an AC perturbation pulse or a DC perturbation pulse as in the following embodiments.

When the complex pulse shown in FIGS. 2 to 5 is applied to the charge trapping flash memory device, a program or erase operation is performed.

However, the complex pulse shown in FIGS. 2 to 5 is applied to the gate electrode 27 during programming, and for example, the substrate 11 may be left at 0V. In addition, the complex pulse shown in FIGS. 2 to 5 is applied to, for example, the substrate 11 at the time of erasing, and the gate electrode 27 can be left at 0V.

Therefore, from the viewpoint of the gate electrode 27, the program voltage is a positive voltage, the erase voltage is a negative voltage, and the polarities are opposite to each other, and the basic pulse structure except for the DC pulse section and the perturbation pulse frequency is the same. Accordingly, the complex pulse of FIGS. 2 to 5 may be commonly applied to a program or erase operation. FIG. 2 illustrates a complex pulse according to a method of operating a charge trapping flash memory device according to an embodiment of the present invention. Shown in comparison with DC pulse.

As can be seen in Figure 2, the voltage applied for the program or erase operation according to the conventional method consists of only the DC pulse component. The DC pulse time period to which the DC pulse is applied may be approximately 10 μs in the program mode and approximately 10 ms in the erase mode.

On the other hand, it consists of a complex pulse, a DC pulse (program pulse or erase pulse) component and a perturbation pulse component applied for a program or erase operation according to the present invention.

In the embodiment shown in Figure 2, the perturbation pulse is an AC perturbation pulse. This AC perturbation pulse preferably has a frequency greater than the inverse of the time period during which the DC pulse appears.

2 shows an embodiment in which a complex pulse applied for a program or erase operation according to the present invention is in the form of an AC perturbation pulse following a DC pulse for a predetermined time.

The predetermined time may correspond to a DC pulse section of a program or erase voltage composed of only DC pulses according to a conventional method. That is, conventionally, the voltage applied for the program or erase operation is formed in the form of a DC pulse only, whereas the complex pulse applied for the program or erase operation in the present invention is the DC pulse corresponding to the conventional and the stabilization of the charge and the electrons. Perturbation pulses that promote recombination of holes may be combined.

In the complex pulse of FIG. 2, the DC pulse duration may be, for example, approximately 10 μs in the program mode, for example, approximately 10 ms in the erase mode. In this case, in the program mode, the AC perturbation pulse component may be an AC pulse that has a frequency greater than 1/10 μs = 0.1 MHz, and in the erase mode the AC perturbation pulse component has a frequency greater than 1/10 ms = 100 Hz. It can be an AC pulse. The perturbation pulses of the complex pulses of the embodiments of FIGS. 3 to 5 below are also AC perturbation pulses, and this AC perturbation pulse may also satisfy the frequency range as in the embodiment of FIG. 2.

3 to 5 show complex pulses according to a method of operating a charge trapping flash memory device of other embodiments of the present invention.

Referring to FIG. 3, the complex pulse of the present invention may be configured such that a DC pulse and an AC perturbation pulse appear alternately a plurality of times. FIG. 3 shows an example in which a complex pulse applied for a program or erase operation appears in three pairs of a DC pulse and an AC perturbation pulse.

Referring to FIG. 4, the complex pulse of the present invention may be configured such that a DC pulse and an AC perturbation pulse superimposed on a DC level having the same polarity as the DC pulse and smaller than the DC pulse signal alternately appear. 4 shows an example in which the complex pulse is a form in which a DC pulse and a DC level + AC perturbation pulse (overlapping) pair appear three times.

Referring to FIG. 5, the complex pulse of the present invention may be a form in which an AC perturbation pulse is superimposed on a DC pulse. At this time, the DC pulse section of the memory voltage may correspond to the DC pulse section of the memory voltage consisting of only the DC pulse according to the conventional method.

In programming, a program voltage having a complex pulse shape of any one of FIGS. 2 to 5 is applied to a memory cell of a charge trapping flash memory device. Subsequently, a program verify operation is performed to determine whether the memory cell is programmed by applying a verify voltage.

When programming by the ISPP method, the program voltage is applied and programmed, and then the verify voltage is applied to verify the threshold voltage of the memory cell until the threshold voltage of the memory cell reaches the program state. .

At the time of erasing, an erase voltage having a complex pulse form of any one of FIGS. 2 to 5 is applied to the memory cell of the charge trapping flash memory device. Subsequently, an erase verify operation is performed to determine whether the memory cell is properly erased by applying the verify voltage.

It is well known in the art to verify a program or erase state by applying a verify voltage followed by a program or erase voltage. In addition, as can be seen in other embodiments described below, the program voltage and the verify voltage may have the same polarity, and the erase voltage and the verify voltage may have opposite polarities. Therefore, in order to explain that the complex pulse is commonly applied as a program or an erase voltage for simplicity, the illustration of the verification pulse voltage is omitted in FIGS. 2 to 5 for convenience.

As described above, according to the method for operating a charge trapping flash memory device according to the present invention which performs a program or erase operation using the complex pulse shown in FIGS. Hole) After the injection, the movement of the charges can be temporarily smoothed by external perturbation by the AC perturbation pulse component, so that the charge stabilization and electron-hole recombination rate can be greatly improved, which greatly shortens the stabilization and recombination time. can do.

The evidence that AC perturbation can enhance the rate of stabilization and recombination can be found in the literature on the frequency dependence of AC conductivity as disclosed in R. D. Gould and S. A. Awan, Thin Solid Films, 443, 309 (2003).

6 is a graph showing the frequency dependence of the AC conductivity disclosed in this document.

As can be seen in Figure 6, the AC conductivity increases with increasing ac frequency, in the present invention the frequency of the AC perturbation signal used in the program mode or the erase mode in the range of several hundred Hz to several MHz, the AC conductivity is It can be seen that the value is quite large. The higher the frequency, the greater the AC conductivity, so the larger the frequency, the longer the charge travels.

Therefore, it can be seen that the conduction of the charge is possible by the AC perturbation pulse component, and the movement of the charge can be more actively by the AC perturbation.

At this time, the AC conduction in the insulator is a directional conduction of the charge, that is, conduction due to an increase in the mean free path of the charge, not DC conduction.

Therefore, when the AC perturbation pulse is applied to the charge trapping flash memory device, the movement of the trapped charges in the nitride constituting the charge trap layer, for example, the charge trap layer becomes active. Thereby, the rate of stabilization of the charge can be greatly enhanced. In addition, the recombination rate of electron-holes can be greatly enhanced, thereby significantly lowering the possibility of incomplete recombination, thereby greatly reducing the possibility of coexistence with opposite charges.

In addition, even when the charge is trapped in the deep trap, since the charge trapped in the deep trap is easy to move due to AC perturbation, the recombination probability can be greatly increased.

7A and 7B show the possibility of recombination of electron-holes in the absence of AC perturbation and in the presence of AC perturbation when there are electrons trapped in the deep trap and immovable.

As shown in FIG. 7A, in the absence of AC perturbation, the probability of electrons trapped in deep traps and immovable is recombined with the holes. However, as shown in FIG. 7B, when there is AC perturbation, the electrons trapped in the deep trap are also easily moved by AC perturbation, so that the probability of electrons recombining with holes increases. At this time, since the electric charges are moved randomly without directivity due to AC perturbation, there is no substantial transfer of charge even if AC perturbation occurs.

2 to 5, the perturbation pulse included in the complex pulse applied to the charge trapping flash memory device for programming or erasing to facilitate the stabilization of the charge and the promotion of electron-hole recombination is more specifically, the AC perturbation pulse. Embodiments that have been described are AC perturbation pulses that do not include DC levels of opposite polarity to DC pulses.

In another embodiment, the perturbation pulse included in the complex pulse of the present invention has a polarity opposite to that of the program or erase DC pulse as shown in FIGS. 8, 13, 14a, 14b, 15a, and 15b. It may have a DC level. That is, if the DC pulse during programming is a positive voltage, the DC level of the perturbation pulse becomes a negative voltage, and conversely, if the DC pulse during erasing is a negative voltage, the DC level of the perturbation pulse becomes a positive voltage. In the following description, the erase voltage and the program voltage are separately described in consideration of the fact that the perturbation pulse has a DC level of opposite polarity to the DC pulse.

8 illustrates an erase voltage according to a method of operating a charge trapping flash memory device according to another embodiment of the present invention. For comparison, FIG. 9 shows an erase voltage according to a conventional method of operation.

Referring to FIG. 8, the erase voltage according to the present invention for the erase operation may be a complex pulse type voltage including an erase pulse and a perturbation pulse which are DC pulses. At this time, the complex pulse is formed in the form of a perturbation pulse following the erase pulse, the perturbation pulse has a DC level of the opposite polarity to the erase pulse. That is, the erase voltage consists of an erase pulse of negative voltage followed by a perturbation pulse of positive voltage.

8 shows an embodiment where the perturbation pulse is a DC perturbation pulse of opposite polarity to the erase pulse.

In the erase operation, a complex pulse voltage consisting of an erase pulse (DC pulse) and a perturbation pulse is applied to erase. A verify pulse voltage is then applied to verify that the erase was successful. This verify pulse voltage may be a voltage of opposite polarity to the erase pulse.

As a comparative example, referring to FIG. 9, conventionally, an erase operation is performed by applying only an erase pulse voltage consisting of a DC pulse only for an erase operation, and then applying a verification pulse voltage after a predetermined time to confirm that the erase is properly performed. The operation was performed.

FIG. 10 illustrates a change of drain current Id over time in a memory cell of a charge trapping flash memory device when erased with the complex pulse of FIG. 8. FIG. 11 illustrates a change of drain current Id in a memory cell of a charge trapping flash memory device when an erase pulse voltage including only the DC pulse of FIG. 9 is applied.

In a charge trapping flash memory cell, the drain current increases with time after application of an erase pulse and saturates to a predetermined value. The Id transient phenomenon in which such drain current increases over time may be due to relocation of charges. An increase in drain current over time means that the threshold voltage decreases after an erase pulse is applied.

As such, due to the charge transfer after the program / erase in the charge trap layer, the threshold voltage Vth value fluctuates over time not only after programming but also after erasing. As a result, an error occurs in an operation of reading the erase verification or the erase state after the erase. This verification error causes an erase fail.

In erasing according to the conventional method shown in Fig. 9, as shown in Fig. 11, since a saturation time takes about 1 second or more, it is difficult to make a quick and accurate erasure determination.

Therefore, in order to make a fast and accurate erase determination or to prevent erase failure, it is necessary to effectively reduce the threshold voltage saturation time after erasing.

As shown in FIG. 8, when a DC perturbation pulse of opposite polarity is applied after the erase pulse, as shown in FIG. 10, the drain current transient can be accelerated to saturate the erase state within a shorter time. The time can be reduced effectively. The results of FIG. 10 show the change over time of the transient drain (Id) current upon application of a perturbation pulse of opposite polarity after application of an erase pulse voltage of 10 ms width. In FIG. 10, the drain current was almost saturated after approximately 15 ms.

FIG. 12 shows a comparison of the drain current Id over time when applying the complex pulse of the present invention of FIG. 8 and applying the erase pulse voltage composed of only the conventional DC pulse shown in FIG. 9.

As can be seen from FIG. 12, when the complex pulse according to the present invention of FIG. 8 is applied, the time for saturation of the drain current, that is, the time for saturation of the threshold voltage, can be significantly shortened as compared with the related art. Therefore, according to the present invention using the complex pulse of FIG. 8 in the erase operation, a rapid erase determination is possible by applying a verify pulse voltage following the erase operation, and an error in an operation of reading the erase verify or erase state after erase is performed. Erase failure due to occurrence can be prevented.

Figure 8 shows an example in which the composite pulse consists of an erase pulse followed by a single DC perturbation pulse of opposite polarity.

As another embodiment, as shown in FIG. 13, the complex pulse for the erase operation may be in the form of an erase pulse and a plurality of DC perturbation pulses of the opposite polarity.

In addition, as shown in FIGS. 14A and 14B, the complex pulse for the erase operation may be modified in FIGS. 8 and 13 so that the AC perturbation pulse is superimposed on a DC level having a polarity opposite to that of the erase pulse.

The perturbation pulse having a DC level of opposite polarity to that of the DC pulse described with reference to FIGS. 8 to 14B can also be applied during programming.

15A and 15B show embodiments of a program voltage corresponding to FIGS. 8 and 13.

As shown in FIG. 15A, a complex pulse for a program operation may be in the form of a program pulse which is a DC pulse and a DC perturbation pulse of opposite polarity.

In addition, as shown in FIG. 15B, the complex pulse for the program operation may be formed of a program pulse which is a DC pulse and a plurality of DC perturbation pulses of opposite polarity.

As another example, the complex pulse for the program operation may have a structure in which the AC perturbation pulse is superimposed on a DC level having a polarity opposite to that of the program pulse, corresponding to the erase voltage characteristic of FIGS. 14A and 14B. This can be sufficiently inferred by applying the erase voltage characteristics of FIGS. 14A and 14B to the program voltages of FIGS. 15A and 15B, and thus the illustration is omitted here.

Meanwhile, FIGS. 16A and 16B show program voltages when programming in the ISPP method using the program voltages of FIGS. 15A and 15B, respectively. 16A and 16B show that the operation method of the present invention can also be applied to an ISPP program. In FIG. 16A and FIG. 16B, Vpgm represents a basic program pulse voltage when ISPP programming is performed, and ΔVpgm represents a program pulse voltage increase magnitude in ISPP.

When the operating method of the present invention is applied to an ISPP program, a program pulse having a predetermined size is applied and then programmed, followed by a perturbation pulse to promote saturation of the threshold voltage. A verify pulse voltage is then applied to verify that the threshold voltage has reached the program state. If the program state is not reached, the previous process is repeated by increasing the size of the program pulse by a certain amount. This process is repeated a plurality of times until the threshold voltage reaches the program state.

1 schematically shows an example of a charge trap type flash memory device in which a program or erase operation may be performed by applying an operating method according to the present invention.

2 shows a composite pulse according to a method of operating a charge trapping flash memory device according to an embodiment of the present invention in comparison with a DC pulse according to a conventional operating method.

 3 to 5 show complex pulses according to a method of operating a charge trapping flash memory device of other embodiments of the present invention.

FIG. 6 is a graph showing the frequency dependence of AC conductivity disclosed in R. D. Gould and S. A. Awan, Thin Solid Films, 443, 309 (2003).

7A and 7B show the possibility of recombination of electron-holes in the absence of AC perturbation and in the presence of AC perturbation when there are electrons trapped in the deep trap and immovable.

8 illustrates an erase voltage according to a method of operating a charge trapping flash memory device according to another embodiment of the present invention.

9 shows an erase voltage according to a conventional operating method as a comparative example.

FIG. 10 illustrates a change of drain current Id over time in a memory cell of a charge trapping flash memory device when erased with the complex pulse of FIG. 8.

FIG. 11 illustrates a change of drain current Id in a memory cell of a charge trapping flash memory device when an erase pulse voltage including only the DC pulse of FIG. 9 is applied.

FIG. 12 shows a comparison of the drain current Id over time when applying the complex pulse of the present invention of FIG. 8 and when applying an erase pulse voltage composed of only the conventional DC pulse shown in FIG. 9.

13, 14A, and 14B show an erase voltage according to a method of operating a charge trapping flash memory device according to still another embodiment of the present invention, respectively.

15A and 15B show a program voltage according to a method of operating a charge trapping flash memory device according to embodiments of the present invention, respectively.

16A and 16B show program voltages when programming in the ISPP method using the program voltages of FIGS. 15A and 15B, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

10 ... Charge trap type flash memory element 21 ... Tunnel insulating film

23.Charge trap layer 25.Blocking insulating film

27 ... gate electrode

Claims (9)

An operation method of performing an erase operation on a charge trapping flash memory device having a charge trap layer, A method for operating a charge trapping flash memory device, comprising: applying a complex pulse of a DC pulse and a DC perturbation pulse to the charge trapping flash memory device for erasing. The method of claim 1, wherein the complex pulse is formed in a form in which the DC perturbation pulse appears after the DC pulse, And the DC perturbation pulse has a DC level of opposite polarity to the DC pulse. The method of operating a charge trapping flash memory device according to claim 1, wherein the magnitude of the DC level of the DC perturbation pulse is smaller than the DC pulse. The method of claim 1, wherein the complex pulse has a form in which a DC pulse and a DC perturbation pulse appear alternately a plurality of times. The device of claim 1, wherein the charge trapping flash memory device comprises: A substrate; A gate structure on the substrate, The gate structure, And a tunnel insulating film, a charge trap layer, a blocking insulating film, and a gate electrode. 6. The charge trapping flash memory device according to claim 5, wherein the tunnel insulating film is an oxide film, the charge trap layer is a nitride film, the blocking insulating film includes a high dielectric material, and the gate electrode is formed of a metal film. How it works. 6. The method of claim 5, wherein said complex pulse is input to said substrate upon erase. 5. The method of any one of claims 1 to 4, wherein the DC perturbation pulse facilitates recombination or rearrangement of charges. The method of any one of claims 1 to 4, wherein an erase state is verified by applying a verification pulse following the complex pulse.

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