CN101256837A - Method of operating nonvolatile memory device - Google Patents

Method of operating nonvolatile memory device Download PDF

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Publication number
CN101256837A
CN101256837A CNA2008100741982A CN200810074198A CN101256837A CN 101256837 A CN101256837 A CN 101256837A CN A2008100741982 A CNA2008100741982 A CN A2008100741982A CN 200810074198 A CN200810074198 A CN 200810074198A CN 101256837 A CN101256837 A CN 101256837A
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pulse
perturbation
voltage
assembled
charge trap
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CN101256837B (en
Inventor
薛光洙
朴祥珍
李晟熏
朴星一
金钟燮
崔正达
崔奇焕
沈载星
文承炫
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Provided is a method of operating a nonvolatile memory device to perform a programming operation or an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and an AC perturbation pulse to the nonvolatile memory device to perform the programming operation or the erase operation.

Description

The method of operation non-volatile memory device
Technical field
Example embodiment relates to a kind of method of operating nonvolatile memory, more particularly, relate to a kind of by accelerated charge stable and electronics and hole compound improve the method for operation nonvolatile memory of the stability of programming and/or erase status.
Background technology
Even non-volatile memory device is also to preserve the semiconductor memory system of the data of storage when cutting off the electricity supply supply.
The structure of memory cell (memory cell, that is, the fundamental element of non-volatile memory device) changes according to the application of non-volatile memory device.
At NAND flash semiconductor storage arrangement (promptly, the high power capacity Nonvolatile semiconductor memory device) under the situation, transistorized grid can have such structure: wherein, the control gate of the floating boom (floating gate) of stored charge (that is data) and control floating boom is by sequence stack.
For the flash semiconductor storage arrangement, in order to satisfy the more demand of large storage capacity, the size of memory cell is reduced.In addition, according to reducing of primitive size, may also need to reduce the height of floating boom.
For the memory attribute of keeping memory cell (for example, the data of storage are preserved the maintenance attribute of sufficiently long time), and reduce the vertical height of memory cell simultaneously, proposed such semiconductor memory system: it has use silicon nitride (Si 3N 4) layer rather than floating boom be as SONOS (silicon-oxide-nitride--oxide-semiconductor) storage arrangement of the unit of stored charge with such as MOIOS (metal-oxide-insulator-oxide-semiconductor) structure of MONOS (metal-oxide-nitride-oxide-semiconductor) storage arrangement.Under the situation of SONOS device, silicon is as control gate, and under the situation of MONOS device, metal is as control gate.
SONOS and MONOS storage arrangement use for example silicon nitride (Si 3N 4) charge trap (charge trap) layer (rather than floating boom) of layer is as the unit of stored charge.That is to say, in SONOS and MONOS storage arrangement, stacked structure between substrate and the control gate (floating boom and be stacked on the floating boom/under insulation course) is replaced by following stacked structure (ONO): in this stacked structure, oxide skin(coating), nitride layer and oxide skin(coating) sequence stack are in memory cell.Therefore, SONOS and MONOS storage arrangement can be considered to charge trap flash (CTF) storage arrangement, wherein, when nitration case is caught electric charge, threshold voltage shift.
The basic structure of SONOS type stores apparatus can be as follows: the first silicon dioxide (SiO with the contact source of blocking (contacting source) and drain region 2) layer (that is, tunnel insulation layer) can be formed at, just on Close Tunnel between source region and the drain region the semiconductor-based end.First silicon oxide layer can be the layer of tunnelling electric charge.Silicon nitride (Si 3N 4) layer can be used as the charge trap layer and be formed on first silicon dioxide layer.Silicon nitride layer can be the material layer of actual storage data, can catch electric charge by the first silicon dioxide layer tunnelling by silicon nitride layer.Silicon dioxide layer can be formed on the silicon nitride layer, as the blocking insulation layer that is used to stop electric charge to move on after by silicon nitride layer.Grid can be formed on second silicon dioxide layer.
Yet in having the SONOS storage arrangement of said structure, the specific inductive capacity of silicon nitride layer and silicon dioxide layer is relatively low, and the density of the point of the trap in the silicon nitride layer (trap site) is not enough.Therefore, the operating voltage of storage arrangement is higher, and the speed of record data (program rate) is fast inadequately, and the charge retention time on vertical and horizontal direction may fall short of.
Recently, report is arranged when using aluminium oxide (Al with specific inductive capacity bigger than silicon dioxide layer 2O 3) when layer replaces silicon dioxide layer as blocking insulation layer, can improve program rate and retention performance.
In CTF storage arrangement with the charge trap layer that replaces floating boom, electronics is injected into the charge trap layer during programming, and the hole is injected into the charge trap layer to use the compound electronics that is stored in the charge trap layer that removes of hole and electronics between erasing period.
Yet injected electrons may not caught by the charge trap layer and locate in using the initial programming process of CTF storage arrangement, and then, electronics can the space diffuses into the deep trap in the nitride layer by thermalization the time.Therefore, the starting voltage of device may change, thereby needs some times up to having fixed starting voltage (Vth) according to the thermalization of the electronics of locating.
The variation of the starting voltage Vth of time correlation may make the dispersion that is difficult to control threshold voltage when using incremental steps pulse program (ISPP) method.
According to the ISPP method, in the amplitude that increases programming pulse voltage, programming pulse voltage can be applied, and the starting voltage of verifying voltage can be applied with the recognition memory primitive, then, can repeat said process and reach expectation value up to the voltage of memory cell.Owing to form the initial starting voltage of a plurality of memory cells of storage arrangement may be highly discrete, therefore, can use the ISPP method, thereby consider the dispersion between the starting voltage in described a plurality of memory cell, all memory cells can have the starting voltage of expectation.
Yet, if starting voltage changes in time, may more be difficult to use the dispersion between the ISPP method control starting voltage, and be not easy the memory cell programming so that starting voltage within the scope of expectation.
When wiping the information of programming, the electronics of injected holes and the location that discharges by electric field or the electronics of non-location can be compound, and the residual hole that is not removed fully and the electronics of location may redistribute.
During the heavily distribution of the compound and electric charge in electronics-hole, the starting voltage of storage arrangement may change, thus effectively the erasing time can be considered to carry out compound and the heavy summation of time of spending of distribution, rather than time of injected hole.
At K.S.Seol et al., disclose among the Phys.Rev.B 62,1532 (2000) and in the silicon nitride layer that uses low-pressure chemical vapor deposition (LPCVD) method to make, carried out the distribution that optical pumping is handled the life span (recombination time) in electronics-hole of measuring afterwards.
Can be distributed in the recombination time in electronics and hole on the very wide scope, for example, from ns to ms.According to the LESR measurement result, can be some 10 recombination time 3Second.
Can use the electronics of equation 1 compute location and the recombination time (τ) in hole.
τ＝τ 0exp(2R/R 0)(τ 0＝10 -8s)----------------------------------------(1)
Wherein, R 0The position length in expression electronics or hole, and satisfy R 0(E)=[h 2/ m (E c-E)] 1/2Or [h 2/ m (E v-E)] 1/2, R represents the distance between the hole of the electronics of locating and location.
Shown in equation 1, R in deep trap 0Can reduce, may increase recombination time in deep trap.
In erasing mode, can as time passes injected holes be stabilized to deep level.
In programming mode or erasing mode, when charge space spread, the variation of starting voltage can be very big, and produce thermalization.When thermalization further promoted, the variation of starting voltage may reduce, yet electric charge may be positioned in darker energy level thereby more be difficult to motion.
Therefore, if compound spending for a long time then possibly can't be moved by thermalization and the electronics or the hole that navigate to deep level according to time of spending, therefore, more be difficult to composite electron and hole.In addition, when the motion in electronics or hole because thermalization and when limited, the thermalization time may increase.
In addition, when recombination time is very long, electric charge may according to time of spending by thermalization, thereby cannot carry out the compound of sufficient hole-electronics.Because incomplete compound, during residual electronics of catching, dispersion may increase in programming operation after carrying out erase operation.
For example, in erasing mode because under the state in the incomplete compound and residual electronics in electronics and hole and hole, even inject with compound fully situation under the residual identical hole of electron amount, it is not exclusively compound that electronics and hole also may quilts, thereby electronics and hole may and be deposited.Even inject the electronics of some in addition, thereby compoundly still may not exclusively still there be the hole.When injecting when carrying out programmed process and using the ISPP method to carry out checking by repeating electronics, residual hole can with electron recombination, and may cause the variation of threshold voltage, therefore, when programming was finished, the dispersion of starting voltage may increase.
As mentioned above, owing to the incomplete existence of the compound opposite charges that causes may in programming operation, cause discrete, only can be by in erasing mode, removing the increase that electronics prevents dispersion fully.
When having opposite charges, carrying out the compound of electronics and hole owing to not exclusively compound in high temperature storage (HTS) operation, therefore, starting voltage may change.
Therefore, when owing to long thermalization time and long recombination time causing incomplete compound tense, the stability of erase status and programming state may reduce, and the dispersion of threshold voltage may reduce in programming or erase operation, and starting voltage may change in the HTS operation.
Summary of the invention
Example embodiment provides a kind of method of operating charge trap flash memory device, its can be by improving electric charge thermalization speed and/or the recombination rate in electronics and hole guarantee stability higher under the program/erase state, with reduce or prevent under programming state or the erase status in the charge trap layer residual opposite charges.
According to example embodiment, provide a kind of operating charge trap memory device to carry out the method for erase operation, described method comprises: the assembled pulse that will comprise direct current (DC) pulse and DC perturbation pulse puts on charge trap memory device to carry out erase operation.
In assembled pulse, DC perturbation pulse can be followed after the DC pulse.
Assembled pulse can comprise the DC pulse and the DC perturbation pulse of alternately arranging repeatedly.
Assembled pulse can comprise the DC pulse of following DC perturbation pulse, and DC perturbation pulse can have the DC level with the polarity opposite polarity of DC pulse.
The amplitude of the DC level in the DC perturbation pulse can be less than the amplitude of DC pulse.
The DC pulse is the basic pulse of erase operation.
Charge trap memory device can comprise: substrate; With suprabasil grid structure, wherein, the grid structure comprises: tunnel insulation layer, charge trap layer, blocking insulation layer and/or grid.
Tunnel insulation layer can be an oxide skin(coating), and the charge trap layer can be a nitride layer, and blocking insulation layer can comprise the high dielectric property material, can form grid by metal level.
Assembled pulse can be put on grid or substrate.
The DC pulse can be put on anodal substrate, and DC perturbation pulse can be put on anodal grid.
The DC pulse can be put on the grid of negative pole, and DC perturbation pulse can be put on anodal grid.
The DC pulse can be put on the substrate of negative pole, and DC perturbation pulse can be put on anodal substrate.
The DC pulse can be put on the grid of negative pole, and DC perturbation pulse can be put on anodal substrate.
But the compound or heavily distribution of DC perturbation pulse accelerated charge.
Can after applying assembled pulse, apply the checking pulse with the checking erase status.
The example embodiment of assembled pulse and method for deleting can put on various nonvolatile memories, for example, and flash memory.The example embodiment of assembled pulse and method for deleting can put on floating-gate memory and/or trap memory.The example embodiment of assembled pulse and method for deleting can put on nand memory and/or NOR storer.
Description of drawings
By the detailed description of reference accompanying drawing to example embodiment, it is clearer that the feature and advantage of example embodiment will become, wherein:
Fig. 1 is to use the cross sectional view of carrying out the charge trap flash memory device of programming operation or erase operation according to the method for example embodiment;
Fig. 2 illustrates the diagrammatic sketch that compares according to the assembled pulse of example embodiment and direct current (DC) pulse according to conventional art;
Fig. 3 to Fig. 5 is the diagrammatic sketch that illustrates according to the assembled pulse of example embodiment;
Fig. 6 is the synoptic diagram that the program voltage when the assembled pulse that uses the ISPP method with Fig. 2 puts on programming is shown;
Fig. 7 is the curve map that the legacy frequencies correlativity of AC conductivity is shown;
Fig. 8 A and Fig. 8 B illustrate under the situation that is not having the AC perturbation in deep trap when electronics is hunted down and can not moves and have electronics under the situation of AC perturbation and the compound example probability between the hole;
Fig. 9 is the diagrammatic sketch that illustrates according to the erasing voltage of example embodiment;
Figure 10 is the diagrammatic sketch that illustrates according to the erasing voltage of conventional art;
Figure 11 is the exemplary graph that the variation of the leakage current (Id) in the memory cell of the charge trap flash memory device when the assembled pulse that uses Fig. 9 is carried out erase operation is shown;
Figure 12 is the exemplary graph that the variation of the leakage current (Id) in the memory cell of the charge trap flash memory device when applying the erase pulse voltage of the Figure 10 that comprises the DC pulse is shown;
Figure 13 is illustrated under the situation that applies the assembled pulse shown in Fig. 9 and applies under the situation of existing erase pulse voltage of the DC pulse that comprises shown in Fig. 10 exemplary graph according to the variation of the leakage current (Id) of the time that spends;
Figure 14, Figure 15 A and Figure 15 B are the diagrammatic sketch that illustrates according to the erasing voltage of example embodiment;
Figure 16 A and Figure 16 B are the diagrammatic sketch that illustrates according to the program voltage of example embodiment;
Figure 17 A and Figure 17 B are the synoptic diagram that the program voltage when the ISPP method of using the program voltage shown in Figure 16 A and Figure 16 B is carried out programming is shown; And
Figure 18 A and Figure 18 B illustrate the example of circuit diagram of the nand flash memory device of usage example embodiment, and wherein, Figure 18 A illustrates the programming operation state, and Figure 18 B illustrates the erase operation state.
Embodiment
Now will be in detail with reference to example embodiment, the example of embodiment is shown in the drawings.Yet, the embodiment that illustrates after example embodiment is not limited thereto, the embodiment that is introduced in this is to provide the simple and complete understanding to the scope and spirit of example embodiment.In the accompanying drawings, for clear, exaggerated the thickness in layer and zone.
Should understand when assembly or layer are called as " on another assembly or layer ", " be connected to another assembly or layer " or " with another assembly or layer coupling ", described assembly or layer can be directly on another assembly or layer, be connected to another assembly or layer, with another assembly or layer coupling or can have intermediate module or layer.On the contrary, when assembly or layer are called as " directly on another assembly or layer ", " be directly connected to another assembly or layer " or " with another assembly or directly coupling of layer ", there are not intermediate module or layer.Identical numeral is indicated identical assembly all the time.As used herein, term " and/or " comprise one or more any one and all combinations in the relevant listed item.
Can use the term first, second, third, etc. to describe various assemblies, element, zone, layer and/or part at this though should understand, these assemblies, element, zone, layer and/or part be not restricted to these terms.These terms only are used for an assembly, element, zone, layer and/or part and other assembly, element, zone, layer or part are distinguished.Therefore, under the situation of the instruction that does not break away from example embodiment, first assembly discussed below, element, zone, layer and/or part can be described as second assembly, element, zone, layer and/or part.
Can this usage space relational language (for example, " and ... under ", " ... following ", " being lower than ", " ... top ", " being higher than " etc.) so that describe as shown in the figure assembly or feature and other assembly or the relation between the feature.Should be understood that the space correlation term is to be used for comprising in the drawings the use outside the orientation of describing or the different azimuth of the device in the work.For example, the assembly that, then is described as " below other assemblies or feature " or " under other assemblies or feature " if the device among the figure is reversed will be positioned at " at other assemblies or above the feature ".Therefore, the term of example " ... following " can comprise up and down two kinds of orientation.Device also can carry out respective explanations in this usage space relevant descriptors towards other directions (revolve turn 90 degrees or towards other directions).
The purpose of term only is to describe specific embodiment rather than restriction example embodiment as used herein.Unless the clear indication of context, otherwise singulative " " and " this " will also comprise plural form as used herein.Will also be understood that, when in this instructions, using term " to comprise " and/or when " comprising ", specify to have feature, integral body, step, operation, assembly and/or the element of mentioning, but do not get rid of existence or increase one or more other features, integral body, step, operation, assembly, element and/or their combination.
As the cross-sectional view of the synoptic diagram of example embodiment (and intermediate structure) example embodiment is described in this reference.Therefore, by for example manufacturing technology and/or deviation and the change of shape that causes with respect to diagrammatic sketch can reckon with.Therefore, example embodiment should not be understood that to be limited to the given shape in the zone shown in this, but comprises the change of shape that is for example caused by manufacturing.For example, will have the implantation concentration of circle or curvilinear characteristic and/or inclination usually at its boundary with the injection region shown in the rectangle (implanted region), rather than from the injection region to the two kinds of variations in non-injection region.Similarly, can cause the zone between the surface of buried region and injection generation to form some injections by injecting the buried region (buried region) that forms.Therefore, the zone of Miao Shuing is actually schematically in the drawings, and their shape is not the true form that the zone of device is shown, and does not limit the scope of example embodiment.
Unless otherwise defined, otherwise as used herein all terms (comprising technical term and scientific terminology) have the identical implication with example embodiment those of ordinary skill in the field common sense.Will also be understood that, term (for example, being included in the term that defines in the normally used dictionary) implication that should be interpreted as having is consistent with their implications in the linguistic context of correlation technique, unless clearly define, should not make an explanation with idealized or too formal implication at this.
Below, describe method with reference to the accompanying drawings in detail according to the operating charge trap flash memory device of example embodiment.
Fig. 1 illustrates the charge trap flash memory device 10 of programming operation or erase operation is carried out in use according to the method for example embodiment cross sectional view.
With reference to Fig. 1, charge trap flash memory device 10 can comprise substrate 11 and the grid structure 20 that is formed in the substrate 11.
First impurity range 13 and second impurity range 15 of conductivity impurity of predetermined or expectation of having mixed can be formed in the substrate 11.One in first impurity range 13 and second impurity range 15 can be used as drain D, and another can be used as source S.
Grid structure 20 can comprise: be formed at suprabasil tunnel insulation layer 21, be formed at the charge trap layer 23 on the tunnel insulation layer 21 and/or be formed at blocking insulation layer 25 on the charge trap layer 23.Grid 27 can be formed on the blocking insulation layer 25.In Fig. 1, label 19 expression light spacer assemblys (spacer).
Tunnel insulation layer 21 is the layers that are used for the tunnelling electric charge, and can be formed in the substrate 11.Tunnel insulation layer 21 can electrically contact with first impurity range 13 and second impurity range 15.Tunnel insulation layer 21 is can be by for example SiO 2, various high k oxide materials or oxide material the tunnel oxide that is combined to form.
In addition, tunnel insulation layer 21 can form silicon nitride layer, for example, and Si 3N 4Can use silicon that silicon nitride layer is formed not have high impurity concentration (that is, the concentration of impurity can be compared with the concentration of the impurity of silicon dioxide layer), and have enough interface property and silicon.In order to form the silicon nitride layer of enough quality, can use such as the method for spraying vapor phase method and form the silicon nitride layer that constitutes tunnel insulation layer 21.
When using said method to form silicon nitride layer, can form the flawless silicon nitride layer (Si that impurity concentration is not higher than the impurity concentration of silicon dioxide layer and has the good interface performance 3N 4).
Perhaps, tunnel insulation layer 21 can form and have the double-decker that comprises silicon nitride layer and oxide skin(coating).
As mentioned above, tunnel insulation layer 21 can form the single layer structure of oxide skin(coating) or nitride layer, perhaps the sandwich construction that is formed by the material with mutually different band gap.
Charge trap layer 23 is zones of coming canned data by charge-trapping.Charge trap layer 23 can form and comprise polysilicon, nitride material, has one or more in the high k dielectric material of high-k and the nano dot.
For example, charge trap layer 23 can be by nitride material (for example, Si 3N 4) or high k oxide material (for example, SiO 2, HfO 2, ZrO 2, Al 2O 3, HfSiON, HfON or HfAlO) form.
In addition, charge trap layer 23 can comprise the discontinuous a plurality of nano dots that are arranged as the charge trap side.Nano dot can form nanocrystal.
Blocking insulation layer 25 is used to stop electric charge by charge trap layer 23 and move to fartherly, and can be formed by oxide skin(coating).
Blocking insulation layer 25 can be by SiO 2Form, perhaps by high k material (for example, Si with specific inductive capacity higher than the specific inductive capacity of tunnel insulation layer 21 3N 4, Al 2O 3, HfO 2, Ta 2O 5Or ZrO 2) form.Blocking insulation layer 25 can form has sandwich construction, and for example, blocking insulation layer 25 can form has two or more layers, comprises by for example SiO 2The insulation course that forms of insulating material and the high dielectric property layer that forms by material with specific inductive capacity higher than the specific inductive capacity of tunnel insulation layer 21.
Grid 27 can form metal level.For example, grid 27 can be by the metallic aluminium (Al), Ru or the TaN that are used as the grid of semiconductor memory system usually, and perhaps silicide material (for example NiSi) forms.
Other SONOS or MONOS feature, for example, " An Embedded 90nm SONOSNonvolatile Memory Utilizing Hot Electron Programming and Uniform TunnelErase (using the embedded 90nm SONOS nonvolatile memory of hot electron programming and even tunnel erase) ", C.T.Swift, et al., (IEDM 2002 for international electronic installation conferencing technology summary, Dec) feature of describing in the 927th page to the 930th page, can be added into or alternative above-mentioned feature, and by reference these disclosed themes be incorporated into fully.
When electronics is injected into the charge trap flash memory device, trap point by the charge trap layer is caught injected electrons, therefore, can carry out programming operation, thereby make voltage that starting voltage becomes programming state (for example, 3V), perhaps the hole is injected into storage arrangement, thus can be by the compound electronics that removes in electronics-hole, therefore, can carry out erase operation, thereby make voltage that starting voltage becomes erase status (for example, 0V).As mentioned above, the memory cell in the flash memory device can have two states, that is, and and programming state and erase status.The ON state is an erase status, and in this state, the starting voltage of memory cell reduces, thereby makes current direction be connected to the drain electrode of bit line by the voltage that puts on grid 27 during reading storage arrangement.The OFF state can be called as programming state, and in this state, the starting voltage of memory cell increases, thereby electric current does not flow to the drain electrode that is connected to bit line during reading storage arrangement.
As mentioned above, the voltage that can apply the assembled pulse that comprises direct current (DC) pulse and perturbation pulse is to carry out programming operation or erase operation, therefore, electric charge during programming operation or erase operation (electronics and/or hole) is thermalization more promptly, and can reduce or prevent electronics-hole not exclusively compound in the erase operation.The perturbation pulse can be AC perturbation pulse or DC perturbation pulse.
When the assembled pulse shown in Fig. 2 to Fig. 5 is put on the charge trap flash memory device, can carry out programming operation or erase operation.
During programming operation, the assembled pulse shown in Fig. 2 to Fig. 5 can be put on grid 27, and substrate 11 can remain unchanged (for example, at 0V).In addition, during erase operation, the assembled pulse shown in Fig. 2 to Fig. 5 can be put on substrate 11, and grid 27 can remain unchanged (for example, 0V).
Therefore, from the angle of grid 27, program voltage is a positive voltage, and erasing voltage is a negative voltage, and except DC segment pulse and perturbation pulsed frequency, the basic pulse structure of voltage is identical.Therefore, the assembled pulse shown in Fig. 2 to Fig. 5 can be put in programming operation and the erase operation commonly.Fig. 2 is illustrated in the assembled pulse that uses in the method according to the operating charge trap flash memory device of example embodiment and compares with DC pulse according to classic method.
As shown in Figure 2, be applied in the voltage that is used to carry out traditional programming operation or traditional erase operation and only comprise the DC pulse component.In programming mode, the DC cycle in burst length that applies the DC pulse can be about 10 μ s, and in erasing mode, can be about 10ms.
On the other hand, the assembled pulse that is used to carry out programming operation or erase operation according to being applied in of example embodiment can comprise DC pulse (programming pulse or erasing pulse) component and perturbation pulse component.
But the compound or value (for example, amplitude and/or duration) predetermined or expectation that heavily distributes, and can have of perturbation pulse component accelerated charge.
In the example embodiment of Fig. 2, the perturbation pulse is AC perturbation pulse.AC perturbation pulse can have the higher frequency of inverse than the DC cycle in burst length.
In Fig. 2, be applied in the DC pulse that the assembled pulse that is used to carry out programming operation or erase operation can comprise predetermined or cycle expected time of following AC perturbation pulse thereafter.
Predetermined or cycle expected time can be corresponding with the DC recurrence interval in tradition programming that only comprises the DC pulse or the erasing voltage.That is to say, only comprise that being applied in of DC pulse component is used to carry out the voltage of traditional programming operation or traditional erase operation, yet the assembled pulse that being applied in of this example embodiment is used to carry out programming or erase operation can comprise: the compound perturbation pulse in the DC pulse corresponding with traditional DC pulse and the thermalization of accelerated charge and/or electric charge and hole.
In the assembled pulse of Fig. 2, the DC recurrence interval can be about 10 μ s in programming mode, can be about 10ms in erasing mode.In example embodiment, in programming mode, AC perturbation pulse component can be the AC pulse that frequency is higher than 1/10 μ s=0.1MHz, and in erasing mode, AC perturbation pulse component can be the AC pulse that frequency is higher than 1/10ms=100Hz.In Fig. 3 to Fig. 5, the perturbation pulse in the assembled pulse also is AC perturbation pulse, and this AC perturbation pulse can be satisfied the frequency range of example embodiment as shown in Figure 2.
Fig. 3 to Fig. 5 illustrates the assembled pulse according to the method for operating charge trap flash memory device according to example embodiment.
With reference to Fig. 3, the assembled pulse of example embodiment can comprise repetition and the DC pulse and the AC perturbation pulse of (N time, wherein, N 〉=2) alternately are provided repeatedly.In Fig. 3, be applied in the assembled pulse that is used to carry out programming operation or erase operation and comprise three pairs of DC pulses and AC perturbation pulse.
With reference to Fig. 4, DC pulse and the AC perturbation pulse that alternately provides repeatedly is provided the assembled pulse of example embodiment, and AC perturbation superimposed pulses has polarity to be same as the polarity of described DC pulse and less than the DC level of DC pulse signal.In Fig. 4, assembled pulse comprises three pairs of DC pulses and DC level+AC perturbation pulse (stack).
With reference to Fig. 5, the assembled pulse of example embodiment can comprise the DC pulse and be superimposed with the AC perturbation pulse of DC pulse.In example embodiment, the DC recurrence interval of voltage can be corresponding with the DC recurrence interval of the conventional voltage that only comprises the DC pulse.
In programming mode, the program voltage that forms assembled pulse (it is in the assembled pulse shown in Fig. 2 to Fig. 5) can be put on the memory cell of charge trap flash memory device, to carry out programming operation.In addition, verifying voltage can be put on memory cell to carry out the program verification operation.
When the ISPP method is used to programme, can repeat to apply program voltage carrying out programming operation and to apply the processing of verifying voltage with the starting voltage of recognition memory primitive, reach programming state up to the starting voltage of memory cell.
In erasing mode, the erasing voltage that forms assembled pulse (it is in the assembled pulse shown in Fig. 2 to Fig. 5) can be put on the memory cell of charge trap flash memory device, to carry out erase operation.In addition, verifying voltage can be put on memory cell so that whether identification has wiped memory cell.
As mentioned above, can apply the checking pulse voltage in case before or after applying assembled pulse voltage Recognition and Programming state or erase status.Prevent that by applying verifying voltage verification operation from being known in the prior art.In addition, as describing afterwards, program voltage can have identical polarity with verifying voltage, and erasing voltage and verifying voltage can have reciprocal polarity.Therefore, in Fig. 2 to Fig. 5, omitted the checking pulse, can generally have been applied as program voltage or erasing voltage so that describe the assembled pulse shown in Fig. 2 to Fig. 5.
In programming operation, can in the amplitude of the DC pulse in increasing the assembled pulse shown in Fig. 2 to Fig. 5 gradually, apply assembled pulse and apply the checking pulse.That is to say, can in the ISPP method of using the assembled pulse shown in Fig. 2 to Fig. 5, carry out programming.
Fig. 6 illustrates the program voltage when having applied the assembled pulse of Fig. 2 in the programming operation that is using the ISPP method.In Fig. 6, Vpgm is illustrated in the amplitude that is used for the DC pulse voltage of programming operation in the programming of ISPP method, and Δ Vpgm represents the increment of DC pulse voltage.As shown in Figure 6, can when increasing the amplitude of (for example, increasing gradually) DC pulse voltage, apply the assembled pulse that comprises DC pulse and AC perturbation pulse, and apply the checking pulse voltage.
When use ISPP method was as shown in Figure 6 carried out programming, the amplitude of AC perturbation pulse can be constant, perhaps can increase according to the increase of DC pulse height.In addition, AC perturbation pulse can be the suitable amplitude in the compound of accelerated charge or the scope that heavily distributes, therefore, the voltage amplitude of checking pulse can with AC perturbation pulsion phase with, also can less than or greater than AC perturbation pulse.
Because the program voltage when the assembled pulse shown in Fig. 3 to Fig. 5 being put on the programming operation that uses the ISPP method is similar to the above-mentioned program voltage about Fig. 2, therefore will omit description to it.
As mentioned above, when use is carried out programming or erase operation with reference to the assembled pulse described in Fig. 2 to Fig. 6, method according to operating charge trap flash memory device, at the iunjected charge (electronics in the programming mode, hole in the erasing mode) afterwards, can electric charge be moved actively by the perturbation that causes by AC perturbation pulse component electric charge, therefore, can reduce the thermalization of execution electric charge and/or the compound required time in electronics and hole.
Can pass through as R.D.Gould and S.A.Awan, Thin Solid Films, relating to the AC perturbation of describing in the document of frequency dependence of AC conductivity in 443,309 (2003) increases thermalization and recombination rate, and the full content of the document is incorporated herein by reference.
Fig. 7 is illustrated in the above-mentioned document disclosed AC conductivity about the exemplary graph of the correlativity of frequency.
As shown in Figure 7, when the AC frequency increased, the AC conductivity increased, and the AC conductivity is in the very large scope of hundreds of Hz to several MHz, that is, and and in the frequency range of the AC perturbation signal that in the programming mode of example embodiment or erasing mode, uses.Owing to the AC conductivity along with frequency increases, therefore when frequency increased, the move distance of electric charge also increased.
Therefore, can pass through AC perturbation pulse component conduct charges, can electric charge be moved actively by the AC perturbation.
AC in insulating material conduction is the conduction that the increase by the mean free path (mean free path) of electric charge causes, rather than with the conduction of the direction of electric charge, that is, and the DC conduction.
Therefore, when AC perturbation pulse was put on the charge trap flash memory device, the electric charge of catching in charge trap layer (for example, forming the nitride material of charge trap layer) moved actively.Therefore, can improve the thermalization speed of electric charge.In addition, can improve the recombination rate in electronics and hole, therefore, can reduce not exclusively compound probability of happening, also can reduce the probability of residual opposite charges polymerization.
In addition, in deep trap, under the captive situation, can pass through AC perturbation dislocation charge easily at electric charge, thereby improve recombination rate.
Fig. 8 A and Fig. 8 B illustrate when electronics and are hunted down in deep trap and are not having can not move the time under the situation of AC perturbation respectively and have electronics under the situation of AC perturbation and the compound probability in hole.
Shown in Fig. 8 A,, be difficult in deep trap, to be hunted down and can not ELECTRON OF MOTION and hole-recombination if there is not the AC perturbation.Yet, shown in Fig. 8 B,, can move captive electronics in deep trap by the AC perturbation if apply the AC perturbation, therefore, with the probability increase of electronics and hole-recombination.In example embodiment, move by the direction that the AC perturbation forms in electric charge random motion rather than edge.Therefore, even there is the AC perturbation, in fact also cannot transfer charge.
In Fig. 2 to Fig. 5, putting on the charge trap flash memory device is AC perturbation pulse with the perturbation pulse that is included in the assembled pulse of carrying out programming operation or erase operation, for example, does not comprise the AC perturbation pulse that has with the DC level of DC pulsion phase reversed polarity.
Shown in Fig. 9, Figure 14, Figure 15 A, Figure 15 B, Figure 16 A and Figure 16 B, be included in perturbation pulse in the assembled pulse of example embodiment and have DC level with DC pulsion phase reversed polarity, so that accelerated charge compound or heavily distribute, this will describe afterwards.That is to say that in programming mode, if the DC pulse is a positive voltage, then the DC level of perturbation pulse can be a negative voltage.In erasing mode, if the DC pulse is a negative voltage, then the DC level of perturbation pulse can be a positive voltage.Below, will the erasing voltage and the program voltage of example embodiment be described separately, wherein, the perturbation pulse has the DC level with the opposite polarity polarity of DC pulse.
Fig. 9 illustrates the erasing voltage according to the method for the operating charge trap flash memory of example embodiment.Figure 10 illustrates according to the erasing voltage of traditional operation method example as a comparison.
With reference to Fig. 9, the erasing voltage of example embodiment is the voltage that comprises the assembled pulse waveform of erasing pulse, that is, and and DC pulse and perturbation pulse.In example embodiment, in assembled pulse, can follow the perturbation pulse after the erasing pulse, the perturbation pulse can have the DC level with the opposite polarity polarity of erasing pulse.That is to say that erasing voltage can comprise the erasing pulse of negative voltage and the perturbation pulse of positive voltage.
In Fig. 9, the perturbation pulse is the DC perturbation pulse that has with the opposite polarity polarity of erasing pulse.
In erasing mode, the DC pulse can put on anodal substrate, and DC perturbation pulse can put on anodal grid.In erasing mode, the DC pulse can put on the grid of negative pole, and DC perturbation pulse can put on anodal grid.In erasing mode, the DC pulse can put on the substrate of negative pole, and DC perturbation pulse can put on anodal substrate.In erasing mode, the DC pulse can put on the grid of negative pole, and DC perturbation pulse can put on anodal substrate.
In erasing mode, can apply the assembled pulse that comprises erasing pulse (DC) and perturbation pulse to carry out erase operation.In addition, whether the checking pulse voltage can put on identification and suitably carried out and wipe.Whether the checking pulse voltage can put on identification and suitably carry out and wipe.The checking pulse voltage has the opposite polarity polarity with erasing pulse.
Example as a comparison, with reference to Figure 10, according to conventional art, apply only comprise the DC pulse erase pulse voltage to carry out erase operation, at the fixed time after, apply the checking pulse voltage and whether suitably carried out with identification and wipe.
Figure 11 illustrates leakage current (Id) in the memory cell of the charge trap flash memory when carrying out erase operation by the assembled pulse that applies Fig. 9 according to the example of the variation of time.Figure 12 illustrate when provide shown in Figure 10 only comprise the erase pulse voltage of DC pulse the time the memory cell of charge trap flash memory device in the example of variation of leakage current (Id).
In the memory cell of charge trap flash memory device, when applying erasing pulse, leakage current increased according to the time that spends, and is then, saturated in predetermined value.Heavily distributing of electric charge may cause the Id transient phenomena that increase leakage current according to the time.Increase according to the leakage current that spends the time means that starting voltage reduces after applying erasing pulse.
As mentioned above, because the motion of the electric charge in the charge trap layer after carrying out program/erase operations, starting voltage (Vth) changed according to the time after carrying out programming operation and erase operation.Therefore, when after erase operation, reading erase verification or erase status, make a mistake, wipe failure owing to the authentication error that produces causes.
When using the classic method shown in Figure 10 to carry out erase operation, as shown in figure 12, saturation time be at least 1 second, therefore, be difficult to more rapidly and/or exactly acquisition wipe decision.
Therefore, must reduce the saturation time of the starting voltage after carrying out erase operation effectively, so that rapider and/or obtain to wipe decision exactly, and minimizing or prevent to wipe failure.
As shown in Figure 9, applying before or after the erasing pulse under the situation about having with the DC perturbation pulse of the opposite polarity polarity of erasing pulse, can quicken the Id transient phenomena, thereby erase status can be saturated in the time of as shown in figure 11 minimizing, therefore, can reduce the saturation time of starting voltage effectively.Figure 11 is illustrated in the change that applies after the erase pulse voltage 10ms leakage current (Id) when the perturbation pulse that has with the opposite polarity polarity of erasing pulse.In Figure 11, leakage current is approaching saturated after 15ms.
Figure 13 illustrate when applying the assembled pulse of Fig. 9 and when apply shown in Figure 10 comprise traditional erase pulse voltage of DC pulse the time the example of variation of leakage current (Id).
As shown in figure 13, when the assembled pulse that applies according to Fig. 9 of example embodiment, can reduce the saturation time (that is the saturation time of starting voltage) of leakage current.Therefore, in erase operation, example embodiment according to the assembled pulse that uses Fig. 9, can carry out and wipe decision more rapidly by after carrying out erase operation, applying the checking pulse voltage, can reduce or prevent in the erase verification operation and the mistake that produces in the erase operation erase status read operation afterwards and cause wipe failure.
In Fig. 9, assembled pulse comprises erasing pulse and has DC perturbation pulse with the opposite polarity polarity of erasing pulse.
In example embodiment, as shown in figure 14, the assembled pulse that is used to carry out erase operation can comprise wipes pulse and a plurality of DC perturbation pulse that has with the opposite polarity polarity of erasing pulse.
In addition, shown in Figure 15 A and Figure 15 B, the assembled pulse of carrying out erase operation from the assembled pulse shown in Fig. 9 and Figure 14 being used to of revising can have erasing pulse and AC perturbation pulse, described AC perturbation pulse and the DC level stack that has with the opposite polarity polarity of erasing pulse.
In programming mode, can apply the perturbation pulse that has with the DC level of the opposite polarity polarity of the DC pulse of describing with reference to Fig. 9 to Figure 15 B.
Figure 16 A and Figure 16 B illustrate corresponding with Fig. 9 and Figure 14 respectively program voltage according to example embodiment.
Shown in Figure 16 A, the assembled pulse that is used to carry out programming operation can comprise the programming pulse (that is, the DC pulse) of following DC perturbation pulse thereafter, and described DC perturbation pulse has the opposite polarity polarity with programming pulse.
In addition, shown in Figure 16 B, the assembled pulse that is used to carry out programming operation can comprise the programming pulse (that is, the DC pulse) of following a plurality of DC perturbation pulses thereafter, and described a plurality of DC perturbation pulses have the opposite polarity polarity with programming pulse.
As another example, the assembled pulse that is used to carry out programming operation can comprise programming pulse and AC perturbation pulse, with corresponding to the erasing voltage shown in Figure 15 A and Figure 15 B, described AC perturbation pulse and the DC level stack that has with the opposite polarity polarity of programming pulse.Can use the erasing voltage characteristic of the program voltage shown in Figure 16 A and Figure 16 B and Figure 15 A and Figure 15 B to release this assembled pulse, therefore, described assembled pulse is not shown in the accompanying drawings.
Figure 17 A and Figure 17 B illustrate the program voltage when using the ISPP method that has adopted the program voltage shown in Figure 16 A and Figure 16 B to carry out programming.Figure 17 A and Figure 17 B are illustrated in the ISPP programmed method and can use example embodiment.In Figure 17 A and Figure 17 B, Vpgm is illustrated in the basic programming pulse voltage in the ISPP programming, and Δ Vpgm is illustrated in the increment of the programming pulse voltage amplitude in the ISPP method.
When the method with the operating charge trap flash memory device of example embodiment is applied to the programming of ISPP type, can apply have predetermined or expectation amplitude programming pulse to carry out programming operation, then, can apply the perturbation pulse to quicken the saturated of starting voltage.In addition, can apply the checking pulse voltage and whether reach programming state with recognition threshold voltage.If starting voltage does not reach programming state, then can increase the amplitude of programming pulse, and can repeat above-mentioned processing by the level of predetermined or expectation.Can repeatedly repeat above-mentioned processing and reach programming state up to starting voltage.
Can be applicable to as shown in figure 18 structure according to the method for the operating charge trap flash memory device of example embodiment with the charge trap flash memory device of NAND type arrangement.
Figure 18 A and Figure 18 B illustrate the example of nand flash memory manipulated or operated apparatus of the method for operating of usage example embodiment, and Figure 18 A illustrates example programming operation state, and Figure 18 B illustrates example erase operation state.
With reference to Figure 18 A and Figure 18 B, NAND charge trap flash memory device comprises a plurality of primitive strings (string).In Figure 18 A and Figure 18 B, two primitive strings 30 and 31 are shown as example.
In the primitive string 30 and 31 each all comprises with adjacent charge trap memory primitive shares source electrode and a plurality of charge trap memory primitive arrays of drain electrode.For example, each the charge trap memory primitive in the primitive string can have the structure shown in Fig. 1.
Ground connection selects transistor (GST), a plurality of memory cell and/or string select transistor (SST) can be connected in series to the primitive string.One end of primitive string can be connected to bit line, and the other end of primitive string can be connected to common source line (CSL).GST can be connected to CSL, and SST can be connected to bit line.
Word line (WL) can be connected to the grid of described a plurality of charge trap memory primitive with the direction of intersecting with the primitive string.In addition, string selection wire (SSL) can be connected to the grid of SST, and ground connection selection wire (GSL) can be connected to the grid of GST.
Data programmed can change according to the voltage of bit line in the charge trap memory primitive.If the voltage of bit line is supply voltage (Vcc), then can forbid programming.On the other hand, if the voltage of bit line is ground voltage (0V), then carry out programming.Figure 18 A illustrates ground voltage (0V) is put on bit line BLn-1, and supply voltage (Vcc) is put on the example of the situation of bit line BLn.
In programming mode, the program voltage (that is, assembled pulse voltage) that is used to carry out programming operation can be put on the word line of selection, for example, WL29.Path voltage (Vpass) can be put on nonoptional word line, for example, WL31, WL30, WL28 ..., WL0.The DC pulse voltage of program voltage (Vpgm, i.e. coincidence impulse) begins to increase with for example 0.5V from for example 16V, and path voltage (Vpass) can for example be 9V.
In the word line WL29 that selects, the charge trap memory primitive (it is applied ground voltage) that is included among the bit line BLn-1 is programmed.In Figure 18 A, charge trap memory primitive A is programmed.With reference to Figure 18 B, in erasing mode, bit line, SSL and GSL float (float), and ground voltage 0V is put on word line WL0-WL31, and the erasing voltage (that is assembled pulse voltage) that will be used to carry out erase operation puts on body (bulk, i.e. substrate).The DC pulse voltage that Figure 18 B illustrates the assembled pulse that is used to carry out erase operation is 20V.
According to example embodiment, in programming operation or erase operation, except the DC pulse, also can apply the perturbation pulse, therefore, electric charge can motion actively in the charge trap layer.Therefore, can improve the thermalization speed of electric charge and/or the recombination velocity of electric charge, can reduce to produce not exclusively compound probability, therefore, can reduce the residual of opposite charges in the charge trap layer.Therefore, can improve the stability of erase status and programming state, can reduce in programming state and erase status, to reduce the probability of the dispersion of starting voltage, and can reduce or prevent the change of threshold voltage in the HTS operation.
The example embodiment of assembled pulse and programming and/or the method for wiping can be applicable to various nonvolatile memories, for example, and flash memory.The example embodiment of assembled pulse and programming and/or the method for wiping can be applicable to floating-gate memory and/or charge trap memory.The example embodiment of assembled pulse and programming and/or the method for wiping can be applicable to nand memory and/or NOR storer.
Though specifically illustrated and described example embodiment, those of ordinary skill in the art will understand, and under the situation of principle of the present invention that does not break away from the claim qualification and spirit, can make various changes to it in form and details.

Claims (16)

1, a kind of operating charge trap memory device is carried out the method for erase operation, and described method comprises:
The assembled pulse that will comprise DC pulse and DC perturbation pulse puts on charge trap memory device, to carry out erase operation.
2, the method for claim 1, wherein in assembled pulse, DC pulse heel is with DC perturbation pulse is arranged.
3, the method for claim 1, wherein assembled pulse comprises the DC pulse and the DC perturbation pulse of alternately arranging repeatedly.
4, the method for claim 1, wherein assembled pulse comprises the DC pulse of following DC perturbation pulse, and described DC perturbation pulse has the DC level, and described DC level has the opposite polarity polarity with the DC pulse.
5, the method for claim 1, wherein the amplitude of the DC level in the DC perturbation pulse less than the amplitude of DC pulse.
6, the method for claim 1, wherein the DC pulse is the basic pulse of erase operation.
7, the method for claim 1, wherein compound or heavily distribution of DC perturbation pulse accelerated charge.
8, the method for claim 1 also comprises:
After assembled pulse, apply the checking pulse, with the checking erase status.
9, the method for claim 1, wherein charge trap memory device is NAND or NOR charge trap memory device.
10, method as claimed in claim 9, wherein, charge trap memory device comprises:
Substrate; With
Suprabasil grid structure,
Wherein, described grid structure comprises tunnel insulation layer, charge trap layer, blocking insulation layer and grid.
11, method as claimed in claim 10, wherein, tunnel insulation layer is an oxide skin(coating), and the charge trap layer is a nitride layer, and blocking insulation layer comprises the high dielectric property material, and grid is formed by metal level.
12, method as claimed in claim 10 wherein, puts on grid or substrate with assembled pulse.
13, method as claimed in claim 10 puts on anodal substrate with the DC pulse, and DC perturbation pulse is put on anodal grid.
14, method as claimed in claim 10 puts on the grid of negative pole with the DC pulse, and DC perturbation pulse is put on anodal grid.
15, method as claimed in claim 10 puts on the substrate of negative pole with the DC pulse, and DC perturbation pulse is put on anodal substrate.
16, method as claimed in claim 10 puts on the substrate of negative pole with the DC pulse, and DC perturbation pulse is put on anodal substrate.
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