CN101383378A - Non-volatile memory of multi-layered nano-crystal floating gate structure - Google Patents
Non-volatile memory of multi-layered nano-crystal floating gate structure Download PDFInfo
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Abstract
The invention discloses a nonvolatile memory with a multi-layer nanocrystal floating gate structure, which belongs to the technical field of the nonvolatile memory. The nonvolatile memory comprises a semiconductor substrate 11 used for supporting the entire nonvolatile memory, a source 9 and a drain 10 which are formed in the semiconductor substrate 11 in a doped way, a channel 12 between the source 9 and the drain 10, a tunneling oxidizing layer 13 positioned on the channel 12, a control oxidizing layer 14 used for controlling oxidation of the multi-layer nanocrystal floating gate structure, a gate electrode 16 positioned on the control oxidizing layer 14 and a multi-layer nanocrystal floating gate structure 15 positioned between the tunneling oxidizing layer 13 and the control oxidizing layer 14 and used as the floating gate storage unit of the nonvolatile memory. The invention also discloses a method for preparing the nonvolatile memory with the multi-layer nanocrystal floating gate structure. The invention solve the contradiction between the programming time/voltage of the single-layer nanocrystal floating gate memory and the storage time, and increases the storage time of the element under the precondition of shorter programming time.
Description
Technical field
The present invention relates to the technical field of non-volatile in the integrated circuit, relate in particular to non-volatility memorizer of the brilliant floating gate structure of a kind of multi-layer nano and preparation method thereof.
Background technology
In recent years, the growth rate of memory has surpassed logical circuit in the integrated circuit, the ratio that memory accounts for chip area by 1999 20% increase to 2005 71%, logical circuit then by 1999 66% drop to 2005 16%.
In memory product, the market demand is fastest-rising to be nonvolatile memory.Flash memory (FlashMemory) has been widely used in the multiple hand-held mobile storage electronic products such as USB flash disk, MP3 player and mobile phone at present as the typical device of non-volatility memorizer.Yet at present extensively by flash memory device structure that industrial quarters adopted in the nanometer feature sizes development, be faced with stern challenge at aspects such as memory time and power consumptions.
And be a kind of discrete memory mechanism based on the non-volatility memorizer of nanocrystalline floating gate structure, electric charge is stored in independently on the nanocrystal, is separated by dielectric layer between the nanocrystal.Therefore, avoided having strengthened the electric charge hold facility because the defective on the tunnel layer causes the situation of entire device dropout.
Fig. 1 is the schematic cross-section of conventional nanocrystalline floating gate memory.With reference to Fig. 1, conventional nanocrystalline floating gate memory comprises P type semiconductor substrate 3, the n type source electrode 1 and the drain electrode 2 of in semiconductor silicon substrate 3, mixing and forming, be raceway groove 4 between the source-drain electrode, raceway groove top growth tunnel oxide 5, nanocrystal 6 is deposited on the tunnel oxide, covers then with controlled oxidation layer 7 and grid 8.
In such nanocrystalline floating gate memory, thereby the electric charge direct Tunneling is injected the change that nanocrystal causes device threshold voltage.Yet at present the charge storage time of nanocrystal memory, memory window does not also reach the demand of industrial production, is badly in need of the appearance based on the new construction nanocrystalline floating gate memory.
Summary of the invention
(1) technical problem that will solve
In view of this, one object of the present invention is to provide the non-volatility memorizer of the brilliant floating gate structure of a kind of multi-layer nano, to solve the programming time (or voltage) and the contradiction between memory time of individual layer nanocrystalline floating gate memory, the memory time of boost device under short programming time prerequisite.
Another object of the present invention is to provide a kind of method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano, can solve the programming time (or voltage) of individual layer nanocrystalline floating gate memory and the non-volatility memorizer of the contradiction between memory time with preparation.
(2) technical scheme
For reaching an above-mentioned purpose, the invention provides the non-volatility memorizer of the brilliant floating gate structure of a kind of multi-layer nano, this non-volatility memorizer comprises:
Be used to support the Semiconductor substrate 11 of whole non-volatility memorizer;
In Semiconductor substrate 11, mix and form source electrode 9 and drain electrode 10;
At source electrode 9 and the raceway groove 12 between 10 of draining;
Be positioned at the tunnel oxide 13 on the raceway groove 12;
Be used to control the controlled oxidation layer 14 of the brilliant floating gate structure oxidation of multi-layer nano;
Be positioned at the gate electrode 16 on the controlled oxidation layer 14;
It is characterized in that this non-volatility memorizer further comprises:
The brilliant floating gate structure 15 of multi-layer nano between tunnel oxide 13 and controlled oxidation layer 14 is used for the floating gate memory cell as non-volatility memorizer.
In the such scheme, the brilliant floating gate structure 15 of described multi-layer nano is the sandwich construction that nanocrystalline granulosa and oxide layer are formed by stacking successively alternately.
In the such scheme, described Semiconductor substrate is the P type semiconductor silicon substrate, or is the N type semiconductor silicon substrate.
In the such scheme, described nanocrystalline be metal nano-crystalline particle, or be semiconductor nano crystal grain, or the nano heterogeneous crystal grain that forms for different materials.
In the such scheme, described metal nano-crystalline particle is the nanocrystal that W, Ti, Ni, Au, Co or Pt material form, described semiconductor nano crystal grain is the nanocrystal that silicon, germanium or cadmium sulfide material form, and the nano heterogeneous crystal grain that described different materials forms is the nano heterogeneous crystal grain of germanium/silicon.
For reaching above-mentioned another purpose, the invention provides a kind of method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano, this method comprises:
Mixing in Semiconductor substrate forms source electrode and drain electrode, forms raceway groove between source electrode and drain electrode, and the raceway groove top forms tunnel oxide;
Preparation one deck nano-crystalline granule on tunnel oxide, on nano-crystalline granule, cover then with the layer of oxide layer film, then on the oxide layer film, prepare one deck nano-crystalline granule again, equally also on nano-crystalline granule, cover with the layer of oxide layer film, one deck nano-crystalline granule one deck sull superposes alternately successively, forms the brilliant floating gate structure of multi-layer nano;
On the brilliant floating gate structure of the multi-layer nano that forms, cover one deck controlled oxidation layer and one deck gate electrode successively at last.
In the such scheme, described Semiconductor substrate is the P type semiconductor silicon substrate, and source electrode that described doping forms and drain electrode are the source electrode and the drain electrode of N type.
In the such scheme, described nano-crystalline granule is the metallic nano crystal particle, and described one deck nano-crystalline granule for preparing on tunnel oxide adopts electron beam evaporation and rapid thermal annealing process combined to carry out.
In the such scheme, described metallic nano crystal particle diameter is between 5nm to 10nm, and surface density is 10
10Cm
-2
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano provided by the invention, adopt the multi-layer nano crystal structure to substitute traditional individual layer nanocrystalline structure as floating gate memory cell, under fixing cellar area, effectively raise the quantity of nanocrystal, thereby under same operating voltage, increase the memory window of device; And, owing to the influence of coulomb blockade effect, reduced the leakage current of device, promoted the memory time of device, solved the programming time (or voltage) and the contradiction between memory time of nanocrystal floating-gate memory.
2, utilize the present invention,, thereby can under same area, improve the memory space of electric charge, increase memory window greatly, make the memory of floating gate structure can realize that high density is integrated because the multilayer potential barrier of using the multi-layer nano crystal structure is as floating gate memory cell.
3, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano provided by the invention has manufacture craft simple and flexible, low, the plurality of advantages such as the programming time is short, memory window is big, memory time is long, integration density height of read-write voltage.
Description of drawings
Fig. 1 is the schematic cross-section of conventional nanocrystalline floating gate memory;
Fig. 2 is the structural representation of the brilliant floating gate structure non-volatility memorizer of multi-layer nano provided by the invention;
Fig. 3 for provided by the invention have a brilliant floating gate structure non-volatility memorizer of multi-layer nano can be with schematic diagram.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 2, Fig. 2 is the structural representation of the brilliant floating gate structure non-volatility memorizer of multi-layer nano provided by the invention, and this non-volatility memorizer comprises: the Semiconductor substrate 11 that is used to support whole non-volatility memorizer; In Semiconductor substrate 11, mix and form source electrode 9 and drain electrode 10; At source electrode 9 and the raceway groove 12 between 10 of draining; Be positioned at the tunnel oxide 13 on the raceway groove 12; Be used to control the controlled oxidation layer 14 of the brilliant floating gate structure oxidation of multi-layer nano; The brilliant floating gate structure 15 of multi-layer nano between tunnel oxide 13 and controlled oxidation layer 14; Be positioned at the gate electrode 16 on the controlled oxidation layer 14.Wherein, the brilliant floating gate structure 15 of described multi-layer nano is as the floating gate memory cell of non-volatility memorizer.
The brilliant floating gate structure 15 of above-mentioned multi-layer nano is the sandwich construction that nanocrystalline granulosa and oxide layer are formed by stacking successively alternately.
Above-mentioned Semiconductor substrate is the P type semiconductor silicon substrate, or is the N type semiconductor silicon substrate.
Above-mentioned nanocrystalline be metal nano-crystalline particle, or be semiconductor nano crystal grain, or the nano heterogeneous crystal grain that forms for different materials.When nanocrystalline when being metal nano-crystalline particle, the nanocrystal that can select for use W, Ti, Ni, Au, Co or Pt material to form; When nanocrystalline when being semiconductor nano crystal grain, the nanocrystal that can select for use silicon, germanium or cadmium sulfide material to form; When the nanocrystalline nano heterogeneous crystal grain that forms for different materials, can select the nano heterogeneous crystal grain of germanium/silicon for use.
Refer again to Fig. 2, the brilliant floating gate structure 15 of multi-layer nano is embedded between tunnel oxide 13 and the controlled oxidation layer 14, places the top of raceway groove 12, the below of control grid 16.9,10 be respectively source electrode and drain electrode, 11 is substrate.Add one deck tunnel oxide by one deck nanocrystal and pile the brilliant floating gate structure of the multi-layer nano that falls successively, under fixing unit are, effectively raise the quantity of nanocrystal, solved because nanocrystalline surface density improves the problem of the reduction of the difficult memory property of bringing, effectively increased memory window, and because the influence of coulomb blockade effect, make leakage current obviously reduce, reduced requirement to the tunnel oxide layer defects, and then the further attenuate of tunnel oxide, memory density can further improve.Owing to the obvious reduction of leakage current, extend the memory time of device greatly simultaneously.
As shown in Figure 3, after adding suitable voltage on the control grid 16B, the electric charge direct Tunneling among the raceway groove 12B is crossed tunnel oxide 13B, crosses potential barrier among the brilliant floating gate structure 15B of multi-layer nano and is stored in the potential well material among the 15B.At first, therefore under same area, can store more electric charge, thereby improve the memory window of device owing to have a plurality of potential wells among the brilliant floating gate structure 15B of multi-layer nano.Next is stored in electronics in the 15B potential well and wants tunnelling to cross the multilayer potential barrier just to get back among the raceway groove 12B, and because the influence of coulomb blockade effect, is stored in the probability that electron tunneling in the 15B potential well returns raceway groove 12B and reduces greatly, thereby make significantly increase memory time.
Non-volatility memorizer based on the brilliant floating gate structure of multi-layer nano shown in Figure 2, below introduce in detail the method that prepare multi-layer nano crystalline substance floating gate structure non-volatility memorizer, this method comprises: mixing in Semiconductor substrate forms source electrode and drain electrode, form raceway groove between source electrode and drain electrode, the raceway groove top forms tunnel oxide; Preparation one deck nano-crystalline granule on tunnel oxide, on nano-crystalline granule, cover then with the layer of oxide layer film, then on the oxide layer film, prepare one deck nano-crystalline granule again, equally also on nano-crystalline granule, cover with the layer of oxide layer film, one deck nano-crystalline granule one deck sull superposes alternately successively, forms the brilliant floating gate structure of multi-layer nano; On the brilliant floating gate structure of the multi-layer nano that forms, cover one deck controlled oxidation layer and one deck gate electrode successively at last.
Referring again to Fig. 2, prepare the method for the brilliant floating gate structure non-volatility memorizer of multi-layer nano below in conjunction with the specific embodiment introduction.Non-volatility memorizer with multiple layer metal nanocrystalline floating gate structure provided by the invention comprises P type semiconductor silicon substrate 11, in the semiconductor silicon substrate, mix and form n type source electrode 9 and drain electrode 10, be raceway groove 12 between the source-drain electrode, the raceway groove top is a tunnel oxide 13.Applying electronic beam evaporation and rapid thermal annealing process combined, the preparation layer of metal is nanocrystalline on tunnel oxide, and the metallic nano crystal particle diameter is between 5nm to 10nm, and surface density is 10
10Cm
-2More than, cover then with one deck compact oxide film, then use the same method again and prepare the layer of metal nano-crystalline granule thereon, equally also cover the sull of one deck densification, layer of metal nano-crystalline granule one deck dense oxide film superposes alternately successively, forms multiple layer metal nanocrystalline floating gate structure 15.Cover at last with controlled oxidation layer 14 and gate electrode 16, finish the preparation of the non-volatile shape memory of multiple layer metal nanocrystalline floating gate structure.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, the non-volatility memorizer of the brilliant floating gate structure of a kind of multi-layer nano, this non-volatility memorizer comprises:
Be used to support the Semiconductor substrate (11) of whole non-volatility memorizer;
In Semiconductor substrate (11), mix and form source electrode (9) and drain electrode (10);
Raceway groove (12) between source electrode (9) and drain electrode (10);
Be positioned at the tunnel oxide (13) on the raceway groove (12);
Be used to control the controlled oxidation layer (14) of the brilliant floating gate structure oxidation of multi-layer nano;
Be positioned at the gate electrode (16) on the controlled oxidation layer (14);
It is characterized in that this non-volatility memorizer further comprises:
Be positioned at the brilliant floating gate structure (15) of multi-layer nano between tunnel oxide (13) and the controlled oxidation layer (14), be used for floating gate memory cell as non-volatility memorizer.
2, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano according to claim 1 is characterized in that, the brilliant floating gate structure of described multi-layer nano (15) is the sandwich construction that nanocrystalline granulosa and oxide layer are formed by stacking successively alternately.
3, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano according to claim 1 is characterized in that described Semiconductor substrate is the P type semiconductor silicon substrate, or is the N type semiconductor silicon substrate.
4, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano according to claim 1 is characterized in that, described nanocrystalline be metal nano-crystalline particle, or be semiconductor nano crystal grain, or be the nano heterogeneous crystal grain of different materials formation.
5, the non-volatility memorizer of the brilliant floating gate structure of multi-layer nano according to claim 4, it is characterized in that, described metal nano-crystalline particle is the nanocrystal that W, Ti, Ni, Au, Co or Pt material form, described semiconductor nano crystal grain is the nanocrystal that silicon, germanium or cadmium sulfide material form, and the nano heterogeneous crystal grain that described different materials forms is the nano heterogeneous crystal grain of germanium/silicon.
6, a kind of method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano is characterized in that this method comprises:
Mixing in Semiconductor substrate forms source electrode and drain electrode, forms raceway groove between source electrode and drain electrode, and the raceway groove top forms tunnel oxide;
Preparation one deck nano-crystalline granule on tunnel oxide, on nano-crystalline granule, cover then with the layer of oxide layer film, then on the oxide layer film, prepare one deck nano-crystalline granule again, equally also on nano-crystalline granule, cover with the layer of oxide layer film, one deck nano-crystalline granule one deck sull superposes alternately successively, forms the brilliant floating gate structure of multi-layer nano;
On the brilliant floating gate structure of the multi-layer nano that forms, cover one deck controlled oxidation layer and one deck gate electrode successively at last.
7, the method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano according to claim 6 is characterized in that described Semiconductor substrate is the P type semiconductor silicon substrate, and source electrode that described doping forms and drain electrode are the source electrode and the drain electrode of N type.
8, the method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano according to claim 6, it is characterized in that, described nano-crystalline granule is the metallic nano crystal particle, and described one deck nano-crystalline granule for preparing on tunnel oxide adopts electron beam evaporation and rapid thermal annealing process combined to carry out.
9, the method for preparing the brilliant floating gate structure non-volatility memorizer of multi-layer nano according to claim 8 is characterized in that described metallic nano crystal particle diameter is between 5nm to 10nm, and surface density is 10
10Cm
-2
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800198A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing crystalline silicon memory |
| CN103066074A (en) * | 2011-10-21 | 2013-04-24 | 华东师范大学 | Double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with double layer dielectric charge trapping layer and preparation method thereof |
| CN107567583A (en) * | 2015-07-29 | 2018-01-09 | 惠普发展公司，有限责任合伙企业 | The luminous electric field generation base of surface enhanced |
| CN110634875A (en) * | 2019-09-24 | 2019-12-31 | 上海华力微电子有限公司 | Memory cell, NAND flash memory architecture and forming method thereof |
| CN111834393A (en) * | 2019-04-22 | 2020-10-27 | 中国科学院金属研究所 | Flexible carbon nanotube photoelectric memory based on aluminum nanocrystalline floating gate |
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2007
- 2007-09-05 CN CNA2007101213679A patent/CN101383378A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800198A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Method for manufacturing crystalline silicon memory |
| CN101800198B (en) * | 2010-03-12 | 2013-08-14 | 上海宏力半导体制造有限公司 | Method for manufacturing crystalline silicon memory |
| CN103066074A (en) * | 2011-10-21 | 2013-04-24 | 华东师范大学 | Double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with double layer dielectric charge trapping layer and preparation method thereof |
| CN107567583A (en) * | 2015-07-29 | 2018-01-09 | 惠普发展公司，有限责任合伙企业 | The luminous electric field generation base of surface enhanced |
| US10444151B2 (en) | 2015-07-29 | 2019-10-15 | Hewlett-Packard Development Company, L.P. | Surface enhanced luminescence electric field generating base |
| CN111834393A (en) * | 2019-04-22 | 2020-10-27 | 中国科学院金属研究所 | Flexible carbon nanotube photoelectric memory based on aluminum nanocrystalline floating gate |
| CN111834393B (en) * | 2019-04-22 | 2022-12-02 | 辽宁冷芯半导体科技有限公司 | Flexible carbon nanotube photoelectric memory based on aluminum nanocrystalline floating gate |
| CN110634875A (en) * | 2019-09-24 | 2019-12-31 | 上海华力微电子有限公司 | Memory cell, NAND flash memory architecture and forming method thereof |
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