CN103066074A - Double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with double layer dielectric charge trapping layer and preparation method thereof - Google Patents
Double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with double layer dielectric charge trapping layer and preparation method thereof Download PDFInfo
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- CN103066074A CN103066074A CN2011103228938A CN201110322893A CN103066074A CN 103066074 A CN103066074 A CN 103066074A CN 2011103228938 A CN2011103228938 A CN 2011103228938A CN 201110322893 A CN201110322893 A CN 201110322893A CN 103066074 A CN103066074 A CN 103066074A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000002360 preparation method Methods 0.000 title claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 title abstract 2
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002131 composite material Substances 0.000 claims abstract description 4
- 230000015654 memory Effects 0.000 claims description 63
- 238000003475 lamination Methods 0.000 claims description 17
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 239000000203 mixture Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 26
- 230000005641 tunneling Effects 0.000 abstract 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 16
- 239000002800 charge carrier Substances 0.000 description 15
- 230000014759 maintenance of location Effects 0.000 description 13
- 238000003860 storage Methods 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000007667 floating Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 3
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- 230000002950 deficient Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
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- 238000000151 deposition Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 229910052682 stishovite Inorganic materials 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
The invention relates to the field of semiconductor charge capture memorizers, and discloses a nonvolatile double capture-silicon oxide nitride oxide semiconductor (SONOS) memorizer with a double layer dielectric charge capture layer. The nonvolatile DC-SONOS memorizer with the double layer dielectric charge trapping layer comprises a semiconductor substrate of a channel which is provided with a channel surface, a source terminal adjacent to the channel and a drain terminal adjacent to the channel, a grid electrode, a dielectric stack arranged between the grid electrode and the channel surface, and side walls arranged at two sides of the grid electrode and two sides of the dielectric stack. The dielectric stack comprises a tunneling layer contacted with the surface of the channel, a charge capture layer superimposed on the tunneling layer, the charge capture layer is of a double layer dielectric composite structure, a barrier layer superimposed on the charge capture layer, and the barrier layer is contacted with the grid electrode. The charge capture layer comprises a first layer dielectric contacted with the tunneling layer, wherein the first layer dielectric is made of Si3N4, the thickness of the first layer dielectric is 1-30, a second layer dielectric adjacent to the first layer dielectric, wherein the second layer dielectric is made of SiN, and the thickness of the second layer dielectric is 1-50. According to the DC-SONOS memorizer with the double layer dielectric charge capture layer, performance of traditional SONOS nonvolatile memorizers is improved, data-hold feature of the memorizer is improved, and the memorizer which is capable of keeping high data-hold feature under poor operating conditions is easy to obtain.
Description
Technical field
The present invention relates to semiconductor electric charge capturing memory field, relate in particular to a kind of DC-SONOS memory and preparation method thereof that the double-layer electric dielectric charge is caught layer that has.
Background technology
In the semiconductor memory field, flash memory is a kind of in the non-volatile memory technologies, conventional flash memory utilizes floating grid as charge storage elements, but the development along with flash memory technology, storage density constantly increases, and the distance between the floating grid reduces, and can produce between the stored charge of adjacent floating grid to influence each other, for the floating gate flash memory technology, this has just hindered the increase of storage density.And SONOS (silicon one silicon dioxide one silicon nitride one silicon dioxide one silicon) memory adopts the electric charge capture layer of insulation to replace floating grid, avoided influencing each other between the stored charge fully, simultaneously it is also with its unique ONO structure so that flash memory has good stability, the high and low power consumption of reliability, Radiation hardness is strong and easily and the characteristics such as standard CMOS process compatibility be considered to the high-density storage technology of tool potentiality.In addition, compare with other embedded non-volatile memories (NVM) technology, the required mask of SONOS preparation technology is less, has higher cost performance; This technology has also been inherited the achievement of flash memory technology accumulation decades, have good reliability, integrated level is high and with the characteristics of substrate CMOS process compatible; The technology such as the particularity of its ONO structure of while and discrete charge storage are so that the memory cell that the SONOS technology can realize and unfailing performance improve constantly.
Figure 1A is depicted as the cross sectional representation of the SONOS type nonvolatile memory of prior art.Its structure comprises substrate 1, source drain terminal 2, grid 3, the dielectric lamination 4 between grid and substrate, and abutment wall 5.Wherein, be respectively electric charge barrier layer (SiO from top to bottom in the dielectric lamination 4 of memory as shown in Figure 1B
2) 4-1, electric charge capture layer (Si
3N
4) 4-2, tunnel layer (SiO
2) 4-3.
Existing " SONOS " type memory refers to that electric charge capture layer is the nonvolatile memory device of Single Medium and single structure, and the structure of memory is followed successively by silicon substrate, silicon dioxide tunnel layer, silicon nitride charge storage layer (electric charge capture layer), silicon dioxide electric charge barrier layer and grid from top to bottom.At room temperature, the electric charge of traditional SONOS memory is lost and is mainly circulated in the defective of introducing in the tunnel layer silicon dioxide by P/E and cause; Along with the rising of working temperature, the impact of this factor descends gradually, the principal element that the electric charge that pile up in the hole vertical transport in the electric charge capture layer silicon nitride and hole becomes traditional SONOS memory is lost.Under high temperature (more than or equal to 250 degrees centigrade) adverse circumstances, there is the particular storage device that data is being maintained high requirement.Tradition SONOS device can't provide enough data retentions because of its single charge-trapping layer structures.
The electric charge capture layer that the present invention has overcome prior art is the limitation of single structure, a kind of DC-SONOS memory that the double-layer electric dielectric charge is caught layer that has has been proposed, improve the data retention characteristics of memory by changing device architecture, be conducive to obtain more still to keep in condition of work the SONOS nonvolatile memory of higher data retention performance.Simultaneously, the two-layer electric charge capture layer of memory of the present invention prepares by LPCVD and two kinds of methods of PECVD respectively, and the silicon nitride of lower floor uses the deposit of LPCVD technique to form, and film quality is high, can improve erasable speed and the anti-erasable ability of device; The silicon nitride on upper strata uses the pecvd process deposit to form, and defect concentration increases, and is conducive to catching of electric charge; Therefore improved the performance of DC-SONOS type nonvolatile memory of the present invention.
Summary of the invention
The present invention proposes a kind of DC-SONOS memory that the double-layer electric dielectric charge is caught layer that has, comprising:
Semiconductor substrate comprises the raceway groove with channel surface, and source and the drain terminal contiguous with described raceway groove;
Grid;
Dielectric lamination between described grid and described channel surface; And
Be positioned at the abutment wall of described grid and dielectric lamination both sides;
Wherein, described dielectric lamination comprises:
Tunnel layer contacts with described channel surface;
Be superimposed on the electric charge capture layer of described tunnel layer top; Described electric charge capture layer is double-deck dielectric composite construction;
Be superimposed on the barrier layer of described electric charge capture layer top, with described gate contact.
Wherein, described electric charge capture layer comprises:
The ground floor dielectric that contacts with described tunnel layer, its composition are Si
3N
4, thickness is 1-30;
The second layer dielectric of contiguous described ground floor, its composition is SiN, thickness is 1-50.
The invention allows for a kind of preparation method of described DC-SONOS memory, dry-oxygen oxidation forms described tunnel layer above described Semiconductor substrate, form described electric charge capture layer in described tunnel layer top again, adopt LPCVD technique to form the barrier layer in described electric charge capture layer top, adopt again LPCVD technique above described barrier layer, to form grid, form abutment wall in described grid both sides, last autoregistration Implantation forms source and drain terminal.Wherein, the ground floor dielectric adopts pecvd process deposit under 300-500 ℃ of temperature to be prepared from the electric charge capture layer, and second layer dielectric adopts the deposit under 500-900 ℃ of temperature of LPCVD technique to be prepared from.
The present invention " DC-SONOS " refers to Double Capture-SONOS type memory, is with the memory of two-layered medium structure " silicon nitride-silicon nitride " as electric charge capture layer.
The present invention has proposed a kind of DC-SONOS memory that the double-layer electric dielectric charge is caught layer that has on the basis of existing SONOS type nonvolatile memory device structure.The present invention not only catches layer to the double-layer electric dielectric charge and adopts different manufacturing process, can also obtain better data retention characteristics, so that device can be worked under the rugged environment condition.Simultaneously, in traditional SONOS memory, after its silicon nitride charge-trapping layer thickness is less than 7nm, its data retention characteristic and to the capture ability of charge carrier reducing and reduce with the charge-trapping layer thickness all, when silicon nitride charge-trapping layer thickness drops to about 3nm, its data retention characteristic and almost can ignore the capture rate of charge carrier.The present invention is by adopting the double-layer electric dielectric charge to catch layer, improved the memory data retention characteristic and to the capture ability of charge carrier.
The present invention has proposed the improvement technology for charge-trapping layer structures on the basis of SONOS type nonvolatile memory device structure, namely have the DC-SONOS nonvolatile memory of double-layer electric dielectric charge trapping layer structures.Compared with prior art, the present invention have the double-layer electric dielectric charge catch the layer the DC-SONOS memory overcome traditional SONOS memory in adverse circumstances work hours such as high temperature the problem according to the retention performance deficiency.Only adopted the LPCVD method in the preparation of tradition SONOS device electric charge capture layer, has the compound electric charge arresting structure of double-layer electric medium, two-layer electric charge capture layer prepares by LPCVD and two kinds of methods of PECVD respectively, the silicon nitride of lower floor uses the LPCVD deposit to form, film quality is high, can improve erasable speed and the anti-erasable ability of device; And the silicon nitride on upper strata uses the PECVD deposit to form, and defect concentration increases, and is conducive to catching of electric charge; Therefore improved the performance of DC-SONOS type nonvolatile memory of the present invention.Simultaneously, there is more defective in the interface in the compound electric charge capture layer of the present invention between the two-layer silicon nitride, is conducive to the more storage of multi-charge, suppresses simultaneously the vertical transport in hole under the high temperature, can slow down charge leakage, improves the data retention characteristics of device.
Description of drawings
Figure 1A is the cross sectional representation of traditional SONOS type nonvolatile memory.
Figure 1B is the enlarged diagram of traditional SONOS type nonvolatile memory dielectric lamination.
Fig. 2 is that the present invention has the DC-SONOS memory that the double-layer electric dielectric charge is caught layer.Wherein, Fig. 2 A is the cross sectional representation of memory of the present invention, and Fig. 2 B is the enlarged diagram of memory dielectric lamination of the present invention.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail, and protection content of the present invention is not limited to following examples.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included in the present invention, and take appending claims as protection range.
As shown in Figure 2, the 1-Semiconductor substrate, 2-source and drain terminal, 3-grid, 5-abutment wall, the dielectric lamination of 6-DC-SONOS type of the present invention memory, barrier layer in the 6-1 dielectric lamination, the compound electric charge capture layer in the 6-2 dielectric lamination, the ground floor dielectric in the compound electric charge capture layer of 6-2a, second layer dielectric in the compound electric charge capture layer of 6-2b, the tunnel layer in the 6-3 dielectric lamination.
As shown in Figure 2, the present invention has the DC-SONOS memory that the double-layer electric dielectric charge is caught layer, comprising: Semiconductor substrate 1, the raceway groove that has channel surface on it, and source and the drain terminal 2 contiguous with described raceway groove; Grid 3; Dielectric lamination 6 between grid 3 and channel surface; And a pair of abutment wall 5 that lays respectively at grid 3 and dielectric lamination 6 both sides, abutment wall 5 is connected with source 2, drain terminal 2.
Wherein, dielectric lamination comprises: tunnel layer 6-3 contacts with channel surface; Be superimposed on the electric charge capture layer 6-2 of tunnel layer 6-3 top; Electric charge capture layer 6-2 is double-deck dielectric composite construction; Be superimposed on the barrier layer 6-1 of electric charge capture layer 6-2 top, contact with described grid 3.
Wherein, electric charge capture layer 6-2 comprises: the ground floor dielectric 6-2a that contacts with tunnel layer, its composition is Si
3N
4, thickness is 1-30; The second layer dielectric 6-2b of adjacent first layer, its composition is SiN, thickness is 1-50.
Compare with traditional SONOS type nonvolatile memory, the present invention has the double-layer electric dielectric charge and catches the novel part of DC-SONOS memory of layer and be compound electric charge capture layer 6-2.Used simple Si3N4 in the tradition SONOS type nonvolatile memory device structure, and novel structure SONOS type nonvolatile memory device provided by the invention has used the electric charge capture layer of the two-layer compound medium of Si3N4 and SiN.
Embodiment 1:
Present embodiment provides a kind of concrete preparation method of memory of the present invention.
DC-SONOS memory of the present invention in actual use, when bias voltage is arranged, charge carrier is injected into the silicon nitride layer through the silicon dioxide tunnel layer from silicon substrate, wherein charge carrier is at first caught by formed surface trap between tunnel layer silicon dioxide and the electric charge capture layer silicon nitride, and then with remaining carrier injection in electric charge capture layer, because the quantity of the trapped charge in the electric charge capture layer is more, most charge carrier all is stored in the electric charge capture layer, and the charge carrier that surface trap is caught almost can be ignored.In the compound electric charge arresting structure of the double-layer electric medium of DC-SONOS memory of the present invention, the silicon nitride of lower floor uses the LPCVD deposit to form, and film quality is high, can improve erasable speed and the anti-erasable ability of device; And the Si on upper strata
3N
4Silicon nitride uses the PECVD deposit to form, the PECVD technology is temperature required lower when making silicon nitride, thickness is unrestricted, also may contain a small amount of hydrogen impurity in the silicon nitride, the stoichiometric(al) of silicon nitride can be not desirable as the result of LPCVD yet, therefore defect concentration increases, and is conducive to catching of electric charge; Simultaneously, compare with individual layer silicon nitride in the legacy memory, there is more defective in the interface among the present invention between the two-layer silicon nitride, and this has just increased the storage capacity of capture ability and the charge carrier of charge carrier greatly.During no-bias, charge carrier is difficult to cross the barrier height of silicon dioxide tunnel layer, the auxiliary tunnelling of trap becomes main leakage mechanisms, the most of shallow surface traps of trap of the auxiliary tunnelling of trap, and the trap that two-layer silicon nitride is introduced all is deep trap, and the auxiliary tunnelling of the trap of charge carrier is very difficult, has suppressed the vertical transport of high temperature download stream, can slow down charge leakage, improve the data retention characteristics of device.
Compare with traditional SONOS type nonvolatile memory, the present invention has the double-layer electric dielectric charge and catches layer, and this structure has increased effective trap density, and its trap number has improved about 5 times, the memory space of charge carrier has also increased by 3 times, and action pane has also increased about 1V.For traditional SONOS memory, action pane just can work greater than 0.5V, therefore the 1V action pane that has increased has improved the memory data retention characteristic widely, memory of the present invention also has the data holding ability above 10 years under 120 ℃ of extremely abominable hot environments, simultaneously because the increase of charge carrier memory space, the charge carrier of losing is on a small quantity compared fully and can be ignored with total charge carrier of storing, and the job stability of memory of the present invention and the anti-erasable ability memory of the present invention that all increases can be applicable to some memory performance is required in the very high field.For traditional SONOS type nonvolatile memory, although the silicon nitride charge storage has more satisfactory charge-trapping ability when depositing thickness greater than 7nm, but its charge-trapping ability sharply descends when its thickness constantly reduces, the data retention characteristic is also very low, and its charge-trapping ability and data reserve capability almost can be ignored when its thickness drops to the 3nm left and right sides.And the while is along with the development of microelectric technique, chip integration must improve constantly, the horizontal and vertical size of its device is all constantly dwindled for memory, therefore traditional SONOS device can't overcome along with device size constantly reduces the integrity problem that brings, and DC-SONOS memory of the present invention also has extraordinary data retention characteristic and charge-trapping ability when device size constantly dwindles, and is the optimal selection of following memory development.
Claims (3)
1. one kind has the DC-SONOS memory that the double-layer electric dielectric charge is caught layer, it is characterized in that, comprising:
Semiconductor substrate comprises the raceway groove with channel surface, and source and the drain terminal contiguous with described raceway groove;
Grid;
Dielectric lamination between described grid and described channel surface; And
Be positioned at the abutment wall of described grid and dielectric lamination both sides;
Wherein, described dielectric lamination comprises:
Tunnel layer contacts with described channel surface;
Be superimposed on the electric charge capture layer of described tunnel layer top; Described electric charge capture layer is double-deck dielectric composite construction;
Be superimposed on the barrier layer of described electric charge capture layer top, with described gate contact.
2. DC-SONOS memory according to claim 1 is characterized in that, described electric charge capture layer comprises:
The ground floor dielectric that contacts with described tunnel layer, its composition are Si
3N
4, thickness is 1-30;
The second layer dielectric of contiguous described ground floor, its composition is SiN, thickness is 1-50.
3. the preparation method of DC-SONOS memory according to claim 1 and 2, it is characterized in that, dry-oxygen oxidation forms described tunnel layer above described Semiconductor substrate, form described electric charge capture layer in described tunnel layer top again, adopt LPCVD technique to form the barrier layer in described electric charge capture layer top, adopt LPCVD technique to form grid above described barrier layer again, form abutment wall in described grid both sides, last autoregistration Implantation forms source and drain terminal; Wherein, the ground floor dielectric adopts the deposit under 500-900 ℃ of temperature of LPCVD technique to be prepared from the described electric charge capture layer, and described second layer dielectric adopts pecvd process deposit under 300-500 ℃ of temperature to be prepared from.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552081A (en) * | 2016-01-22 | 2016-05-04 | 清华大学 | Charge trap type memory and preparation method thereof |
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