CN102097436B - SONOS storage unit and operating method thereof - Google Patents
SONOS storage unit and operating method thereof Download PDFInfo
- Publication number
- CN102097436B CN102097436B CN2009102019321A CN200910201932A CN102097436B CN 102097436 B CN102097436 B CN 102097436B CN 2009102019321 A CN2009102019321 A CN 2009102019321A CN 200910201932 A CN200910201932 A CN 200910201932A CN 102097436 B CN102097436 B CN 102097436B
- Authority
- CN
- China
- Prior art keywords
- silica
- sonos
- injection region
- trap
- conduction band
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a silicon-oxide-nitride-oxide-silicon (SONOS) storage unit, which comprises an SONOS device and a selective transistor, wherein an oxide-nitride-oxide-nitride-oxide (ONONO) layer (12) is positioned between a polycrystalline silicon grid (141) and a channel region (11) of an SONOS device, and data are stored in silicon nitride (122) on the lower part of the ONONO layer (12) under low write-in voltage VP1 to meet the high-speed data storage requirement; and the data are stored in silicon oxynitride (124) on the upper part of the ONONO layer (12) under high write-in voltage VP2 to meet the high-reliability data storage requirement. The invention also discloses an operating method for the SONOS storage unit. The SONOS storage unit simultaneously integrates data storage structures of high capacity, high durability and high data holding capacity, and provides a feasible solution for the requirements of high performance and high integration degree of the semiconductor industry.
Description
Technical field
The present invention relates to a kind of NVM (non-volatile memory, nonvolatile memory), particularly relate to a kind of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon-silica-silicon-nitride and silicon oxide-silicon).
Background technology
See also Fig. 1, this is the sketch map of the memory cell of a kind of traditional SONOS, comprises SONOS device that is positioned at the left side and the selection transistor that is positioned at the right.Having n type light doping section 11 in the left area of p trap 10, is ONO (Oxide-Nitride-Oxide, silica-silicon-nitride and silicon oxide) layer 12 on the n type light doping section 11 of p trap 10.ONO layer 12 specifically comprises silica 121, silicon nitride 122 in the middle of being positioned at that is positioned at the below and the silica 123 that is positioned at the top.It on the ONO layer 12 the silicon nitride side wall 15 of polysilicon gate 141 and both sides thereof.Has n type lightly doped drain injection region 16 in the p trap 10 of silicon nitride side wall 15 down either side.Have n type source in the p trap 10 and in 16 outsides, n type lightly doped drain injection region and leak injection region 17.Grid and the source drain terminal of injection region 17 as the SONOS device leaked in polysilicon gate 141, two sources.Has gate oxide 13 on the zone, the right of p trap 10.It on the gate oxide 13 the silicon nitride side wall 15 of polysilicon gate 142 and both sides thereof.Has n type lightly doped drain injection region 16 in the p trap 10 of silicon nitride side wall 15 down either side.Have n type source in the p trap 10 and in 16 outsides, n type lightly doped drain injection region and leak injection region 17.Injection region 17 is leaked as selecting transistorized grid and source drain terminals in polysilicon gate 142, two sources.The SONOS device leaks injection region 17 with the shared source of selection transistor.
The memory cell each several part structure doping type of SONOS shown in Figure 1 is opposite, also be feasible.
The memory cell of above-mentioned SONOS is when carrying out write operation; Polysilicon gate 141 biasing positive voltage VPOS at the SONOS device; The drain terminal 17 bigoted negative voltage VNEG in the source of SONOS device; At the also bigoted negative voltage VNEG of trap end 10, so just form tunnelling voltage difference VPOS-VNEG from the channel region (being light doping section 11) below the polysilicon of SONOS device to polysilicon gate 141, the F-N that electronics takes place wears (Fowler-Nordheim tunneling then; The Fowler-Nordheim tunnelling), electronics enters into the nitride medium 122 of ONO layer 12 and is hunted down.
See also Fig. 6, according to band theory of solid, adding higher positive voltage VPOS at the polysilicon gate 141 of SONOS device, that being with of light doping section 11, silica 121 and silicon nitride 122 produced is crooked.In case the conduction band height N1 near the light doping section 11 (silicon) of silica 121 those sides is higher than the conduction band height N2 near the silica 121 of silicon nitride 122 those sides, then electronics will pass through silica 121 from light doping section 11 and arrive silicon nitrides 122.
The memory cell of above-mentioned SONOS only is used for the storage of high-speed high capacity usually, and can't be used for the storage of high-durability, high data retention ability.
Summary of the invention
Technical problem to be solved by this invention provides a kind of SONOS memory cell, both can be used for the storage of high-speed high capacity, also can be used for the storage of high-durability, high data retention ability.For this reason, the present invention also will provide the manufacturing approach of said SONOS memory cell.
For solving the problems of the technologies described above, the memory cell of SONOS of the present invention comprises the SONOS device and selection transistor of series connection;
In trap 10, has light doping section 11; Be ONONO layer 12 ' on the light doping section 11 of trap 10; ONONO layer 12 ' comprises first silica 121, silicon nitride 122, second silica 123, silicon oxynitride 124, the 3rd silica 125 from bottom to top; It on the ONONO layer 12 ' the silicon nitride side wall 15 of polysilicon gate 141 and both sides thereof; Has lightly doped drain injection region 16 in the trap 10 of silicon nitride side wall 15 down either side; Have the source in the trap 10 and in 16 outsides, lightly doped drain injection region and leak injection region 17; Grid and the source drain terminal of injection region 17 as the SONOS device leaked in polysilicon gate 141, two sources;
Also has gate oxide 13 on the trap 10; It on the gate oxide 13 the silicon nitride side wall 15 of polysilicon gate 142 and both sides thereof; Has lightly doped drain injection region 16 in the trap 10 of silicon nitride side wall 15 down either side; Have the source in the trap 10 and in 16 outsides, lightly doped drain injection region and leak injection region 17; Injection region 17 is leaked as selecting transistorized grid and source drain terminals in polysilicon gate 142, two sources;
The SONOS device leaks injection region 17 with the shared source of selection transistor.
In the memory cell of said SONOS, trap 10 is the p type; It is the n type that injection region 17 is leaked in light doping section 11, lightly doped drain injection region 16, source.
Perhaps, in the memory cell of said SONOS, trap 10 is the n type; It is the p type that injection region 17 is leaked in light doping section 11, lightly doped drain injection region 16, source.
A kind of method of operation of the memory cell of said SONOS is, the polysilicon gate 141 of the SONOS device in the SONOS memory cell is added positive voltage VP1, and to source drain terminal 17 and trap end 10 ground connection, applied voltage VP1 makes N1＞N2 and N3≤N4 and N5≤N6;
Wherein N1 is the conduction band height near the light doping section 11 of first silica, 121 those sides;
N2 is the conduction band height near first silica 121 of silicon nitride 122 those sides;
N3 is the conduction band height near the silicon nitride 122 of second silica, 123 those sides;
N4 is the conduction band height near second silica 123 of silicon oxynitride 124 those sides;
N5 is the conduction band height of the silicon oxynitride 124 of nearly the 3rd silica 125 those sides;
N6 is the conduction band height near the 3rd silica 125 of polysilicon gate 141 those sides.
The another kind of method of operation of the memory cell of said SONOS is, the polysilicon gate 141 of the SONOS device in the SONOS memory cell is added positive voltage VP2, and to source drain terminal 17 and trap end 10 ground connection, applied voltage VP2 makes N1＞N2 and N3＞N4 and N5≤N6;
In the memory cell of SONOS of the present invention, the ONO layer 12 in traditional SONOS device is changed into the ONONO layer 12 ' among the present invention.Wherein silicon nitride 122 is as the storage medium of high-speed high capacity, and first silica 121 is as the tunnel oxide of silicon nitride 122.Wherein silicon oxynitride 124 is as the storage medium of high-durability and high data retention ability, and the ONO layer that first silica 121, silicon nitride 122, the 3rd silica 123 are formed is as the tunnel oxide of silicon oxynitride 124.The data store organisation of the memory cell of SONOS of the present invention like this is just simultaneously integrated big fast capacity and high-durability, high data retention ability is for the demand of semiconductor industry high-performance and high integration provides feasible solution.
Description of drawings
Fig. 1 is the generalized section of existing SONOS memory cell;
Fig. 2 is the generalized section of SONOS memory cell of the present invention;
Fig. 3 is that SONOS memory cell of the present invention can be with sketch map during extra electric field;
Band curvature sketch map one when Fig. 4 is a SONOS memory cell extra electric field of the present invention;
Band curvature sketch map two when Fig. 5 is a SONOS memory cell extra electric field of the present invention;
Fig. 6 is existing SONOS memory cell band curvature sketch map when write operation.
Description of reference numerals among the figure:
10 is the p trap; 11 is n type light doping section; 12 is the ONO layer; 121 is first silica; 122 is silicon nitride; 123 is second silica; 12 ' is the ONONO layer; 124 is silicon oxynitride; 125 is the 3rd silica; 13 is gate oxide; 141 is the polysilicon gate of SONOS device; 142 for selecting transistorized polysilicon gate; 15 is the silicon nitride side wall; 16 is n type lightly doped drain injection region; 17 is that the injection region is leaked in n type source; N1 is the conduction band height near the light doping section 11 of first silica, 121 those sides; N2 is the conduction band height near first silica 121 of silicon nitride 122 those sides; N3 is the conduction band height near the silicon nitride 122 of second silica, 123 those sides; N4 is the conduction band height near second silica 123 of silicon oxynitride 124 those sides; N5 is the conduction band height near the silicon oxynitride 124 of the 3rd silica 125 those sides; N6 is the conduction band height near the 3rd silica 125 of polysilicon gate 141 those sides.
Embodiment
See also Fig. 2, the memory cell of SONOS of the present invention comprises the SONOS device and selection transistor of series connection.
In p trap 10, has n type light doping section 11.On the n type light doping section 11 of p trap 10 is ONONO layer 12 '.ONONO layer 12 ' comprises first silica 121, silicon nitride 122, second silica 123, silicon oxynitride 124, the 3rd silica 125 from bottom to top.It on the ONONO layer 12 ' the silicon nitride side wall 15 of polysilicon gate 141 and both sides thereof.Has n type lightly doped drain injection region 16 in the p trap 10 of silicon nitride side wall 15 down either side.Have n type source in the p trap 10 and in 16 outsides, n type lightly doped drain injection region and leak injection region 17.Grid and the source drain terminal of injection region 17 as the SONOS device leaked in polysilicon gate 141, two sources.
Also has gate oxide 13 on the p trap 1O.It on the gate oxide 13 the silicon nitride side wall 15 of polysilicon gate 142 and both sides thereof.Has n type lightly doped drain injection region 16 in the p trap 10 of silicon nitride side wall 15 down either side.Have n type source in the p trap 10 and in 16 outsides, n type lightly doped drain injection region and leak injection region 17.Injection region 17 is leaked as selecting transistorized grid and source drain terminals in polysilicon gate 142, two sources.
The SONOS device leaks injection region 17 with the shared source of selection transistor.
In the memory cell of above-mentioned SONOS, trap 10 changes the n type into; Light doping section 11, lightly doped drain injection region 16, source are leaked injection region 17 and are changed the p type into, also are another embodiment of the present invention.
In the said ONONO layer 12 ', require the thickness of thickness＞first silica 121 of thickness＞second silica 123 of the 3rd silica 125 usually.Wherein, the thickness of first silica 121 for example be
silicon nitride 122 thickness for example for the thickness of
second silica 123 for example for the thickness of
silicon oxynitride 124 for example for the thickness of
the 3rd silica 125 for example for
See also Fig. 3; This is that outer being biased of the SONOS device in the SONOS memory cell all is zero; And all storage mediums (like silicon nitride 122, silicon oxynitride 124, polysilicon gate 141 etc.) are not when obtaining external charge, the SONOS device can be with sketch map.Usually, the energy gap of silicon is about 1.1, and the energy gap of silica is about 8.1～9, and the energy gap of silicon nitride is about 3.9～4, and the energy gap of silicon oxynitride is about 5～6.5 between silica and silicon nitride.The doping type of various materials, doping content will have considerable influence to its energy gap, and therefore the energy gap (being the height of layers of material in vertical direction) of layers of material shown in Figure 3 is merely signal.
See also Fig. 4, this is that the polysilicon gate 141 of working as the SONOS device in the SONOS memory cell adds positive voltage VP1, in the time of all the other ends (source drain terminal 17, trap end 10) ground connection, and the band curvature sketch map of SONOS device.The electric field that add this moment makes the conduction band height N1 near the light doping section 11 (silicon) of first silica, 121 those sides be higher than the conduction band height N2 near first silica 121 of silicon nitride 122 those sides; Electron production F-N tunnelling is passed through first silica 121 from silicon and is arrived silicon nitride 122.Because the thickness of second silica 123 is greater than the thickness of first silica 121; The extra electric field of this moment is not enough so that near the conduction band height N3 of the silicon nitride 122 of second silica, 123 those sides greater than conduction band height N4 near second silica 123 of silicon oxynitride 124 those sides, so the electric charge in the silicon nitride 122 can't arrive silicon oxynitride 124.Again since the thickness of the 3rd silica 125 greater than the thickness of second silica 123; The extra electric field of this moment is also not enough so that near the conduction band height N5 of the silicon oxynitride 124 of the 3rd silica 125 those sides greater than conduction band height N6 near the 3rd silica 125 of polysilicon gate 141 those sides, so the electric charge in the silicon oxynitride 124 also can't arrive polysilicon gate 141.This wiring method be with storage in silicon nitride 122, it is lower that integral body writes voltage VP1, tunnel oxide is that silica 121 one decks are thinner, data can write fast, are applicable to that the high-speed high capacity data write.
See also Fig. 5, this is that the polysilicon gate 141 of working as the SONOS device in the SONOS memory cell adds positive voltage VP2, in the time of all the other ends (source drain terminal 17, trap end 10) ground connection, and the band curvature sketch map of SONOS device.Obvious VP2＞VP1.The electric field that add this moment makes the conduction band height N1 near the light doping section 11 (silicon) of first silica, 121 those sides be higher than the conduction band height N2 near first silica 121 of silicon nitride 122 those sides; Electron production F-N tunnelling is passed through first silica 121 from silicon and is arrived silicon nitride 122.The extra electric field of this moment also makes near the conduction band height N3 of the silicon nitride 122 of second silica, 123 those sides greater than the conduction band height N4 near second silica 123 of silicon oxynitride 124 those sides; Therefore the electric charge in the silicon nitride 122 is not stored; But produce the F-N tunnelling once more, pass through second silica 123 from silicon nitride 122 and arrive silicon oxynitride 124.In other words, electronics directly passes through first silica 121, silicon nitride 122, second silica 123 from silicon and arrives silicon oxynitrides 124.Because the thickness of the 3rd silica 125 is greater than the thickness of second silica 123; The extra electric field of this moment is not enough so that near the conduction band height N5 of the silicon oxynitride 124 of the 3rd silica 125 those sides greater than conduction band height N6 near second silica 125 of polysilicon gate 141 those sides, so the electric charge in the silicon oxynitride 124 can't arrive polysilicon gate 141.This wiring method is that data all are stored in the silicon oxynitride 124; It is higher that integral body writes voltage VP2; Tunnel oxide be first silica 121, silicon nitride 122 and second silica 123 totally three layers thicker; Data remain on that to lose probability in the silicon oxynitride relatively low, and device durability and data holding ability are high, are applicable to that the data of high-durability and high data retention ability write.
Need to prove silicon, silica, silicon nitride, silicon oxynitride (SiO
xN
yX, y are natural number) the conduction band height when band curvature, receive the influence (silicon oxynitride also receives the wherein influence of nitrogen, oxygen ratio) of its doping type, doping content, thickness, therefore be difficult to the conduction band height and the applied voltage size of layers of material are provided concrete numerical value or number range.
In sum, the invention provides memory cell and the method for operation thereof of a kind of SONOS, in the less storage that writes under the voltage VP1 in the silicon nitride 122 of ONONO layer 12 ', to satisfy the high-speed data storage demand than the below; In the bigger storage that writes under the voltage VP2 in the silicon oxynitride 124 of ONONO layer 12 ', to satisfy the high reliability data storage demand than the top.
Claims (7)
1. the memory cell of a SONOS comprises the SONOS device of series connection and selects transistor; It is characterized in that:
In trap (10), has light doping section (11); On the light doping section (11) of trap (10) is ONONO layer (12 '); ONONO layer (12 ') comprises first silica (121), silicon nitride (122), second silica (123), silicon oxynitride (124), the 3rd silica (125) from bottom to top; It on the ONONO layer (12 ') the silicon nitride side wall (15) of polysilicon gate (141) and both sides thereof; Has lightly doped drain injection region (16) in the trap (10) of silicon nitride side wall (15) down either side; Has leakage injection region (17), source in the trap (10) and in lightly doped drain injection region (16) outside; Grid and the source drain terminal of injection region (17) as the SONOS device leaked in polysilicon gate (141), two sources;
Also has gate oxide (13) on the trap (10); It on the gate oxide (13) the silicon nitride side wall (15) of polysilicon gate (142) and both sides thereof; Has lightly doped drain injection region (16) in the trap (10) of silicon nitride side wall (15) down either side; Has leakage injection region (17), source in the trap (10) and in lightly doped drain injection region (16) outside; Injection region (17) is leaked as selecting transistorized grid and source drain terminal in polysilicon gate (142), two sources;
The SONOS device leaks injection region (17) with the shared source of selection transistor.
2. the memory cell of SONOS according to claim 1 is characterized in that, trap (10) is the p type; It is the n type that injection region (17) is leaked in light doping section (11), lightly doped drain injection region (16), source;
Perhaps, trap (10) is the n type; It is the p type that injection region (17) is leaked in light doping section (11), lightly doped drain injection region (16), source.
3. the memory cell of SONOS according to claim 1 is characterized in that, the thickness of the thickness of the thickness of the 3rd silica (125)＞second silica (123)＞first silica (121).
4. the memory cell of SONOS according to claim 1; It is characterized in that, the thickness of first silica (121) be
silicon nitride (122) thickness for the thickness of
second silica (123) for the thickness of
silicon oxynitride (124) for
the 3rd silica (125) thickness is
5. the method for operation of the memory cell of SONOS as claimed in claim 1; It is characterized in that; When carrying out write operation; Polysilicon gate (141) to the SONOS device in the SONOS memory cell adds positive voltage VP1, and to source drain terminal (17) and trap end (10) ground connection, applied voltage VP1 makes N1＞N2 and N3≤N4 and N5≤N6;
Wherein N1 is the conduction band height near the light doping section (11) of that side of first silica (121);
N2 is the conduction band height near first silica (121) of that side of silicon nitride (122);
N3 is the conduction band height near the nitrogenize (122) of that side of second silica (123);
N4 is the conduction band height near second silica (123) of that side of silicon oxynitride (124);
N5 is the conduction band height of the silicon oxynitride (124) of that side of nearly the 3rd silica (125);
N6 is the conduction band height near the 3rd silica (125) of that side of polysilicon gate (141).
6. the method for operation of the memory cell of SONOS as claimed in claim 1; It is characterized in that; When carrying out write operation; Polysilicon gate (141) to the SONOS device in the SONOS memory cell adds positive voltage VP2, and to source drain terminal (17) and trap end (10) ground connection, applied voltage VP2 makes N1＞N2 and N3＞N4 and N5≤N6;
Wherein N1 is the conduction band height near the light doping section (11) of that side of first silica (121);
N2 is the conduction band height near first silica (121) of that side of silicon nitride (122);
N3 is the conduction band height near the silicon nitride (122) of that side of second silica (123);
N4 is the conduction band height near second silica (123) of that side of silicon oxynitride (124);
N5 is the conduction band height of the silicon oxynitride (124) of that side of nearly the 3rd oxidation (125);
N6 is the conduction band height near the 3rd silica (125) of that side of polysilicon gate (141).
7. according to the method for operation of the memory cell of claim 5 or 6 described SONOS, it is characterized in that VP1＜VP2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102019321A CN102097436B (en) | 2009-12-15 | 2009-12-15 | SONOS storage unit and operating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102019321A CN102097436B (en) | 2009-12-15 | 2009-12-15 | SONOS storage unit and operating method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102097436A CN102097436A (en) | 2011-06-15 |
| CN102097436B true CN102097436B (en) | 2012-06-20 |
Family
ID=44130428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009102019321A Active CN102097436B (en) | 2009-12-15 | 2009-12-15 | SONOS storage unit and operating method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102097436B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931196B (en) * | 2011-08-08 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device |
| CN102324429B (en) * | 2011-09-29 | 2017-09-29 | 上海华虹宏力半导体制造有限公司 | New pair transistor SONOS flash memory unit structures and its operating method |
| CN102709330B (en) * | 2012-05-22 | 2016-04-27 | 上海华力微电子有限公司 | A kind of BE-SONOS structure device and formation method with low operating voltage |
| CN102769031B (en) * | 2012-07-03 | 2015-08-26 | 上海华力微电子有限公司 | A kind of SONOS structure devices with low operating voltage |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7250654B2 (en) * | 2005-11-07 | 2007-07-31 | Ememory Technology Inc. | Non-volatile memory device |
| CN101587863A (en) * | 2008-05-23 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Polysilicon grid etching method for flash memory based on SONOS and device |
-
2009
- 2009-12-15 CN CN2009102019321A patent/CN102097436B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7250654B2 (en) * | 2005-11-07 | 2007-07-31 | Ememory Technology Inc. | Non-volatile memory device |
| CN101587863A (en) * | 2008-05-23 | 2009-11-25 | 中芯国际集成电路制造(上海)有限公司 | Polysilicon grid etching method for flash memory based on SONOS and device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102097436A (en) | 2011-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7768062B2 (en) | Combined volatile and non-volatile memory device with graded composition insulator stack | |
| US7629641B2 (en) | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection | |
| US7859046B2 (en) | Ballistic direct injection NROM cell on strained silicon structures | |
| US20040156240A1 (en) | Method of erasing non-volatile semiconductor memory device and such non-volatile semiconductor memory device | |
| CN103226973A (en) | NAND flash memory unit, NAND flash memory array, and methods for operating them | |
| US7838920B2 (en) | Trench memory structures and operation | |
| WO2011055433A1 (en) | Nonvolatile semiconductor storage device | |
| JP2011129816A (en) | Semiconductor device | |
| US20070063268A1 (en) | Non-volatile memory, and operation and fabrication of the same | |
| CN102097436B (en) | SONOS storage unit and operating method thereof | |
| US20130313628A1 (en) | Sonos structure, manufacturing method thereof and semiconductor with the same structure | |
| US7221597B2 (en) | Ballistic direct injection flash memory cell on strained silicon structures | |
| CN113707205B (en) | Erasing method of flash memory array | |
| CN102931196B (en) | SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device | |
| US20070183222A1 (en) | Semiconductor memory device | |
| US7723757B2 (en) | Vertical nonvolatile memory cell, array, and operation | |
| CN102130179B (en) | Silicon-oxide-nitride-oxide-silicon (SONOS) device | |
| US20030025148A1 (en) | Structure of a flash memory | |
| US20110037119A1 (en) | Memory | |
| KR100950044B1 (en) | Multi-bit flash memory device, flash memory, and apparatus and method for driving the flash memory device | |
| CN104253160A (en) | B4-Flash with convexity grid electrode structure | |
| JP5002172B2 (en) | Nonvolatile semiconductor memory device | |
| CN102760773B (en) | NVN (Non-Volatile Memory) device and manufacturing method thereof | |
| CN102610617A (en) | Multi-bit SONOS (silicon-oxide-nitride-oxide-silicon) flash memory unit, multi-bit SONOS (silicon-oxide-nitride-oxide-silicon) flash memoryarray and operation method | |
| KR101052328B1 (en) | Charge-Trap Nonvolatile Memory Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20131216 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20131216 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |