KR101052328B1 - Charge-Trap Nonvolatile Memory Devices - Google Patents

Abstract

In the present invention, a nonvolatile semiconductor device having a trench structure having good recording / erasing characteristics is provided. The semiconductor device comprises a trenched gate structure comprising a semiconductor substrate and trench channels forming source and drain regions on the substrate and etching the substrate to form lower than the source and drain regions, the gate structure comprising an etched trench A source and drain extension (SDE) region of a sidewall spacer structure on a side wall of the channel, and a first silicon nitride layer (Si ₃ N ₄ ) having a thickness of 3 nm or less on the trench channel. A tunneling insulating film, a second tunneling insulating film formed on the first tunneling insulating film having a higher conduction band energy than the first tunneling insulating film and having a silicon oxide film (SiO ₂ ) having a thickness of 4 nm or less, and 4 nm on the second tunneling insulating film. or less thick silicon nitride film (Si ₃ N ₄₎ the third tunneling insulating film formed by, the first phase 3 tunneling insulation film The silicon nitride film (Si ₃ N ₄₎ than the conduction band energy level is low and the conduction band than the charge trap layer, wherein the charge trap layer and the hafnium oxide film on the (HfO ₂₎ formed of a hafnium oxide film (HfO ₂₎ of 10nm or less thick energy A blocking insulating film formed of an aluminum oxide film (Al ₂ O ₃ ) having a high level and a thickness of 20 nm or less, and a metal gate electrode layer formed on the blocking insulating film and having a work function of 4.5 eV or more.

Nonvolatile Memory, Charge Trap, Silicon Nitride, Blocking Insulation

Description

Charge trap flash type nonvolatile memory device

In the present invention, a tunneling insulating film is formed in a stacked structure of a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film (SiO ₂ ) / silicon nitride film (Si ₃ N ₄ ) on a trench structure channel, and a charge trap layer and a blocking insulating film are inherently formed. The present invention relates to a nonvolatile memory device formed of a thin film and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor fabrication capable of reading, writing, and storing electrical information, and having high-capacity and high-density features and capable of high-speed write / erase operations.

The present invention is derived from a study performed by the Kwangwoon University Industry-Academic Cooperation Group with the support of the Ministry of Knowledge Economy. [Task unique number: 10029946, Title: Development of high reliability TBE-NFGM device]

Semiconductor memory devices are classified into volatile memory devices and nonvolatile memory devices according to data storage methods. Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory includes dynamic random access memory (DRAM) or static random access memory (SRAM). On the other hand, the nonvolatile memory device retains data even when power is not supplied. Representative examples of the nonvolatile memory device include flash memory devices.

Such flash memory is widely used as a personal communication device such as a mobile phone that requires mobility to be portable, various small electronic devices such as USB memory, MP3, and PMP, and a data storage device such as a digital voice recorder or a memory card. have.

In particular, NAND (NOT-AND) flash memory, which is used in mobile phones, MP3s, digital cameras, and USB memories, is a representative nonvolatile memory device that solves a disadvantage of volatile operation of a DRAM (Dynamic Random Access Memory) device.

As such, flash memory has started to be used as a main memory device for portable devices due to its nonvolatile and low power consumption. In particular, the demand for flash memory is rapidly increasing as a mass storage medium such as digital home appliances due to its higher density than DRAM.

Flash memory technology, on the other hand, is not only a technical advantage of EPROM (Erasable-Programmable Read-Only Memory) and EEPROM (Electrically Erasable-Programmable Read-Only Memory), but also a memory with both DRAM and Read-Only Memory (ROM). to be. In particular, it has a higher density than the density of DRAM and ROM, and can rewrite the storage contents as necessary, such as EPROM or DRAM, and has both non-volatile ROM and EEPROM. NAND-type flash memory, which is currently commercialized, is 2 gigabytes in density, has a slow storage and erase time of several tens of us, and operates at a high supply voltage of 10V to 20V.

Current flash memories have a structure in which an oxide film, a floating gate, and an oxide film are inserted between a gate electrode and a channel based on a metal-oxide semiconductor field effect transistor (MOSFET) structure. The operation principle of such a flash memory device is to use a change in the threshold voltage of a transistor depending on whether or not charge is injected into a floating gate made of polysilicon.

Typically, once data has been written to a nonvolatile memory, the time to retain that data is more than 10 years. In order to store electrons in the floating gate during this period, there is a limit to thinning the thickness of the tunneling oxide film. The thickness of the current tunneling oxide layer of the flash memory device is 7 nm to 8 nm, which is a thickness that cannot inject or remove electrons by tunneling directly to the floating gate. Therefore, other methods are used to inject or remove electrons into the floating gate for speed improvement and low power operation.

Typically, channel hot-electron (CHE) injection or Fowler-Nordheim (F-N) tunneling is used instead of direct tunneling to store or remove electrons in nonvolatile memory. For this reason, high operating voltages are required for the storage and removal of electrons.

Current flash memories have a storage and erase voltage of more than 10V, which is very large compared to complementary metal-oxide-semiconductor (CMOS) driving voltages. This causes defects in the tunneling oxide film due to the high voltage and causes the performance of the memory device to deteriorate. Therefore, it is expected that more serious problems will occur when the cell size of the flash memory is reduced.

In addition, since the conventional flash memory uses a floating gate made of polysilicon as a storage electrode, interference occurs between adjacent gates when high integration, and stored charge can move freely through polysilicon, so that if there is a defect in the oxide film, The disadvantage is that all stored charges leak out.

1 illustrates a cross-sectional structure of a charge trapping nonvolatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) type, which is a charge trapping nonvolatile memory manufactured to solve such a problem.

Referring to FIG. 1, a tunneling insulating film made of silicon oxide (SiO ₂ ), a charge trap layer made of silicon nitride (Si ₃ N ₄ ), a blocking insulating film made of silicon oxide (SiO ₂ ), and a gate of polysilicon are formed on a semiconductor channel. The electrode layer has a structure in which the electrode layers are sequentially stacked. SONOS-type charge trap type nonvolatile memory eliminates interference problems caused by floating gate memory below 40 nm and has discrete traps to improve the reliability of memory devices. Has its drawbacks.

First, the tunneling insulating layer composed of a single layer of silicon oxide has a non-volatile property due to an increase in direct tunneling and stress induced leakage current when the thickness is reduced to improve the operation speed. Data retention characteristics of more than 10 years that memory must have cannot be obtained. When the thickness of the tunneling insulating film composed of a single layer of silicon oxide film is increased to achieve data retention characteristics, there is a disadvantage in that deterioration of data recording / erasing characteristics occurs.

Second, since the charge trap layer made of a silicon nitride film has a high process temperature, the application of the tunneling insulating film of the high dielectric film having a low allowable process temperature is limited.

Third, the blocking insulating film made of the silicon oxide film requires a high voltage to form charge in the channel because the dielectric constant is low. In addition, due to the high voltage, an electron back injection phenomenon occurs from the gate electrode, which is canceled with the hole injected from the silicon substrate side for data erasing, so that the erase speed is lowered. Therefore, there is a problem that data is not completely erased.

FIG. 2A shows an energy band diagram in thermal equilibrium with respect to the cross-sectional structure in the A-A 'direction of the SONOS memory device of FIG. 1.

Referring to FIG. 2A, since the Fermi level is constant in the entire system, the energy bands of the semiconductor substrate doped with P-type and the control gate electrode doped with N-type are bent in the thermal equilibrium state as shown in FIG. .

Referring to FIG. 2B, a high voltage is applied to the semiconductor substrate as compared to the control gate electrode of the SONOS memory device in the erase mode. As shown in FIG. 2B, the thermal equilibrium is broken by an externally applied voltage so that the Fermi level E _fn of the electrode rises higher than the Fermi level of the semiconductor substrate, and the tunneling insulating layer 22 and the charge trap layer 23 are formed. , The shape of the conduction band of the blocking insulation film 24 is modified.

In this erase operation, electrons stored in the charge trap layer 23 are tunneled through the tunneling insulating layer 22 and injected into the semiconductor substrate, thereby performing data erasing. However, since the hole injection is not easy and the work function of the polysilicon is low, the electron is injected into the charge trapping layer by tunneling the blocking insulating film from the electrode, so that it takes a long time to lower the threshold voltage, which results in a long data erasing time. Is generated.

As these problems are solved, and as the memory devices are highly integrated, new device structures and manufacturing process technologies are required to simultaneously secure fast write / erase operations and data retention characteristics of 10 years or more.

Current non-volatile memory stores voltages that are very large. This causes defects in the tunneling oxide film due to the high voltage and causes the performance of the memory device to deteriorate. Therefore, it is expected that more serious problems will occur when the cell size of the flash memory becomes smaller.

In order to solve the above problems, by improving the material and structure of the tunneling insulating film of the conventional nonvolatile memory, a nonvolatile memory device and a method of manufacturing the same, which have a high speed at a low voltage at the time of writing and erasing and can improve data retention characteristics simultaneously. of

To provide.

In order to solve the above problems, a semiconductor memory device including a trench type gate structure including a trench channel having a source and a drain region formed on the substrate and etching the substrate to be lower than the source and drain regions. A trench gate structure of such a semiconductor memory device is provided on a sidewall of the etched trench channel, a source drain drain (SDE) region of a sidewall spacer structure, on the trench channel. A first tunneling insulating film formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 3 nm or less, and a silicon oxide film having a higher conduction band energy than the first tunneling insulating film (SiO ₂ ) on the first tunneling insulating film (SiO _2). The second tunneling insulating film formed on the second tunneling insulating film; A silicon nitride (Si ₃ N ₄₎ The third tunneling insulation film, said third tunnel of the silicon nitride film on the insulating film (Si ₃ N ₄₎ than the conduction band was the energy level is low, the hafnium oxide film is 10nm or less thick (HfO ₂₎ formed by a On the charge trap layer to be formed, a blocking insulating film formed of an aluminum oxide film (Al ₂ O ₃ ) having a higher energy level than the hafnium oxide film (HfO ₂ ) and having a thickness of 20 nm or less on the charge trap layer, and the blocking insulating film It is characterized in that it comprises a metal gate electrode layer having a work function of 4.5 eV or more.

Forming a trench channel by etching the semiconductor substrate after forming a source and a drain on a semiconductor substrate to solve another problem; Forming a source drain drain (SDE) region of a sidewall spacer structure on a side wall of the etched trench channel; Forming a first tunneling insulating film including a silicon nitride film (Si ₃ N ₄ ) having a thickness of 3 nm or less on the trench channel; 4 nm having a higher conduction band energy than the first tunneling insulating film on the first tunneling insulating film; Forming a second tunneling insulating film made of a silicon oxide film (SiO ₂ ) having a thickness less than or equal to; Forming a third tunneling insulating film including a silicon nitride film (Si ₃ N ₄ ) having a thickness of 4 nm or less on the second tunneling insulating film; Forming a charge trap layer including a hafnium oxide layer (HfO ₂ ) having a conduction band energy level lower than that of the silicon nitride layer (Si ₃ N ₄ ) and having a thickness of 10 nm or less on the third tunneling insulating layer; Forming a blocking insulating film formed of an aluminum oxide film (Al ₂ O ₃ ) having a thickness of 20 nm or less and having a higher energy level than that of the hafnium oxide film (HfO ₂ ) on the charge trap layer, and 4.5 eV or more on the blocking insulating film There is provided a method for manufacturing a charge trapping nonvolatile memory device comprising forming a gate electrode layer having a work function.

The nonvolatile memory employing the trench structure according to the present invention can be expected to improve the write / erase characteristics and the data retention characteristics at the same time.

Hereinafter, a charge trapping nonvolatile semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to a client's or operator's intention or custom. Therefore, the definition should be based on the contents throughout this specification.

3 to 9 illustrate a method and an experimental result of a charge trapping type nonvolatile memory device having a CRESTED barrier having a Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ stacked structure according to a preferred embodiment of the present invention. It is sectional drawing and graph which are shown schematically for explanation.

First, FIG. 3 shows a step by step method of manufacturing a charge trap type nonvolatile memory device according to the present invention.

In FIG. 3A, a doped silicon thin film is formed on the substrate 30. The substrate 30 may use a semiconductor substrate, such as a silicon substrate, and may use an SOI substrate or a polycrystalline silicon substrate. In this case, the doped silicon thin film 31 is formed of a polycrystalline silicon thin film doped with a high concentration of n-type impurities to a thickness of 5 to 100 nm by CVD (chemical vapor deposition) or sputtering, or doped with impurities by an epitaxy method. The single crystal silicon thin film can be formed.

In another embodiment, a shallow dopant-doped layer may be formed on the surface of the silicon semiconductor using ion implantation, plasma doping, or solid phase diffusion instead of the silicon thin film.

Referring to FIG. 3B, the doped silicon thin film 31 and the substrate 30 are etched to form trench regions on the silicon surface. In this case, the etching for forming the trench region may use a reactive ion etching (RIE) process using plasma or a wet etching method using a chemical solution.

Referring to FIG. 3C, an embodiment in which a sidewall spacer 31b is formed inside a trench region and used as a source drain extension region (SDE) is shown.

The sidewall spacer 31b has an extended region of the source and drain of the sidewall structure by an etchback process using an ion etching process (RIE) after growing a polycrystalline silicon or silicon epitaxy film doped with impurities. One structure is shown. At this time, the gate length can be adjusted by adjusting the thickness of the sidewall spacers, thus making it possible to fabricate an element having an ultra-fine gate length. In addition, by adjusting the concentration of the impurities doped in the sidewall spacer by controlling the electric field of the drain-side channel can also have the effect of suppressing the generation of hot carriers and short-channel effects.

In addition, as shown in FIG. 3C, after the silicon sidewall spacer is formed, a channel may be formed in a fine trench in the silicon channel portion through over etching by an ion etching process (RIE), which has an advantage of suppressing a short channel effect.

After forming the fine trench through silicon sidewall spacer etching, the silicon defect and the surface roughness inside the trench channel may be removed by hydrogen heat treatment at atmospheric pressure or reduced pressure at a temperature of 700 ° C. or higher.

Referring to FIG. 3D, a fine trench type channel region is formed between regions of the silicon sidewall spacers 31b doped to serve as SDE regions. The gate structure is formed by sequentially stacking a first tunneling insulating film 32, a second tunneling insulating film 33, a third tunneling insulating film 34, a charge trap layer 35, a blocking insulating film 36, and a metal gate electrode 37. Has a structure.

The first tunneling insulating film 32 is formed to a thickness where electrons or holes are easy to tunnel. The first tunneling insulating layer 32 is a Si ₃ N ₄ 1 ~ 3 by a low pressure chemical vapor deposition (LPCVD) method, a sputtering method or an ALD method at 700 ~ 800 ℃ using DCS (dichlorosilane) and NH ₃ gas It is formed to a thickness of nm.

The second tunneling insulating layer 33 is a tetraethyl orthosilicate (TEOS) gas containing SiO ₂ , which has a higher conduction band energy level, a lower valence band energy level, and a lower dielectric constant than the first tunneling insulating layer 32. It is formed to a thickness of 2 ~ 4 nm by LPCVD method, sputtering method or ALD method at 600 ~ 700 ℃ using.

The third tunneling insulating film 34 is formed of Si ₃ N ₄ to a thickness of 2 to 4 nm by LPCVD method, sputtering method or ALD method at 700 ~ 800 ℃ using DCS and NH ₃ gas.

The charge trapping layer 35 on the third tunneling insulating layer 34 has a lower energy level of the conduction band than Si ₃ N ₄ and has a high dielectric constant of hafnium oxide (HfO ₂ ) by ALD (atomic layer deposition) or sputtering. Deposit 5-10 nm thick.

The entirety of the first tunneling insulating film 32, the second tunneling insulating film 33, and the third tunneling insulating film 34 is referred to as a tunneling insulating film 38.

The blocking insulating film 36 on the charge trap layer 35 has a higher energy level in the conduction band than the hafnium oxide film HfO ₂ and lowers the valence band energy level from the aluminum oxide film Al ₂ O ₃ by ALD method or sputtering method. Deposit 20 nm thick.

A gate electrode 37 having a high work function of 4.5 eV or more, for example, TiN or TaN, is deposited on the blocking insulating layer 36 by 100 to 200 nm by CVD or sputtering.

4 is a cross-sectional view illustrating a structure of a charge trap type nonvolatile memory device including a tunneling insulating layer having a NON stacked structure by forming a gate region through etching after forming a gate structure as shown in FIG. 3D.

After forming the gate structure as shown in FIG. 3d, regions other than the gate are removed by a dry etching method using an ion etching process or a wet etching method using a chemical solution. After forming the gate region, defects generated in the gate etching process may be removed through a subsequent heat treatment process at a low temperature of 300 ~ 500 ℃ in an atmosphere containing hydrogen.

5A and 5B show energy band diagrams in write and erase modes for the cross-sectional structure in the direction B-B 'in the device of FIG.

Referring to FIG. 5A, a high voltage is applied to the gate electrode in the write mode as compared with the semiconductor substrate of the memory device shown in FIG. 4. As shown in FIG. 5A, the thermal equilibrium is broken by an external applied voltage, and electrons are stored in the charge trap layer 35 through the tunneling insulating layer 38. At this time, the conduction band energy level barrier of the stacked tunneling insulating film 38 is lowered, so that a larger current flow can be expected.

Referring to FIG. 5B, a high voltage is applied to the semiconductor substrate in the erase mode compared to the gate electrode of the memory device illustrated in FIG. 4. In this erase mode, the electrons stored in the charge trap layer 35 are tunneled through the tunneling insulating layer 38 and injected into the semiconductor substrate to perform data erasing. At the same time, as the valence band energy level barrier is lowered, the injection of holes into the inside of the charge trap layer 35 is facilitated, thereby improving the erase speed.

6 is a diagram showing the write characteristics of the charge trap type nonvolatile memory device according to the present invention.

NONHA is a memory device having a Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ tunneling insulating film, an HfO ₂ charge trap layer and an Al ₂ O ₃ blocking insulating film shown in FIG. 4, and OHA is a single layer of SiO instead of the NON tunneling insulating film. ₂ is a memory device having an HfO ₂ charge trap layer and an Al ₂ O ₃ blocking insulating film, and NONNO is a memory device having a NON tunneling insulating film and a Si ₃ N ₄ charge trap layer and an SiO ₂ blocking insulating film. In all three cases, TiN was applied to the gate electrode.

Referring to FIG. 6, it can be seen that a NONHA memory device according to an embodiment of the present invention has a faster writing speed than an OHA or NONNO device.

7 is a diagram illustrating erase characteristics of a charge trap type nonvolatile memory device according to the present invention.

Similarly, NONHA is a memory device having a Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ tunneling insulating film, an HfO ₂ charge trap layer, and an Al ₂ O ₃ blocking insulating film shown in FIG. 4, and OHA is a single layer instead of a NON tunneling insulating film. A memory device having SiO _{2 and} having a HfO ₂ charge trap layer and an Al ₂ O ₃ blocking insulating film, NONNO is a memory device having a NON tunneling insulating film and a Si ₃ N ₄ charge trap layer and a SiO ₂ blocking insulating film. In all three cases, TiN was applied to the gate electrode.

Referring to FIG. 7, it can be seen that a NONHA memory device has a faster erase speed than an OHA or NONNO device. This recording and erasing rate is due to not only the field sensitivity being improved by stacking the tunneling barrier, but also the electric field is concentrated in the tunneling barrier due to the application of the high-permittivity charge trap layer and the blocking insulating film.

8 is a view showing the durability of the charge trap type nonvolatile memory device according to the present invention. According to FIG. 8, it can be seen that a memory window of 1.92 V remains even after a total of 10 ⁴ write / erase operations. This is because deterioration of the tunneling insulating film is reduced by the low driving voltage and the high speed.

9 shows data retention characteristics of a charge trap type nonvolatile memory device according to the present invention.

After 10 years, the memory window has been 1.65V at room temperature and 1.2V at 85 ℃. It can be seen that the memory window of more than 1 V is shown after 10 years even at high temperature, and the leakage current is reduced due to the increase in the physical thickness of the stacked tunneling insulating layer and the gate electrode of high work function, which results in the data retention characteristics. Because it improved.

10 is a flowchart illustrating a method of manufacturing a charge trap type nonvolatile memory device according to the present invention.

First, a source and a drain are formed on a semiconductor substrate (1010).

Next, the semiconductor substrate is etched to form a trench channel (1020).

When the trench channel is formed, a source drain drain (SDE) region having a sidewall spacer structure is formed on the side wall of the trench channel (1030). This sidewall spacer structure determines the characteristics of the semiconductor device according to the present invention.

When the source and drain extension regions of the sidewall space structure are formed, a first tunneling insulating layer made of a silicon nitride layer (Si ₃ N ₄ ) having a thickness of 3 nm or less is formed on the trench channel (1040).

A second tunneling insulating layer formed of silicon oxide (SiO ₂ ) having a thickness of 4 nm or less and having a higher conduction band energy than the first tunneling insulating layer is formed on the first tunneling switching layer (1050).

In operation 1060, a third tunneling insulating film including a silicon nitride film Si ₃ N ₄ having a thickness of 4 nm or less is formed on the second tunneling insulating film. In this way, a tunneling insulating film was formed from the first tunneling insulating film to the third tunneling insulating film.

On the third tunneling insulating layer, a charge trap layer including a hafnium oxide layer (HfO ₂ ) having a thickness of 10 nm or less while having a lower conduction band energy level than the silicon nitride layer (Si ₃ N ₄ ) is formed (1070).

On the charge trap layer, a blocking insulating layer made of aluminum oxide (Al ₂ O ₃ ) having a thickness of 20 nm or less is formed while the energy level of the conduction band is higher than that of the hafnium oxide (HfO ₂ ) (1080).

When the gate electrode layer having a work function of 4.5 eV or more is formed on the blocking insulating film (1090), the basic structure of the device is achieved.

As described above, in the present invention, the tunneling insulating layer is formed by using a stacked Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ tunneling insulating layer, a high-k dielectric charge trap layer, and a blocking insulating layer instead of a single layer of SiO _2. The recording / erasing characteristics were checked, which resulted in improved durability. In addition, due to the increase in the physical thickness of the stacked tunneling insulating layer and the gate electrode having a high work function, the leakage current is reduced, thereby improving data retention characteristics.

As described above, the present invention has been described based on the preferred embodiments, but these embodiments are intended to illustrate the present invention, not to limit the present invention. Various changes, modifications or adjustments to the examples will be possible. Therefore, the protection scope of this invention will be limited only by the appended claims, and should be construed as including all changes, modifications or adjustments.

1 is a cross-sectional view of a structure of a charge trapping nonvolatile memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) type according to the prior art.

FIG. 2 is an energy band diagram in thermal equilibrium with respect to the cross-sectional structure in the A-A 'direction of the SONOS memory element of FIG.

3 is a view showing a method for manufacturing a charge trap type nonvolatile memory device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a structure of a charge trapping nonvolatile memory device including a tunneling insulating layer having a NON stacked structure by forming a gate region through etching after forming the gate structure as shown in FIG. 3D.

5A and 5B show energy band diagrams in write and erase modes for the cross-sectional structure in the direction B-B 'in the device of FIG.

6 is a diagram showing the write characteristics of the charge trap type nonvolatile memory device according to the present invention.

7 is a diagram illustrating erase characteristics of a charge trap type nonvolatile memory device according to the present invention.

8 is a view showing the durability of the charge trap type nonvolatile memory device according to the present invention.

9 is a view showing data retention characteristics of a charge trap type nonvolatile memory device according to the present invention.

10 is a flowchart illustrating a method of manufacturing a charge trap type nonvolatile memory device according to the present invention.

Claims (7)

12. A semiconductor memory device comprising a semiconductor substrate, a trench type gate structure including a trench channel having a source and a drain region formed on the substrate and etching the substrate to form a lower channel than the source and drain regions. Is A source drain drain (SDE) region of a sidewall spacer structure on a side wall of the etched trench channel, A first tunneling insulating layer formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 3 nm or less on the trench channel; A second tunneling insulating film formed on the first tunneling insulating film with a silicon oxide film (SiO ₂ ) having a thickness of 4 nm or less while having a higher conduction band energy than the first tunneling insulating film, A third tunneling insulating film formed on the second tunneling insulating film by a silicon nitride film having a thickness of 4 nm or less; A charge trap layer formed of a hafnium oxide film having a lower conduction band energy level than the silicon nitride film and having a thickness of 10 nm or less on the third tunneling insulating film; A blocking insulating film formed on the charge trap layer with an aluminum oxide film having a higher energy level than the hafnium oxide film and having a thickness of 20 nm or less, and And a metal gate electrode layer formed on the blocking insulating layer and having a work function of 4.5 eV or more. The charge trap type nonvolatile memory device of claim 1, wherein the trench channel is formed lower than a source drain drain (SDE) region of the sidewall spacer structure. delete delete Forming a trench channel by etching the semiconductor substrate after forming a source and a drain on the semiconductor substrate; Forming a source drain drain (SDE) region of a sidewall spacer structure on a side wall of the etched trench channel; Forming a first tunneling insulating film formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of 3 nm or less on the trench channel; Forming a second tunneling insulating layer on the first tunneling insulating layer, the second tunneling insulating layer having a higher conduction band energy than the first tunneling insulating layer and having a silicon oxide film (SiO ₂ ) having a thickness of 4 nm or less; Forming a third tunneling insulating film including a silicon nitride film (Si ₃ N ₄ ) having a thickness of 4 nm or less on the second tunneling insulating film; Forming a charge trap layer including a hafnium oxide layer (HfO ₂ ) having a conduction band energy level lower than that of the silicon nitride layer (Si ₃ N ₄ ) and having a thickness of 10 nm or less on the third tunneling insulating layer; Forming a blocking insulating layer formed of an aluminum oxide film (Al ₂ O ₃ ) having a thickness of 20 nm or less on the charge trap layer and having a higher energy level than that of the hafnium oxide film (HfO ₂ ); And forming a gate electrode layer having a work function of 4.5 eV or more on the blocking insulating layer. delete delete

Images