CN102769031B - Sonos structure having a low operating voltage of the device - Google Patents

Sonos structure having a low operating voltage of the device Download PDF

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CN102769031B
CN102769031B CN201210225786.8A CN201210225786A CN102769031B CN 102769031 B CN102769031 B CN 102769031B CN 201210225786 A CN201210225786 A CN 201210225786A CN 102769031 B CN102769031 B CN 102769031B
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silicon
gate
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田志
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上海华力微电子有限公司
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Abstract

本发明提供一种具有低操作电压的SONOS结构器件及其制备方法。 SONOS structure of the present invention provides a device and method of preparation having a low operating voltage. 在传统的阻挡氧化层和多晶硅栅极之间插入一层具有电荷存储能力的氮化硅层,使得阈值电压降低,从而使编译时所需的门极电压下降,减少由于高电压引起的应力诱导的漏电流和降低器件的功耗。 A silicon nitride barrier layer between the conventional gate oxide layer and the polysilicon layer insert having a charge storage capacity, so that the threshold voltage is reduced, so that the time required to compile the gate voltage is decreased to reduce the stress caused due to the induction of a high voltage leakage current and power consumption of the device.

Description

一种具有低操作电压的SONOS结构器件 SONOS device structure having a low operating voltage

技术领域 FIELD

[0001] 本发明涉及微电子制造领域,尤其涉及一种利用氮化硅双极性存储降低SONOS结构器件操作电压的结构器件。 [0001] The present invention relates to microelectronics manufacturing, and more particularly relates to a bipolar silicon SONOS memory device structure of the device structure to reduce the operating voltage.

背景技术 Background technique

[0002]随着 SONOS (Si licon-Oxide-Nitride-Oxide-Si I icon,娃-氧化物-氮化物-氧化物-硅)结构逐渐取代多晶硅浮栅极闪存结构成为非易失存储器的主要的闪存存储结构以来,关于如何改善SONOS结构的编译和擦除速度,电荷保持能力(retent1n)和器件的耐久能力(edurance)结构和方法的研宄日益增多。 [0002] As SONOS (Si licon-Oxide-Nitride-Oxide-Si I icon, baby - oxide - nitride - oxide - silicon) floating gate polysilicon structure gradually substituted flash structure made nonvolatile main since flash memory structure, a Subsidiary endurance programming and erasing speed on how to improve the SONOS structure, the charge holding capacity (retent1n) and devices (edurance) structures and methods of growing. 到目前为止,围绕SONOS存储性能的改进,研宄工作主要集中在以下几个方面:1)在存储层中引入纳米晶从而得到深势阱,提高俘获电荷稳定性。 So far, around the SONOS memory performance improvements, work focused on the study based on the following aspects: 1) introducing nanocrystals in the storage layer to obtain a potential well, to improve the stability of trapped charge. 2)通过工艺改变存储电荷氮化硅层Si/N原子百分比从而改变能带结构,提高俘获电荷的数量和稳定性。 2) changing the charge stored by a process silicon nitride layer Si / N atomic percent to change the number of the band structure and stability, improve the trapped charges. 3)设计新结构从而实现更快的存储速度。 3) design of the new structure in order to achieve faster memory speeds. 也有研宄者通过改变隧穿介质或者对阻挡氧化层进行改进来提高存储的稳定性,从而改进器件的存储性能。 There are also a Subsidiary by changing the tunneling barrier dielectric or oxide layer to improve the storage stability improved, thereby improving memory device performance. 研宄均不同程度改善了存储性能,如写/擦操作更快,操作电压窗口更宽,存储保持时间更长等等。 Study based on different degrees of improved storage properties, such as write / erase operation faster, wider operating voltage window, longer lasting memory and the like.

[0003] 对于SONOS结构而言:在编译时,为了实现电子隧穿过隧穿氧化硅层,通常需要加一个大的正门极电压(η沟道器件)。 [0003] For SONOS structure: at compile time, in order to achieve electron tunneling through the tunneling silicon oxide layer, typically requires a large main entrance of a voltage ([eta] channel device). 在擦除时,为了将电子推回到衬底或是引入空穴到存储电荷氮化硅层中与电子复合,也需要一个大的门极电压。 When erasing, electrons pushed back to the substrate or the charge is introduced into the storage holes with electrons in the silicon nitride layer, but also requires a large gate voltage. 但是大的门极电压在器件的编译和擦除循环过程中会引起隧穿氧化硅层的陷阱能级的产生和大的功耗,怎样降低编译和擦除态的大电压(电压绝对值)对器件的性能的影响和降低器件的功耗,一直是相关研宄努力的方向。 However, a large gate voltage in programming and erasing cycle will cause the device to produce a large power consumption and tunneling silicon oxide layer, a trap level, how to reduce a large voltage programming and erasing state (the absolute value voltage) impact on device performance and lower power consumption of the device, has been the driving directions study based efforts.

发明内容 SUMMARY

[0004] 本发明针对现有技术中存在的不足之处,提供一种具有低操作电压的SONOS结构器件,能降低编译时所需的门极电压, [0004] The present invention is directed to the shortcomings of the prior art provided a SONOS device structure having a low operating voltage, required for the compiler to reduce the gate voltage,

[0005] 为了实现上述目的,本发明提供一种具有低操作电压的SONOS结构器件,在具有源漏极的硅衬底上设有多层结构的栅极,所述栅极从下至上包括:隧穿氧化硅层、氮化硅层、阻挡氧化硅层、电荷存储氮化硅层和多晶硅控制栅,所述隧穿氧化硅层与硅衬底相接触;所述栅极四周设有侧墙,所述源漏极分别设在栅极两侧的硅衬底中。 [0005] To achieve the above object, the present invention provides a SONOS device structure having a low operating voltage, a multilayer structure is provided with a gate on a silicon substrate having source and drain electrodes, said gate comprising from bottom to top: tunneling silicon oxide layer, a silicon nitride layer, a silicon oxide barrier layer, a silicon nitride charge storage layer and a polysilicon control gate, the tunneling silicon oxide layer and the silicon substrate contact; surrounded by the gate sidewall spacer the source and drain are respectively provided on both sides of the gate electrode in the silicon substrate.

[0006] 在本发明一优选实施例中,所述娃衬底为P型娃衬底。 [0006] In this embodiment, the substrate is a P-type substrate baby doll In a preferred embodiment of the present invention.

[0007] 本发明另外一个目的在于提供一种形成上述的具有低操作电压SONOS结构器件的方法,在硅衬底上先后制备隧穿氧化硅层、氮化硅层、阻挡氧化硅层、电荷存储氮化硅层和多晶硅控制栅,后刻蚀除去多余部分,制作侧墙和源漏极。 [0007] Another object of the present invention is to provide a method for operating a low voltage device according to the SONOS structure is formed, it has prepared the tunneling silicon oxide layer on a silicon substrate, a silicon nitride layer, a silicon oxide barrier layer, a charge storage a silicon nitride layer and a polysilicon control gate, the excess portions removed by etching, and source and drain spacer production.

[0008] 在本发明一优选实施例中,所述娃衬底为P型娃衬底。 [0008] In this embodiment, the substrate is a P-type substrate baby doll In a preferred embodiment of the present invention.

[0009] 本发明还提供第二种形成上述的具有低操作电压SONOS结构器件的方法,首先,在硅衬底上制备隧穿氧化硅层和第一硬掩膜层,刻蚀形成栅极的隧穿氧化硅层;其次,在上述器件表面依次制备氮化硅层和第二硬掩膜层,刻蚀形成栅极的氮化硅层;然后,在上述器件表面依次制备阻挡氧化硅层和第三硬掩膜层,刻蚀形成栅极的阻挡氧化硅层;再次,在上述器件表面依次制备电荷存储氮化硅层和第四硬掩膜层,刻蚀形成栅极的电荷存储氮化硅层;最后,在器件栅极上制备多晶硅控制栅以及侧墙和源漏极。 [0009] The present invention further provides a method of operating a low voltage device according to the SONOS structure is formed of a second, first, on a silicon substrate prepared tunneling silicon oxide layer and a first hard mask layer is etched to form the gate tunneling silicon oxide layer; Next, a silicon nitride layer and the second hard mask layer are sequentially prepared in the above the device surface, etching to form a gate silicon nitride layer; then, successively, the device prepared in the above silicon oxide layer and the surface of the barrier the third hard mask layer, etching to form a gate silicon oxide barrier layer; again, the charge storage layer and a fourth nitride hard mask layer are sequentially prepared in the above the device surface, etching to form the gate of a charge storage nitride silicon layer; Finally, preparation of polycrystalline silicon and the control gate sidewall spacer on the source and drain and gate of the device.

[0010] 在本发明一优选实施例中,所述娃衬底为P型娃衬底。 [0010] In this embodiment, the substrate is a P-type substrate baby doll In a preferred embodiment of the present invention.

[0011] 本发明提供一种SONOS结构器件,在SONOS结构的阻挡氧化硅层02和多晶硅栅极之间插入一层氮化硅,使得阈值电压降低,从而使编译时所需的门极电压下降,减少由于高电压引起的应力诱导的漏电流和降低器件的功耗。 [0011] When required SONOS structure of the present invention provides a device, inserted between a layer of silicon nitride oxide silicon SONOS structure barrier layer 02 and the polysilicon gate, the threshold voltage decreases, so that the gate voltage drops compiled to reduce power consumption due to stress-induced leakage currents and high voltages due to reduction of the device.

附图说明 BRIEF DESCRIPTION

[0012] 图1是本发明提供的具有低操作电压SONOS结构器件的结构示意图。 [0012] FIG. 1 is a schematic structural diagram of a low operating voltage of the SONOS structure of the device provided by the invention.

[0013] 图2是本发明提供的SONOS结构器件在零场下的能带示意图。 [0013] FIG. 2 is a SONOS device structure of the present invention can be provided in the band diagram at zero field.

[0014] 图3 Ca)是本发明提供的SONOS结构器件在编译时的结构示意图。 [0014] FIG. 3 Ca) is a schematic view SONOS device structure of the present invention provides at compile time.

[0015] 图3 (b)是本发明提供的SONOS结构器件在编译时的能带示意图。 [0015] FIG. 3 (b) is a SONOS device structure of the present invention provides a schematic energy band diagram at compile time.

[0016] 图4 Ca)是本发明提供的SONOS结构器件在擦除时的结构示意图。 [0016] FIG. 4 Ca) is a schematic diagram of the present invention provides a SONOS device structure during erasure.

[0017] 图4 (b)是本发明提供的SONOS结构器件在擦除时的能带示意图。 [0017] FIG. 4 (b) is a SONOS device structure of the present invention provides a schematic energy band diagram during erase.

具体实施方式 Detailed ways

[0018] 本发明提供一种具有低操作电压SONOS结构器件,利用氮化硅中的两性势阱特点,既氮化硅中的陷阱电荷对于电子和空穴都有陷阱能力,这样捕获电荷的陷阱会因为外部电场的不同而不同。 Trap [0018] The present invention provides a low operation voltage SONOS device structure, the characteristics of the potential well amphoteric trapped charge in the silicon nitride, silicon nitride for both electron and hole traps have the ability, such trapped charge because of the different external electric field is different.

[0019] 在传统的阻挡氧化层和多晶硅栅极之间插入一层具有电荷存储能力的氮化硅层。 [0019] a silicon nitride layer is inserted into one of the charge storage capacity between the conventional barrier oxide layer and a polysilicon gate. 利用氮化硅的双极性电荷存储的能力,当编译时:这层氮化硅带正电,降低器件阈值电压,可在较小的门极电压下,达到编译所需的电场;擦除时:这层氮化硅带负电,有利于衬底空穴的注入,降低所需的电压(电压绝对值),从而减少由于高电压引起的应力诱导的漏电流和降低器件的功耗的效果。 Bipolar silicon nitride charge storage capacity of, when compiled: This silicon nitride layer is positively charged, the threshold voltage of the device lowered, may be at a smaller gate voltage, the electric field reaches the desired compilation; Erase time: this silicon nitride layer is negatively charged, the substrate is conducive to injection of holes, to reduce the voltage (the absolute value voltage) required to reduce the stress-induced leak current and a high voltage due to the effect of reducing power consumption of the device . 而且由于氮化硅层具有良好的抗湿法刻蚀能力,这样可以有效的减少栅氧化前清洗对ONO膜层的影响。 And because the silicon nitride layer has good resistance to wet etching ability, which can effectively reduce the cleaning effect on the film before the ONO gate oxide. 同时由于氮化硅具有较高的介电常数,在相同等效氧化层厚度(EOT)之下,可以具有更厚的物理厚度。 And because silicon nitride has a high dielectric constant, under the same equivalent oxide thickness (the EOT), may have a thicker physical thickness. 这样可以有效的减弱栅电极注入的电荷进入存储电荷的氮化硅层NI。 This can effectively reduce the gate electrode of the silicon nitride layer NI injected into the charge storing charge.

[0020] 以下通过实施例对本发明提供的具有低操作电压SONOS结构器件及其制备方法作进一步详细说明,以便更好理解本发明创造的内容,但实施例的内容并不限制发明创造的保护范围。 [0020] The following SONOS structure having a low operating voltage device and is further illustrated by the preparation method of the present invention provides embodiments in detail, in order to create a better understanding of the present invention, but the embodiments do not limit the contents of the scope of the inventions .

[0021] 实施例1 [0021] Example 1

[0022] 在准备好的P型硅衬底上先后制备隧穿氧化硅层31 (01)、存储电荷氮化硅层32(NI)、阻挡氧化硅层33 (02)、电荷存储氮化硅层34 (N2)和多晶硅控制栅35,后刻蚀除去多余部分,制作相应侧墙41、42和源漏极21、22,从而形成如图1所示的SNONS结构器件。 [0022] In the prepared P type silicon substrate prepared has the tunneling silicon oxide layer 31 (01), a silicon nitride charge storage layer 32 (NI), a silicon oxide barrier layer 33 (02), a silicon nitride charge storage layer 34 (N2) and a polysilicon control gate 35, the excess portions removed by etching, production of the corresponding side walls 41, 42 and source and drain electrodes 21 and 22, thereby forming a device structure shown in FIG. 1 SNONS.

[0023] 实施例2 [0023] Example 2

[0024] 首先,在硅衬底上制备隧穿氧化硅层31和第一硬掩膜层,刻蚀形成栅极的隧穿氧化硅层31 (01)。 [0024] First, on a silicon substrate prepared tunneling silicon oxide layer 31 and the first hard mask layer, etching to form a gate silicon oxide tunneling layer 31 (01). 其次,在上述器件表面依次制备存储电荷氮化硅层32和第二硬掩膜层,刻蚀形成栅极的氮化硅层32 (NI)。 Secondly, the preparation of a silicon nitride charge storage layer 32 and the second hard mask layer are sequentially on the surface of the above-described device, etching to form a gate silicon nitride layer 32 (NI). 然后,在上述器件表面依次制备阻挡氧化硅层33和第三硬掩膜层,刻蚀形成栅极的阻挡氧化硅层33 (02)。 Then, a silicon oxide layer sequentially prepared block 33 and the third hard mask layer on the surface of the device, a gate silicon oxide layer 33 of the barrier (02) formed by etching. 再次,在上述器件表面依次制备电荷存储氮化硅层34和第四硬掩膜层,刻蚀形成栅极的电荷存储氮化硅层34 (N2)。 Again, preparation of the charge storage layer 34 and the fourth nitride hard mask layer above the device surface are sequentially etched to form the gate of a charge storage nitride layer 34 (N2). 最后,在器件栅极上制备多晶硅控制栅35以及侧墙41、42和源漏极21、22,从而形成如图1所示的SNONS结构器件。 Lastly, a polysilicon control gate 35 and sidewall spacer 41 and source and drain electrodes 21 and 22, thereby forming SNONS device structure shown in Figure 1 was prepared on the gate of the device.

[0025] 隧穿氧化硅层31用来阻挡存储的电荷返回到衬底,存储电荷氮化硅层32用来存储电荷。 [0025] The silicon oxide tunneling barrier layer 31 to return to the charge stored in the charge used to store the substrate 32, a silicon nitride charge storage layer. 阻挡氧化硅层33用来阻挡存储的电荷进入栅极,同时也能阻挡栅极的电荷进入存储氮化硅层,氮化硅层34用来降低所需操作电压。 Silicon oxide barrier layer 33 to block the stored charge into the gate, but also to the barrier gate into the charge storage nitride layer, a silicon nitride layer 34 is used to reduce the required operating voltage.

[0026]图2是带有附加电荷存储氮化硅层N2的SONOS结构器件零场下的能带示意图。 [0026] FIG. 2 is a schematic energy band diagram at a zero field SONOS device structure with an additional charge storage nitride layer N2. 其中,存储在电荷存储氮化硅层NI中的电子或是空穴,由于隧穿氧化硅层01的高势皇和一定的介质厚度不能返回到衬底中。 Wherein electrons or holes are stored in the charge storage nitride layer in the NI Since the tunneling silicon oxide layer 01 and a high potential Huang constant thickness can not be returned to the media substrate. 而由阻挡氧化硅层02和电荷存储氮化硅N2组成的层可以防止存储的电荷流向多晶娃栅极,从而保持较好的存储电荷保持能力。 And a barrier layer made of silicon oxide and the charge storage layer 02 composed of silicon nitride can be prevented N2 stored charge flows poly baby gate, thereby maintaining good charge retention capability of the memory.

[0027] 图3 (a)和图3 (b)分别是SONOS结构进行编译时的能带和各层结构的示意图。 [0027] FIG. 3 (a) and 3 (b) are schematic band structure of layers and at compile SONOS structure. 当施加正电压时,氮化硅层(N2)中硅的悬挂键中的电子进入多晶硅栅极,使氮化硅层N2带正电。 When a positive voltage is applied, dangling bonds of silicon nitride layer (N2) of silicon electrons into the gate polysilicon, silicon nitride layer N2 is positively charged. 降低了器件的阈值电压。 It lowers the threshold voltage of the device. 对于同样的隧穿所需的电场,门极应加的电压降低。 For the same tunneling electric field required to be applied the gate voltage decreases.

[0028] 图4 Ca)和图4 (b)分别是SONOS结构进行擦除时的能带和各层结构的示意图。 [0028] FIG. 4 Ca) and 4 (b) are schematic band structure of layers and at the SONOS structure is erased. 门极施加负电压,氮化硅N2会从门极得到一部分电子,氮化硅N2带负电。 Applying a negative gate voltage, silicon nitride would be extremely N2 electronic part obtained from the gate, the silicon nitride N2 are negatively charged. 这部分电荷可以使衬底的栅极注入的速度增加。 This charge may be part of the substrate gate of the injection speed increases. 在同样的空穴隧穿电场下,所需的门极电压(电压的绝对值)下降。 In the same hole tunneling electric field, the desired gate voltage (the absolute value voltage) drops.

[0029] 以上对本发明的具体实施例进行了详细描述,但其只是作为范例,本发明并不限制于以上描述的具体实施例。 [0029] The foregoing specific embodiments of the present invention has been described in detail, but just as an example, the present invention is not limited to the specific embodiments described above. 对于本领域技术人员而言,任何对本发明进行的等同修改和替代也都在本发明的范畴之中。 To those skilled in the art, any equivalent modifications and alternatives to the present invention are also in the scope of the invention. 因此,在不脱离本发明的精神和范围下所作的均等变换和修改,都应涵盖在本发明的范围内。 Thus, variations and modifications made to uniformly without departing from the spirit and scope of the present invention, shall fall within the scope of the present invention.

Claims (6)

1.一种具有低操作电压的SONOS结构器件,其特征在于,在具有源漏极的硅衬底上设有多层结构的栅极,所述栅极从下至上包括: 隧穿氧化硅层、氮化硅层、阻挡氧化硅层、电荷存储氮化硅层和多晶硅控制栅,所述隧穿氧化硅层与硅衬底相接触; 所述栅极四周设有侧墙,所述源漏极分别设在栅极两侧的硅衬底中。 A SONOS device structure having a low operating voltage, wherein the gate is provided with a multilayer structure on a silicon substrate having a source and drain, the gate, from bottom comprising: a tunneling oxide layer, a silicon , a silicon nitride layer, a silicon oxide barrier layer, a silicon nitride charge storage layer and a polysilicon control gate, the tunneling silicon oxide layer in contact with the silicon substrate; surrounded by the gate sidewall spacer, the source and drain electrodes respectively provided on both sides of the gate electrode in the silicon substrate.
2.根据权利要求1所述SONOS结构器件,其特征在于,所述硅衬底为P型硅衬底。 2. The device according to claim 1 SONOS structure of claim wherein said silicon substrate is a P-type silicon substrate.
3.一种形成如权利要求1所述的具有低操作电压SONOS结构器件的方法,其特征在于,在硅衬底上先后制备隧穿氧化硅层、氮化硅层、阻挡氧化硅层、电荷存储氮化硅层和多晶硅控制栅,后刻蚀除去多余部分,制作侧墙和源漏极。 3. A method of forming a low operating voltage of the SONOS device structure as claimed in claim 1, wherein the preparation has a tunneling silicon oxide layer on a silicon substrate, a silicon nitride layer, a silicon oxide barrier layer, a charge storing the silicon nitride layer and a polysilicon control gate, the excess portions removed by etching, and source and drain spacer production.
4.根据权利要求3所述的方法,其特征在于,所述硅衬底为P型硅衬底。 4. The method according to claim 3, wherein said silicon substrate is a P-type silicon substrate.
5.一种形成如权利要求1所述的具有低操作电压SONOS结构器件的方法,其特征在于, 首先,在硅衬底上制备隧穿氧化硅层和第一硬掩膜层,刻蚀形成栅极的隧穿氧化硅层; 其次,在上述器件表面依次制备氮化硅层和第二硬掩膜层,刻蚀形成栅极的氮化硅层; 然后,在上述器件表面依次制备阻挡氧化硅层和第三硬掩膜层,刻蚀形成栅极的阻挡氧化硅层; 再次,在上述器件表面依次制备电荷存储氮化硅层和第四硬掩膜层,刻蚀形成栅极的电荷存储氮化硅层; 最后,在器件栅极上制备多晶硅控制栅以及侧墙和源漏极。 A method of forming a low operating voltage of the SONOS device structure as claimed in claim 1, characterized in that, first, on a silicon substrate a silicon oxide tunneling layer and a first hard mask layer is etched to form a gate silicon oxide tunneling layer; Next, a silicon nitride layer and the second hard mask layer are sequentially prepared in the above the device surface, etching to form a gate silicon nitride layer; then, successively, the surface of the device prepared in the above oxide barrier re-charge, the charge storage layer and a fourth nitride hard mask layer are sequentially prepared in the above the device surface, etching to form a gate electrode; a silicon layer and a third hard mask layer, etching to form a gate silicon oxide barrier layer storing the silicon nitride layer; Finally, preparation of polycrystalline silicon and the control gate sidewall spacer on the source and drain and gate of the device.
6.根据权利要求5所述的方法,其特征在于,所述硅衬底为P型硅衬底.。 6. The method according to claim 5, wherein said silicon substrate is a P-type silicon substrate ..
CN201210225786.8A 2012-07-03 2012-07-03 Sonos structure having a low operating voltage of the device CN102769031B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383353A (en) * 2007-08-27 2009-03-11 旺宏电子股份有限公司 Memory device having memory cell array and manufacturing process thereof
CN102097436A (en) * 2009-12-15 2011-06-15 上海华虹Nec电子有限公司 SONOS storage unit and operating method thereof

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US8208300B2 (en) * 2008-01-08 2012-06-26 Spansion Israel Ltd Non-volatile memory cell with injector

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383353A (en) * 2007-08-27 2009-03-11 旺宏电子股份有限公司 Memory device having memory cell array and manufacturing process thereof
CN102097436A (en) * 2009-12-15 2011-06-15 上海华虹Nec电子有限公司 SONOS storage unit and operating method thereof

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