JP5002172B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device that stores information by storing charges in a laminated film composed of a plurality of insulating films.

Nonvolatile semiconductor memory devices that store information by storing charges in a stacked film provided between a semiconductor substrate and a gate electrode are roughly divided into two structures with different types of stacked films. One is a FG (floating gate) type in which a conductive film is used as a part of the laminated film and charges are stored in the conductive film, and the other is an insulating film as a part of the laminated film. There are a MNOS (Metal-Nitride-Oxide-Silicon) type and a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type that store charges in this insulating film.
The FG type has a structure in which a conductive film for storing electric charges is surrounded by an oxide film as an insulator and electrically insulated. The MNOS type and the MONOS type have a structure in which a nitride film and an oxide film, which are different types of insulating films, are stacked.

  In order to extract charges from a semiconductor substrate and store them in a laminated film, a method using charge tunneling in an insulating film called FN (Fowler Nordheim) writing and a lowermost insulating film called CHE (Channel Hot Electron) injection There is a method in which electric charges are excited energetically to such an extent that the insulating barrier can be overcome.

  In a nonvolatile semiconductor memory device using a conductive film as a stacked film, injected charges are uniformly distributed in the conductive film. In a non-volatile semiconductor memory device using an insulating film for a laminated film such as a MONOS type, electric charges remain only in the vicinity of the injected insulating film. This is the difference in film quality used for the laminated film.

  When a conductive film is used for the laminated film, the injected charges are immediately and uniformly distributed, so that stable writing and erasure without unevenness can be performed. On the other hand, in recent years, by using an insulating film as a laminated film and staying in a place where charges are injected and not moving so much, by selectively injecting charges into a predetermined part of the insulating film, multi-value information The technique of writing is known, and many proposals are seen (for example, refer to Patent Document 1).

  The prior art shown in Patent Document 1 will be described. FIG. 13 is a simplified diagram for explaining the structure of a MONOS type nonvolatile semiconductor memory device, and is a diagram rewritten without departing from the gist of the prior art disclosed in Patent Document 1 for easy explanation.

  In FIG. 13, reference numeral 100 denotes a MONOS type nonvolatile semiconductor memory device, 11 denotes a p-type semiconductor substrate, 12 denotes an n-type source region, 13 denotes an n-type drain region, and 14 denotes gate insulation composed of three layers of insulating films. A film, 15 is a gate electrode, 130 is a p-type high concentration region, 141 is a tunnel oxide film, 142 is a memory nitride film, and 143 is a top oxide film.

A gate insulating film 14 is provided on the channel region between the source region 12 and the drain region 13.
The gate insulating film 14 includes a tunnel oxide film 141 that is closest to the semiconductor substrate 11, a memory nitride film 142 that is an intermediate silicon nitride film, and a top oxide film 143 that is provided as the uppermost layer. A gate electrode 15 is provided on the gate insulating film 14.
Further, a high concentration region 130 is provided in a portion in contact with the drain region 13 at the end of the channel region.

At the time of writing information, a write drain voltage that is a positive voltage is applied to the drain region 13 with the potential of the source region 12 as a reference, and a write gate voltage that is a positive voltage is applied to the gate electrode 15.
As a result, negative charges, which are minority carriers for the p-type semiconductor substrate 11, flow in the channel region from the source region 12 to the drain region 13 as a potential reference.
Negative charges are accelerated by the electric field in the channel direction within the channel region.
The accelerated negative charge obtains high energy near the end of the drain region 13 in the channel region, and is injected into the gate insulating film 14 over the potential barriers of the plurality of insulating films.

  At this time, due to the presence of the high concentration region 130, the concentration of the electric field in the channel direction is increased near the end of the drain region 13 in the channel region, and more negative charges are efficiently injected into the gate insulating film 14.

At the time of reading information, a read source voltage that is a positive voltage is applied to the source region 12 with a potential of the drain region 13 as a reference, and a read gate voltage that is a positive voltage is applied to the gate electrode 15.
As in the writing, the concentration of the electric field in the channel direction is partially increased due to the presence of the high concentration region 130 at this time.
However, the region where the electric field concentration is high is a region near the drain region 13 to which charges are supplied during reading. For this reason, when the charge passes through this region, energy sufficient to overcome the potential barriers of the plurality of insulating films is not yet obtained, and erroneous writing is prevented.

At the time of erasing information, an erase drain voltage that is a positive voltage is applied to the drain region 13 with a potential of the semiconductor substrate 11 as a reference, and an erase gate voltage that is a negative voltage is applied to the gate electrode 15.
As a result, positive charges having the opposite polarity to the written charges are supplied from the drain region 13 into the gate insulating film 14, and charges having different polarities are combined and neutralized, so that information is erased.

  The prior art disclosed in Patent Document 1 has a feature that charges are locally and efficiently stored at the end of the gate insulating film 14 by providing the high concentration region 130. In addition, this technique allows charges to be taken in and out of both ends of the gate insulating film 14, and multi-value information can be written to one nonvolatile semiconductor memory device.

Japanese Unexamined Patent Publication No. 2004-214365 (Section 5-7, FIG. 1)

  In a MNOS type or MONOS type non-volatile semiconductor memory device, in a situation where charges are stored biased toward the source region side or the drain region side of the gate insulating film on the channel region, from the source region side to the drain region side during reading It is known that the threshold value of the non-volatile semiconductor memory device to be read is different between when a current is passed and when a current is passed from the drain region side to the source region side.

  Since the prior art shown in Patent Document 1 is a technique that utilizes this, it is necessary to provide a plurality of current paths. Further, it is necessary to switch the current path in accordance with written information at the time of reading, and there is a problem that both the reading circuit and the reading method become complicated.

Further, when charge is stored in the gate insulating film at the time of information writing or the like, generally, FN writing and CHE injection require higher power consumption in CHE injection. This is because CHE injection requires a current to flow between the source region and the drain region, and the current value is such that it can overcome the insulating barrier of the lowermost insulating film constituting the gate insulating film. Since it is necessary to excite the charge energetically, the current value becomes considerably large.
In the prior art disclosed in Patent Document 1, since this CHE injection is performed when information is written, it is necessary to pass a current from the source region 12 to the drain region 13.
In recent years, semiconductor devices are required to be miniaturized and have low power consumption. The conventional technique shown in Patent Document 1 has a problem that it cannot respond to the request because CHE injection is performed in the first place.

  An object of the present invention is to provide a nonvolatile semiconductor memory device capable of storing multi-value information that can reduce power consumption.

  In order to solve the above problems, the present invention adopts the following configuration.

Semiconductor substrate provided apart source and drain regions when in the channel region provided between these regions and,
In a nonvolatile semiconductor memory device having a gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order from the semiconductor substrate side above the channel region, and having a gate electrode above the gate insulating film.
An element isolation oxide film is provided on the surface of the semiconductor substrate where the source region, drain region, and channel region are not provided,
The tunnel oxide film is in contact with the bird's beak, which is the end of the element isolation oxide film on the channel region side, and the difference between the thickness of the bird's beak and the thickness of the tunnel oxide film is perpendicular to the direction in which the current flows in the channel region. have a stepped portion thickness of the tunnel oxide film is made of a thick portion and a thin portion by,
Depending on the information to be written, the tunnel oxide film having a thin film thickness can be tunneled, and the tunnel oxide film having a thick film thickness cannot be tunneled. Data is written by switching a thin write part and a thick film part to a second write voltage that can be tunneled and applying it to the gate electrode .

The non-volatile semiconductor memory device of the present invention is a MONOS type non-volatile semiconductor memory device, and has a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order from the semiconductor substrate side on the channel region of the semiconductor substrate It has an insulating film.
The tunnel oxide film at the lowest layer of the gate insulating film has a stepped portion composed of a thick portion and a thin portion of the tunnel oxide film in a direction orthogonal to the direction in which the current flows in the channel region.

  In addition, according to the information to be written, the tunnel oxide film having a thin film thickness can be tunneled, and the tunnel oxide film having a thick film thickness cannot be tunneled. A thin write portion and a thick portion are switched to the second write voltage that can be tunneled and applied to the gate electrode.

By the configuration as described above, in a memory nitride film overlying the film thickness thin portion in plan view of the tunnel oxide film, a tunnel oxide film of the thickness of the thick portion and the memory nitride film planarly overlapping the The charge accumulation state changes.
Therefore, the state in which charges are written only in the memory nitride film that overlaps with the thin portion of the tunnel oxide film in a plane, the state in which charges are written on the entire surface of the memory nitride film, It is possible to store ternary information corresponding to the threshold values in the above three states, the state stored on the entire surface of the nitride film.

  In all the above three states, information is written by FN writing, so the distribution of charges stored in the memory nitride film is uniform in a direction parallel to the direction in which the channel region current flows. . Therefore, the threshold value does not change depending on the direction of current flow during reading, and multi-value information can be read out using one current path.

As described above, the nonvolatile semiconductor memory device of the present invention uses the FN writing by providing the step portion in the tunnel oxide film in the direction orthogonal to the direction in which the current flows in the channel region, and providing the portion having a different thickness. Even multi-value information can be stored.
Further, unlike a nonvolatile semiconductor memory device that requires CHE injection, it is not necessary to pass a current at the time of writing, so its power consumption is low and it is not necessary to provide a plurality of current paths for reading information. This has the excellent advantage of reducing the number of wires and simplifying the circuit.

[Structure of Embodiment 1: FIGS. 1 and 2]
FIG. 1 is a plan view for explaining the structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure taken along the cutting line AA ′ in FIG. In FIG. 1, the gate electrode is omitted for easy understanding of the drawing.

  1 and 2, 10 is a MONOS type nonvolatile semiconductor memory device, 11 is a p-type semiconductor substrate, 12 is an n-type source region, 13 is an n-type drain region, and 14 is a three-layer insulating film. A gate insulating film, 15 is a gate electrode, and 16 is a field oxide film which is an element isolation oxide film. Reference numeral 20 denotes a stepped portion. 141 is a tunnel oxide film, 142 is a memory nitride film, and 143 is a top oxide film. Reference numeral 150 denotes a channel region.

The source region 12 and the drain region 13 are formed in the surface layer portion of the semiconductor substrate 11 with a predetermined interval. On the semiconductor substrate 11, a gate insulating film 14 is provided on the channel region 150, which is a region that bridges the source region 12 and the drain region 13. A gate electrode 15 is provided on the gate insulating film 14.
The field oxide film 16 is provided on the semiconductor substrate 11 in which the source region 12, the drain region 13, and the channel region 150 are not provided.

The gate insulating film 14 includes a tunnel oxide film 141 that is closest to the semiconductor substrate 11, a memory nitride film 142 that is an intermediate silicon nitride film, and a top oxide film 143 that is provided as the uppermost layer.
The tunnel oxide film 141 has a step portion 20 composed of a thick portion and a thin portion in a direction orthogonal to the direction in which the current in the channel region flows.
In the example shown in FIG. 2, the step portion 20 indicates the corner portion, but the step portion 20 indicates the step formed in the tunnel oxide film 141 itself.

[Description of Operation of Embodiment 1: FIGS. 1 and 2]
Next, the operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS.

  In the method of writing information to the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the thin portion of the tunnel oxide film 141 where negative charges are thin can be tunneled and the film thickness according to the written information. A thick write portion is a first write voltage VW1 that cannot be tunneled, a negative charge is a second write voltage VW2 that can tunnel a thin portion of the tunnel oxide film, and a thick portion of the tunnel oxide film. The charge is applied to the gate electrode 15 by switching the erasing voltage VE which can be tunneled in the thin part and the thick part of the tunnel oxide film.

  Since the first write voltage VW1, the second write voltage VW2, and the erase voltage VE can use known voltage generating means, description thereof is omitted.

  Here, the threshold value when the positive charge is uniformly stored in the memory nitride film 142 of the nonvolatile semiconductor memory device is VT1, and the threshold value when the positive charge and the negative charge are not stored. Is VT2, and the threshold when negative charges are uniformly stored is VT3.

  In the first state, when the erase voltage VE is applied to the gate electrode 15 with reference to the potential of the semiconductor substrate 11, positive charges are tunneled through the tunnel oxide film 141 and accumulated in the memory nitride film 142, and the threshold value is VT1. It becomes.

As a second state, when the first write voltage VW1 is applied to the gate electrode 15 with the potential of the semiconductor substrate 11 as a reference, the memory nitride film 142 that overlaps the thin portion of the tunnel oxide film 141 in a plane is formed. Negative charges are stored, and the memory nitride film 142 that overlaps with the thick portion of the tunnel oxide film 141 in a planar manner is in a state where neither negative charges nor positive charges are stored.
The example shown in FIG. 2 represents the state of charge accumulation in the second state.

The second state shows the same electrical characteristics as a state in which the nonvolatile semiconductor memory device having the threshold value VT3 and the nonvolatile semiconductor memory device having the threshold value VT2 are electrically connected in parallel. In other words, when a read voltage of VT2 or higher is applied to the gate electrode 15, a channel is formed on the surface of the semiconductor substrate 11 that overlaps with the thick portion of the tunnel oxide film 141 in a planar manner, and the source region 12 to the drain region 13 Current flows into the.
Therefore, it can be said that the threshold value of the nonvolatile semiconductor memory device 10 in the second state is VT2.

  As a third state, when the second write voltage VW2 is applied to the gate electrode 15 with reference to the potential of the semiconductor substrate 11, negative charges are tunneled through the tunnel oxide film 141 and accumulated on the entire surface of the memory nitride film 142. The threshold value is VT3.

  As described above, by associating information with the first, second, and third states, it is possible to store ternary information in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. .

[Description of Structure of Second Embodiment: FIG. 3]
Next, the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described. FIG. 3 is a sectional view thereof. Since the planar structure of the second embodiment is the same as that of the first embodiment already described, description thereof is omitted.

  In FIG. 3, 10 is a MONOS nonvolatile semiconductor memory device, 11 is a p-type semiconductor substrate, 14 is a gate insulating film made of a three-layer insulating film, 15 is a gate electrode, and 16 is a field oxide film. A bird's beak 16 a is an end of the field oxide film 16. Reference numeral 20 denotes a stepped portion. 141 is a tunnel oxide film, 142 is a memory nitride film, and 143 is a top oxide film.

The structure of the second embodiment is different from the structure of the first embodiment in the configuration of the gate insulating film 14.
In the first embodiment, the tunnel oxide film 141 has a thick part and a thin part, and the memory nitride film 142 and the top oxide film 143 are planar with the tunnel oxide film 141. It was the structure provided in the overlapping area | region.
On the other hand, in the second embodiment, the tunnel oxide film 141 is constituted only by a thin portion, and the memory nitride film 142 and the top oxide film 143 are only in a region overlapping the tunnel oxide film 141 in a plane. In other words, it also overlaps the portion where the bird's beak 16a, which is the end of the field oxide film 16, is in contact with the tunnel oxide film 141. That is, the bird's beak 16a is in contact with the tunnel oxide film 141 and has a continuous shape as the same oxide film. The bird's beak 16a and the tunnel oxide film 141 constitute the stepped portion 20. Therefore, in the example shown in FIG. 3, there are two step portions 20.

  In such a configuration, the bird's beak 16a can also function as a part of the gate insulating film, which is the same as providing a thick part in the tunnel oxide film 141 in the first embodiment. The effect is obtained.

  Since the operation of the second embodiment is similar to the operation of the first embodiment already described, the description thereof is omitted.

[Description of Manufacturing Method of First Embodiment: FIGS. 4 to 9]
Next, a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. Since the same number is given to the same configuration as already described, the description is omitted. Note that the orientations of the configurations shown in FIGS. 4 to 9 are the same as the orientations of the configurations shown in FIG.

First, as shown in FIG. 4, a field oxide film 16 which is an element isolation oxide film is formed on the semiconductor substrate 11 by using a known LOCOS isolation method, and then a dummy oxide film is formed on the surface of the semiconductor substrate 11. A dummy oxide film 140 is formed using a formation process. Here, the dummy oxide film forming step is, for example, a thermal oxidation step in an atmosphere in which oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.

Next, the removal process will be described with reference to FIG.
First, a photoresist 30 is formed on the field oxide film 16 and the dummy oxide film 140 by using a known photolithography technique.
Here, the region where the photoresist 30 is formed is a region excluding a portion where the thickness of the tunnel oxide film 141 is reduced in the completed nonvolatile semiconductor memory device of the present invention.
Next, using the photoresist 30 as a mask, the dummy oxide film 140 is removed using a dry etching technique to expose the surface of the semiconductor substrate 11.
Thereafter, the photoresist 30 is removed using a wet etching technique.

Next, the tunnel oxide film forming step will be described with reference to FIG.
First, the surfaces of the semiconductor substrate 11, the dummy oxide film 140, and the field oxide film 16 are thermally oxidized in an atmosphere in which, for example, oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.
By this thermal oxidation process, an oxide film is formed in a portion other than the region where the field oxide film 16 is formed, so that the newly formed oxide film and the dummy oxide film 140 are formed seamlessly in the channel region 150. As a result, a tunnel oxide film 141 is formed. The tunnel oxide film 141 is thick only in the portion where the dummy oxide film 140 is formed, whereby the stepped portion 20 is formed.

Next, the nitride film forming step and the top oxide film forming step will be described with reference to FIG.
First, the memory nitride film 142 is formed on the surfaces of the tunnel oxide film 141 and the field oxide film 16 using a nitride film forming process. In this step, for example, it is formed by a CVD method using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) as a reaction gas.
Next, a top oxide film 143 is formed on the surface of the memory nitride film 142 by a top oxide film forming step. In this step, for example, it is formed by thermal oxidation in a steam atmosphere using an oxidation diffusion furnace.

Next, the gate insulating film forming process will be described with reference to FIG.
First, as shown in FIG. 8, a photoresist 31 is formed on the top oxide film 143 by using a known photolithography technique.
Using the photoresist 31 formed on the top oxide film 143 as a mask, the top oxide film 143, the memory nitride film 142, and the tunnel oxide film 141 are removed using a dry etching technique. By this step, the gate insulating film 14 is formed only on the channel region 150.
Later, the photoresist 31 is removed using a wet etching technique.

Next, the process of forming a gate electrode is demonstrated using FIG.
First, although not shown, a polysilicon film for forming the gate electrode 15 is formed on the entire upper surface of the semiconductor substrate 11 using the CVD method. In this step, for example, monosilane (SiH ₄ ) is used as a reaction gas.
Thereafter, as shown in FIG. 9, a photoresist 32 is formed on a portion where the gate electrode 15 is to be formed by using a known photolithography technique, and the polysilicon film is removed by using the dry etching technique by using this as a mask. .
Later, the photoresist 32 is removed using a wet etching technique.
As a result, the gate electrode 15 is completed on the gate insulating film 14.

  Next, the source region 12 and the drain region 13 are formed by a known ion implantation method, thereby completing the structure that forms the basis of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. Thereafter, using a known technique, an interlayer insulating film, various wirings and the like (not shown) are formed, and the semiconductor device having the nonvolatile semiconductor memory device according to the first embodiment of the present invention is completed.

[Description of Manufacturing Method of Second Embodiment: FIGS. 10 to 12]
Next, a manufacturing method according to the second embodiment of the present invention will be described with reference to FIGS. The description of the same steps as those of the manufacturing method of the first embodiment of the present invention already described is omitted.

First, the element isolation oxide film forming step will be described with reference to FIG.
As shown in FIG. 10, a field oxide film 16 that is an element isolation oxide film is formed on a semiconductor substrate 11 by using a known LOCOS isolation method. At this time, a bird's beak 16 a having a smaller thickness than the other regions of the field oxide film 16 is formed at the end of the field oxide film 16.
The bird's beak 16a can be formed freely by selecting the formation conditions of the field oxide film 16 and, in particular, the thickness thereof.

Next, the tunnel oxide film forming step will be described with reference to FIG.
First, the surfaces of the semiconductor substrate 11 and the field oxide film 16 are thermally oxidized in an atmosphere in which, for example, oxygen (O ₂ ) and nitrogen (N ₂ ) are mixed.
By this thermal oxidation process, a tunnel oxide film 141 is formed in a portion other than the region where the field oxide film 16 is formed. The tunnel oxide film 141 is in contact with the bird's beak 16a and has a continuous shape as the same oxide film. Thereby, the step part 20 is formed.

Next, a gate insulating film forming process will be described with reference to FIG.
First, as shown in FIG. 12, the memory nitride film 142 and the top oxide film 143 are formed on the surfaces of the tunnel oxide film 141 and the field oxide film 16 as in the manufacturing method of the first embodiment of the present invention.
Next, a photoresist 33 is formed on the top oxide film 143 by using a known photolithography technique. At this time, the photoresist 33 is formed not only in a region overlapping the tunnel oxide film 141 above the channel region 150 but also in a region overlapping the bird's beak 16 a above the channel region 150. That is, the photoresist 33 also covers the upper part of the bird's beak 16a.

Using the photoresist 33 thus formed on the top oxide film 143 as a mask, the top oxide film 143, the memory nitride film 142, and the tunnel oxide film 141 are removed using a dry etching technique. By this step, a gate insulating film constituted by the top oxide film 143, the memory nitride film 142, the tunnel oxide film 141, and the bird's beak 16a is formed.
Later, the photoresist 33 is removed using a wet etching technique.

Next, the gate electrode 15 is formed in the same manner as in the manufacturing method of the first embodiment of the present invention, and the source region 12 and the drain region 13 are formed by a known ion implantation method. Thus, the structure that forms the basis of the nonvolatile semiconductor memory device according to the embodiment is completed. Thereafter, using a known technique, an interlayer insulating film (not shown), various wirings and the like are formed, and the second embodiment of the present invention.
A semiconductor device having the nonvolatile semiconductor memory device of the embodiment is completed.

  The manufacturing method according to the second embodiment of the present invention differs from the manufacturing method according to the first embodiment of the present invention in that there is no dummy oxide film 140 forming step and part of the dummy oxide film 140 removing step. That is. This is because the stepped portion 20 is formed by the difference between the film thickness of the bird's beak 16 a and the film thickness of the tunnel oxide film 141.

  In the manufacturing method of the second embodiment of the present invention described above, the tunnel oxide film 141 is formed with a film thickness thinner than that of the bird's beak 16a. However, the present invention is not limited to this. The tunnel oxide film 141 may be formed thicker than the bird's beak 16a. What is important is that the tunnel oxide film 141 and the bird's beak 16a have different thicknesses, and the stepped portion 20 is thereby formed.

  The nonvolatile semiconductor memory device of the present invention has low power consumption and can store multi-value information. Therefore, the nonvolatile semiconductor memory device is suitable for portable electronic devices that require low power consumption and computer devices that require high integration. is there.

1 is a plan view illustrating a basic structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 is a cross-sectional view illustrating a basic structure of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is sectional drawing explaining the basic structure of the non-volatile semiconductor memory device of the 2nd Embodiment of this invention. It is sectional drawing explaining the manufacturing process of the field oxide film and dummy oxide film of the non-volatile semiconductor memory device of the 1st Embodiment of this invention. It is sectional drawing explaining formation of the dummy oxide film of the non-volatile semiconductor memory device of the 1st Embodiment of this invention. It is sectional drawing explaining formation of the tunnel oxide film of the non-volatile semiconductor memory device of the 1st Embodiment of this invention. FIG. 3 is a cross-sectional view illustrating formation of a memory nitride film and a top oxide film of the nonvolatile semiconductor memory device according to the first embodiment of the invention. It is sectional drawing explaining formation of the gate insulating film of the non-volatile semiconductor memory device of the 1st Embodiment of this invention. It is sectional drawing explaining formation of the gate electrode of the non-volatile semiconductor memory device of the 1st Embodiment of this invention. It is sectional drawing explaining formation of the field oxide film and bird's beak of the non-volatile semiconductor memory device of the 2nd Embodiment of this invention. It is sectional drawing explaining formation of the tunnel oxide film of the non-volatile semiconductor memory device of the 2nd Embodiment of this invention. It is sectional drawing explaining formation of the gate insulating film of the non-volatile semiconductor memory device of the 2nd Embodiment of this invention. It is sectional drawing explaining the non-volatile semiconductor memory device of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Nonvolatile semiconductor memory device 11 Semiconductor substrate 12 Source region 13 Drain region 14 Gate insulating film 15 Gate electrode 16 Field oxide film 16a Bird's beak 20 Step part 30-33 Photoresist 100 Nonvolatile semiconductor memory device 130 High concentration area | region 140 Dummy oxide film 141 Tunnel oxide film 142 Memory nitride film 143 Top oxide film 150 Channel region

Claims (1)

A source region and a drain region are provided apart from each other on a semiconductor substrate, and a channel region is provided between these regions,
In the nonvolatile semiconductor memory device having a gate insulating film having a structure in which a tunnel oxide film, a memory nitride film, and a top oxide film are stacked in this order from the semiconductor substrate side above the channel region, and having a gate electrode above the gate insulating film.
An element isolation oxide film is provided on the surface of the semiconductor substrate where the source region, the drain region, and the channel region are not provided.
The tunnel oxide film is in contact with a bird's beak that is an end portion of the element isolation oxide film on the channel region side, and the thickness of the bird's beak and the tunnel oxide film are perpendicular to the direction in which the current flows in the channel region. Having a step portion consisting of a thick portion and a thin portion of the tunnel oxide film due to the difference in film thickness,
Depending on the information to be written, the tunnel oxide film having a thin film thickness can be tunneled, and the tunnel oxide film having a thick film thickness cannot be tunneled. A nonvolatile semiconductor memory device, wherein data is written by switching a thin write portion and a thick portion to a second write voltage that can be tunneled and applying the second write voltage to the gate electrode.

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