JP2005328029A - Nonvolatile semiconductor storage element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage element contributing to improvement in the speed of data rewriting operation and the miniaturization and high density of the element, and to provide a method for manufacturing the nonvolatile semiconductor storage element. <P>SOLUTION: The nonvolatile semiconductor storage element is provided with a source area 6 and a drain area 7 which are formed on a semiconductor substrate 1, a tunnel insulating layer 2 formed on a channel formation area, a charge holding layer 3 for holding charge injected from the channel, an inter-gate insulating layer 4, and a control gate 5. The charge holding layer 3 is constituted of ultrafine particulates (a work function is ≥4.2 eV) which are independently dispersed at the density of 10<SP>12</SP>to 10<SP>14</SP>particulates/cm<SP>3</SP>serving as floating gates having grain size of ≤5 nm, and a mother phase insulator (amorphous substance of which electron affinity is ≤1.0 eV). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory element and a method for manufacturing the same, and more particularly to a nonvolatile semiconductor memory element having a charge retention layer composed of ultrafine particles functioning as a floating gate and a matrix insulator and a method for manufacturing the same. .

  Conventionally, as a large-capacity storage element or recording medium for storing data in a rewritable manner, there are semiconductor storage elements such as DRAM and SRAM, or rotating disk type recording media such as a hard disk, a magneto-optical disk, and an optical disk. Systems have been developed and used. Among these, DRAMs having characteristics such as high data writing and reading speed and easy high integration have been widely used as temporary storage elements such as personal computers. However, since the DRAM is a volatile memory (which means that the stored record disappears when the external power supply is stopped), an external power supply is required to maintain the record. is necessary. For this reason, DRAMs are not normally used in devices such as portable terminal devices that require a reduction in power consumption, because this leads to an increase in power consumption.

  On the other hand, the hard disk system or the like has no data volatility, but has the disadvantages that the writing and reading speed is slower and the power consumption is relatively higher than that of the above storage element. Moreover, there exists a fault that it is weak to a mechanical vibration and an impact on an apparatus structure. For this reason, a rotating disk type recording medium is usually not used in many portable terminal devices.

  Along with the recent expansion of the mobile terminal equipment market, the storage element used in mobile terminal equipment is non-volatile, has a large storage capacity, can be written and read at high speed, and is free from mechanical vibration during use. However, there is a demand for a device having stable performance and low power consumption. In addition, it is also required that it can be easily created using conventional semiconductor manufacturing technology.

  Here, as a memory element that satisfies the above requirements, nonvolatile semiconductor memory elements such as a flash memory, a ferroelectric memory, an MRAM (Magnetic Random Access Memory), and a phase change memory are currently in a development stage or a partial practical stage. However, future use is expected.

  The nonvolatile semiconductor memory element has advantages and disadvantages as described below, for example. First, MRAM has many advantages such as high writing speed and a large number of rewritable times, and is said to be one of the most promising candidates as a replacement memory for DRAM. However, since the memory cell of the MRAM is composed of a transistor and a TMR (Tunnel Magneto Resistive) element (tunnel magnetoresistive element), the structure is relatively complicated, and it is difficult to miniaturize the element. Therefore, there are problems such as the fact that it cannot be easily produced and that it is necessary to introduce a ferromagnetic material with many technical problems in the production process. Above all, there is a problem that it is difficult to establish a manufacturing technique of a TMR element with small variation in characteristics.

  On the other hand, a memory cell of a flash memory basically has a simple configuration composed of a single transistor, so that the cell size can be reduced and miniaturized using conventional DRAM process technology. It is possible to easily manufacture a flash memory having the same. For these reasons, flash memory has already formed a large market as a storage element for portable terminal devices. In recent years, high-speed and miniaturization of semiconductor devices has been promoted, but along with this trend, research for high performance such as device miniaturization, high-speed, and improvement of charge retention capability is also active in flash memory. Line 40 is an ultrafine particle floating gate type nonvolatile semiconductor memory element.

  Of the flash memories currently used as storage elements for portable terminal devices, a NOR type flash memory will be described as an example. First, regarding the read time from the NOR flash memory, the read of the retained data from the designated memory cell is completed in a relatively short time of about 100 ns or less.

  On the other hand, data is written by channel hot electron (CHE) injection from the channel to the floating gate, but the charge injection efficiency of CHE injection (which means the ratio of the injection current to the supply current) is low. The time required for writing data becomes longer than the time required for reading data. In addition, data is erased by charge discharge by a Fowler-Nordheim (hereinafter referred to as FN) tunnel current from the floating gate to the channel formation region or source, but it takes time to discharge the charge by the FN tunnel current. Therefore, the time required for erasing data is longer than the time required for reading data.

  Specifically, it takes a relatively long time of 1 μs for writing and several hundred ms to several s for erasing. For this reason, even though it is relatively easy to increase the capacity and cost of the flash memory, its application is limited, and replacement with a high-speed memory such as a DRAM is difficult. In order to solve such a problem, there is an attempt to reduce the time required for charge discharge or charge injection, which reduces the physical thickness of the tunnel insulating layer between the channel and the floating gate to control the rewrite time. .

  However, if this tunnel insulating layer is made thin, a very strong electric field inversely proportional to the thickness of the tunnel insulating layer is applied to the tunnel insulating layer when the floating gate is charged. Stresses due to the passage of a large number of times, and the tunnel insulating layer is likely to break down.

  If breakdown occurs anywhere in the tunnel insulating layer, the current flash memory is a bulk floating gate type flash memory, so most of the charge held in the floating gate leaks. Data retention ability is lost. Therefore, at present, in order to maintain charge retention reliability, the thickness of the tunnel insulating layer has to be increased to about 10 nm, and it is difficult to shorten the rewriting time. In addition, since there is a law that the thickness of the tunnel insulating layer and the size of the entire device are reduced in a similar manner, it also hinders miniaturization of the entire device.

  Furthermore, as the flash memory is highly integrated, the gap between the floating gates between adjacent elements is reduced, and the capacitive coupling between the adjacent floating gates is strengthened. It has been pointed out that this causes mutual floating gates to affect each other, such as a change in the potential of the floating gate of the element adjacent to the element at the specified address, and malfunctions are likely to occur during reading and writing. The influence of capacitive coupling between adjacent floating gates is particularly remarkable in a NAND flash memory in which the progress of high integration is remarkable.

  For the above reasons, it has been said that the advancement of miniaturization and higher density of the above-mentioned bulk floating gate type flash memory device will become increasingly difficult in the future and even reach the limit of miniaturization as early as around 2007. ing.

As a technology that realizes high-speed operation, prevents a decrease in charge retention capability due to dielectric breakdown, and reduces the effect of parasitic capacitance between floating gates of adjacent elements, the floating gate is divided into multiple parts, and the gate with the conventional structure There is a technique in which held charges are spatially dispersed and held.
Non-volatile semiconductor memory using this technology is a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory, or a SONOS (MONOS memory in which the gate electrode material is replaced from a metal to a semiconductor. For example, Poly-Si is used.

FIG. 4 is a diagram showing an example of a conceptual cross-sectional structure of a transistor constituting the MONOS memory. 4 includes a p-type semiconductor substrate 1, a tunnel insulating layer 2 made of an oxide film, and a SiN _x film that is stacked on the tunnel insulating layer 2 instead of a floating gate. The charge holding layer 3, the insulating layer 4 made of an oxide film stacked on the charge holding layer 3, the control gate 5, the source region 6, and the drain region 7.

The transistor that constitutes the MONOS memory 40 has at least two types of levels that retain electric charges. One of which is the interface level 43a ₁ in the interface between the charge retention layer 3 made of the tunnel insulating layer 2 or the insulating layer 4 and the SiN _x film and one charge retention consisting the SiN _x film The trap levels 43 a ₂ are discretely distributed in the layer 3. The transistors constituting the MONOS memory 40 are configured to separate and hold charges at these levels.

Since the interface level 43a ₁ and the trap level 43a ₂ for holding charges are distributed spatially discrete, even breakdown occurs in any one place of the tunnel insulating layer 2, the insulating Charge leakage due to breakdown occurs only locally. Therefore, even if local dielectric breakdown occurs in part, the charge retention capability of the memory cell can be substantially maintained. For the above reasons, the MONOS memory is superior to the current bulk floating gate type flash memory in terms of the number of times of rewriting and the physical thickness of the tunnel insulating layer 2 can be made relatively thin, so that the memory cell is miniaturized. It is also advantageous in that it can be done.

However, the depth of the trap level of the charge holding layer 3 made of the SiN _x film (for electrons, the energy difference between the trap level and the bottom of the conduction band, for holes, the trap level and the top of the valence band) Is not necessarily deep enough to trap the charge, and the trapped charge is easy to escape, and there is an element that does not have absolute charge retention capability (current leakage due to dielectric breakdown). It has a drawback that it is low.

  On the other hand, the problem of the breakdown of the tunnel insulating layer and the problem of the parasitic capacitance between adjacent floating gates can be solved by holding charges discretely as in the case of the MONOS memory, and more absolute charge retention than the MONOS memory. As a method for further enhancing the capability, a structure in which a large number of Si ultrafine particles are dispersed in a gate insulating layer to form a floating gate is considered.

  FIG. 5 is a diagram showing an example of a conceptual cross-sectional structure of a semiconductor memory element using Si ultrafine particles as a floating gate (see, for example, Patent Document 1). Among the components constituting the semiconductor memory element 50 shown in FIG. 5, the same components as those constituting the MONOS memory 40 shown in FIG. 4 are denoted by the same reference numerals and description thereof is omitted. To do. In the technique disclosed in Patent Document 1, a large number of Si ultrafine particles 53 formed by a CVD method are formed as floating gates on the tunnel insulating layer 2 as shown in FIG.

When Si ultrafine particles 53 containing no impurities are used as a floating gate, the injected electrons are trapped in the conduction band level of Si, and the height of the potential barrier viewed from the trapped electrons This is the difference between the conduction band level of each of the surrounding oxide films (tunnel insulating layer 2 and insulating layer 4) and the conduction band level of Si, that is, the difference in electron affinity between Si and the oxide film. Since this potential barrier is generally deeper than the barrier formed by the trap in the charge retention layer 3 made of the SiN _x film of the MONOS memory 40, the trapped electrons are unlikely to move to the semiconductor substrate 1, the control gate 5, and the like. Therefore, the charge retention capability of the semiconductor memory element 50 having the cross-sectional structure shown in FIG. 5 is higher than that of the MONOS memory.

  However, from the viewpoint of the height of the potential barrier described above, Si as a material constituting the ultrafine particles cannot be said to be an excellent material for obtaining a high charge retention capability. Needless to say, since Si is a semiconductor, electrons confined in Si fine particles occupy a conduction band of Si higher than the Fermi level. On the other hand, when a metal is used for the above fine particles, the electrons confined in the metal fine particles occupy the Fermi level.

The level of electrons confined in Si can be expressed by the electron affinity, which is the energy difference between the vacuum level and the bottom of the conduction band, and the levels of electrons confined in the metal are the vacuum level and the Fermi level. It can be expressed by a work function that is an energy difference of Here, the electron affinity of Si is generally smaller than the work function of metal. For this reason, the potential barrier formed between the Si ultrafine particles and the oxide film is generally lower than the potential barrier formed between the metal fine particles and the oxide film. FIG. 6 theoretically shows the probability that electrons trapped in the ultrafine particles of each material tunnel to the Si substrate through the insulating layer of the SiO ₂ film when Si, W and Co ultrafine particles are used as the floating gate. It is a figure which shows the calculated result. The horizontal axis of the graph represents the thickness of the tunnel insulating layer of the SiO ₂ film through which electrons are transmitted. According to this result, the tunnel probability when using the Si floating gate is about 2 to 5 digits higher than when using the metal floating gate of W or Co. That is, the leakage current from the Si floating gate is 100 to 100,000 times larger than that of the metal floating gate. As a result, the use of Si as a fine particle material for the floating gate has caused a reduction in charge retention capability from the viewpoint of material properties.
Japanese Patent Laid-Open No. 11-186421

  However, such a conventional flash memory such as a bulk floating gate type flash memory, a MONOS memory, a SONOS memory, or an Si ultrafine particle floating gate type flash memory has a low charge holding capability as described above. There was a problem that it was difficult to reduce the thickness. Further, since it is difficult to reduce the thickness of the tunnel insulating layer, as described above, it is difficult to improve the speed of data writing and erasing operations and miniaturize and increase the density of elements. It was.

  The present invention has been made to solve such problems, and improves the speed of data writing and erasing operations by improving the charge retention capability in a room temperature environment and a high temperature environment as compared with conventional devices. The present invention also provides a nonvolatile semiconductor memory element that contributes to miniaturization and high density of the element and a method for manufacturing the same.

It has the following gist.
1. A tunnel insulating layer formed on a semiconductor substrate and formed on a source region, a drain region, and a channel formation region for forming a channel between the source region and the drain region; and A charge retention layer that retains charges injected from the channel through the channel, an intergate insulating layer formed on the charge retention layer, and an electric charge retained in the charge retention layer formed on the intergate insulating layer In the non-volatile semiconductor memory device including a control gate for performing control to be released or released, the charge retention layer includes one super-element having a particle diameter of 5 nm or less made of a single element substance or compound that functions as a floating gate. 10 ¹ per square centimeter, having an average particle diameter of 5 nm or less, consisting of fine particles, or one or more of the above-mentioned single element substances or compounds. A plurality of ultrafine particles independently dispersed in ^{two 1014} pieces of density, each said configured by a matrix insulator surrounding a part or the whole of the ultrafine particles, each of the ultrafine particles work function than 4.2eV A non-volatile semiconductor memory element made of a good conductor material, wherein the matrix insulator is made of an amorphous substance having an electron affinity of 1.0 eV or less.

  With this configuration, the dispersion density and particle diameter of the ultrafine particles are optimized, and the energy barrier height is optimized by selecting the materials constituting the ultrafine particles and the matrix insulator. It is possible to improve the charge retention capability in a room temperature environment and a high temperature environment as compared with the device, and to reduce the thickness of the tunnel insulating layer, to improve the speed of data writing and erasing operations, and to the device It is possible to realize a nonvolatile semiconductor memory element that contributes to miniaturization and high density.

2. A tunnel insulating layer formed on a semiconductor substrate and formed on a source region, a drain region, and a channel formation region for forming a channel between the source region and the drain region; and A charge retention layer that retains charges injected from the channel through the channel, an intergate insulating layer formed on the charge retention layer, and an electric charge retained in the charge retention layer formed on the intergate insulating layer In the non-volatile semiconductor memory device including a control gate for performing control to be released or released, the charge retention layer includes one super-element having a particle diameter of 5 nm or less made of a single element substance or compound that functions as a floating gate. 10 ¹ per square centimeter, having an average particle diameter of 5 nm or less, consisting of fine particles, or one or more of the above-mentioned single element substances or compounds. ^{It is} composed of a plurality of ultrafine particles independently dispersed at a density of ² to 10 ¹⁴ and a matrix insulator surrounding a part or all of each ultrafine particle, and each ultrafine particle has an electron affinity of 4.2 eV or more A nonvolatile semiconductor memory element, wherein the matrix insulator is made of an amorphous material having an electron affinity of 1.0 eV or less.

  With this configuration, the dispersion density and particle diameter of the ultrafine particles are optimized, and the energy barrier height is optimized by selecting the materials constituting the ultrafine particles and the matrix insulator. It is possible to improve the charge retention capability in a room temperature environment and a high temperature environment as compared with the device, and to reduce the thickness of the tunnel insulating layer, to improve the speed of data writing and erasing operations, and to the device It is possible to realize a nonvolatile semiconductor memory element that contributes to miniaturization and high density.

  3. 3. The nonvolatile semiconductor memory element according to 1 or 2, wherein an absolute value of a difference between a work function of the single element substance or the compound forming each ultrafine particle and a work function of the semiconductor substrate is 0.5 eV or less.

  With this configuration, in addition to the effects of the above-described nonvolatile semiconductor memory element 1 or 2, the density of ultrafine particles, the particle diameter, and the like have been optimized, so that the charge retention capability can be improved over conventional elements. In addition to making the tunnel insulating layer thinner, it can improve the speed of data write and erase operations, and contribute to the miniaturization and high density of the elements, as well as the substances that make up each ultrafine particle Since the absolute value of the difference between the work function of the semiconductor substrate and the work function of the semiconductor substrate is 0.5 eV or less, the charge can be prevented from moving from the semiconductor substrate to the ultrafine particles before the writing operation for injecting the charges into the ultrafine particles. Realizes a nonvolatile semiconductor memory device that can prevent the transfer of charges, which are not useful for information retention, to ultrafine particles during operation in room temperature and high temperature environments Kill.

  4). 3. The nonvolatile semiconductor memory element according to 1 or 2, wherein an absolute value of a difference between a work function of the single element material or the compound forming each ultrafine particle and a work function of the control gate is 0.5 eV or less.

  With this configuration, the absolute value of the difference between the work function of the substance forming each ultrafine particle and the work function of the control gate is 0.5 eV or less in addition to the effect of the nonvolatile semiconductor memory element of 1 or 2 above. Nonvolatile semiconductor memory capable of preventing charge from moving from control gate to ultrafine particle before writing operation for injecting charge into ultrafine particle and preventing transfer of charge which is not useful for information retention to ultrafine particle An element can be realized.

  5). The method for manufacturing a nonvolatile semiconductor memory element according to any one of 1 to 4, wherein the charge retention layer is formed by physical vapor deposition.

  With this configuration, the physical vapor deposition method is likely to cause phase separation, so that it is possible to easily create the charge retention layer of the nonvolatile semiconductor memory element having the effect of any one of the nonvolatile semiconductor memory elements 1 to 4 above. The manufacturing method of the non-volatile semiconductor memory element which can be realized is realizable.

  6). The method for manufacturing a nonvolatile semiconductor memory element according to any one of 1 to 4, wherein the charge retention layer is formed by a sputtering method.

  With this configuration, the sputtering method can be used for a wide range of film forming materials, easy to obtain a dense film, a film having high adhesion to the base, and excellent mass productivity. To 4. The method for manufacturing a nonvolatile semiconductor memory element capable of suitably manufacturing the charge retention layer of the nonvolatile semiconductor memory element having the effect of any one of the nonvolatile semiconductor memory elements from 1 to 4 can be realized.

In the present invention, since the dispersion density and particle diameter of the ultrafine particles have been optimized, the height of the energy barrier has been optimized by selecting the materials constituting the ultrafine particles and the parent phase insulator. It is possible to improve the charge retention capability in a room temperature environment and a high temperature environment as compared with the device, and to reduce the thickness of the tunnel insulating layer, to improve the speed of data writing and erasing operations, and to the device It is possible to provide a nonvolatile semiconductor memory element having an effect of contributing to miniaturization and high density of the semiconductor device and a method for manufacturing the same. The theoretical explanation for this can be explained using FIG. FIG. 6 can also be seen as a diagram showing the tunnel probability when electrons trapped in the floating gate pass through the insulating layer, using the work function or electron affinity of the material constituting the floating gate as a parameter. Here, each curve shown in FIG. 6 is obtained when an SiO ₂ film having an electron affinity of 1.0 eV is used as the insulating layer. From this graph, it can be seen that the higher the work function or the electron affinity of the material as the floating gate, the lower the tunnel probability. In other words, to obtain the same tunnel probability, the thickness of the SiO ₂ film can be reduced as the material having a higher work function is used.

  In addition, the explanation about the optimization of the height of the energy barrier, that is, the explanation about the difference in tunnel probability depending on the material used for the floating gate, as shown in FIG. The present invention can be applied not only to suppressing the dissipation to the control gate, but also to suppressing the movement of electrons between adjacent ultrafine particles. As a result, even when the density of the ultrafine particles used for the floating gate is increased, it is possible to obtain electrical insulation between the ultrafine particles by using the ultrafine metal particles rather than using the ultrafine Si particles as the floating gate. Can do. As a result, it contributes to the reliability of charge retention of the element and the stabilization of multi-value operation.

  Hereinafter, embodiments of the present invention will be described.

  FIG. 1 is an explanatory diagram conceptually showing a cross-sectional structure of a nonvolatile semiconductor memory element according to an embodiment of the present invention. In FIG. 1, a nonvolatile semiconductor memory element 10 is formed on a semiconductor substrate 1, and a channel formation region for forming a source region 6, a drain region 7, and a channel between the source region 6 and the drain region 7. A tunnel insulating layer 2 formed thereon, a charge holding layer 3 for holding charges injected from the channel through the tunnel insulating layer 2, an intergate insulating layer 4 formed on the charge holding layer 3, And a control gate 5 which is formed on the inter-gate insulating layer 4 and controls the charge holding layer 3 to hold or release charges.

The charge retention layer 3 includes one ultrafine particle 3a having a particle diameter of 5 nm or less made of a single element substance or compound that functions as a floating gate, or an average particle made of one or more kinds of single element substances or compounds. A plurality of ultrafine particles 3a having a diameter of 5 nm or less and independently dispersed at a density of 10 ¹² to 10 ¹⁴ per square centimeter, and a matrix insulator 3b surrounding part or all of each ultra fine particle. Here, the above average particle size means, for example, that 10% of the ultrafine particles dispersed in the region excluding the peripheral portion of the element are removed from the larger particle size, and the particle size is small. The arithmetic average when 10% of ultrafine particles are removed from the side is assumed.

  Here, the parent phase insulator 3b is an insulator composed of a film-like region surrounding part or all of the side surface of each ultrafine particle 3a. Therefore, the charge retention layer 3 is composed of the ultrafine particles 3a dispersed in the matrix insulator 3b and the matrix insulator 3b. Further, the mother phase insulator 3b may be made of a material different from that of the tunnel insulating layer 2 and the intergate insulating layer 4. Similarly, the tunnel insulating layer 2 and the inter-gate insulating layer 4 may be made of different materials.

In the following, a p-type semiconductor substrate is used as the semiconductor substrate 1, but an SOI (Silicon On Insulator) substrate having a buried oxide film (Buried Oxide, BOX) may be used. Here, as the tunnel insulating layer 2, an oxide film such as SiO ₂ having relatively good interface bonding with the p-type semiconductor substrate 1, and the controllability of the electric field distribution on the surface of the p-type semiconductor substrate 1 by the control gate voltage. For example, a material such as a SiO _x N _y (0 ≦ x <2, 0 <y ≦ 4/3) material or HfO ₂ having a high dielectric constant can be preferably used.

Further, as the material of the tunnel insulating layer 2, the use of a nitrogen compound insulating film such as SiN _x (0 <x ≦ 4/3 ₎ or a non-Si oxide such as HfO ₂ or LaO _x is a floating gate material. In the case where heavy metal is employed, it is extremely desirable because part of the heavy metal of the floating gate material can be prevented from diffusing to the semiconductor substrate 1 side through the tunnel insulating layer and changing the threshold voltage of the MOSFET.

  The film thickness of the tunnel insulating layer 2 is preferably as thin as possible in order to perform data writing / erasing operations at high speed, and is preferably 8 nm or less. Furthermore, it is extremely preferable that the thickness of the tunnel insulating layer 2 be 5 nm or less in order to increase the speed.

  It is preferable that a large number of the ultrafine particles 3a constituting the charge retention layer 3 are dispersed in order to suppress the loss of accumulated charges due to the dielectric breakdown of the tunnel insulating layer 2 as much as possible. However, it is more preferable to disperse the ultrafine particles 3a so that the distance between the ultrafine particles 3a is not less than a predetermined value so as to ensure electrical insulation between the ultrafine particles 3a. The particle size of the ultrafine particles 3a is preferably 5 nm or less.

On the other hand, for the purpose of increasing the threshold voltage shift amount (ΔVth, memory window) due to the presence or absence of accumulated charges in the ultrafine particles 3a, and suppressing the increase in variation of the threshold voltage shift amount, the ultrafine particles 3a. The surface density of the charge retention layer 3 is preferably high, and is preferably 10 ¹² to 10 ¹⁴ / cm ² . Further, as the ultrafine particles 3a and the mother phase insulator 3b, it is preferable to use a high-melting point material, which will be described later, having resistance to high-temperature processing in the semiconductor manufacturing process.

  In order to improve the charge retention capability of the charge retention layer 3, the ultrafine particles are arranged in two or more stages, that is, a three-dimensional multilayer structure (like the charge retention layer 23 constituting the nonvolatile semiconductor memory element 20 shown in FIG. On the other hand, it is also effective to use the charge retention layer 3 shown in FIG. 1 as a charge retention layer having a single layer structure. In other words, the charge retention layer 23 of the nonvolatile semiconductor memory element 20 has a structure in which a plurality of single-layer charge retention layers are stacked.

Hereinafter, the reason why the charge retention capability is improved by the multilayer structure will be described assuming that the ultrafine particles in the charge retention layer have a two-layer structure. First, the ultrafine particle layers constituting the charge retention layer 23 are defined as a first layer 3a ₁ and a second layer 3a _{2 in} order from the side closer to the semiconductor substrate 1, respectively. In the state where charges (electrons in the present embodiment) are accumulated in both the first layer 3a ₁ and the second layer 3a ₂ , the electrons accumulated in the second layer 3a ₂ enter the semiconductor substrate 1. To leak, the leakage of electrons from the second layer 3a ₂ to the semiconductor substrate 1 is inhibited by the electrostatic potential formed by the electrons of the first layer 3a ₁ existing in the middle of the leak path. As a result, the charge retention capability is improved in the case of the multilayer structure than in the case of the single layer structure.

The effect in which the movement of charged particles having the same sign of “+” or “−” is inhibited by the electrostatic potential formed by the ultrafine particles in which charges are accumulated is called the Coulomb blockade effect. In order to exhibit this effect, it is necessary that ΔE = q ² / (2C) is sufficiently higher than thermal energy (also referred to as fluctuation energy) determined by temperature. Here, q is the charge amount of the charged particles injected into the ultrafine particles, C is the tunnel junction capacitance between the regions having the potential to be tunneled, and ΔE is that the ultrafine particles accumulate the charge q. This is the increase in electrostatic potential due to, that is, the height of the Coulomb blockade barrier.

From the equation of ΔE = q ² / (2C), the height ΔE of the Coulomb blockade barrier increases as the charge amount q of the charged particles forming the electrostatic potential increases and the tunnel junction capacitance C decreases. The blockade effect is easily developed. Therefore, in order to sufficiently exhibit the Coulomb blockade effect, it is preferable that each of the ultrafine particles is small.
In order to obtain the Coulomb blockade effect spatially and uniformly, it is preferable that the surface density of the ultrafine particles be as high as 10 ¹² to 10 ¹⁴ / cm ² .

From the viewpoints of improving the controllability of the electric field distribution near the surface of the p-type semiconductor substrate 1 in accordance with the control gate voltage and increasing the discharge operation at the time of data erasing, the inter-gate insulating layer 4 It is preferable to form a thin film using a material having a high dielectric constant. By doing so, the capacitive coupling between the control gate 5 and the semiconductor substrate 1 and the capacitive coupling between the control gate 5 and the floating gate, that is, the ultrafine particles 3a can be strengthened. Specifically, the SiO ₂ film, the SiO _x N _y (0 ≦ x <2, 0 <y ≦ 4/3) film, or the SiO ₂ film and the SiO _x N _y (0 ≦ x <2, 0 <y ≦ 4/3) A film with a thickness of 10 nm or less is preferable.

  On the other hand, from the viewpoint of increasing the memory window obtained per unit charge amount with respect to the charge accumulated in the ultrafine particles 3a constituting the floating gate, or the charge accumulated in the ultrafine particles 3a leaks to the control gate 5. From the viewpoint of suppressing this, it is preferable that the intergate insulating layer 4 is thick. From the above, the material and thickness of the inter-gate insulating layer are adjusted or determined according to the characteristics required for the memory device.

  The charge retention layer 3 is formed using a so-called physical vapor deposition method. As a method for forming a thin film for the charge retention layer 3, a chemical vapor deposition method (chemical vapor deposition method, also called CVD method) or the like is known in addition to a physical vapor deposition method. However, the CVD method has a higher gas phase pressure at the time of film formation than the physical film formation method, and therefore the collision frequency of the reactive atomic species and molecular species in the gas phase is high, and the gas phase and substrate surface temperature are high. Thus, a single-phase film without phase separation, that is, an equilibrium phase film is easily formed. Therefore, the chemical vapor deposition method is suitable for the purpose of forming a film of a quasi-equilibrium phase or a non-equilibrium phase in which the ultrafine particles 3a such as the charge retention layer 3 of the present invention and the matrix insulator 3b are separated. Absent.

  On the other hand, the charge retention layer 3 can be formed by a single process by using a physical vapor deposition method. Examples of physical vapor deposition include sputtering, thermal vapor deposition, electron beam vapor deposition, laser ablation, and molecular beam epitaxy. Among these, the sputtering method is particularly preferable because it can select a wide range of film forming materials, easily obtain a dense film, and obtain a film with high adhesion to a base, and is excellent in mass productivity.

Further, as a sputtering apparatus, an apparatus using an inductively coupled plasma (ICP) or an electromagnetically coupled plasma (ECR plasma) or a counter target type apparatus is used because the damage to the underlying tunnel oxide film is small. What is used is more preferable.
The sputtering method is preferable because a substrate temperature suitable for self-organization when forming ultrafine particles can be obtained. Specifically, self-organization can be caused by migrating film-forming seed particles on the surface of the semiconductor substrate at an appropriate substrate temperature in the element creation process.

  Here, the self-organization means that the atomic group constituting the ultrafine particle 3a and the atomic group constituting the matrix insulator 3b are spontaneously separated from each other by thermodynamic interaction, and the like. As a result, nanoscale ultrafine particles of metal or semiconductor are organized in the insulator. This phenomenon depends on the combination of the constituent material of the ultrafine particles 3a and the constituent material of the mother phase insulator 3b, the target creation conditions such as the abundance ratio, and the deposition conditions such as the vapor pressure during deposition and the substrate temperature. To do.

  The self-organization can be realized relatively easily by appropriately selecting the materials of the ultrafine particles 3a and the matrix insulator 3b, generating the target, and appropriately selecting the sputtering conditions, and the charge retention layer 3 can be formed. . The sputtering method is a suitable film forming method capable of obtaining a thermodynamic condition suitable for manifestation of self-organization.

  When the charge retention layer 3 is formed by sputtering, a material for forming the ultrafine particles 3a (hereinafter referred to as an ultrafine particle phase dispersed in the matrix insulator 3b) is used as a target for film formation. And a mixed target including both the material forming the phase of the mother phase insulator 3b. The method of creating the mixed target is not limited to a specific method, and a single-phase target composed of a mixture of both phase powder materials and sintered, or one phase material, It may be produced by embedding an appropriate number of chip pieces of the material of the other phase so as to be exposed on the surface.

  In addition, when the sputtering surface of the target is installed vertically upward in the film forming chamber of the film forming apparatus, an appropriate number of chip pieces of the other phase material are placed on the single phase target of the one phase material. Or a mixture of both phases mixed in a glass petri dish can be used as a target. However, the powder target is not so preferable in manufacturing a semiconductor device because the powder is scattered in a film forming environment and may adversely affect other element manufacturing processes.

  When the charge retention layer 3 is formed, a material for obtaining a phase composed of ultrafine particles appearing as a dispersed phase in the charge retention layer 3 (hereinafter referred to as ultrafine particle dispersed phase), and a matrix insulator 3b are obtained. As a combination with a material (hereinafter referred to as a matrix phase material), a combination material that causes phase separation between a material of an ultrafine particle dispersed phase and a matrix phase material during film formation is selected.

The material for the ultrafine particle dispersed phase can be selected from any of metals, semiconductors, and insulators, but from the viewpoint of obtaining a high charge retention capability, a substance having as large a work function or electron affinity as possible is preferable. Theoretically, as shown in FIG. 6, the tunnel probability when passing through an insulator around the ultrafine particles capturing electrons differs depending on the material constituting the ultrafine particles, and the work function of the material Or it is explained from the fact that the greater the electron affinity, the lower the tunnel probability. In addition, the difference in work function of the material used for the floating gate also affects the charge retention capability of the device in a high temperature environment. In a high-temperature environment, the thermal energy of the retained charge (this thermal energy takes a value proportional to kT, where k is a Boltzmann constant and T is an absolute temperature) is higher than that in a room temperature environment. Will lower the potential barrier. Furthermore, the energy band gap of the insulator surrounding the floating gate has a relatively strong temperature dependence. In the case of SiO ₂ or the like that is most frequently used as an insulator, the band gap tends to become smaller as the temperature rises, and the influence of gap reduction accompanying the temperature rise is so large that it cannot be ignored. Due to the effects of thermal energy of retained charge and gap reduction accompanying temperature rise, the potential barrier in high temperature environment is reduced to a negligible level compared to that in room temperature environment, which degrades charge retention capability at high temperature. It is a factor. At this time, by using a metal having a large work function for the floating gate, it becomes possible to sufficiently compensate for the potential barrier effectively lowered in a high temperature environment. Compared to the case where Si is used for the floating gate even in a high temperature environment. The tunnel probability can be kept low. Therefore, using a material with a high work function for the floating gate is a charge in a high-temperature environment rather than using a material with a low work function or a semiconductor whose potential barrier is substantially lowered as the temperature rises, such as Si. The holding ability can be increased. Specifically, a material having a work function of 4.2 eV or more is preferable for a metal material, and a material having an electron affinity of 4.2 eV or more is preferable for a semiconductor and an insulator material. In addition, it is preferable to use a high melting point material as a material for the ultrafine particle dispersed phase because of its excellent heat resistance against heat treatment in the element fabrication process.

  Furthermore, as a material for the ultrafine particle dispersed phase, from the viewpoint of increasing the effective height of the potential barrier that prevents the electrons trapped in the ultrafine particles from jumping to the outside, and obtaining a high charge retention capability, A material that is as close as possible to the work function of the control gate is preferred. Specifically, the absolute value of the work function difference between the material of the ultrafine particle dispersed phase and the material of the semiconductor substrate, or the absolute value of the work function difference between the material of the ultrafine particle dispersed phase and the material of the control gate is The material is 0.5 eV or less.

  This is due to the following reason. When materials having different work functions are joined, in a thermal equilibrium state, electrons move from one material to another so that the Fermi levels of the materials coincide with each other. Therefore, when the work function of the ultrafine particles is excessively high, the action of moving electrons from the semiconductor substrate to the ultrafine particles works strongly, and the electrons spontaneously flowed into the ultrafine particles before injecting the electrons into the ultrafine particles. It becomes a state.

  If electrons are to be injected for writing data from this state, the second and subsequent electrons are injected. Hereinafter, for convenience of explanation, the above “second and subsequent electrons” are referred to as “second electrons”. Here, since the size of the ultrafine particles is on the order of nm, the energy level that can be taken by the electrons is quantized, and the second electron injected into the ultrafine particles has an energy level higher than the ground level ( Usually, it occupies the excitation level directly above.)

If the energy difference between the ground level and the level just above the ground level by quantization is ΔE _Q, and the energy rising by the Coulomb blockade is ΔE _CB , the second electron is in the tunnel insulating layer. The second electron needs to occupy an energy level higher than the ground level by ΔE _Q + ΔE _CB . As a result, the effective work function of the ultrafine particles was relatively lowered by ΔE _Q + ΔE _CB in order to determine whether the data in which the presence or absence of the second electron is written is “0” or “1”. Is equivalent to When the work function of the ultrafine particles is excessively high, an effective work function may be lowered because a state where electrons are constantly trapped is formed.

  As metal materials for ultrafine particles, Os, Pt, Pd, Ni, Au, Co, Be, Rh, Te, Re, Ru, Cu, Mo, Sb, W, Cr having a work function of 4.2 eV or more. Fe, Ir, Sr, Se, Ba, etc., or alloys thereof, or alloys containing these as main components are suitable. From the viewpoint of heat resistance, the melting point of the ultrafine particles is preferably 1400 ° C. or higher.

  Furthermore, the material for the ultrafine particles is such that when the atoms constituting the ultrafine particles enter a semiconductor substrate, for example, a Si substrate, and form a recombination center, this recombination center is the center of the gap of the semiconductor substrate, for example, the Si substrate. Is preferably at least 0.1 eV or more from. This is because if there is an electron-hole recombination center in the part where the channel is formed, the probability of electron-hole recombination via this recombination center is a function of the energy of the recombination center from the center of the gap. This is because it changes with the reciprocal of the hyperbolic cosine function. In the nonvolatile semiconductor memory element 10, since minority carriers are used for operation, such as electrons flowing through a channel formed in a p-type semiconductor substrate, the influence of recombination is larger. In addition, since the ultrafine particles are formed at positions close to the order of nanometers on the channel and the distance between the ultrafine particles and the channel is small, the influence of the diffusion of atoms constituting the ultrafine particles into the channel becomes a problem. As described above, if the energy of the recombination center from the center of the gap is 0.1 eV or more, the recombination probability can be suppressed to the extent necessary for the operation of the nonvolatile semiconductor memory element 10. . From the viewpoint of the work function, melting point, and impurity level, specifically, W, Mo, Ti, Pt, Pd, Ni, Ta, Cr and the like are preferable, but Os, Re, Nb, Ru Rh may be used.

  Further, as the elemental semiconductor for ultrafine particles, it is preferable to use any one of semiconductors such as Si, Ge, amorphous Se, and amorphous Te. The semiconductor may include at least one element of P, As, Sb, B, Al, Ga, In, and Cu as an impurity. Here, the use of Si doped with impurities as ultrafine particles has the effect of reducing the lifetime of minority carriers even if atoms constituting the ultrafine particles or impurity atoms diffuse to reach the semiconductor substrate 1. This is preferable because the influence on the fluctuation of the threshold voltage of the transistor can be reduced.

As compound semiconductors or insulators for ultrafine particles, InAs, InGaAs, InGaNAs, InAlAs, InAsP, InGaAsP, InSb, InGaSb, InAlSb, InGaAsSb, SiC, Cu ₂ O, ZnO, CdO, BaO, PbO, NiO, In ₂ O ₃ , Sb ₂ O ₃ , SnO ₂ , Ag ₂ O, AgO, RuO ₂ , V ₃ Ga, Nb ₃ Sn, Nb ₃ Al, Nb ₃ Ga, Nb ₃ Ge, NbTi, NbMo ₆ S ₈ , ZnS, CdS _{, HgS, PbS, Sb 2 S} 3, Bi 2 S 3, ZnSe, CdSe, HgSe, SnSe, PbSe, In 2 Se 3, Sb 2 Se 3, BiSe 3, ZnTe, CdTe, HgTe, SnTe, PbTe, In 2 _{Te 3, Bi 2 Te 3,} BN, GaN, I _{N, TiN, BP, AlP,} GaP, InP, Zn 3 P 2, Cd 3 P 2, ZnP 2, CdP 2, AlAs, GaAs, Zn 3 As 2, Cd 3 As 2, ZnAs 2, CdAs 2, AlSb, It is preferably at least one compound of GaSb, ZnSb, CdSb, and Si ₃ N ₄ .

Among these substance groups, at least one compound of In ₂ O ₃ , Sb ₂ O ₃ , SnO ₂ , ZnO, and GaAs is at least one of Sn, Sb, Ga, Al, and In. An element may be included as an impurity.

  The material of the parent phase insulator can be selected from either a semiconductor or an insulator, but its electron affinity is as much as possible from the viewpoint of increasing the potential barrier against electrons trapped in the ultrafine particles and obtaining high charge retention capability. Small materials are preferred. Specifically, a material having an electron affinity of 1.0 eV or less is preferable. In addition, it is preferable to use a high-melting-point substance as a material for the parent phase insulator because it has excellent heat resistance against heat treatment in the element manufacturing process.

  Furthermore, it is preferable to use an amorphous material as the parent phase insulator in the following points. That is, when electrons trapped in ultrafine particles leak through the parent phase insulator due to tunnel conduction, the tunnel electrons are more amorphous than the crystalline one when the parent phase insulator is crystalline. This is because the probability of being scattered by the constituent atoms constituting the is increased. As a result, it is expected that the effective amount of leakage due to electron tunneling is reduced. The melting point of the matrix insulator is preferably 1,400 ° C. or higher. When the melting point of the matrix insulator and the ultrafine particles is 1,400 ° C. or higher, the growth of the ultrafine particles can be suppressed even in the heat treatment of the semiconductor process, and the dispersion structure of the ultrafine particles can be maintained.

Specific examples of matrix insulators include oxides such as silica, alumina, titania, mullite, cordierite, spinel, zeolite, and forsterite, and carbides such as boron carbide (B ₄ C), silicon nitride, and boron nitride. A nitride such as aluminum nitride, a fluoride such as magnesium fluoride or aluminum fluoride, or any two or more of these compounds may be used.

FIG. 3 is an energy diagram in a state where electrons 37 are injected into the ultrafine particles 3a.
FIGS. 3A and 3B are energy diagrams when a metal and a semiconductor are used as the ultrafine particles 3a, respectively. By injecting electrons into the ultrafine particles 3a, the energy of the ultrafine particles 3a is increased by the Coulomb blockade action, and the bottom level 35 of the conduction band of the tunnel insulating layer 2 and the intergate insulating layer 4 is tilted. It is shown that the Fermi level of the fine particles 3a is higher than the Fermi level of the semiconductor substrate 1.

  In FIG. 3, the upper end level of the valence band is indicated by reference numeral 31, the Fermi level is indicated by reference numeral 32, the bottom level of the conduction band is indicated by reference numeral 33, the Fermi level of metal ultrafine particles is indicated by reference numeral 34, and the tunnel insulating layer 2 The height of the energy barrier is represented by reference numeral 36, and the bottom level of the conduction band of the ultrafine particles 3a is represented by reference numeral 38. FIG. 3 shows an example in which a material such as polysilicon is used as the control gate 5.

  When forming the charge retention layer 3 by sputtering, the average particle diameter of each ultrafine particle grown in the region of the matrix phase can be changed by controlling the target composition and film formation conditions. In particular, it has been confirmed that the average particle diameter of each ultrafine particle varies depending on the volume fraction of the dispersed phase portion and the matrix phase portion, and the film forming conditions such as the Ar gas pressure during sputtering and the substrate temperature. Yes.

Specifically, when forming a film in which Co metal ultrafine particles are dispersed in a SiO ₂ insulator using a Co—SiO ₂ target, the volume ratio of Co to SiO ₂ is set to 50:50 and 0.5 Pa. When the film is formed at an Ar gas pressure of Co, the particle diameter of the ultrafine particles made of Co is about 2 nm, whereas when the film is formed at an Ar gas pressure of 8 Pa, the particle diameter of the ultrafine particles made of Co is It has been confirmed that the thickness is about 5 nm.

  From the above, as the charge retention layer 3, ultrafine particles 3a having a particle diameter of 5 nm or less made of a material having a work function or electron affinity of 4.2 eV or more are converted into an amorphous matrix phase insulation having an electron affinity of 1.0 eV or less. By using a film dispersed in the body, a large amount of charges can be independently dispersed and retained, and the ability to retain electrons can be improved.

  As described above, the nonvolatile semiconductor memory element according to the embodiment of the present invention is optimized for the dispersion density, particle diameter, etc. of the ultrafine particles, and the material constituting the ultrafine particles and the parent phase insulator. Since the height of the energy barrier has been optimized by selecting the device, the charge retention capability can be improved as compared to the conventional device, and the thickness of the tunnel insulating layer can be reduced. This can contribute to an increase in operation speed and miniaturization and high density of the device.

  In addition, since the semiconductor material having an electron affinity of 4.2 eV or more can be used as the ultrafine particles 3a, the types of materials that can be used as the ultrafine particles can be expanded, and the degree of freedom in device design can be increased. Can be expanded.

  In addition, since the absolute value of the difference between the work function of the substance forming each ultrafine particle 3a and the work function of the semiconductor substrate 1 is 0.5 eV or less, the semiconductor substrate 1 before the write operation for injecting charges into the ultrafine particle 3a is performed. It is possible to prevent the charge from moving to the ultrafine particles 3a, and it is possible to prevent the charge that is not useful for retaining information from moving to the ultrafine particles 3a.

  In addition, since the absolute value of the difference between the work function of the substance forming each ultrafine particle 3a and the work function of the control gate 5 is 0.5 eV or less, the control gate 5 is in a state before the writing operation for injecting charges into the ultrafine particle 3a. It is possible to prevent the charge from moving to the ultrafine particles 3a, and it is possible to prevent the charge that is not useful for retaining information from moving to the ultrafine particles 3a.

  Further, when a physical vapor deposition method is used for forming the charge retention layer 3, the physical vapor deposition method easily causes phase separation, so that the charge retention layer of the nonvolatile semiconductor memory element can be easily formed. Further, when the sputtering method is used for forming the charge retention layer 3, the sputtering method can select a wide range of film forming materials, easily obtain a dense film, obtain a film having high adhesion to the base, and mass productivity. Therefore, the charge retention layer of the nonvolatile semiconductor memory element can be preferably manufactured.

  Further features of the nonvolatile semiconductor memory element of the present invention will be specifically described with reference to the following examples.

  The nonvolatile semiconductor memory element of this example will be described with reference to FIG. The tunnel insulating layer 2 was formed by thermally oxidizing the p-type semiconductor substrate 1 in an oxygen atmosphere at a temperature of 800 ° C. for a treatment time of 5 nm. The processing time for forming the tunnel insulating layer 2 having a film thickness of 5 nm was determined based on the relationship between the processing time and the film thickness measured in advance.

After the tunnel insulating layer 2 was formed, the charge retention layer 3 having a thickness of 5 nm was formed by the capacitive coupling type magnetron sputtering method in the following manner. Metal Co having a work function of 5.0 eV was selected as the material of the ultrafine particles 3a constituting the charge retention layer 3, and SiO ₂ having a work function of 1.0 eV was selected as the material of the matrix insulator 3b. As a sputtering target, a 5 mm square Co chip placed on a 3 inch (7.62 cm) diameter SiO ₂ target was used. As the amount of the Co chip, 20% of the vertical projected surface area of the target was the amount occupied by the area of the Co chip.

During film formation, the film formation chamber of the sputtering apparatus was evacuated to 5 × 10 ⁻⁴ Pa, and then Ar gas was introduced, and the gas flow rate was adjusted so that the gas pressure in the film formation chamber was 0.5 Pa. Plasma was generated by inputting high-frequency (13.56 MHz) power of 200 W. Under the above conditions, a film (hereinafter, referred to as a Co—SiO ₂ -based charge retention layer) in which the ultrafine particles 3a are made of Co and the matrix insulator 3b is made of SiO ₂ was formed. As a result of observing the thus formed Co—SiO ₂ -based charge retention layer with a TEM (transmission electron microscope), Co crystal ultrafine particles having an average particle diameter of about 2 nm were found to be about 8 × 10 6 in amorphous SiO _2. It was confirmed that it was dispersed with a surface density of ¹² / cm ² .

An SiO ₂ film was formed as the intergate insulating layer 4 on the Co—SiO ₂ charge retention layer, and then tungsten nitride (W ₂ N) and tungsten were stacked as the control gate 5 by sputtering. Thereafter, a SiO ₂ film used as a hard mask was formed. Patterning was performed using a positive photoresist as a mask for gate etching, and the SiO ₂ hard mask was etched. Then, tungsten and tungsten nitride as the control gate 5, the intergate insulating layer 4, and the charge retention layer 3 were dry etched.

  Thereafter, As (which may be P) is ion-implanted, and further annealing is performed to activate the carriers to form the source region 6 and the drain region 7. Next, a protective film was formed, contact holes were formed after the protective film was formed, and an Al electrode was formed so as to contact the source region 6, the drain region 7, and the control gate 5.

The memory cell using the Co—SiO ₂ -based charge retention layer thus prepared as the charge retention layer 3 has a charge retention time of 20 years or longer compared to each memory cell using Si as the material of the ultrafine particles 3a. It was shown to be extremely long. The charge retention time was obtained by extrapolating the measurement results.

  A nonvolatile semiconductor memory element according to Example 2 will be described with reference to FIG. In Example 2, an SOI (Silicon On Insulator) substrate (hereinafter referred to as a semiconductor substrate 21) was used as the semiconductor substrate. In FIG. 2, a semiconductor substrate 21 includes a substrate 1a, a buried oxide film 1b with a thickness of 100 nm provided on the substrate 1a, and a buried p-type SOI layer 1c with a thickness of 50 nm provided on the buried oxide film 1b. Consists of.

  The nonvolatile semiconductor memory element according to Example 2 has a mesa structure to provide isolation between elements, and a gate control voltage threshold value is adjusted by boron (B) implantation. The work function of the p-type SOI layer 1c of the nonvolatile semiconductor memory element thus produced was estimated to be 4.95 eV. Thereafter, the tunnel insulating layer 2 was formed on the p-type SOI layer 1c. This tunnel insulating layer 2 is obtained by thermally oxidizing the semiconductor substrate 21 at 800 ° C. in an oxygen atmosphere, and has a film thickness of 3 nm.

Thereafter, a charge retention layer 23 composed of the ultrafine particles 3a ₁ , 3a ₂ and the mother phase insulator 3b was formed to a thickness of 3 nm as follows by a capacitively coupled magnetron sputtering method. Metal Ru having a work function of 4.7 eV was selected as the material of the ultrafine particles 3a ₁ and 3a ₂ , and AlN having negative electron affinity was selected as the material of the matrix insulator 3b. In this case, the work function difference between the p-type SOI substrate 1c and the Ru ultrafine particles 3a ₁ and 3a ₂ is 0.25 eV. For sputtering, a sintered target obtained by sintering a powder of high purity Ru and high purity AlN mixed at a volume ratio of 15:85 was used.

During film formation, the film formation chamber of the sputtering apparatus was evacuated to 5 × 10 ⁻⁴ Pa, and then Ar gas was introduced, and the gas flow rate was adjusted so that the gas pressure in the film formation chamber was 0.5 Pa. Plasma was generated by inputting high-frequency (13.56 MHz) power of 200 W. Under the above conditions, a film (hereinafter, referred to as a Ru—AlN-based charge retention layer) in which the ultrafine particles 3a ₁ and 3a ₂ are made of Ru and the mother phase insulator 3b was made of AlN was formed.

Next, a SiO ₂ film was formed as an inter-gate insulating layer 4 on the Ru—AlN charge retention layer by low pressure CVD. Next, polycrystalline Si was formed as a control gate 5 on the intergate insulating layer 4 made of a SiO ₂ film by low pressure CVD. Thereafter, a positive photoresist was formed as a mask for gate etching, and the polycrystalline Si serving as the control gate 5, the intergate insulating layer 4, and the charge retention layer 23 were dry etched.

Next, As ions were implanted shallowly with low energy to form the junction regions 6a and 7a, and a SiO ₂ film was formed by low-pressure CVD. Side walls 8 were formed by anisotropic etching of the SiO ₂ film. Thereafter, As ions are implanted somewhat deeply to form contact regions 6b and 7b, and carriers are activated by RTA (Rapid Thermal Anneal) treatment to form source regions 6 consisting of junction regions 6a and 7a and contact regions 6b and 7b, A drain region 7 was formed. Next, a protective film is formed, and contact holes for obtaining electrical contact with the source region 6, the drain region 7, and the control gate 5 are formed, and the source region 6 and the drain region are formed through these contact holes. 7. An Al electrode was formed in contact with the control gate 5.

  The nonvolatile semiconductor memory element according to the present invention can improve the charge retention capability as compared with the conventional element and can reduce the thickness of the tunnel insulating layer, and can increase the speed of data writing and erasing operations. It can also be applied to uses such as a nonvolatile semiconductor memory element and a method for manufacturing the same, which are useful in improving and contributing to miniaturization and higher density of the element.

Explanatory drawing which shows notionally the cross-section of the non-volatile semiconductor memory element concerning embodiment of this invention Explanatory drawing which shows notionally the cross-section of the non-volatile semiconductor memory element with which the arrangement | sequence of an ultrafine particle has multilayer structure based on embodiment of this invention Energy diagram in which electrons 27 are injected into the ultrafine particles 3a The figure which shows an example of the conceptual cross-section of the transistor which comprises a MONOS memory The figure which shows an example of conceptual sectional structure of the semiconductor memory element which uses Si ultrafine particle as a floating gate Figure Si as a floating gate, in the case of using the W and Co ultra-fine particles, electrons trapped in the ultrafine particles of the materials showing the probability of tunneling insulating layers of SiO ₂ film

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 21 Semiconductor substrate 1a Substrate 1b Embedded oxide film 1c SOI layer 2 Tunnel insulating layer 3, 23, 53 Charge retention layer 3a, 3a ₁ , 3a ₂ Ultrafine particle 3b Mother phase insulator 4 Intergate insulating layer 5 Control gate 6 Source Region 6a, 7a Junction region 6b, 7b Contact region 7 Drain region 8 Side wall 10, 20 Non-volatile semiconductor memory element 31 Upper level of valence band 32, 34 Fermi level 33, 38 Bottom level of conduction band 35 Level of bottom of conduction band of insulator 36 Energy barrier height of tunnel insulating layer 37 Electron in ultrafine particle 40 MONOS memory 43a ₁ interface level 43a ₂ trap level 50 Semiconductor memory element

Claims (6)

A tunnel insulating layer formed on a semiconductor substrate and formed on a source region, a drain region, and a channel formation region for forming a channel between the source region and the drain region; and A charge retention layer that retains charges injected from the channel through the channel, an intergate insulating layer formed on the charge retention layer, and an electric charge retained in the charge retention layer formed on the intergate insulating layer In a non-volatile semiconductor memory device comprising a control gate for performing control to be released or released,
The charge retention layer has an average particle diameter of one ultrafine particle having a particle diameter of 5 nm or less made of a single element substance or compound functioning as a floating gate, or one or more kinds of the single element substance or compound. Is composed of a plurality of ultrafine particles independently dispersed at a density of 10 ¹² to 10 ¹⁴ per square centimeter, and a matrix insulator surrounding a part or all of each of the ultra fine particles,
Each of the ultrafine particles is made of a good conductor material having a work function of 4.2 eV or more,
The nonvolatile semiconductor memory element, wherein the matrix insulator is made of an amorphous material having an electron affinity of 1.0 eV or less. A tunnel insulating layer formed on a semiconductor substrate and formed on a source region, a drain region, and a channel formation region for forming a channel between the source region and the drain region; and A charge retention layer that retains charges injected from the channel through the channel, an intergate insulating layer formed on the charge retention layer, and an electric charge retained in the charge retention layer formed on the intergate insulating layer In a non-volatile semiconductor memory device comprising a control gate for performing control to be released or released,
The charge retention layer has an average particle diameter of one ultrafine particle having a particle diameter of 5 nm or less made of a single element substance or compound functioning as a floating gate, or one or more kinds of the single element substance or compound. Is composed of a plurality of ultrafine particles independently dispersed at a density of 10 ¹² to 10 ¹⁴ per square centimeter, and a matrix insulator surrounding a part or all of each of the ultra fine particles,
Each of the ultrafine particles is made of a semiconductor material having an electron affinity of 4.2 eV or more,
The nonvolatile semiconductor memory element, wherein the matrix insulator is made of an amorphous material having an electron affinity of 1.0 eV or less. 3. The nonvolatile semiconductor memory element according to claim 1, wherein an absolute value of a difference between a work function of the single element substance or the compound forming each ultrafine particle and a work function of the semiconductor substrate is 0.5 eV or less. . 3. The nonvolatile semiconductor memory according to claim 1, wherein an absolute value of a difference between a work function of the single element substance or the compound forming each ultrafine particle and a work function of the control gate is 0.5 eV or less. element. 5. The method of manufacturing a nonvolatile semiconductor memory element according to claim 1, wherein the charge retention layer is formed by a physical vapor deposition method. 6. Method. 5. The method of manufacturing a nonvolatile semiconductor memory element according to claim 1, wherein the charge retention layer is formed by a sputtering method. 6.

Images