KR101608886B1 - Nonvolatile Memory Device - Google Patents

Abstract

A non-volatile memory device is disclosed. The disclosed nonvolatile memory device is characterized in that the active region is formed of a first type material, which is either n-type or p-type material, and the source region is formed of a second type material different from the active region, Can be improved.

Description

[0001] Nonvolatile Memory Device [0002]

The disclosed embodiments relate to non-volatile memory devices, and more particularly, to non-volatile memory devices having improved electrical characteristics by forming active and source regions of different types of materials.

BACKGROUND OF THE INVENTION The performance of semiconductor memory devices has been developed with a focus on increasing the information storage capacity and the speed of recording and erasing the information. A typical semiconductor memory array structure includes a large number of memory unit cells connected in a circuit, and includes a nonvolatile memory and a volatile memory such as a dynamic random access memory (DRAM) Volatile Memory).

Various types of memory devices have been introduced as nonvolatile memories. For example, a semiconductor memory device in which a GMR (Giant Magneto-Resistance) structure or a Tunneling Magneto-Resistance (TMR) structure is formed on a transistor has been introduced to utilize the magnetoresistance characteristic. In addition, a novel structure of non-volatile memory such as PRAM (Phase-change Random Access Memory) using a phase transition material characteristic and SONOS having a tunneling oxide layer, a charge storage layer and a blocking oxide layer structure, volatile semiconductor memory devices are emerging.

Recently, various devices using an oxide thin film transistor have been studied. This is due to various advantages of the oxide thin film transistor in comparison with the conventional Si technology. For example, stacking is possible Transparent, transparent, and flexible (fFlexible) devices. However, when the oxide thin film transistor is applied to a memory device, there is a problem in its usability due to a problem of information erasing process.

According to an aspect of the present invention, there is provided a nonvolatile memory device including an oxide thin film transistor.

Another aspect of the present invention provides a nonvolatile memory device including an oxide thin film transistor having improved information erase characteristics.

An active region formed in one region on the substrate and including an n-type or p-type material;

A source region formed on one side of the active region and formed of a material different from the active region;

A tunneling layer, an information storage layer, a blocking layer and a gate sequentially formed on the active region; And

A first electrode formed on the source region, and a second electrode electrically connected to the active region.

And an oxide layer formed on the substrate surface.

Wherein the active region is formed of an n-type oxide and is made of an oxide selected from the group consisting of Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, And at least one material selected from oxides, Ge oxides, Na oxides, Ln oxides, Al oxides, W oxides and Ta oxides.

The active region may be formed of a p-type material and include at least one material selected from the group consisting of Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide and pentacene .

The active region may be formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs, and InGaAs.

The source region is formed of an n-type material and is made of Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, An oxide, a Ge oxide, an Na oxide, an Ln oxide, an Al oxide, a W oxide, or a Ta oxide.

Wherein the source region is formed of a p-type material and is formed of a material selected from the group consisting of Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, ZnCu oxide, SrCu oxide, or the like.

The source region may be formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs, and InGaAs.

And a drain region formed between the active region and the second electrode and formed of a material different from that of the active region.

A gate formed in one region on the substrate;

A tunneling layer, an information storage layer and a blocking layer sequentially formed on the gate;

An active region formed on the blocking layer and including an n-type or p-type material;

A source region formed on one side of the active region and formed of a material different from the active region; And

A first electrode formed on the source region, and a second electrode electrically connected to the active region.

According to an embodiment of the present invention, a source region or a source region and a drain region are formed of a material different from that of the active region to improve the electron tunneling and hole tunneling characteristics, thereby reducing temperature dependence upon information erasing and improving information erasing characteristics .

Hereinafter, a nonvolatile memory device according to an embodiment will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the size and thickness of each element may be exaggerated for clarity of explanation.

1 and 2 are views showing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, an active region 13 is formed in one region on a substrate 10 and includes a source region 14 formed on one side of the active region 13. The insulating layer 12 may be formed on both sides of the active region 13 and the source region 14. A first electrode 15a is formed on the source region 14 and a second electrode 15b electrically connected to the active region 13 is formed on one region of the active region 13. A tunneling layer 16a, an information storage layer 16b, and a blocking layer 16c are sequentially formed on the active region 13 between the first electrode 15a and the second electrode 15b. Both sides of the information storage layer 16b have a structure embedded between the tunneling layer 16a and the blocking layer 16c so as not to contact the first electrode 15a and the second electrode 15b. A gate 17 is formed on the blocking layer 16c. Optionally, an oxide layer 11 may be further formed on the surface of the substrate 10.

2 is a view showing a structure in which a source region 14a and a drain region 14b are formed on both sides of the active region 13. FIG. 2, an active region 13 is formed in one region on the substrate 10, and a source region 14a and a drain region 14b are formed on both sides of the active region 13. An insulating layer 12 may be formed on the sides of the source region 14a and the drain region 14b. A first electrode 15a is formed on the source region 14a and a second electrode 15b is formed on the drain region 14b. A tunneling layer 16a, an information storage layer 16b and a blocking layer 16c are sequentially formed on the active region 13 between the first electrode 15a and the second electrode 15b, 16b are embedded between the tunneling layer 16a and the blocking layer 16c so as not to contact the first electrode 15a and the second electrode 15b. A gate 17 is formed on the blocking layer 16c. An oxide layer 11 may be selectively formed on the surface of the substrate 10.

Hereinafter, materials for forming each layer of the nonvolatile memory device shown in FIGS. 1 and 2 will be described. The substrate 10 may be formed of a substrate material typically used for semiconductor devices, and may be formed of, for example, Si, Ge, C, SiC, GaN, GaAs, InGaAs, The oxide layer 11 may be SiO ₂ selectively formed on the surface of the substrate 10, for example, the surface of the Si substrate formed by thermal oxidation. The insulating layer 12 is formed of an insulating material and may be formed of Si oxide, Si nitride, Al oxide, Hf oxide, or the like.

The active region 13 may be formed using an n-type or p-type material. For example, it may be formed of a semiconductor oxide. Specifically, an n-type semiconductor oxide such as Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mo oxides, Nb oxides, Ag oxides, Ge oxides, Na oxides, Ln oxides, Al oxides, W oxides or Ta oxides, and the like. As the p-type semiconductor oxide, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, or the like can be used, and a single material or a composite material thereof can be used. An organic polymer material such as pentacene may also be used. Then, an n-type dopant or a p-type dopant may be doped to a material such as SiC, GaN, GaAs, and InGaAs.

In the nonvolatile memory device according to the embodiment of the present invention, the source regions 14 and 14a and the drain region 14b may be formed of a material different from that of the active region 13. For example, when the active region 13 is formed of an n-type material, the source regions 14 and 14a and the drain region 14b are formed of a p-type material, and the active region 13 ) Is formed of a p-type material, the source regions 14 and 14a and the drain region 14b are formed of an n-type material.

Examples of the n-type oxide semiconductor include Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag oxide , Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide, or Ta oxide, and a single material or a composite material thereof can be used. The p-type oxide semiconductor may be Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, DyCu oxide, ZnCu oxide SrCu oxide and the like, and a single material or a composite material thereof can be used. Then, an n-type dopant or a p-type dopant may be doped to a material such as SiC, GaN, GaAs, and InGaAs.

The tunneling layer 16a and the blocking layer 16c may be formed of an insulating material. Specifically, for example, Si and an n-type dopant or a p-type dopant may be used by doping them. At least one of Si oxide, Si nitride, Al oxide, Hf oxide, Mg oxide, Sr oxide, Ba oxide, Ti oxide, Ta oxide, BaTi oxide, BaZr oxide, Zr oxide, Y oxide, ZrSi oxide, HfSi oxide, As shown in FIG.

A charge storage layer (16b) is to be formed of a material that can store charge Si nitride, SiON, SiO _x, GeON, GeN, GeO poly-Silicon metal nitride, a metal boron nitride, a metal silicon nitride, a metal aluminum nitride, or metal silicide of Or at least one of them.

The gate 17 is formed of a conductive material and may be formed of a metal such as Au, Ag, Al, Ta, Ni, Ir, Pt, W, Nb, Ti, Mo, Ru, Zr, or Hf or ITO, IZO (InZnO), or AZO AlZnO). ≪ / RTI >

The materials of each layer as described above may also be used in the same named layer of Figs. 3-6.

Hereinafter, the reason why the sources 14 and 14a and the drain 14b are formed of a material different from that of the active region 13 will be described.

The nonvolatile memory device according to the embodiment of the present invention records information in the information storage layer 16b by the Fowler-Nordheim (FN) method and erases the information.

First, when a predetermined positive voltage is applied to the gate 17 to record information, an electric field is formed between the gate 17 and the active region 13, and an FN current across the tunneling layer 16a is generated . Electrons traveling in the active region 13 between the source regions 14 and 14a and the drain region 14b by the FN current are stored in the information storage layer 16b by tunneling the energy barrier of the tunneling layer 16a . The electrons e temporarily stored in the information storage layer 16b are blocked by the energy barrier of the blocking layer 16c and trapped in the information storage layer 16b to record information.

The process of erasing information will be described with reference to FIG. 7A. 7A is a diagram illustrating energy bandgaps in the information erasing process of the nonvolatile memory device according to the embodiment of the present invention. 7A, the conduction band energy Ec and the balance band energy Ev of the tunneling layer Tu, the information storage layer Tr and the blocking layer Bl are shown. When information is erased, a predetermined negative voltage is applied to the gate 17 to form an electric field in a direction opposite to that at the time of information recording. The electrons are tunneled from the information storage layer 16b, Tr to the tunneling layers 16a, Tu and moved toward the substrate 10 by the FN current, do. At this time, in the method of erasing the electrons of the information storage layers 16b and Tu, electrons of the information storage layers 16b and Tu can be tunneled through the tunneling layers 16a and Tu, The electrons can be neutralized by tunneling with the information storage layers 16b and Tu, and the information erasing efficiency is greatly improved when electron and hole tunneling occur simultaneously.

FIGS. 7B and 7C show the change in threshold voltage with time in the case where no tunneling occurs in the information erase, and data measured at 85 degrees Celsius and -10 degrees Celsius. Referring to FIGS. 7B and 7C, when holes are tunneled to the information storage layers 16b and Tu at the time of information erase, variations due to the temperature are not shown much (FIG. 7C). However, when tunneling of holes does not occur, it can be seen that a large variation occurs with temperature (FIG. 7B).

This phenomenon is particularly noticeable when the hole tunneling height of the material having a large energy band gap (Eg> 1.5 eV), for example, an oxide semiconductor material in the active region, is higher than the electron barrier height ), Which may be caused by the fact that the hole tunneling may not occur in a state in which sufficient energy is not supplied. Therefore, the hole tunneling may not occur at the time of information erasing, and deterioration of the information erasing is exhibited, in particular, depending on the temperature dependency. As a result, in the embodiment of the present invention, the source region or the source region and the drain region are formed of a material different from the active region to improve the electron tunneling and hole tunneling characteristics, thereby reducing the temperature dependence upon information erasing and improving the information erasing characteristic . Junction (junction), the source region affecting: (threshold voltage V _th), the source region (14a) and a drain region (14b) may be formed in the active region 13 and a different type, in particular, the threshold voltage of the transistor Only the source region 14 can be formed of a material different from that of the active region 13 as shown in FIG.

The fabrication process of the nonvolatile memory device according to the embodiment of the present invention will be described briefly as follows.

Referring to FIGS. 1 and 2, an oxide layer 11 is selectively formed on a substrate 10. At this time, the oxide layer may be a SiO ₂ layer formed on the surface of the Si substrate by a thermal oxidation process. Then, the active region 13, the source region 14, and the like are formed on the oxide layer 12. Here, the active region 13 and the source region 14 may form separate processes, and one material layer may be formed and doped to be formed simultaneously. For example, an active region 13 is formed by applying an n-type oxide semiconductor such as Zn oxide on the oxide layer 11, and a p-type dopant is doped to one side or both sides of the oxide region 11 to form source regions 14 and 14a and And / or the drain region 14b. After forming the tunneling layer 16a, the information storage layer 16b and the blocking layer 16c on the active region 13, the gate 17 may be formed on the blocking layer 16c. Next, the first electrode 15a may be formed by exposing the source regions 14 and 14a, and the second electrode 15b may be formed by exposing the active region 13 or the drain region 14b.

The structure of the non-volatile memory device of Figs. 1 and 2 can be modified into various forms. For example, as shown in FIGS. 3 and 4, the information storage layer 26b may be formed in a deformed structure in order to enlarge the area. Although FIGS. 1 and 2 disclose a top gate structure, the present invention is not limited thereto and may be formed as a bottom gate structure as shown in FIGS. 5 and 6. FIG.

3 and 4, an active region 23 is formed in one region on the substrate 20, and an insulating layer 22 is formed on both sides of the active region 23. A tunneling layer 26a, an information storage layer 26b and a blocking layer 26c are sequentially formed on the active region 23. A source region 24 and a first electrode 25a are formed on the insulating layer 22 on one side of the active region 23 and a second electrode 25a is formed on the insulating layer 22 on the other side of the active region 23. [ 25b may be formed, and the drain region 24b and the second electrode 25b may be sequentially formed. At this time, the source region 24 or the source and drain regions 24a and 24b may be in direct contact with the active region 23. Here, both sides of the information storage layer 26b have a structure embedded between the tunneling layer 26a and the blocking layer 26c so as not to contact the first electrode 25a and the second electrode 25b. Alternatively, an oxide layer 21 may be formed on the surface of the substrate 20.

3 and 4, an insulating layer 22 is formed on both sides of the active region 23, and a source region 24 or source and drain regions 24a and 24b are formed on the insulating layer 22. [ The insulating layer 22 may be formed to extend the source region 24 or the source and drain regions 24a and 24b.

5 and 6 are views showing a nonvolatile memory element of a bottom gate structure.

5 and 6, a gate 32 is formed in one region on the substrate 30 and a tunneling layer 33a, an information storage layer 33b, and a blocking layer 33b are formed on the substrate 30 and the gate 32, (33c) are sequentially formed. Here, the information storage layer 33b may have a buried structure between the tunneling layer 33a and the blocking layer 33c. An active region 34 is formed on the blocking layer 33c. A source region 35 may be formed on one side of the active region 34 and a first electrode 36a may be formed on the source region 35. A second electrode 36b electrically connected to the active region 34 may be formed on the other side of the active region 34. A drain region 34b may be formed between the active region 34 and the second electrode 36b. Specifically, a source region 35a and a first electrode 36a are formed on one side of the active region 34 And the drain region 35b and the second electrode 36b may be formed on the other side of the active region 34. [

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined by the appended claims.

1 and 2 are views showing a nonvolatile memory device according to an embodiment of the present invention.

FIG. 3 and FIG. 4 are views showing a modified example in which the area of the information storage layer of FIGS. 1 and 2 is enlarged.

5 and 6 are views showing a top gate structure of a nonvolatile memory device according to an embodiment of the present invention.

7A is a diagram illustrating energy bandgaps in the information erasing process of the nonvolatile memory device according to the embodiment of the present invention.

FIGS. 7B and 7C are graphs showing a change in threshold voltage with time when tunneling of holes does not occur during information erasing. FIG.

Description of the Related Art

10, 20, 30 substrate 11, 21, 31,

12, 22 ... insulation layer 13, 23, 34 ... active region

14, 14a, 24, 24a, 35, 35a,

14b, 24b, 35b, ..., drain regions 15a, 25a, 36a,

15b, 25b, 36b ... second electrodes 16a, 26b, 33a ... tunneling layer

16b, 26b, 33b ... information storage layers 16c, 26c, 33c ... blocking layer

17, 27, 32 ... Gate

Claims (18)

An active region formed in one region on the substrate and including an n-type or p-type material; A source region formed on one side of the active region and formed of a material different from the active region; A tunneling layer, an information storage layer, a blocking layer and a gate sequentially formed on the active region; And A first electrode formed on the source region and a second electrode electrically connected to the active region, Wherein the source region is formed by doping an n-type dopant or a p-type dopant into at least one of SiC, GaN, GaAs, and InGaAs. The method according to claim 1, And an oxide layer formed on the substrate surface. The method according to claim 1, Wherein the active region is formed of an n-type oxide and is made of an oxide of Zn, In, Ga, O, Zr, Hf, Sr, Sc, Mn, Mo, Nb, Na oxide, Ln oxide, Al oxide, W oxide, or Ta oxide. The method according to claim 1, The active region is formed of a p-type material and includes at least one material selected from the group consisting of Cu oxide, CuAl oxide, CuGa oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, and pentacene. The method according to claim 1, Wherein the active region is formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs, and InGaAs. delete delete delete The method according to claim 1, And a drain region formed between the active region and the second electrode and formed of a material different from that of the active region. A gate formed in one region on the substrate; A tunneling layer, an information storage layer and a blocking layer sequentially formed on the gate; An active region formed on the blocking layer and including an n-type or p-type material; A source region formed on one side of the active region and formed of a material different from the active region; And A first electrode formed on the source region and a second electrode electrically connected to the active region, Wherein the source region is formed by doping an n-type dopant or a p-type dopant into at least one of SiC, GaN, GaAs, and InGaAs. 11. The method of claim 10, And an oxide layer formed on the substrate surface. 11. The method of claim 10, Wherein the active region is formed of an n-type oxide and is made of an oxide of Zn, In, Ga, O, Zr, Hf, Sr, Sc, Mn, Mo, Nb, Na oxide, Ln oxide, Al oxide, W oxide, or Ta oxide. 11. The method of claim 10, The active region is formed of a p-type material and includes at least one material selected from the group consisting of Cu oxide, CuAl oxide, CuGa oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, and pentacene. 11. The method of claim 10, Wherein the active region is formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs, and InGaAs. delete delete delete 11. The method of claim 10, And a drain region formed between the active region and the second electrode and formed of a material different from that of the active region.

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