CN107230677B

CN107230677B - A kind of the data cell array structure and its manufacturing method of nand flash memory

Info

Publication number: CN107230677B
Application number: CN201610170806.4A
Authority: CN
Inventors: 黄新运; 肖磊; 沈晔晖; 沈磊; 刘岐; 刘红霞
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2016-03-24
Filing date: 2016-03-24
Publication date: 2019-08-16
Anticipated expiration: 2036-03-24
Also published as: CN107230677A

Abstract

A kind of the data cell array structure and its manufacturing method of nand flash memory, fin is formed on a semiconductor substrate, fin is included in the vertical upper source layer being laminated, channel layer and drain electrode layer, or include source layer and drain electrode layer, several laminated construction are formed on fin, laminated construction includes the tunneling medium layer at the top of covering fin with two sides, cover the charge trapping layer at the top of tunneling medium layer with two sides, it covers the gate dielectric layer at charge trapping layer top and two sides and is covered on the top of the gate dielectric layer and the grid of two sides, the string source electrode of connection source layer is formed in one end of fin, the string drain electrode of connection drain electrode layer is formed in the other end of fin.There is the present invention good process persistently to reduce ability, solve the problems, such as data cell reading interference.Data cell has used TFET, and being one has two grid device, and switching speed is fast, and cut-off current is small.The forming method and tradition FinFET process compatible of data cell, simplify technique, reduce process costs.

Description

A kind of the data cell array structure and its manufacturing method of nand flash memory

Technical field

The present invention relates to the data cell array structure and its manufacturing method of a kind of nand flash memory more particularly to a kind of uses Fin formula field effect transistor technique manufactures the method for the data cell array structure of nand flash memory and its TFET data sheet of acquisition Element array structure.

Background technique

NAND flash is a kind of nonvolatile flash memory technology of Toshiba's exploitation, has higher cell density, Ke Yida To high storage density, write-in and erasing speed are very fast.The unit size of NAND flash is almost the half of NOR device, can be with Higher capacity is provided in given die size, there is cracking write-in and erasing speed, major function is data on file, It is used primarily in digital camera flash card and MP3 player at present.

As shown in Figure 1, existing nand flash memory includes the channel region 1 in semiconductor substrate, the tunnel on channel region 1 Dielectric layer 2 is worn, multiple discrete floating gates 3 in tunneling medium layer 2, the gate dielectric layer 4 on floating gate 3 is located at grid and is situated between Control gate 5 on matter layer 4, and the interlayer dielectric layer 6 between each floating gate 3, gate dielectric layer 4 and control gate 5.

Two adjacent floating gates 3 are shown in Fig. 1, therefore are corresponding with two adjacent data cells.However, repeatedly to it In after a data cell is read, such as 1 to 0 overturning can occur for the data of data cell adjacent thereto.This Be because, to one of data cell read data when, the drain terminal of this data cell has hot carrier and is formed, this A little hot carriers a part under the action of electric field can enter in the floating gate of adjacent data cell.If this original adjacent data list Without electronics in the floating gate of member, then the entrance of these hot carriers can allow the data of this adjacent data cell to be flipped.

Hot carrier in jection (HCI) has occurred in the above process, and hot carrier in jection is that one occurs in solid electronic device A phenomenon, after electronics or hole acquisition enough kinetic energy, they can break through the constraint (" heat " in hot carrier of potential barrier This term refers to the effective temperature for being modeled to carrier density, and the temperature of non-device itself).Due to carrier It is bound in the gate dielectric layer of metal oxide semiconductor field effect tube, the switch performance of transistor can be by for good and all Change, hot carrier in jection be it is a kind of may be to the mechanism that semiconductor device reliability has a negative impact.For nand flash memory, Hot carrier (usually thermoelectron) may be injected into floating gate, to change the data mode that data cell is saved.

As shown in Fig. 2, being the simplified structure chart of existing nand flash memory, wherein floating gate and control gate are parallel with two Strigula indicates.Therefrom it can be seen that, when one of data cell generate hot carrier in jection arrive adjacent data cell After floating gate, there is mistake in the data that will lead to adjacent data cell storage, so as to cause the storage number of this adjacent data cell According to go wrong (no good, NG).

In order to solve the problems, such as reading interference, the method used at present to nand flash memory is wordline when changing read operation The voltage of (word line), slows down the formation of hot carrier.Such as the voltage between reduction reading unit and its adjacent power wordline Difference.

However, this reading interference can only be alleviated by reducing the voltage difference between reading unit and its adjacent power wordline The generation of phenomenon.Since the threshold difference (Δ Vth) between the corresponding data cell of data 0 and 1 must assure that distinguishing for data, no It can continue to reduce.So with the reduction of flush memory device size and the increase of integrated level, this method will be unable to use.In addition, For long numeric data unit (MLC, a data element memory put long numeric data) threshold value span than a data unit (SLC, One data element memory puts a data) it is bigger, so the case where this reading interference, can be more serious.

Summary of the invention

The present invention provides the data cell array structure and its manufacturing method of a kind of nand flash memory, has good technique ruler It is very little persistently to reduce ability, solve the problems, such as data cell reading interference.Data cell has used TFET, and being one has double grid The device of pole, switching speed is fast, and cut-off current is small.The forming method and tradition FinFET process compatible of data cell, simplify Technique reduces process costs.

In order to achieve the above object, the present invention provides a kind of data cell array structure of nand flash memory, includes:

Semiconductor substrate；

Fin in the semiconductor substrate, the fin includes: the source layer that is vertically laminated, channel layer and Drain electrode layer, the channel layer are located among the source layer and drain electrode layer；

Several laminated construction, each laminated construction is covered on the top and two sides of the part fin, described folded The quantity of layer structure is more than or equal to 1, and the laminated construction is intervally arranged along the fin length direction, the laminated construction Include: be covered on the top of the part fin and the tunneling medium layer of two sides, be covered on the tunneling medium layer top and The charge trapping layer of two sides, the top for being covered on the charge trapping layer and two sides gate dielectric layer and be covered on the gate medium The top of layer and the grid of two sides；

Positioned at fin one end and the string source electrode of the connection source layer；

Positioned at the string drain electrode of the fin other end and the connection drain electrode layer；

Wherein, the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type, and the channel layer is P-type is lightly doped or intrinsic semiconductor layer, and the string source electrode is P+ type heavy doping, and the string drain electrode is that the heavy doping of N+ type is intrinsic Semiconductor layer.

In the fin length direction, all the grid is located between the string source electrode and string drain electrode.

In the fin length direction, also there is source selection transistor between string source electrode and the grid, or Also there is leakage selection transistor between the grid and string drain electrode.

The present invention also provides a kind of data cells of nand flash memory, include:

Semiconductor substrate；

Wherein, the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type, and the channel layer is P-type is lightly doped or intrinsic semiconductor layer.

The present invention also provides the forming methods of the data cell array structure of nand flash memory comprising the steps of:

Semiconductor substrate is provided；

Form fin on the semiconductor substrate, the fin includes: the source layer that is vertically laminated, channel layer and Drain electrode layer, the channel layer are located among the source layer and drain electrode layer；

Form several laminated construction on fin, each laminated construction be covered on the part fin top and Two sides, the laminated construction are intervally arranged along the fin length direction, and the laminated construction includes: being covered on part institute State the top of fin and the tunneling medium layer of two sides, be covered on the top of the tunneling medium layer and the charge trapping layer of two sides, It is covered on the top of the charge trapping layer and the gate dielectric layer of two sides and is covered on the top and two sides of the gate dielectric layer Grid；

String source electrode is formed in wherein one end of the fin, the string source electrode connects the source layer；

String drain electrode is formed in the other end of the fin, the string drain electrode connects the drain electrode layer.

The laminated construction is formed between the string source electrode and string drain electrode.

The step of forming the fin includes:

Grown epitaxial layer on a semiconductor substrate carries out N+ heavy doping in epitaxial layer and forms drain electrode layer；

Channel layer is epitaxially-formed on the drain electrode layer；

In channel layer growing epitaxial layers, P+ heavy doping is carried out in epitaxial layer and forms source layer；

Patterned hard mask layer is formed on the source layer；

Using the patterned hard mask layer as mask, the source layer, channel layer, drain electrode layer and semiconductor lining are etched Bottom, until forming the fin.

Optionally, the step of forming the fin includes:

Grown epitaxial layer on a semiconductor substrate carries out P+ heavy doping in epitaxial layer and forms source layer；

Channel layer is epitaxially-formed on the source layer；

In channel layer growing epitaxial layers, N+ heavy doping is carried out in epitaxial layer and forms drain electrode layer；

Patterned hard mask layer is formed on the drain electrode layer；

Using the patterned hard mask layer as mask, the drain electrode layer, channel layer, source layer and semiconductor lining are etched Bottom, until forming the fin.

The step of forming the laminated construction includes:

It forms mask layer and covers the entire fin；

Etching mask layer is to form groove, the top and two sides of fin described in the groove expose portion；

Tunneling medium layer is formed in the fin portion surface of the bottom portion of groove；

Charge trapping layer is formed, so that charge trapping layer be made to be covered on the groove inner wall；

Continue wall in the groove and form gate dielectric layer, so that gate dielectric layer be made to cover charge trapping layer；

It forms grid and fills the groove, to make gate dielectric layer between charge trapping layer and grid.

The step of forming the string source electrode and string drain electrode includes:

The mask layer is etched with the both ends of the exposure fin, and retains the institute with the charge trapping layer contact portion State mask layer；

In the both ends epitaxial growth silicon carbide or germanium silicon of the fin, and carry out it is in situ adulterate formed the string source electrode with String drain electrode.

Optionally, the step of forming the laminated construction includes:

It forms Tunnel dielectric material layer and covers the fin；

It forms charge-trapping material layer and covers the Tunnel dielectric material layer；

It forms gate dielectric material layer and covers the charge-trapping material layer；

It forms gate material layer and covers the gate dielectric material layer；

It is sequentially etched the gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric material layer, until Form the grid, gate dielectric layer, charge trapping layer and tunneling medium layer.

The present invention also provides a kind of data cell array structures of nand flash memory, include:

Semiconductor substrate；

Fin in the semiconductor substrate, the fin includes: the source layer and drain electrode layer being vertically laminated；

Wherein, the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type, and the string source electrode is P+ type heavy doping, the string drain electrode is the heavy doping of N+ type.

Semiconductor substrate；

Wherein, the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type.

The present invention also provides a kind of forming methods of the data cell array structure of nand flash memory comprising the steps of:

Semiconductor substrate is provided；

Fin is formed on the semiconductor substrate, the fin includes: the source layer and drain electrode layer being vertically laminated；

The step of forming the fin includes:

In the drain electrode layer growing epitaxial layers, P+ heavy doping is carried out in epitaxial layer and forms source layer；

Patterned hard mask layer is formed on the source layer；

Using the patterned hard mask layer as mask, the source layer, drain electrode layer and semiconductor substrate are etched, until shape At the fin.

Optionally, the step of forming the fin includes:

In the source layer growing epitaxial layers, N+ heavy doping is carried out in epitaxial layer and forms drain electrode layer；

Patterned hard mask layer is formed on the drain electrode layer；

Using the patterned hard mask layer as mask, the drain electrode layer, source layer and semiconductor substrate are etched, until shape At the fin.

The step of forming the laminated construction includes:

It forms mask layer and covers the entire fin；

Optionally, the step of forming the laminated construction includes:

It forms Tunnel dielectric material layer and covers the fin；

It forms gate material layer and covers the gate dielectric material layer；

There is the present invention good process persistently to reduce ability, solve the problems, such as data cell reading interference.Number TFET is used according to unit, being one has two grid device, and switching speed is fast, and cut-off current is small.The formation of data cell Method and tradition FinFET process compatible, simplify technique, reduce process costs.

Detailed description of the invention

Fig. 1 is the structural schematic diagram of nand flash memory in background technique.

Fig. 2 is the simplified structure chart of nand flash memory in background technique.

Fig. 3~Fig. 5 is the manufacturing process signal of fin in the data cell array structure of nand flash memory provided by the invention Figure.

Fig. 6~Fig. 9 is the manufacturing process of laminated construction in the data cell array structure of nand flash memory provided by the invention Schematic diagram.

Figure 10~Figure 12 is string source electrode and string drain electrode in the data cell array structure of nand flash memory provided by the invention Manufacturing process schematic diagram.

Figure 13 is the structural schematic diagram of the data cell array structure of nand flash memory in one embodiment of the invention.

Figure 14 is the structural schematic diagram of the data cell array structure of nand flash memory in another embodiment of the present invention.

Figure 15 is source selection transistor in the data cell array structure of nand flash memory in another embodiment of the present invention Diagrammatic cross-section.

Specific embodiment

Below according to Fig. 3~Figure 15, presently preferred embodiments of the present invention is illustrated.

The present invention provides a kind of data cell array structure of nand flash memory, is made using fin formula field effect transistor technique Make the data cell array structure of nand flash memory, which is tunneling field-effect transistor (TFET).

TFET, which is one, simply has grid control P-I-N diode, it is diode of the work in reverse bias condition. Whether the working mechanism of MOSFET is to circulate to carry out work in channel by carrier, but a TFET is to utilize inter-band tunneling (band to band tunneling) electric current is as working mechanism.In the off condition, the potential barrier between source and channel is very wide, There is no BTBT, only very small leakage current exists.But when grid voltage is more than threshold voltage, channel and source electrode it Between potential barrier become sufficiently narrow, to allow very big tunnel current to flow through, here it is so-called on states.Because of TFET The carrier of middle circulation is BTBT electric current, so the opening speed of TFET is not limited by SS limit 60mV/dec in MOSFET. This feature allows TFET to have higher switching speed relative to common MOSFET.

Fin formula field effect transistor (FinFET) is that positive penetrating judgment awards (Profs. recklessly by Univ California-Berkeley Chenming Hu, Tsu-Jae King-Liu and Jeffrey Bokor) it is named, it is a kind of based on early stage for describing The mono- grid of DELTA() design of transistor is evolved and establishes the non-planar double-gate transistor on silicon on insulating substrate. The main characteristic of FinFET is to be wrapped in conductive channel inside silicon " fin ".The distance between source electrode and drain electrode determines this The equivalent passageway length of element.

The present invention provides a kind of data cell array structure of nand flash memory, includes:

Semiconductor substrate；

Positioned at the string drain electrode of the fin other end and the connection drain electrode layer.

The data cell array structure that nand flash memory is made of fin formula field effect transistor technique, such as Fig. 3~Fig. 5 institute Show, semiconductor substrate 300 is provided, and form fin (not marking) in semiconductor substrate 300, the fin includes vertically Source layer 317, channel layer 315 and the drain electrode layer 313 of stacking, channel layer 315 are located among source layer 317 and drain electrode layer 313.

Fig. 3 is the plan structure of the fin, and the fin has certain length, this length direction and X-X1 point Direction of crossing is identical, and the fin has certain width, this width direction and Y-Y1 chain-dotted line direction phase Together.

In the present invention, the head-tail of the fin length direction is divided into the both ends of the fin, and the fin is wide Two edges for spending direction are the two sides of the fin.

Fig. 4 is the cross-section structure that plan structure shown in Fig. 3 is obtained along X-X1 chain-dotted line cutting.Institute as can see from Figure 4 Stating fin includes in vertical upper source layer 317, channel layer 315, drain electrode layer 313 and the semiconductor layer 311 being laminated.Specifically, source Pole layer 317, channel layer 315, drain electrode layer 313 and semiconductor layer 311 stack gradually from top to bottom, i.e., source layer 317 is located at channel On layer 315, channel layer 315 is located on drain electrode layer 313, and drain electrode layer 313 is located on semiconductor layer 311.

In the present invention, vertically refer to basic with wafer upper surface (wafer upper surface is often referred to 300 upper surface of semiconductor substrate) Vertical direction.Correspondingly, laterally referring to and wafer upper surface direction that is substantially parallel.

Both as shown in figure 4, separated between semiconductor layer 311 and semiconductor substrate 300 with dotted line, this is because usually It is originally used for substrat structure, only by after etching technics, semiconductor layer 311 becomes the part that the fin is located at bottom.? In the fin, there is the shading different with drain electrode layer 313 from part-structure that drain electrode layer 313 is located on the same floor, this be in order to Show that this part-structure is not drain electrode layer 313, this part-structure is not intended as conductive structure, can be described as the first dielectric structure 320. It is separated between first dielectric structure 320 and the semiconductor layer 311 of lower layer with dotted line, this is because first dielectric structure 320 can be structure as a whole with semiconductor layer 311.

The process for forming drain electrode layer 313 and semiconductor layer 311 can be with are as follows: carries out N+ heavy doping to semiconductor substrate 300, so Semiconductor substrate 300 is performed etching afterwards, the part that semiconductor substrate 300 has carried out the N+ heavy doping is left after etching Drain electrode layer 313, and the part that semiconductor substrate 300 does not carry out the N+ heavy doping is then left above-mentioned first dielectric structure 320, Correspondingly, the part semiconductor substrate 300 of 320 lower section of drain electrode layer 313 and first dielectric structure then becomes semiconductor layer 311, it is known that, first dielectric structure and semiconductor layer 311 are to remain after semiconductor substrate 300 is etched at this time Part.

It should be noted that in other embodiments, first dielectric structure 320 can also individually use deposition method It is formed, to become an independent part, the present invention is not construed as limiting the forming method of the first dielectric structure 320.

As shown in figure 4, there is the shading different with source layer 317 from the part-structure that source layer 317 is located on the same floor, this It is to show that this part-structure is not source layer 317, this part-structure is not intended as conductive structure, can be described as the second dielectric knot Structure 319.

Forming 317 process of source layer can be with are as follows: forms semiconductor material layer on channel layer 315, this semiconductor material layer The thickness with a thickness of source layer 317, then to the semiconductor material layer carry out P+ heavy doping, to form source layer 317, and Undoped part is left the second dielectric structure 319, thus second dielectric structure 319 is semiconductor material layer guarantor at this time The overall structure stayed.

It should be noted that in other embodiments, second dielectric structure 319 can also individually use deposition method It is formed, to become an independent part, the present invention is not construed as limiting the forming method of the second dielectric structure 319.

As shown in figure 4, source layer 317 and drain electrode layer 313 vertically overlap, meanwhile, source layer 317 and drain electrode Layer 313 vertically has part not to be overlapped.Also, source layer 317 and drain electrode layer 313 is vertically nonoverlapping is partly due to Caused by the presence of first dielectric structure 320 and the second dielectric structure 319.I.e. described first dielectric structure 320 and second Dielectric structure 319 is not overlapped vertically, and the two is located at two ends of fin, thus guarantee section source layer 317 It is vertically Chong Die with first dielectric structure 320, part drain electrode layer 313 vertically with second dielectric structure 319 Overlapping.

In the present embodiment, on the one hand, source layer 317 and drain electrode layer 313 need vertically to partly overlap, to guarantee source Pole layer 317 and drain electrode layer 313 can be respectively as the source electrode and drain electrodes of nand flash memory storage element；On the other hand, source layer 317 Nonoverlapping two ends are vertically needed with drain electrode layer 313, to guarantee the string source electrode 3431 being subsequently formed and string leakage Pole 3432 can only connect with one of the two respectively, i.e. guarantee forms corresponding nand flash memory data cell array junctions Structure.

Fig. 5 is the cross-section structure that plan structure shown in Fig. 3 is obtained along Y-Y1 chain-dotted line cutting.Equally may be used from Fig. 5 It is stacked gradually from top to bottom to semiconductor layer 311, drain electrode layer 313, channel layer 315, source layer 317.Furthermore, it is possible to further see Matcoveredn 321 is covered to 300 surface of semiconductor substrate.Protective layer 321 can protect semiconductor substrate 300.

It is more intuitive to see from Fig. 5, the semiconductor layer 311 in the fin is usually phase with semiconductor substrate 300 Integral structure even.Therefore, it is separated between the two with dotted line.

It should be noted that in other embodiments, can also be formed in semiconductor substrate 300 using the method for deposition Semiconductor layer 311, semiconductor layer 311 and semiconductor substrate 300 are then the different layers structure of essence at this time.

In the present embodiment, semiconductor substrate 300 is silicon substrate.In other embodiments of the invention, semiconductor substrate 300 Or the substrate that germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their combination are formed, or Person is silicon-on-insulator substrate, or other the suitable semiconductive material substrates being known to the skilled person.

In the present embodiment, the step of forming the fin, be may include:

In 300 growing epitaxial layers of semiconductor substrate, N+ heavy doping is carried out in epitaxial layer and forms drain electrode layer 313；

Channel layer 315 is epitaxially-formed on the drain electrode layer 313；

In 315 growing epitaxial layers of channel layer, P+ heavy doping is carried out in epitaxial layer and forms source layer 317；

Patterned hard mask layer is formed on the source layer 317；

Using the patterned hard mask layer as mask, the source layer 317, channel layer 315,313 and of drain electrode layer are etched Semiconductor substrate 300, until forming the fin.

After forming the fin, the hard mask layer can be removed, and can also be retained.

In other embodiments of the invention, the position of source layer 317 and drain electrode layer 313 can be exchanged.

In the forming process of above-mentioned fin, above-mentioned first dielectric structure 320 and the second dielectric structure can be formed simultaneously 319。

In the forming process of above-mentioned fin, channel layer 315 can be intrinsic semiconductor layer, such as intrinsic silicon material layer, Channel layer 315 can also be lightly doped, the conduction type of the atom that injection is lightly doped is p-type atom.

As shown in figs. 6-9, laminated construction is formed.A tunneling medium layer 331 is formed, tunneling medium layer 331 is covered on The top and two sides of the part fin.Charge trapping layer 333 is formed, charge trapping layer 333 is covered on the tunneling medium layer 331 top and two sides.Gate dielectric layer 335 is formed, gate dielectric layer 335 is covered on the top and two sides of charge trapping layer 333.Shape At grid 337, grid 337 is covered on the top and two sides of the gate dielectric layer 335.

Fig. 6 is the plan structure to be formed after grid 337, it will be seen from figure 6 that in the fin length direction Both ends are covered by mask layer 323, and intermediate one section is covered by grid 337.Also, there is electricity between grid 337 and mask layer 323 Lotus trap layer 333 and gate dielectric layer 335.Gate dielectric layer 335 is between grid 337 and charge trapping layer 333.

Fig. 7 is the schematic diagram of the section structure that structure shown in Fig. 6 is obtained along X-X2 chain-dotted line cutting.As shown in fig. 7, the fin Tunneling medium layer 331, charge trapping layer 333, gate dielectric layer 335 are formd on intermediate one section of top in minister's degree direction With grid 337.

Fig. 8 is the schematic diagram of the section structure that structure shown in Fig. 6 is obtained along Y-Y2 chain-dotted line cutting.In conjunction with Fig. 6, Fig. 7 and Fig. 8 It is recognised that tunneling medium layer 331, charge trapping layer 333, gate dielectric layer 335 and grid 337 not only fin described in covering part Top, also while being covered on the two sides of fin described in these parts.Also, tunneling medium layer 331 is located at the fin and electricity Between lotus trap layer 333.Charge trapping layer 333 is between gate dielectric layer 335 and tunneling medium layer 331 and gate dielectric layer 335. Gate dielectric layer 335 is between grid 337 and charge trapping layer 333.

Fig. 9 is the schematic diagram of the section structure that structure shown in Fig. 6 is obtained along Y-Y3 chain-dotted line cutting.It can also from Fig. 7 It arrives, the top above the fin both ends is covered by mask layer 323, in conjunction with Fig. 7 and Fig. 9 it is found that mask layer 323 also covers simultaneously The two sides of the fin in this section.

In the present embodiment, the material of mask layer 323 can be silicon nitride or carbonitride of silicium or silicon nitride and silica Laminated construction.

In the present embodiment, the material of charge trapping layer 333 can be silicon nitride.Using silicon nitride as charge trapping layer When 333, after corresponding charge enters trap layer, it is not susceptible to move, therefore, corresponding data stabilization.

In the present embodiment, the material of tunneling medium layer 331 and gate dielectric layer 335 all can be silica.Tunnelling is situated between at this time Matter layer 331, charge trapping layer 333 and gate dielectric layer 335 form ONO(oxide-nitride-oxide) laminated construction.

In the present embodiment, the process for forming laminated construction be may include:

It forms mask layer 323 and covers the entire fin；

Etching mask layer 323, to form groove (not shown), the top and two of fin described in the groove expose portion Side, and exposure is one section among the fin length direction, i.e., in remaining such as Fig. 6~Fig. 9 of mask layer 323 at this time It is shown；

Tunneling medium layer 331 is formed in the fin portion surface of the bottom portion of groove；

Charge trapping layer 333 is formed, so that charge trapping layer 333 be made to be covered on the groove inner wall；

Continue wall in the groove and form gate dielectric layer 335, so that gate dielectric layer 335 be made to cover charge trapping layer 333；

Form grid 337 and fill the groove, thus make gate dielectric layer 335 be located at charge trapping layer 333 and grid 337 it Between.

In the present embodiment, tunnel can be formed in the fin portion surface being exposed using thermal oxidation method or chemical oxidization method Dielectric layer 331 is worn, it can be using chemical vapor deposition method (CVD), physical gas-phase deposite method (PVD) or atomic layer deposition Method (ALD) forms charge trapping layer 333, gate dielectric layer 335 and grid 337.

In other embodiments of the invention, forming the laminated construction also may include:

It forms Tunnel dielectric material layer and covers the fin；

It forms gate material layer and covers the gate dielectric material layer；

It is sequentially etched the gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric material layer, until Form the grid 337, gate dielectric layer 335, charge trapping layer 333 and tunneling medium layer 331.

In the present embodiment, the material of grid 337 can be polysilicon or metal.When the material of grid 337 is metal, Corresponding gate dielectric layer 335 can be made for high K dielectric material.

As shown in Figure 10~Figure 12, mask layer 323 shown in Fig. 6 is etched to remove most of mask layer 323, and exposure The both ends of the fin, while retaining the small part mask layer 323(adjacent with tunneling medium layer 331 and charge trapping layer 333 i.e. Retain the part mask layer 323 contacted with the charge trapping layer 333).Then, it is carbonized in the both ends epitaxial growth of the fin Silicon or germanium silicon, and carry out in situ adulterate and form the string source electrode 3431 and string drain electrode 3432.Also, it can also continue in string source Metal silicide 347 is formed on pole 3431, string drain electrode 3432 and grid 337.

Specifically, in the both ends of the fin (the fin both ends of exposure i.e. after removing mask layer 323), at it Middle one end forms string source electrode 3431, and the string source electrode 3431 connects source layer 317, forms string drain electrode 3432 in the other end, described The 3432 connection drain electrode layer 313 of string drain electrode.

In the present embodiment, forming string source electrode 3431 and the step of string drain electrode 3432 be may include:

The fin both ends epitaxial growth silicon carbide perhaps the germanium silicon silicon carbide or germanium silicon as the string source Pole 3431 and string drain electrode 3432.During epitaxial growth string source electrode 3431 and string drain electrode 3432, to the silicon carbide or Germanium silicon carries out doping in situ, and string source electrode carries out P+ heavy doping, and string drain electrode carries out N+ heavy doping, to improve string source electrode 3431 and string The electric conductivity of drain electrode 3432.The conductivity of the silicon carbide or germanium silicon that are lightly doped is higher, the string source electrode 3431 and string worked it out 3432 dead resistances that drain are smaller.

In the present embodiment, in the fin length direction, string source electrode 3431 and string drain electrode 3432 are formed in tunnelling 331 both sides of dielectric layer, i.e. tunneling medium layer 331 are formed between string source electrode 3431 and string drain electrode 3432, that is, grid 337 is located at It goes here and there between source electrode 3431 and string drain electrode 3432, and grid 337 and corresponding source layer 317, channel layer 315, drain electrode layer 313, tunnel It wears dielectric layer 331, charge trapping layer 333 and gate dielectric layer 335 and constitutes nand flash memory data cell, therefore, that is to say, that described Nand flash memory data cell is located between string source electrode 3431 and string drain electrode 3432.

In the present embodiment, string source electrode 3431 is grown in 317 two sides of source layer, therefore string source electrode 3431 and source layer 317 Electrical connection.Meanwhile string source electrode 3431 is not grown in 313 side of drain electrode layer, but it is grown in above-mentioned second dielectric structure, 320 side Face, therefore, mutually insulated between string source electrode 3431 and drain electrode layer 313.Likewise, string drain electrode 3432 is grown in 313 liang of drain electrode layer Side, therefore string drain electrode 3432 is electrically connected with drain electrode layer 313.Meanwhile string drain electrode 3432 is not grown in 317 side of source layer, But it is grown in above-mentioned first dielectric structure, 319 side, and therefore, mutually insulated between string drain electrode 3432 and source layer 317.

Figure 11 is the cross-section structure that plan structure shown in Figure 10 is obtained along X-X3 chain-dotted line cutting.As shown in figure 11, above-mentioned Remaining mask layer 323 is located between string source electrode 3431 and charge trapping layer 333 in the process, and string drain electrode 3432 is fallen into charge Between well layer 333.

Figure 12 is the cross-section structure that plan structure shown in Figure 10 is obtained along Y-Y4 chain-dotted line cutting.As shown in figure 12, string source The shape of pole 3431 is in diamond shape.This is because what the epitaxial crystallization of silicon was formed, mainly the extension of silicon materials determines shape, And carbon or the only a small amount incorporation of germanium, so not influenced substantially on shape.I.e. in the silicon carbide of epitaxial growth or germanium silicon, still So continue to generate along the lattice of silicon atom in the fin, and lattice growth has anisotropy, therefore forms institute in Figure 12 Show shape.In Figure 12 although not shown string drain electrode 3432 shape, it will be appreciated that string drain electrode 3432 shape and string source electrode 3431 is identical, therefore, can refer to structure as shown in figure 12 together.

In the present embodiment, a grid 337, a corresponding only nand flash memory data cell are only formd.This NAND Flash data unit forms nand flash memory data cell array structure with the string source electrode 3431 and string drain electrode 3432 for being located at its both sides.

As shown in figure 13, in another embodiment of the present invention, multiple discrete grids can be formed in the fin, The multiple grids being intervally arranged are being formed along the fin length direction, to form multiple nand flash memory data sheets Member, also, these nand flash memory data cells and string source electrode and string drain electrode form nand flash memory data cell array structure.

Nand flash memory data cell array junctions as shown in fig. 13 that are formed according to the manufacturing method as shown in Fig. 3~Figure 12 Structure.Deep n-type trap 401 and the p-type trap 402(on deep n-type trap 401 are formed in semiconductor substrate 400 in other embodiments In, it is also possible to that there is deep p-type trap and the N-type trap on deep p-type trap 401 in semiconductor substrate 400), on p-type trap 402 Fin is formed, 402 upper surface of p-type trap covers matcoveredn 421, and the fin includes in the vertical upper source layer 417 being laminated, ditch Channel layer 415, drain electrode layer 413 and semiconductor layer 411, wherein channel layer 415 is located among source layer 417 and drain electrode layer 413.Source electrode Layer 417, channel layer 415, drain electrode layer 413 and semiconductor layer 411 stack gradually from top to bottom, i.e., source layer 417 is located at channel layer On 415, channel layer 415 is located on drain electrode layer 413, and drain electrode layer 413 is located on semiconductor layer 411.It is located at drain electrode layer 413 same One layer of part is the first dielectric structure 4130, is the second dielectric structure 419 with the part that source layer 417 is located on the same floor.Source Pole layer 417 and drain electrode layer 413 vertically overlap, meanwhile, source layer 417 and drain electrode layer 413 vertically have part It is not overlapped.Also, source layer 417 and drain electrode layer 413 are vertically nonoverlapping to be partly due to 4130 He of the first dielectric structure Caused by the presence of second dielectric structure 419.That is the first dielectric structure 4130 and the second dielectric structure 419 do not weigh vertically It is folded, and the two is located at two ends of fin, thus guarantee section source layer 417 vertically with the first dielectric structure 4130 overlappings, part drain electrode layer 413 are vertically Chong Die with the second dielectric structure 419.In the fin length direction The multiple tunneling medium layers 431 being intervally arranged are formed, tunneling medium layer 431 is covered on the top and two sides of the part fin. Charge trapping layer 433 is formed, charge trapping layer 433 is covered on the top and two sides of tunneling medium layer 431.Form gate dielectric layer 435, gate dielectric layer 435 is covered on the top and two sides of charge trapping layer 433.Grid 437 is formed, grid 437 is covered on described The top and two sides of gate dielectric layer 435.String source electrode 4431 is formed in one end of the fin, the string source electrode 4431 connects source electrode Layer 417 forms string drain electrode 4432, the 4432 connection drain electrode layer 413 of string drain electrode in the other end.It is subsequent to can also continue to Metal silicide (not shown) is formed on string source electrode 4431, string drain electrode 4432 and grid 437, and forms contact plunger (not shown) Each metal silicide is connected, and at the same time connection grid 437.

In the present embodiment, in the fin length direction, string source electrode 4431 and string drain electrode 4432 are formed in tunnelling 431 both sides of dielectric layer, i.e. tunneling medium layer 431 are formed between string source electrode 4431 and string drain electrode 4432, that is, grid 437 is located at It goes here and there between source electrode 4431 and string drain electrode 4432, and grid 437 and corresponding source layer 417, channel layer 415, drain electrode layer 413, tunnel It wears dielectric layer 431, charge trapping layer 433 and gate dielectric layer 435 and constitutes nand flash memory data cell, therefore, that is to say, that described Nand flash memory data cell is located between string source electrode 4431 and string drain electrode 4432.

In the present embodiment, string source electrode 4431 is grown in 417 two sides of source layer, therefore string source electrode 4431 and source layer 417 Electrical connection.Meanwhile string source electrode 4431 is not grown in 413 side of drain electrode layer, but it is grown in above-mentioned second dielectric structure, 419 side Face, therefore, mutually insulated between string source electrode 4431 and drain electrode layer 413.Likewise, string drain electrode 4432 is grown in 413 liang of drain electrode layer Side, therefore string drain electrode 4432 is electrically connected with drain electrode layer 413.Meanwhile string drain electrode 4432 is not grown in 417 side of source layer, But it is grown in above-mentioned first dielectric structure, 4130 side, and therefore, mutually insulated between string drain electrode 4432 and source layer 417.

In the present embodiment, three grids 437 are formd, corresponding there are three nand flash memory data cells.This three NAND Flash data unit forms nand flash memory data cell array structure with the string source electrode 4431 and string drain electrode 4432 for being located at its both sides. But in other embodiments of the invention, more discrete grids 437, such as 8,16 can be formed in the fin Or 32 grids, and these grids are intervally arranged along the fin length direction, to be formed long along the fin Multiple nand flash memory data cells for being intervally arranged of degree direction, also, these nand flash memory data cells and string source electrode 4431 and String drain electrode 4432 forms nand flash memory data cell array structure.

In the forming method of nand flash memory data cell array structure provided by the present embodiment, in provided semiconductor Fin is formd on substrate, the fin includes the source layer being vertically laminated from top to bottom, channel layer, drain electrode layer and partly leads Then body layer forms and is covered on the fin by the laminated construction that tunneling medium layer, charge trapping layer and gate dielectric layer form Top and two sides re-form grid and cover the laminated construction, so as to form nand flash memory data cell.It was formed entirely Cheng Zhong, lithography and etching technique when being omitted to form multi-crystal silicon floating bar simplify processing step.

Nand flash memory data cell is formed by by source layer as source electrode, channel region is formed in channel layer, by draining Layer is as drain electrode, and therefore, size can substantially reduce.Simultaneously as not adjacent data cell, even if multiple NAND Flash data unit is made in same fin, due to the electricity of drain electrode (drain electrode is the part drain electrode layer) and adjacent data cell Farther out or tortuous path, and direction of an electric field is not pointing at the charge trap of adjacent data cell to distance between lotus trap layer Layer but from source layer to drain electrode layer, therefore can be prevented when being read to a data cell, hot carrier into The phenomenon that entering adjacent data cell solves the problems, such as data cell reading interference from device architecture.

The doping type for being formed by the source electrode and drain electrode of nand flash memory data cell is different, therefore data cell is TFET, rather than MOSFET, and influence of the TFET to switching voltage Vt is more sensitive, switching speed is fast, and cut-off current is small, is suitble to do MLC or TLC etc..

In the forming method of nand flash memory data cell array structure provided by the present invention, dodged foring above-mentioned NAND After deposit data unit, and continue to form string source electrode and string drain electrode at the both ends of the fin, to form data cell battle array Array structure.The size of the array structure equally can substantially reduce, and the performance of data cell array structure improves.

Although each data cell has an independent source electrode and drain electrode, but the data cell on a bit line (bit line) Source electrode and drain electrode is all in parallel, so being still NAND flash memory, it still maintains nand flash memory storage density height and storage Data first read the characteristics of running afterwards.

In the present invention, because channel layer pattern is all different with source layer or drain electrode layer, in the forming process of fin, Using entire fin as source layer, so that it may reduce the use of mask layer.

There is data cell provided by the present invention good process persistently to reduce ability.Meanwhile each data sheet Member, which is all one, has two grid device, has lesser cut-off current.Also, the forming method and biography of the data cell System FinFET process compatible, simplifies technique, reduces process costs.

Semiconductor substrate；

As shown in figure 14, in another embodiment of the present invention, it is made of fin formula field effect transistor technique The data cell array structure of nand flash memory provides semiconductor substrate 500, and deep n-type trap is formed in semiconductor substrate 500 The 501 and p-type trap 502(on deep n-type trap 501 in other embodiments, is also possible to have depth P in semiconductor substrate 500 Type trap and the N-type trap on deep p-type trap 501), fin is formed on p-type trap 502,502 upper surface of p-type trap is covered with protection Layer 521.

The fin is included in vertical upper source layer 517, drain electrode layer 513 and the semiconductor layer 511 being laminated.Specifically, source Pole layer 517, drain electrode layer 513 and semiconductor layer 511 stack gradually from top to bottom, i.e., source layer 517 is located on drain electrode layer 513, and Drain electrode layer 513 is located on semiconductor layer 511.The part being located on the same floor with drain electrode layer 513 is the first dielectric structure 5130, with source The part that pole layer 517 is located on the same floor is the second dielectric structure 519.

Source layer 517 and drain electrode layer 513 vertically overlap, meanwhile, source layer 517 and drain electrode layer 513 are perpendicular There is part not to be overlapped upwards.Also, source layer 517 and drain electrode layer 513 are vertically nonoverlapping to be partly due to the first dielectric Caused by the presence of structure 5130 and the second dielectric structure 519.That is the first dielectric structure 5130 and the second dielectric structure 519 are perpendicular It is not overlapped upwards, and the two is located at two ends of fin, so that guarantee section source layer 517 is vertically situated between with first Electric structure 5130 is being overlapped, and part drain electrode layer 513 is vertically Chong Die with the second dielectric structure 519.On the one hand, source layer 517 It needs vertically to partly overlap with drain electrode layer 513, to guarantee that source layer 517 and drain electrode layer 513 can be respectively as NAND The source electrode and drain electrode of flash memory storage cells；On the other hand, source layer 517 and drain electrode layer 513 vertically need nonoverlapping Two ends, to guarantee that the string source electrode 5431 that is subsequently formed and string drain electrode 5432 can only connect with one of the two respectively It connects, that is, guarantees to form corresponding nand flash memory data cell array structure.

In the present embodiment, semiconductor substrate 500 is silicon substrate.In other embodiments of the invention, semiconductor substrate 500 Or the substrate that germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their combination are formed, or Person is silicon-on-insulator substrate, or other the suitable semiconductive material substrates being known to the skilled person.

In the present embodiment, the step of forming the fin, be may include:

In 500 growing epitaxial layers of semiconductor substrate, N+ heavy doping is carried out in epitaxial layer and forms drain electrode layer 513；

In 513 growing epitaxial layers of drain electrode layer, P+ heavy doping is carried out in epitaxial layer and forms source layer 517；

Patterned hard mask layer is formed on the source layer 517；

Using the patterned hard mask layer as mask, the source layer 517, drain electrode layer 513 and semiconductor substrate are etched 500, until forming the fin.

In other embodiments of the invention, the position of source layer 517 and drain electrode layer 513 can be exchanged.

In the forming process of above-mentioned fin, above-mentioned first dielectric structure 5130 and the second dielectric structure can be formed simultaneously 519。

The multiple laminated construction being intervally arranged are formed in the fin length direction.Tunneling medium layer 531 is formed, Tunneling medium layer 531 is covered on the top and two sides of the part fin.Charge trapping layer 533 is formed, charge trapping layer 533 covers It covers at the top and two sides of tunneling medium layer 531.Gate dielectric layer 535 is formed, gate dielectric layer 535 is covered on charge trapping layer 533 Top and two sides.Grid 537 is formed, grid 537 is covered on the top and two sides of the gate dielectric layer 535.

The exposure fin portion surface forms Tunnel dielectric material layer in the entire fin portion surface；

Charge-trapping material layer is formed in the Tunnel dielectric material layer；

Gate dielectric material layer is formed on charge-trapping material layer；

Gate material layer is formed on gate dielectric material layer；

Hard mask layer is formed in gate material layer；

Photoresist layer is formed on hard mask layer, and the photoresist layer is exposed and developing process carry out pattern Change；

Using patterned photoresist layer as mask, etch the hard mask layer, then with after etching the hard mask layer and The remaining photoresist layer is mask, etches the gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric Material layer, until forming multiple grids 537, gate dielectric layer 535, charge trapping layer 533 and the tunneling medium layer being intervally arranged 531, and the surface of the fin between neighboring gates 537 is exposed again.

In above process, etching off is subsequently formed the region and other of string source electrode and string drain electrode in addition to being located in the same time Above-mentioned each material layer of non-area of grid.In the above process, it can be exposed using thermal oxidation method or chemical oxidization method The fin portion surface forms tunneling medium layer 531.

It should be strongly noted that since charge trapping layer is only required to be formed at data cell region, in above-mentioned etching It in the process, further include the further charge-trapping material layer etched in removal peripheral device region.

In the present embodiment, the material of charge trapping layer 533 can be silicon nitride.Using silicon nitride as charge trapping layer When 533, after corresponding charge enters trap layer, it is not susceptible to move, therefore, corresponding data stabilization.

In the present embodiment, the material of tunneling medium layer 531 and gate dielectric layer 535 all can be silica.Tunnelling is situated between at this time Matter layer 531, charge trapping layer 533 and gate dielectric layer 535 form ONO laminated construction.

In the present embodiment, the material of grid 537 can be polysilicon or metal.When the material of grid 537 is metal, Corresponding gate dielectric layer 535 can be made for high K dielectric material.

The fin both ends epitaxial growth silicon carbide or germanium silicon as the string source electrode 5431 and string drain electrode 5432. What tool was stopped, in the both ends of the fin (the fin both ends of exposure i.e. after removing mask layer), one end is formed wherein Go here and there source electrode 5431, the string source electrode 5431 connects source layer 517, forms string drain electrode 5432 in the other end, and the string drains 5432 Connect the drain electrode layer 513.

In the present embodiment, the forming step of string source electrode 5431 and string drain electrode 5432 be may include:

The fin both ends epitaxial growth silicon carbide perhaps the germanium silicon silicon carbide or germanium silicon as the string source Pole 5431 and string drain electrode 5432.During epitaxial growth string source electrode 5431 and string drain electrode 5432, to the silicon carbide or Germanium silicon carries out doping in situ, and string source electrode carries out P+ heavy doping, and string drain electrode carries out N+ heavy doping, to improve string source electrode 5431 and string The electric conductivity of drain electrode 5432.The conductivity of the silicon carbide or germanium silicon that are lightly doped is higher, the string source electrode 5431 and string worked it out 5432 dead resistances that drain are smaller.

In the present embodiment, in the fin length direction, string source electrode 5431 and string drain electrode 5432 are formed in tunnelling 531 both sides of dielectric layer, i.e. tunneling medium layer 531 are formed between string source electrode 5431 and string drain electrode 5432, that is, grid 537 is located at It goes here and there between source electrode 5431 and string drain electrode 5432, and grid 537 and corresponding source layer 517, drain electrode layer 513, tunneling medium layer 531, charge trapping layer 533 and gate dielectric layer 535 constitute nand flash memory data cell, therefore, that is to say, that the nand flash memory Data cell is located between string source electrode 5431 and string drain electrode 5432.

In the present embodiment, string source electrode 5431 is grown in 517 two sides of source layer, therefore string source electrode 5431 and source layer 517 Electrical connection.Meanwhile string source electrode 5431 is not grown in 513 side of drain electrode layer, but it is grown in above-mentioned second dielectric structure, 519 side Face, therefore, mutually insulated between string source electrode 5431 and drain electrode layer 513.Likewise, string drain electrode 5432 is grown in 513 liang of drain electrode layer Side, therefore string drain electrode 5432 is electrically connected with drain electrode layer 513.Meanwhile string drain electrode 5432 is not grown in 517 side of source layer, But it is grown in above-mentioned first dielectric structure, 5130 side, and therefore, mutually insulated between string drain electrode 5432 and source layer 517.

String source electrode 5431 and the shape of string drain electrode 5432 are in diamond shape.This is because what the epitaxial crystallization of silicon was formed, it is main If the extension decision shape of silicon materials, and carbon or the only a small amount incorporation of germanium, so not influenced substantially on shape.That is extension In the silicon carbide or germanium silicon of growth, continue to generate still along the lattice of silicon atom in the fin, and lattice growth has Anisotropy, therefore form diamond shape.

But the present embodiment is subsequent to be can also continue to form metallic silicon on string source electrode 5431, string drain electrode 5432 and grid 537 Compound (not shown), and form contact plunger (not shown) and connect each metal silicide, and at the same time connection grid 537.

In the present embodiment, three grids 537 are formd, corresponding there are three nand flash memory data cells.This three NAND Flash data unit forms nand flash memory data cell array structure with the string source electrode 5431 and string drain electrode 5432 for being located at its both sides. But in other embodiments of the invention, more discrete grids 537, such as 8,16 can be formed in the fin Or 32 grids, and these grids are intervally arranged along the fin length direction, to be formed long along the fin Multiple nand flash memory data cells for being intervally arranged of degree direction, also, these nand flash memory data cells and string source electrode 5431 and String drain electrode 5432 forms nand flash memory data cell array structure.

As shown in figure 15, in the present embodiment, in the fin length direction, string source electrode 5431 and each grid 537 Between also make active selection transistor 560.

Source selection transistor 560 is similarly formed on the fin, and source selection transistor 560 is with the source layer 517 a portion is channel region 561, i.e., has channel region of the partial region as source selection transistor 560 in source layer 517 561。

The forming process of specific channel region 561 may include: when being doped to form source layer 517 to the fin, Using mask layer protection above channel region 561, so that anti-region here is doped, and it is left intrinsic semiconductor structure (for example, intrinsic silicon structure).Also, opposite with 517 doping type of source layer light mix can also be carried out to this region later It is miscellaneous.Such as when source layer 517 carry out be P+ type heavy doping when, can to channel region 561 carry out N-type be lightly doped.

In source selection transistor 560,561 two sides of channel region are covered by gate dielectric layer 563.In the present embodiment, gate dielectric layer 563 either etching tunneling medium layer 531 and when gate dielectric layer 535, being retained in the laminated construction of 561 two sides of channel region, It is also possible to individually in the single layer structure of 561 two sides of channel region production.

In source selection transistor 560, gate dielectric layer 563 is covered by grid 565, and the encirclement of grid 565 is covered on channel 561 two sides of area.

In the fin length direction, since source selection transistor 560 is produced on string source electrode 5431 and grid 537 Between, i.e., source selection transistor 560 is produced between string source electrode 5431 and each nand flash memory data cell, and therefore, source selection is brilliant Body pipe 560 can control whether be connected between string source electrode 5431 and each nand flash memory data cell.

In the present embodiment, multiple nand flash memory data cells and string source electrode 5431, string drain electrode and source select crystal Pipe 560 forms nand flash memory data cell array structure.

It should be noted that in other embodiments of the invention, in the fin length direction, and described Between string drain electrode and the grid, it can also be formed with leakage selection transistor, and described in the leakage selection transistor also uses A portion of drain electrode layer is channel region, i.e., the described leakage selection transistor is produced on the string drain electrode and each nand flash memory data Between unit, therefore, the leakage selection transistor can control whether be connected between string drain electrode and each nand flash memory data cell.

It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims

1. a kind of data cell array structure of nand flash memory, characterized by comprising:

Semiconductor substrate；

Fin in the semiconductor substrate, the fin includes: source layer, channel layer and the drain electrode being vertically laminated Layer, the channel layer are located among the source layer and drain electrode layer；

Several laminated construction, each laminated construction are covered on the top and two sides of the part fin, the lamination knot The quantity of structure is more than or equal to 1, and the laminated construction is intervally arranged along the fin length direction, the lamination packs Contain: being covered on the top of the part fin and the tunneling medium layer of two sides, the top and two for being covered on the tunneling medium layer The charge trapping layer of side, the top for being covered on the charge trapping layer and two sides gate dielectric layer and be covered on the gate dielectric layer Top and two sides grid；

Wherein, the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type, and the channel layer is p-type It is lightly doped or intrinsic semiconductor layer, the string source electrode is P+ type heavy doping, the string drain electrode is the heavy doping of N+ type.

2. the data cell array structure of nand flash memory as described in claim 1, which is characterized in that in the fin length institute On direction, all the grid is located between the string source electrode and string drain electrode.

3. the data cell array structure of nand flash memory as described in claim 1, which is characterized in that in the fin length institute Also have between source selection transistor or the grid and string drain electrode on direction, between string source electrode and the grid and also has There is leakage selection transistor.

4. a kind of data cell of nand flash memory, characterized by comprising:

Semiconductor substrate；

Wherein, wherein the source layer is P+ type heavy doping, and the drain electrode layer is the heavy doping of N+ type, the channel layer It is lightly doped for p-type or intrinsic semiconductor layer.

5. a kind of method of the data cell array structure of nand flash memory of formation as described in any one of claim 1-2, It is characterized in that comprising the steps of:

Semiconductor substrate is provided；

Fin is formed on the semiconductor substrate, the fin includes: source layer, channel layer and the drain electrode being vertically laminated Layer, the channel layer are located among the source layer and drain electrode layer；

Several laminated construction are formed on fin, each laminated construction is covered on the top and two of the part fin Side, the laminated construction are intervally arranged along the fin length direction, and the laminated construction includes: being covered on described in part The tunneling medium layer of the top of fin and two sides is covered on the top of the tunneling medium layer and the charge trapping layer of two sides, covers It covers the gate dielectric layer at the top and two sides in the charge trapping layer and is covered on the top of the gate dielectric layer and the grid of two sides Pole；

6. the forming method of the data cell array structure of nand flash memory as claimed in claim 5, which is characterized in that described Laminated construction is formed between the string source electrode and string drain electrode.

7. the forming method of the data cell array structure of nand flash memory as claimed in claim 6, which is characterized in that form institute The step of stating fin includes:

Channel layer is epitaxially-formed on the drain electrode layer；

Patterned hard mask layer is formed on the source layer；

Using the patterned hard mask layer as mask, the source layer, channel layer, drain electrode layer and semiconductor substrate are etched, directly To the formation fin.

8. the forming method of the data cell array structure of nand flash memory as claimed in claim 6, which is characterized in that form institute The step of stating fin includes:

Channel layer is epitaxially-formed on the source layer；

Patterned hard mask layer is formed on the drain electrode layer；

Using the patterned hard mask layer as mask, the drain electrode layer, channel layer, source layer and semiconductor substrate are etched, directly To the formation fin.

9. the forming method of the data cell array structure of the nand flash memory as described in any one of claim 7 or 8, special The step of sign is, forms the laminated construction includes:

It forms mask layer and covers the entire fin；

10. the forming method of the data cell array structure of nand flash memory as claimed in claim 9, which is characterized in that formed The step of string source electrode and string drain electrode, includes:

The mask layer is etched with the both ends of the exposure fin, and retains and is covered with the described of the charge trapping layer contact portion Film layer；

In the both ends epitaxial growth silicon carbide or germanium silicon of the fin, and carries out in situ adulterate and form the string source electrode and string leakage Pole.

11. the forming method of the data cell array structure of the nand flash memory as described in any one of claim 7 or 8, The step of being characterized in that, forming the laminated construction includes:

It forms Tunnel dielectric material layer and covers the fin；

It forms gate material layer and covers the gate dielectric material layer；

It is sequentially etched the gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric material layer, until being formed The grid, gate dielectric layer, charge trapping layer and tunneling medium layer.

12. the forming method of the data cell array structure of nand flash memory as claimed in claim 11, which is characterized in that formed The step of string source electrode and string drain electrode, includes:

In the both ends epitaxial growth silicon carbide or germanium silicon of the fin, and carry out it is in situ adulterate formed as the string source electrode with String drain electrode.