CN105810684A

CN105810684A - NAND flash memory storage unit, storage unit array structure and forming method thereof

Info

Publication number: CN105810684A
Application number: CN201410854908.9A
Authority: CN
Inventors: 黄新运; 肖磊; 沈磊; 刘岐; 徐烈伟; 刘红霞
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2014-12-31
Filing date: 2014-12-31
Publication date: 2016-07-27

Abstract

The invention relates to an NAND flash memory storage unit, a storage unit array structure and a forming method thereof. The NAND flash memory storage unit comprises a semiconductor substrate, a fin which is located on the semiconductor substrate, a tunneling dielectric layer which covers the top and both sides of the fin, a charge trap layer which covers the top and both sides of the tunneling dielectric layer, a gate dielectric layer which covers the top and both sides of the charge trap layer, and a gate which covers the top and both sides of the gate dielectric layer. The fin comprises a source layer, a channel layer and a drain layer, wherein the source layer, the channel layer and the drain layer are vertically stacked up. The channel layer is located between the source layer and the drain layer. The NAND flash memory storage unit has the great capability of continuous process dimension reduction and can solve the problem of reading interference of the storage unit from the aspect of device structure. The forming method of the NAND flash memory storage unit array structure has the advantages of being simple and reduced process cost.

Description

Nand flash memory memory element, memory cell array structure and forming method thereof

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to a kind of nand flash memory memory element, memory cell array structure and forming method thereof.

Background technology

Nand flash memory (NANDflash) is a kind of nonvolatile flash memory, major function is data on file, has higher density of memory cells, write and erasing speed are fast, the memory cell size of nand flash memory is almost the half of NOR flash memory memory cell size simultaneously, higher capacity can be provided in given die size, be currently mainly used in digital camera flash card and MP3 player.

The generally planar structure of memory element of existing nand flash memory, it generally adopts polysilicon as floating boom.Along with the reduction of dimensions of semiconductor devices, adopt polysilicon as floating boom be faced with can tunnelling to the electron deficiency of floating boom, and multi-crystal silicon floating bar forming process needs to adopt the repeatedly problem such as photoetching and etching technics.More seriously, existing nand flash memory there is also the problem reading interference (readdisturb).

Summary of the invention

The problem that this invention address that is to provide a kind of nand flash memory memory element, memory cell array structure and forming method thereof, to improve the performance of nand flash memory memory element, reduce the size of nand flash memory memory element and nand flash memory memory cell array structure, and simplify nand flash memory memory element and the processing technology of nand flash memory memory cell array structure.

For solving the problems referred to above, the present invention provides a kind of nand flash memory memory element, including:

Semiconductor substrate；

Being positioned at the fin in described Semiconductor substrate, described fin includes the source layer of stacking, channel layer and drain electrode layer on vertical, and described channel layer is positioned in the middle of described source layer and drain electrode layer；

Tunneling medium layer, covers top and the both sides of the described fin of part；

Charge trapping layer, covers top and the both sides of described tunneling medium layer；

Gate dielectric layer, covers top and the both sides of described charge trapping layer；

Grid, covers top and the both sides of described gate dielectric layer.

Optionally, the thickness range of described channel layer is 50nm～70nm.

Optionally, the thickness range of described charge trapping layer is 15nm～40nm.

For solving the problems referred to above, present invention also offers a kind of nand flash memory memory cell array structure, including:

Semiconductor substrate；

One tunneling medium layer, or along multiple tunneling medium layer that direction, described fin length place is intervally arranged, each described tunneling medium layer all covers top and the both sides of the described fin of part；

Cover the top of described tunneling medium layer and the charge trapping layer of both sides；

Cover the top of described charge trapping layer and the gate dielectric layer of both sides；

Cover the top of described gate dielectric layer and the grid of both sides

Connect the string source electrode of described source layer；

Connect the string drain electrode of described drain electrode layer.

Optionally, on direction, described fin length place, whole described grids are between described string source electrode and described string drain.

Optionally, the thickness range of described channel layer is 50nm～70nm.

Optionally, the material of described string source electrode and the drain electrode of described string is carborundum or germanium silicon.

Optionally, on direction, described fin length place, also there is between described string source electrode and grid source and select transistor, or also there is between described grid and string drain electrode leakage selection transistor.

For solving the problems referred to above, present invention also offers the forming method of a kind of nand flash memory memory cell array structure, including:

Semiconductor substrate is provided；

Forming fin on the semiconductor substrate, described fin includes the source layer of stacking, channel layer and drain electrode layer on vertical, and described channel layer is positioned in the middle of described source layer and drain electrode layer；

Forming tunneling medium layer, described tunneling medium layer covers top and the both sides of the described fin of part；

Forming charge trapping layer, described charge trapping layer covers top and the both sides of described tunneling medium layer；

Forming gate dielectric layer, described gate dielectric layer covers top and the both sides of described charge trapping layer；

Forming a grid, or form the multiple grids being intervally arranged along direction, described fin length place, described grid covers top and the both sides of described gate dielectric layer；

Form string source electrode in wherein one end of described fin, described string source electrode connects described source layer；

The other end at described fin forms string drain electrode, and described string drain electrode connects described drain electrode layer.

Optionally, on direction, described fin length place, described tunneling medium layer is formed between described string source electrode and described string drain.

Optionally, the step forming described fin includes:

Form the first heavily doped layer on a semiconductor substrate；

Described first heavily doped layer is formed channel layer；

Described channel layer is formed the second heavily doped layer；

Described second heavily doped layer is formed the hard mask layer of patterning；

One of them of described first heavily doped layer and the second heavily doped layer respectively described source layer and drain electrode layer, and both are different；

With the hard mask layer of described patterning for mask, etch described second heavily doped layer, channel layer, the first heavily doped layer and Semiconductor substrate, until forming described fin.

Optionally, the step forming described fin includes:

Adulterate Semiconductor substrate to form the first heavily doped layer；

Described first heavily doped layer is formed channel layer；

Described channel layer is formed the second heavily doped layer；

Optionally, epitaxial growth method or vapour deposition process is adopted to form described second heavily doped layer.

Optionally, also including described channel layer is gently adulterated, the atomic concentration that described light doping is injected is 10E17atom/cm³。

Optionally, form described tunneling medium layer to include:

Form mask layer and cover described fin；

Etch described mask layer, to form groove, the top of fin described in described groove expose portion and both sides；

Described fin portion surface at described bottom portion of groove forms described tunneling medium layer.

Optionally, the process forming described string source electrode and string drain electrode includes:

Etch described mask layer to expose the two ends of described fin, and retain mask layer described with the part that described charge trapping layer contacts；

Two ends epitaxial growth carborundum or germanium silicon at described fin drain as described string source electrode and string.

Optionally, form described tunneling medium layer, including:

Form Tunnel dielectric material layer and cover described fin；

Form charge-trapping material layer and cover described Tunnel dielectric material layer；

Form gate dielectric material layer and cover described charge-trapping material layer；

Form gate material layer and cover described gate dielectric material layer；

Etch described gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric material layer, until forming described grid, gate dielectric layer, charge trapping layer and tunneling medium layer.

Optionally, the forming step of described string source electrode and string drain electrode includes: at two ends epitaxial growth carborundum or the germanium silicon of described fin, described carborundum or germanium silicon as described string source electrode and string drain electrode.

Compared with prior art, technical scheme has the advantage that

In technical scheme, Semiconductor substrate is provided, and form the fin being positioned in described Semiconductor substrate, described fin includes the source layer of stacking on vertical, channel layer and drain electrode layer, described channel layer is positioned in the middle of described source layer and drain electrode layer, it is subsequently formed tunneling medium layer to cover top and the both sides of the described fin of part, form charge trapping layer again to cover top and the both sides of described tunneling medium layer, hereafter gate dielectric layer is formed to cover top and the both sides of described charge trapping layer, eventually form grid to cover top and the both sides of described gate dielectric layer.The structure formed forms a kind of nand flash memory memory element, in described nand flash memory memory element, using source layer as source electrode, using drain electrode layer as drain electrode, and raceway groove is formed in described channel layer, and the stacking on vertical of source layer, channel layer and drain electrode layer, therefore, described nand flash memory memory element has good process and continues to reduce ability.And, even when multiple described nand flash memory memory element are made in same fin, owing to carrier when each described nand flash memory memory element works is from source layer to drain electrode layer all, therefore their working method is in parallel, now, easily produce distant or tortuous path between drain electrode (drain electrode and the described drain electrode layer of part) and the charge trapping layer of consecutive storage unit of hot carrier, and direction of an electric field is not pointing at the charge trapping layer of consecutive storage unit, but from source layer to drain electrode layer (or from drain electrode layer to source layer), therefore, it is possible to prevent when a memory element is read, hot carrier enters the phenomenon of consecutive storage unit, namely from device architecture, solve the problem that memory element reads interference.

Further, the thickness range of channel layer can be 50nm～70nm.In the nand flash memory memory element provided, on the one hand, due to the thickness flowing of the electric current vertical furrow channel layer of described nand flash memory memory element, if the thickness of channel layer is less than 50nm, be then difficult to by the corresponding channel current of gate turn-off；On the other hand, if the thickness of channel layer is more than 70nm, corresponding channel resistance increases, and electric current is too little, affects the performance of nand flash memory memory element equally.

Accompanying drawing explanation

Fig. 1 is existing NAND flash memory structure schematic diagram；

Fig. 2 is the structure chart after existing nand flash memory simplifies；

Fig. 3 to Figure 16 is each step counter structure schematic diagram of forming method of the nand flash memory memory cell array structure that the embodiment of the present invention provides；

Figure 17 is the perspective view that another embodiment of the present invention is provided the forming method of another nand flash memory memory cell array structure corresponding；

Figure 18 is the top view cross section structural representation that further embodiment of this invention is provided the forming method of another nand flash memory memory cell array structure corresponding.

Detailed description of the invention

As described in background, there is the problem reading interference in existing nand flash memory, reads interference it is to be understood that the impact that another memory element preserves data that the read-write operation of a memory element is caused.The reason reading interference to find existing nand flash memory to exist, Fig. 1 and Fig. 2 shows the structure of existing nand flash memory.

Refer to Fig. 1, existing nand flash memory includes the channel region 110 being positioned in Semiconductor substrate, it is positioned at the tunneling medium layer 120 on channel region 110, it is positioned at the multiple discrete floating boom 130 in tunneling medium layer 120, it is positioned at the gate dielectric layer 140 on floating boom 130, it is positioned on gate dielectric layer 140 control gate 150, and the interlayer dielectric layer 160 between each floating boom 130, gate dielectric layer 140 and control gate 150.

Fig. 1 shows two adjacent floating booms 130, therefore to there being two adjacent memory element.But, after repeatedly one of them memory element being read, can there is the upset of such as 1 to 0 in the data of memory element adjacent thereto.This is because, when one of them memory element is read data, the drain terminal of this memory element has hot carrier and is formed, and these hot carriers can enter in the floating boom of consecutive storage unit in the effect next part of electric field.If originally there is no electronics in the floating boom of this consecutive storage unit, then the entrance of these hot carriers can allow the data of this consecutive storage unit overturn.

Namely said process there occurs hot carrier in jection (HCI), hot carrier in jection is one phenomenon of generation in solid electronic device, after electronics or hole obtain enough kinetic energy, they just can break through the constraint (" heat " this term in hot carrier refers to the effective temperature for carrier density is modeled, and the temperature of non-device itself) of potential barrier.Owing to carrier is bound in the gate dielectric layer of metal oxide semiconductor field effect tube, the switch performance of transistor can for good and all be changed, and hot carrier in jection is a kind of mechanism being likely to and semiconductor device reliability being had a negative impact.For nand flash memory, hot carrier (is generally thermoelectron) and is likely to be injected in floating boom, thus changing the data mode that memory element preserves.

Refer to Fig. 2, the structure chart after simplifying for existing nand flash memory, wherein, floating boom represents with two parallel strigulas with control gate.Therefrom it can be seen that, the hot carrier in jection produced when one of them memory element is to after the floating boom of consecutive storage unit, can cause that mistake occur in the data that consecutive storage unit stores, thus causing that the storage data of this consecutive storage unit go wrong (nogood, NG).

In order to solve to read the problem of interference, when the method at present nand flash memory adopted is to change read operation, the voltage of wordline (wordline), slows down the formation of hot carrier.Such as reduce the voltage difference read between unit and its adjacent power wordline.

But, by reducing the voltage difference read between unit and its adjacent power wordline, the generation of this reading interference phenomenon can only be alleviated.Owing to the threshold difference (Δ Vth) between the memory element of data 0 and 1 correspondence must assure that distinguishing of data, it is impossible to continue to reduce.So along with the increase of the reduction of flush memory device size and integrated level, this way will be unable to use.Additionally, for long numeric data unit (MLC, one data element memory puts long numeric data) threshold value span bigger than a data unit (SLC, a data element memory puts a data), so this situation reading interference can be more serious.

For this, the present invention provides a kind of new nand flash memory memory element, and described memory element includes Semiconductor substrate, is positioned at the fin in described Semiconductor substrate, described fin includes the source layer of stacking, channel layer and drain electrode layer on vertical, and described channel layer is positioned in the middle of described source layer and drain electrode layer；Tunneling medium layer, covers top and the both sides of the described fin of part；Charge trapping layer, covers top and the both sides of described tunneling medium layer；Gate dielectric layer, covers top and the both sides of described charge trapping layer；Grid, covers top and the both sides of described gate dielectric layer.The stacking on vertical of the source layer of described nand flash memory memory element, channel layer and drain electrode layer, therefore, described nand flash memory memory element has good process and continues to reduce ability.And, even if multiple described nand flash memory memory element are made in same fin, due to distant or tortuous path between drain electrode (drain electrode and the described drain electrode layer of part) and the charge trapping layer of consecutive storage unit, and direction of an electric field is not pointing at the charge trapping layer of consecutive storage unit, but from source layer to drain electrode layer, therefore, it is possible to prevent when a memory element is read, hot carrier enters the phenomenon of consecutive storage unit, namely solves the problem that memory element reads interference from device architecture.

Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.

The embodiment of the present invention provides the forming method of a kind of nand flash memory memory cell array structure, incorporated by reference to reference Fig. 3 to Figure 16.

Refer to Fig. 3 to Fig. 5, Semiconductor substrate 300 is provided, and in Semiconductor substrate 300, forming fin (mark), described fin includes the source layer 317 of stacking, channel layer 315 and drain electrode layer 313 on vertical, and channel layer 315 is positioned in the middle of source layer 317 and drain electrode layer 313.

Fig. 3 is the plan structure of described fin, shows the top of described fin in Fig. 3, and this top is specially semiconductor layer 319 (incorporated by reference to reference Fig. 4).It can be seen in figure 3 that described fin has certain length, this direction, length place is identical with direction, X-X1 chain-dotted line place, and described fin has certain width, and this direction, width place is identical with direction, Y-Y1 chain-dotted line place.The head-tail in direction, described fin length place is divided into the two ends of described fin, and the both sides that two edges are described fin in direction, described fin width place.

Fig. 4 is the cross-section structure that plan structure shown in Fig. 3 obtains along X-X1 chain-dotted line cutting.Described fin includes the semiconductor layer 319 of stacking, source layer 317, channel layer 315, drain electrode layer 313 and semiconductor layer 311 on vertical as can see from Figure 4.Concrete, semiconductor layer 319, source layer 317, channel layer 315, drain electrode layer 313 and semiconductor layer 311 stack gradually from top to bottom, namely semiconductor layer 319 is positioned on source layer 317, source layer 317 is positioned on channel layer 315, channel layer 315 is positioned on drain electrode layer 313, and drain electrode layer 313 is positioned on semiconductor layer 311.

In the present embodiment, vertically refer to the direction substantially vertical with wafer upper surface (wafer upper surface generally that is Semiconductor substrate 300 upper surface).Accordingly, laterally refer to and wafer upper surface direction that is substantially parallel.

In the present embodiment, semiconductor layer 319 can be unadulterated silicon materials.In other embodiments, it is also possible to need not have semiconductor layer 319, it is also possible to adopting hard mask layer alternative semiconductors layer 319, this is not construed as limiting by the present invention.

In Fig. 4, separate with dotted line between semiconductor layer 311 and Semiconductor substrate 300, this is because, generally both are originally used for substrat structure, and simply after etching technics, semiconductor layer 311 becomes described fin and is positioned at the part of bottom.

In Fig. 4, in described fin, the part-structure being positioned at same layer from drain electrode layer 313 has the shading different with drain electrode layer 313, and this is that this part-structure is not intended as conductive structure, can be described as the first dielectric structure in order to show that this part-structure is not drain electrode layer 313.Described first dielectric structure and semiconductor layer 311 separate with dotted line between described first dielectric structure and the semiconductor layer 311 of lower floor, this is because can be structure as a whole.The process forming drain electrode layer 313 and semiconductor layer 311 can be: Semiconductor substrate 300 is carried out source and drain heavy doping, then Semiconductor substrate 300 is performed etching, Semiconductor substrate 300 has carried out the heavily doped part of described source and drain and has been left drain electrode layer 313 after etching, Semiconductor substrate 300 does not carry out the heavily doped part of described source and drain and is then left above-mentioned first dielectric structure, accordingly, part semiconductor substrate 300 below drain electrode layer 313 and described first dielectric structure then becomes semiconductor layer 311, known, now described first dielectric structure and semiconductor layer 311 are the part remained after Semiconductor substrate 300 is etched.

It should be noted that in other embodiments, described first dielectric structure can also individually adopt deposition process to be formed, thus becoming an independent part, the forming method of the first dielectric structure is not construed as limiting by the present invention.

Same, Fig. 4 shows, the part-structure being positioned at same layer from source layer 317 has the shading different with source layer 317, and this is that this part-structure is not intended as conductive structure, can be described as the second dielectric structure in order to show that this part-structure is not source layer 317.Described second dielectric structure and semiconductor layer 319 separate with dotted line between described second dielectric structure and the semiconductor layer 319 on upper strata, this is because can be structure as a whole.The process forming source layer 317 and semiconductor layer 319 can be: forms semiconductor material layer on channel layer 315, the thickness of this semiconductor material layer is source layer 317 and semiconductor layer 319 sum, then described semiconductor material layer is carried out source and drain heavy doping, to form source layer 317, and unadulterated part is left semiconductor layer 319 and described second dielectric structure, thus now described second dielectric structure and semiconductor layer 319 are the overall structure that semiconductor material layer remains.

It should be noted that in other embodiments, described second dielectric structure can also individually adopt deposition process to be formed, thus becoming an independent part, the forming method of the second dielectric structure is not construed as limiting by the present invention.

In Fig. 4, source layer 317 and drain electrode layer 313 overlap on vertical, and meanwhile, source layer 317 and drain electrode layer 313 have part not overlapping on vertical.Further, source layer 317 and drain electrode layer 313 are nonoverlapping partially due to what the existence of described first dielectric structure and the second dielectric structure caused vertical.Namely described first dielectric structure and the second dielectric structure are not overlapping on vertical, and both lay respectively at two ends of fin, thus guarantee section source layer 317 on vertical with described first dielectric structure overlapping, part drain electrode layer 313 is overlapping with described second dielectric structure on vertical.

In the present embodiment, on the one hand, source layer 317 and drain electrode layer 313 need to partly overlap on vertical, thus ensureing that source layer 317 and drain electrode layer 313 can respectively as the source electrode of nand flash memory storage element and drain electrodes；On the other hand, source layer 317 and drain electrode layer 313 need nonoverlapping two ends on vertical, only is connected with both one of them thus ensureing that the string source electrode 3431 being subsequently formed and string drain electrode 3432 (refer to Figure 11) can distinguish, i.e. the corresponding nand flash memory memory cell array structure of guarantee formation.

Fig. 5 is the cross-section structure that plan structure shown in Fig. 3 obtains along Y-Y1 chain-dotted line cutting.It will also be seen that semiconductor layer 311, drain electrode layer 313, channel layer 315, source layer 317 and semiconductor layer 319 stack gradually from top to bottom from Fig. 5.Furthermore, it is possible to it is further seen that Semiconductor substrate 300 surface is coated with protective layer 321.Semiconductor substrate 300 can be protected by protective layer 321.

It is generally more intuitively the integrative-structure being connected with Semiconductor substrate 300 to, semiconductor layer in described fin 311 from Fig. 5.Therefore, separate with dotted line between the two.

It should be noted that in other embodiments, it would however also be possible to employ the method for deposition forms semiconductor layer 311 in Semiconductor substrate 300, and now semiconductor layer 311 and Semiconductor substrate 300 are then the different layers structure of essence.

In the present embodiment, Semiconductor substrate 300 is silicon substrate.In other embodiments of the invention, Semiconductor substrate 300 can also be the substrate that germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their combination are formed, or be silicon-on-insulator substrate, or other suitable semiconductive material substrate being known to the skilled person.

In the present embodiment, form the step of described fin and may include that in Semiconductor substrate 300, form the first heavily doped layer；Described first heavily doped layer is formed channel layer 315；Channel layer 315 is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, channel layer the 315, first heavily doped layer and Semiconductor substrate 300, until forming described fin.After forming described fin, described hard mask layer can be removed, it is also possible to is retained in above semiconductor layer 319.

In the present embodiment, the doping type of described first heavily doped layer and the second heavily doped layer can be N-type, and in other embodiments, the doping type of described first heavily doped layer and the second heavily doped layer can also be P type.

In the forming process of above-mentioned fin, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 317 and drain electrode layer 313, and both are different.Namely in other embodiments of the invention, the position of source layer 317 and drain electrode layer 313 can be exchanged.

In the forming process of above-mentioned fin, it is possible to concurrently form above-mentioned first dielectric structure and the second dielectric structure.

In the forming process of above-mentioned fin, channel layer 315 can be intrinsic semiconductor layer, for instance intrinsic silicon material layer, it is also possible to include channel layer 315 is gently adulterated, and the atomic concentration that described light doping is injected is 10E17atom/cm³, and the conduction type of the atom of described light doping injection is contrary with the conduction type of source layer 317 and drain electrode layer 313.Namely, when source layer 317 and drain electrode layer 313 are n-type doping, channel layer 315 doping is P type atom.

In the forming process of above-mentioned fin, it is possible to adopt epitaxial growth method or vapour deposition process to form described second heavily doped layer.

It should be noted that in other embodiments, the step forming described fin can also for comprising the following steps: adulterates to form the first heavily doped layer to Semiconductor substrate 300；Described first heavily doped layer is formed channel layer 315；Channel layer 315 is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, channel layer the 315, first heavily doped layer and Semiconductor substrate 300, until forming described fin.Wherein, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 317 and drain electrode layer 313, and both are different.

Same, in the forming process of described fin, it is possible to adopt epitaxial growth method or vapour deposition process to form described second heavily doped layer, it is possible to channel layer 315 is gently adulterated, the atomic concentration that described light doping is injected is 10E17atom/cm³。

Refer to Fig. 6 to Fig. 9, form a tunneling medium layer 331, tunneling medium layer 331 covers top and the both sides of the described fin of part.Forming charge trapping layer 333, charge trapping layer 333 covers top and the both sides of described tunneling medium layer 331.Forming gate dielectric layer 335, gate dielectric layer 335 covers top and the both sides of charge trapping layer 333.Forming grid 337, grid 337 covers top and the both sides of described gate dielectric layer 335.

Fig. 6 is the plan structure after forming grid 337, and therefrom it will be seen that the two ends on direction, described fin length place are covered by mask layer 323, and middle one section is covered by grid 337.Further, there is charge trapping layer 333 and gate dielectric layer 335 between grid 337 and mask layer 323.Gate dielectric layer 335 is between grid 337 and charge trapping layer 333.

Fig. 7 is the cross-sectional view that structure shown in Fig. 6 obtains along X-X2 chain-dotted line cutting.See from Fig. 7, in the middle of on direction, described fin length place, the top of a section defines tunneling medium layer 331, charge trapping layer 333, gate dielectric layer 335 and grid 337.

Fig. 8 is the cross-sectional view that structure shown in Fig. 6 obtains along Y-Y2 chain-dotted line cutting.In conjunction with Fig. 6, Fig. 7 and Fig. 8 it is recognised that tunneling medium layer 331, charge trapping layer 333, gate dielectric layer 335 and grid 337 not only cover the top of the described fin of part, also cover the both sides of fin described in these parts simultaneously.Further, tunneling medium layer 331 is between described fin and charge trapping layer 333.Charge trapping layer 333 is between gate dielectric layer 335 and tunneling medium layer 331 and gate dielectric layer 335.Gate dielectric layer 335 is between grid 337 and charge trapping layer 333.

Fig. 9 is the cross-sectional view that structure shown in Fig. 6 obtains along Y-Y3 chain-dotted line cutting.It can further be seen that the top above described fin two ends is covered by mask layer 323 in Fig. 7, in conjunction with Fig. 7 and Fig. 9 it can be seen that mask layer 323 also covers the both sides of fin described in this part simultaneously.

In the present embodiment, the material of mask layer 323 can be wanted or carbonitride of silicium for silicon nitride, or the laminated construction of silicon nitride and silicon oxide.

In the present embodiment, the material of charge trapping layer 333 can be silicon nitride.When adopting silicon nitride as charge trapping layer 333, after corresponding electric charge enters trap layer, it is not susceptible to mobile, therefore, corresponding data stabilization.

In the present embodiment, the material of tunneling medium layer 331 and gate dielectric layer 335 can be all silicon oxide.Now tunneling medium layer 331, charge trapping layer 333 and gate dielectric layer 335 form ONO (oxide-nitride-oxide) laminated construction.

In the present embodiment, the process forming tunneling medium layer 331 may include that formation mask layer 323 covers whole described fin；Then, etching mask layer 323, to form groove (not shown), the top of fin described in described groove expose portion and both sides, and what expose is in the middle of direction, described fin length place one section, namely now remaining mask layer 323 as shown in Fig. 6 to Fig. 9；Afterwards, the described fin portion surface at described bottom portion of groove forms tunneling medium layer 331, concrete, it is possible to adopt thermal oxidation method or chemical oxidization method to form tunneling medium layer 331 in the described fin portion surface being exposed.

In the present embodiment, after forming tunneling medium layer 331, chemical gaseous phase depositing process (CVD), physical gas-phase deposite method (PVD) or Atomic layer deposition method (ALD) specifically can be adopted to form charge trapping layer 333, so that charge trapping layer 333 covers described groove inner wall.Then proceed to form gate dielectric layer 335 at described groove inner wall, so that gate dielectric layer 335 covers charge trapping layer 333.Eventually form grid 337 and fill described groove, so that gate dielectric layer 335 is between charge trapping layer 333 and grid 337.

It should be noted that in other embodiments of the invention, forming described tunneling medium layer 331 can also include: forms Tunnel dielectric material layer and covers described fin；Form charge-trapping material layer and cover described Tunnel dielectric material layer；Form gate dielectric material layer and cover described charge-trapping material layer；Form gate material layer and cover described gate dielectric material layer；Then, it is sequentially etched described gate material layer, gate dielectric material layer, charge-trapping material layer and Tunnel dielectric material layer, until forming described grid 337, gate dielectric layer 335, charge trapping layer 333 and tunneling medium layer 331.

In the present embodiment, the material of grid 337 can be polysilicon or metal.When the material of grid 337 is metal, corresponding gate dielectric layer 335 can be made for high K dielectric material.

Refer to 10 to Figure 12, mask layer 323 shown in etching Fig. 6 is to remove major part mask layer 323, and expose the two ends of described fin, retain the small part mask layer adjacent with tunneling medium layer 331 and charge trapping layer 333 323 (the part mask layer 323 that namely reservation contacts) with described charge trapping layer 333 simultaneously.Then, at the two ends epitaxial growth carborundum of described fin or germanium silicon as described string source electrode 3431 and string drain electrode 3432.And, it is also possible to continue to form metal silicide 347 on string source electrode 3431, string drain electrode 3432 and grid 337.

Tool is stopped, in the two ends of described fin (the described fin two ends namely exposed after removing mask layer 323), one end forms string source electrode 3431 wherein, described string source electrode 3431 connects source layer 317, string drain electrode 3432, the described string drain electrode 3432 described drain electrode layer 313 of connection is formed at the other end.

In the present embodiment, the forming step of string source electrode 3431 and string drain electrode 3432 may include that at the two ends epitaxial growth carborundum of described fin or germanium silicon, described carborundum or germanium silicon as described string source electrode 3431 and string drain electrode 3432.In the process of epitaxial growth string source electrode 3431 and string drain electrode 3432, it is possible to described carborundum or germanium silicon are carried out original position doping, thus improving string source electrode 3431 and the electric conductivity of string drain electrode 3432.The conductivity of lightly doped carborundum or germanium silicon is higher, and string source electrode 3431 and string drain electrode 3432 dead resistances worked it out are less.

In the present embodiment, on direction, described fin length place, string source electrode 3431 and string drain electrode 3432 formation are on tunneling medium layer 331 both sides, namely tunneling medium layer 331 is formed between string source electrode 3431 and string drain electrode 3432, that is grid 337 is between string source electrode 3431 and string drain electrode 3432, and grid 337 and corresponding source layer 317, channel layer 315, drain electrode layer 313, tunneling medium layer 331, charge trapping layer 333 and gate dielectric layer 335 constitute nand flash memory memory element, therefore, that is, described nand flash memory memory element is between string source electrode 3431 and string drain electrode 3432.

In the present embodiment, string source electrode 3431 is grown in source layer 317 two sides, and therefore string source electrode 3431 electrically connects with source layer 317.Meanwhile, string source electrode 3431 is not grown in drain electrode layer 313 side, but is grown in above-mentioned second dielectric structure side, therefore, and mutually insulated between string source electrode 3431 and drain electrode layer 313.Same, string drain electrode 3432 is grown in drain electrode layer 313 two sides, and therefore string drain electrode 3432 electrically connects with drain electrode layer 313.Meanwhile, string drain electrode 3432 is not grown in source layer 317 side, but is grown in above-mentioned first dielectric structure side, therefore, and mutually insulated between string drain electrode 3432 and source layer 317.

Figure 11 is the cross-section structure that plan structure shown in Figure 10 obtains along X-X3 chain-dotted line cutting.Can seeing from Figure 11, in said process, remaining mask layer 323 is between string source electrode 3431 and charge trapping layer 333, and between string drain electrode 3432 and charge trapping layer 333.

Figure 11 also show the lightly-doped source district 3411 that the fin below string source electrode 3431 is also formed, lightly-doped source district 3411 extends to semiconductor layer 311 from semiconductor layer 319, and namely part source layer 317 therein, channel layer 315, drain electrode layer 313 and semiconductor layer 311 also become the part in lightly-doped source district 3411.The lightly doped drain 3412 that fin below string drain electrode 3432 is also formed, lightly doped drain 3412 extends to semiconductor layer 311 from semiconductor layer 319, and namely part source layer 317 therein, channel layer 315, drain electrode layer 313 and semiconductor layer 311 also become a part for lightly doped drain 3412.

In the present embodiment, lightly-doped source district 3411 and lightly doped drain 3412 can adopt lightly doped drain injection technology to be made.But, string source electrode 3431 and string drain electrode 3432 are grown directly upon on the surface of described fin, therefore, in other embodiments of the invention, lightly doped drain injection technology can be carried out, namely being not necessarily forming lightly-doped source district 3411 and lightly doped drain 3412, thus saving processing step, saving process costs.

Figure 12 is the cross-section structure that plan structure shown in Figure 10 obtains along Y-Y4 chain-dotted line cutting.Can seeing from Figure 12, the profile of string source electrode 3431 is diamond profile.This is because what the epitaxial crystallization of silicon was formed, mainly the extension of silicon materials determines shape, and carbon or germanium is only a small amount mixes, so shape is substantially free of impact.Namely, in epitaxially grown carborundum or germanium silicon, continue to generate still along the lattice of silicon atom in described fin, and lattice growth has anisotropy, therefore forms shape shown in Figure 12.Although the shape of not shown string drain electrode 3432 in Figure 12, it will be appreciated that the shape of string drain electrode 3432 is identical with string source electrode 3431, therefore, it can in the lump with reference to structure shown in Figure 12.

Refer to Figure 13 to Figure 16, form contact plunger 351 and connect each metal silicide 347, and be simultaneously connected with grid 337.

Being shown that plan structure in Figure 13, wherein, each metal silicide 347 is generally within the centre position of grid 337 and metal silicide 347.Contact plunger 351 is formed in interlayer dielectric layer, and Figure 13 to 16 omits and shows described interlayer dielectric layer.

Figure 14 is the cross-section structure that plan structure shown in Figure 13 obtains along X-X4 chain-dotted line cutting.Figure 15 is the cross-section structure that plan structure shown in Figure 13 obtains along Y-Y5 chain-dotted line cutting.Figure 16 is the cross-section structure that plan structure shown in Figure 13 obtains along Y-Y6 chain-dotted line cutting.Contact plunger more than 351 is cylindrical, or elliptical cylinder-shape.

In the present embodiment, only defining a grid 337, corresponding only has a nand flash memory memory element.This nand flash memory memory element and the string source electrode 3431 and the string drain electrode 3432 formation nand flash memory memory cell array structure that are positioned at its both sides.But, in other embodiments of the invention, multiple discrete grid 337 can be formed at described fin, namely the multiple grids 337 being intervally arranged are being formed along direction, described fin length place, thus forming multiple nand flash memory memory element, further, these nand flash memory memory element and string source electrode 3431 and string drain electrode 3432 formation nand flash memory memory cell array structure.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, the Semiconductor substrate 300 provided defines fin, described fin includes on vertical the semiconductor layer 319 of stacking, source layer 317, channel layer 315, drain electrode layer 313 and semiconductor layer 311 from top to bottom, then form the laminated construction being made up of tunneling medium layer 331, charge trapping layer 333 and gate dielectric layer 335 and cover top and the both sides of described fin, form grid 337 again and cover described laminated construction, thus defining nand flash memory memory element.In whole forming process, eliminate photoetching when forming multi-crystal silicon floating bar and etching technics, Simplified flowsheet step.

The nand flash memory memory element formed is by source layer 317 as source electrode, and channel region is formed in channel layer 315, and by drain electrode layer 313 as drain electrode, therefore, size can significantly reduce.Simultaneously as there is no adjacent memory element, it is possible to avoid reading interference phenomenon completely.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, after defining above-mentioned nand flash memory memory element, continue again to define string source electrode 3431 and string drain electrode 3432 at the two ends of described fin, thus forming memory cell array structure.The size of described array structure is equally possible significantly to be reduced, and the performance of memory cell array structure improves.

The embodiment of the present invention additionally provides a kind of nand flash memory memory element.Described nand flash memory memory element can adopt the forming method that previous embodiment provides to be formed, and (method that is namely previously formed is when forming nand flash memory memory cell array structure, described nand flash memory memory cell array structure includes nand flash memory memory element, therefore described forming method also form nand flash memory memory element simultaneously), therefore, described nand flash memory memory element is referred to previous embodiment corresponding contents, it is possible to combine with reference to Fig. 3 to Figure 16.

Concrete, described nand flash memory memory element is incorporated by reference to reference to figures 13 to Figure 15.Wherein, Figure 13 illustrates the plan structure of described nand flash memory memory element, and Figure 14 illustrates the cross-section structure that described nand flash memory memory element obtains along X-X4 chain-dotted line cutting.Figure 15 illustrates the cross-section structure that described nand flash memory memory element obtains along Y-Y5 chain-dotted line cutting.Described nand flash memory memory element includes Semiconductor substrate 300 and the fin being positioned in Semiconductor substrate 300, described fin includes the source layer 317 of stacking, channel layer 315 and drain electrode layer 313 on vertical, and channel layer 315 is positioned in the middle of source layer 317 and drain electrode layer 313.Tunneling medium layer 331, covers top and the both sides of part fin；Charge trapping layer 333, covers top and the both sides of tunneling medium layer 331；Gate dielectric layer 335, covers top and the both sides of charge trapping layer 333；Grid 337, covers top and the both sides of gate dielectric layer.

In the present embodiment, the thickness range of channel layer 315 can be 50nm～70nm.In the nand flash memory memory element that the present embodiment provides, on the one hand, due to the thickness flowing of the electric current vertical furrow channel layer 315 of described nand flash memory memory element, if the thickness of channel layer 315 is less than 50nm, then it is difficult to turn off corresponding channel current by grid 337；On the other hand, if the thickness of channel layer 315 is more than 70nm, corresponding channel resistance increases, and electric current is too little, affects the performance of nand flash memory memory element equally.

It should be noted that concrete numerical value corresponding to above-mentioned channel layer 315 thickness is not one to channel layer 315 restriction, a but reference.When other condition variation, the thickness of channel layer 315 can also choose other appropriate value.In this specification, there is same situation in other content relating to numerical range, illustrates in the lump at this.

In the present embodiment, the thickness range of charge trapping layer 333 can be 15nm～40nm.Data charge storage position when charge trapping layer 333 is as nand flash memory storage unit stores data, need enough thickness to ensure that data charge can be stored therein on the one hand, on the other hand, its thickness needs less, to facilitate formation and the control of subsequent gate 337.

In the present embodiment, source layer 317 and drain electrode layer 313 and thickness range can be all 20nm～100nm, this is the result considered structure, if source layer 317 and drain electrode layer 313 thickness are too little, less than 20nm, then electric current handling capacity is too low, and if source layer 317 and drain electrode layer 313 thickness are too big, more than 100nm, now the height of described fin is too big, being difficult to be formed, even if defining, integrity problem also easily occurring.

Additionally, the memory element that the present embodiment provides has good process continues the ability that reduces (scaledown).Meanwhile, each memory element is one and has the two grid device both sides of channel layer 315 (grid 337 simultaneously cover), has less cut-off current.

FinFET transistor is to be awarded by Univ California-Berkeley's positive penetrating judgment recklessly to be named, and is used for describing a kind of on-plane surface dual-gate transistor being evolved and being based upon on silicon on insulated substrate based on the design of early stage DELTA (single gate) transistor.Characteristic main for FinFET is in that conductive channel is wrapped in silicon " fin " the inside.Distance between source electrode and drain electrode determines equivalent passageway (raceway groove) length of this element.Due in the forming method that the present embodiment provides, can by the fin of FinFET transistor be adulterated, corresponding doping process is increased in other words in the fin forming process of FinFET transistor, just can be formed and be arranged in the source layer of fin, channel layer and drain electrode layer, and form corresponding tunneling medium layer and charge trapping layer by increasing, namely nand flash memory memory element can be formed, known, the forming method of described memory element and traditional F inFET process compatible, therefore, simplify technique, decrease process costs.

The embodiment of the present invention additionally provides a kind of nand flash memory memory cell array structure.Described nand flash memory memory cell array structure can adopt the forming method that previous embodiment provides to be formed, and therefore, described nand flash memory memory cell array structure is referred to previous embodiment corresponding contents, it is possible to combine with reference to Fig. 3 to Figure 16.

Concrete, described nand flash memory memory cell array structure is incorporated by reference to reference to figures 13 to Figure 15.Wherein, Figure 13 illustrates the plan structure of described nand flash memory memory cell array structure, and Figure 14 illustrates the cross-section structure that described nand flash memory memory cell array structure obtains along X-X4 chain-dotted line cutting.Figure 15 illustrates the cross-section structure that described nand flash memory memory cell array structure obtains along Y-Y5 chain-dotted line cutting.Described nand flash memory memory cell array structure includes Semiconductor substrate 300 and the fin being positioned in Semiconductor substrate 300, described fin includes the source layer 317 of stacking, channel layer 315 and drain electrode layer 313 on vertical, and channel layer 315 is positioned in the middle of source layer 317 and drain electrode layer 313.Tunneling medium layer 331, covers top and the both sides of part fin；Charge trapping layer 333, covers top and the both sides of tunneling medium layer 331；Gate dielectric layer 335, covers top and the both sides of charge trapping layer 333；Grid 337, covers top and the both sides of gate dielectric layer 335.Additionally, described nand flash memory memory cell array structure also includes the string source electrode 3431 connecting source layer 317 and the string drain electrode 3432 connecting drain electrode layer 313.

In the present embodiment, on direction, described fin length place, tunneling medium layer 331 is between string source electrode 3431 and string drain electrode 3432, and namely grid 337 is between string source electrode 3431 and string drain electrode 3432, that is described nand flash memory memory element is between string source electrode 3431 and string drain electrode 3432.

In the present embodiment, the material of string source electrode 3431 and string drain electrode 3432 can be carborundum or germanium silicon, and carborundum or germanium silicon can have light doping.

In the present embodiment, although each memory element has independent source electrode and drain electrode, it still maintains, and nand flash memory memory density is high first reads, with storage data, the feature run afterwards.

Continue to reduce ability additionally, the memory element that the present embodiment provides has good process.Meanwhile, each memory element is one and has two grid device, has less cut-off current.Further, the forming method of described memory element and traditional F inFET process compatible, simplify technique, decrease process costs.

The forming method of the another kind of nand flash memory memory cell array structure that another embodiment of the present invention provides.

Refer to Figure 17, it is shown that the stereochemical structure that the forming method of the present embodiment provided nand flash memory memory cell array structure is corresponding.Described forming method provides Semiconductor substrate 400, and forms deep n-type trap 401 and the P type trap 402 being positioned on deep n-type trap 401 in Semiconductor substrate 400.It should be noted that in other embodiments, Semiconductor substrate 400 can also be there is deep P type trap and the N-type trap being positioned on deep P type trap 401.

Please continue to refer to Figure 17, forming fin (mark) in Semiconductor substrate 400, described fin is specifically formed on P type trap 402.Described fin includes the semiconductor layer 419 of stacking, source layer 417, channel layer 415, drain electrode layer 413 and semiconductor layer 411 on vertical, and wherein channel layer 415 is positioned in the middle of source layer 417 and drain electrode layer 413.Concrete, semiconductor layer 419, source layer 417, channel layer 415, drain electrode layer 413 and semiconductor layer 411 stack gradually from top to bottom, namely semiconductor layer 419 is positioned on source layer 417, source layer 417 is positioned on channel layer 415, channel layer 415 is positioned on drain electrode layer 413, and drain electrode layer 413 is positioned on semiconductor layer 411.

Described fin has certain length, the head-tail in direction, described fin length place is divided into the two ends (being shown as two ends, left and right in Figure 17) of described fin, the both sides that two edges are described fin (being shown as both sides, front and back in Figure 17) in direction, described fin width place.

In the present embodiment, vertically refer to the direction substantially vertical with wafer upper surface (wafer upper surface generally that is Semiconductor substrate 400 upper surface).Accordingly, laterally refer to and wafer upper surface direction that is substantially parallel.

In Figure 17, separate with dotted line between semiconductor layer 411 and P type trap 402, this is because, generally both are originally used for substrat structure, and simply after etching technics, semiconductor layer 411 becomes described fin and is positioned at the part of bottom.

It should be noted that in other embodiments, it would however also be possible to employ the method for deposition forms semiconductor layer 411 in Semiconductor substrate 400, and now semiconductor layer 411 and Semiconductor substrate 400 are then the different layers structure of essence.

In Figure 17, in described fin, the part-structure being positioned at same layer from drain electrode layer 413 has the shading different with drain electrode layer 413, and this is that this part-structure is not intended as conductive structure in order to show that this part-structure is not drain electrode layer 413, is the first dielectric structure 4130.The process forming drain electrode layer 413 and semiconductor layer 411 can be: Semiconductor substrate 400 is carried out source and drain heavy doping, then Semiconductor substrate 400 is performed etching, Semiconductor substrate 400 has carried out the heavily doped part of described source and drain and has been left drain electrode layer 413 after etching, Semiconductor substrate 400 does not carry out the heavily doped part of described source and drain and is then left above-mentioned first dielectric structure 4130, accordingly, part semiconductor substrate 400 below drain electrode layer 413 and the first dielectric structure 4130 then becomes semiconductor layer 411, known, now the first dielectric structure 4130 and semiconductor layer 411 are the part remained after Semiconductor substrate 400 is etched.

It should be noted that in other embodiments, the first dielectric structure 4130 can also individually adopt deposition process to be formed, thus becoming an independent part, the forming method of the first dielectric structure 4130 is not construed as limiting by the present invention.

Same, Figure 17 shows, the part-structure being positioned at same layer from source layer 417 has the shading different with source layer 417, and this is that this part-structure is not intended as conductive structure in order to show that this part-structure is not source layer 417, is the second dielectric structure 4170.The process forming source layer 417 and semiconductor layer 419 can be: forms semiconductor material layer on channel layer 415, the thickness of this semiconductor material layer is source layer 417 and semiconductor layer 419 sum, then described semiconductor material layer is carried out source and drain heavy doping, to form source layer 417, and unadulterated part is left semiconductor layer 419 and the second dielectric structure 4170, thus now the second dielectric structure 4170 and semiconductor layer 419 are the overall structure that semiconductor material layer remains.

It should be noted that in other embodiments, the second dielectric structure 4170 can also individually adopt deposition process to be formed, thus becoming an independent part, the forming method of the second dielectric structure 4170 is not construed as limiting by the present invention.

In Figure 17, source layer 417 and drain electrode layer 413 overlap on vertical, and meanwhile, source layer 417 and drain electrode layer 413 have part not overlapping on vertical.Further, source layer 417 and drain electrode layer 413 are nonoverlapping partially due to what the existence of the first dielectric structure 4130 and the second dielectric structure 4170 caused vertical.Namely the first dielectric structure 4130 and the second dielectric structure 4170 are not overlapping on vertical, and both lay respectively at two ends of fin, thus guarantee section source layer 417 on vertical with the first dielectric structure 4130 overlapping, part drain electrode layer 413 is overlapping with the second dielectric structure 4170 on vertical.

In the present embodiment, on the one hand, source layer 417 and drain electrode layer 413 need to partly overlap on vertical, thus ensureing that source layer 417 and drain electrode layer 413 can respectively as the source electrode of nand flash memory storage element and drain electrodes；On the other hand, source layer 417 and drain electrode layer 413 need nonoverlapping two ends on vertical, only is connected with both one of them thus ensureing that the string source electrode 4431 being subsequently formed and string drain electrode 4432 can distinguish, i.e. the corresponding nand flash memory memory cell array structure of guarantee formation.

In the present embodiment, Semiconductor substrate 400 is silicon substrate.In other embodiments of the invention, Semiconductor substrate 400 can also be the substrate that germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their combination are formed, or be silicon-on-insulator substrate, or other suitable semiconductive material substrate being known to the skilled person.

In the present embodiment, form the step of described fin and may include that in Semiconductor substrate 400, form the first heavily doped layer；Described first heavily doped layer is formed channel layer 415；Channel layer 415 is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, channel layer the 415, first heavily doped layer and Semiconductor substrate 400, until forming described fin.After forming described fin, described hard mask layer can be removed, it is also possible to is retained in above semiconductor layer 419.

In the forming process of above-mentioned fin, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 417 and drain electrode layer 413, and both are different.Namely in other embodiments of the invention, the position of source layer 417 and drain electrode layer 413 can be exchanged.

In the forming process of above-mentioned fin, it is possible to concurrently form above-mentioned first dielectric structure 4130 and the second dielectric structure 4170.

In the forming process of above-mentioned fin, channel layer 415 can be intrinsic semiconductor layer, for instance intrinsic silicon material layer, it is also possible to include channel layer 415 is gently adulterated, and the atomic concentration that described light doping is injected is 10E17atom/cm³, and the conduction type of the atom of described light doping injection is contrary with the conduction type of source layer 417 and drain electrode layer 413.Namely, when source layer 417 and drain electrode layer 413 are n-type doping, channel layer 415 doping is P type atom.

It should be noted that in other embodiments, the step forming described fin can also for comprising the following steps: adulterates to form the first heavily doped layer to Semiconductor substrate 400；Described first heavily doped layer is formed channel layer 415；Channel layer 415 is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, channel layer the 415, first heavily doped layer and Semiconductor substrate 400, until forming described fin.Wherein, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 417 and drain electrode layer 413, and both are different.

Same, in the forming process of described fin, it is possible to adopt epitaxial growth method or vapour deposition process to form described second heavily doped layer, it is possible to channel layer 415 is gently adulterated, the atomic concentration that described light doping is injected is 10E17atom/cm³。

Please continue to refer to Figure 17, being upwardly formed, in described fin length place side, the multiple tunneling medium layer 431 being intervally arranged, tunneling medium layer 431 covers top and the both sides of the described fin of part.Forming charge trapping layer 433, charge trapping layer 433 covers top and the both sides of tunneling medium layer 431.Forming gate dielectric layer 435, gate dielectric layer 435 covers top and the both sides of charge trapping layer 433.Forming grid 437, grid 437 covers top and the both sides of described gate dielectric layer 435.

nullIn the present embodiment，Form grid 437、Gate dielectric layer 435、The process of charge trapping layer 433 and tunneling medium layer 431 can be: exposes described fin portion surface，To form Tunnel dielectric material layer in whole described fin portion surface，Then on described Tunnel dielectric material layer, form charge-trapping material layer，Charge-trapping material layer is formed gate dielectric material layer，Gate dielectric material layer is formed gate material layer，Then in gate material layer, form hard mask layer，Hard mask layer is formed photoresist layer，And described photoresist layer is exposed and developing process is patterned，Again with the photoresist layer of patterning for mask，Etch described hard mask layer，Again with etching after described hard mask layer and remain described photoresist layer for mask，Etch described gate material layer、Gate dielectric material layer、Charge-trapping material layer and Tunnel dielectric material layer，Until forming the multiple grids 437 being intervally arranged、Gate dielectric layer 435、Charge trapping layer 433 and tunneling medium layer 431，And again expose the surface of described fin between neighboring gates 437.Further, in above process, etching off is except being positioned at the region being subsequently formed string source electrode and string drain electrode in the same time, and above-mentioned each material layer of other non-area of grid.In said process, it is possible to adopt thermal oxidation method or chemical oxidization method to form tunneling medium layer 431 in the described fin portion surface being exposed.

It should be strongly noted that owing to charge trapping layer is only required to be formed at memory cell region, therefore, in above-mentioned etching process, also include etching further and remove the charge-trapping material layer in peripheral device region.

In the present embodiment, the material of charge trapping layer 433 can be silicon nitride.When adopting silicon nitride as charge trapping layer 433, after corresponding electric charge enters trap layer, it is not susceptible to mobile, therefore, corresponding data stabilization.

In the present embodiment, the material of tunneling medium layer 431 and gate dielectric layer 435 can be all silicon oxide.Now tunneling medium layer 431, charge trapping layer 433 and gate dielectric layer 435 form ONO laminated construction.

In the present embodiment, the material of grid 437 can be polysilicon or metal.When the material of grid 437 is metal, corresponding gate dielectric layer 435 can be made for high K dielectric material.

Please continue to refer to Figure 17, at the two ends epitaxial growth carborundum of described fin or germanium silicon as described string source electrode 4431 and string drain electrode 4432.Tool is stopped, in the two ends of described fin (the described fin two ends namely exposed after removing mask layer 423), one end forms string source electrode 4431 wherein, described string source electrode 4431 connects source layer 417, string drain electrode 4432, the described string drain electrode 4432 described drain electrode layer 413 of connection is formed at the other end.

In the present embodiment, the forming step of string source electrode 4431 and string drain electrode 4432 may include that at the two ends epitaxial growth carborundum of described fin or germanium silicon, described carborundum or germanium silicon as described string source electrode 4431 and string drain electrode 4432.In the process of epitaxial growth string source electrode 4431 and string drain electrode 4432, it is possible to described carborundum or germanium silicon are carried out original position doping, thus improving string source electrode 4431 and the electric conductivity of string drain electrode 4432.The conductivity of lightly doped carborundum or germanium silicon is higher, and string source electrode 4431 and string drain electrode 4432 dead resistances worked it out are less.

In the present embodiment, on direction, described fin length place, string source electrode 4431 and string drain electrode 4432 formation are on tunneling medium layer 431 both sides, namely tunneling medium layer 431 is formed between string source electrode 4431 and string drain electrode 4432, that is grid 437 is between string source electrode 4431 and string drain electrode 4432, and grid 437 and corresponding source layer 417, channel layer 415, drain electrode layer 413, tunneling medium layer 431, charge trapping layer 433 and gate dielectric layer 435 constitute nand flash memory memory element, therefore, that is, described nand flash memory memory element is between string source electrode 4431 and string drain electrode 4432.

In the present embodiment, string source electrode 4431 is grown in source layer 417 two sides, and therefore string source electrode 4431 electrically connects with source layer 417.Meanwhile, string source electrode 4431 is not grown in drain electrode layer 413 side, but is grown in above-mentioned second dielectric structure 4170 side, therefore, and mutually insulated between string source electrode 4431 and drain electrode layer 413.Same, string drain electrode 4432 is grown in drain electrode layer 413 two sides, and therefore string drain electrode 4432 electrically connects with drain electrode layer 413.Meanwhile, string drain electrode 4432 is not grown in source layer 417 side, but is grown in above-mentioned first dielectric structure 4130 side, therefore, and mutually insulated between string drain electrode 4432 and source layer 417.

In the present embodiment, it is not necessary to carry out lightly doped drain injection technology, being namely not necessarily forming lightly-doped source district and lightly doped drain, thus saving processing step, saving process costs.

Seeing from Figure 17, the profile of string source electrode 4431 is diamond profile.This is because what the epitaxial crystallization of silicon was formed, mainly the extension of silicon materials determines shape, and carbon or germanium is only a small amount mixes, so shape is substantially free of impact.Namely, in epitaxially grown carborundum or germanium silicon, continue to generate still along the lattice of silicon atom in described fin, and lattice growth has anisotropy, therefore forms shape shown in Figure 17.

Though it is not shown in figure, but follow-up can also continue to of the present embodiment forms metal silicide (not shown) on string source electrode 4431, string drain electrode 4432 and grid 437, and form the contact plunger (not shown) each metal silicide of connection, and it is simultaneously connected with grid 437.

In the present embodiment, defining three grids 437, corresponding has three nand flash memory memory element.These three nand flash memory memory element and the string source electrode 4431 and the string drain electrode 4432 formation nand flash memory memory cell array structure that are positioned at its both sides.But, in other embodiments of the invention, more discrete grid 437 can be formed at described fin, such as 8,16 or 32 grids, and these grids are all intervally arranged along direction, described fin length place, thus multiple nand flash memory memory element that formation is intervally arranged along described fin length direction, and, these nand flash memory memory element form nand flash memory memory cell array structures with string source electrode 4431 and string drain electrode 4432.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, the Semiconductor substrate 400 provided defines fin, described fin includes on vertical the semiconductor layer 419 of stacking, source layer 417, channel layer 415, drain electrode layer 413 and semiconductor layer 411 from top to bottom, then form the laminated construction being made up of tunneling medium layer 431, charge trapping layer 433 and gate dielectric layer 435 and cover top and the both sides of described fin, form grid 437 again and cover described laminated construction, thus defining nand flash memory memory element.In whole forming process, eliminate photoetching when forming multi-crystal silicon floating bar and etching technics, Simplified flowsheet step.

The nand flash memory memory element formed is by source layer 417 as source electrode, and channel region is formed in channel layer 415, and by drain electrode layer 413 as drain electrode, therefore, size can significantly reduce.

In the nand flash memory memory element that the present embodiment is formed, multiple described nand flash memory memory element are made in same fin, but the operating current of each memory element (electric current between operating current finger source electrode and drain electrode herein, and it is left out the electric current of grid) and it is in parallel, carrier is all move from source layer 417 to drain electrode layer 413.nullTherefore，In memory cell data reading process，The drain electrode (drain electrode and the described drain electrode layer of part) of incidental hot carrier in jection and the charge trapping layer of consecutive storage unit exist distant (distant can be caused more greatly by the spacing of neighboring gates 437) or tortuous path, and (tortuous path is by each charge trapping layer and each tunneling medium layer is spaced causes，Owing to each tunneling medium layer and each charge trapping layer are discontinuous，Hot carrier is by moving to consecutive storage unit inside them) situation，And the direction of electric field is also by source layer 317 to drain electrode layer 313 (or by drain electrode layer 313 to source layer 317)，Therefore when a memory element is read，It is prevented from hot carrier in jection consecutive storage unit charge trap layer region，Avoid the phenomenon of hot carrier in jection consecutive storage unit，Namely from device architecture, solve the problem that memory element reads interference.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, after defining above-mentioned nand flash memory memory element, continue again to define string source electrode 4431 and string drain electrode 4432 at the two ends of described fin, thus forming memory cell array structure.The size of described array structure is equally possible significantly to be reduced, and the performance of memory cell array structure improves.

The embodiment of the present invention additionally provides a kind of nand flash memory memory element.Described nand flash memory memory element can adopt the forming method that previous embodiment provides to be formed, and (method that is namely previously formed is when forming nand flash memory memory cell array structure, described nand flash memory memory cell array structure includes nand flash memory memory element, therefore described forming method also form nand flash memory memory element simultaneously), therefore, described nand flash memory memory element is referred to previous embodiment corresponding contents, it is possible to combine with reference to Figure 17.

Concrete, Figure 17 illustrates the stereochemical structure of described nand flash memory memory element.Described nand flash memory memory element includes Semiconductor substrate 400 and the fin being positioned in Semiconductor substrate 400, described fin includes the source layer 417 of stacking, channel layer 415 and drain electrode layer 413 on vertical, and channel layer 415 is positioned in the middle of source layer 417 and drain electrode layer 413.Tunneling medium layer 431, covers top and the both sides of part fin；Charge trapping layer 433, covers top and the both sides of tunneling medium layer 431；Gate dielectric layer 435, covers top and the both sides of charge trapping layer 433；Grid 437, covers top and the both sides of gate dielectric layer.

In the present embodiment, the thickness range of channel layer 415 can be 50nm～70nm.In the nand flash memory memory element that the present embodiment provides, on the one hand, due to the thickness flowing of the electric current vertical furrow channel layer 415 of described nand flash memory memory element, if the thickness of channel layer 415 is less than 50nm, then it is difficult to turn off corresponding channel current by grid 437；On the other hand, if the thickness of channel layer 415 is more than 70nm, corresponding channel resistance increases, and electric current is too little, affects the performance of nand flash memory memory element equally.

In the present embodiment, the thickness range of charge trapping layer 433 can be 15nm～40nm.Data charge storage position when charge trapping layer 433 is as nand flash memory storage unit stores data, need enough thickness to ensure that data charge can be stored therein on the one hand, on the other hand, its thickness needs less, to facilitate formation and the control of subsequent gate 437.

In the present embodiment, source layer 417 and drain electrode layer 413 and thickness range can be all 20nm～100nm, this is the result considered structure, if source layer 417 and drain electrode layer 413 thickness are too little, less than 20nm, then electric current handling capacity is too low, and if source layer 417 and drain electrode layer 413 thickness are too big, more than 100nm, now the height of described fin is too big, being difficult to be formed, even if defining, integrity problem also easily occurring.

In the present embodiment, although each memory element has independent source electrode and drain electrode, but the source electrode of the memory element on a bit line and drain electrode are all series connection, so being still that nand flash memory, it still maintains nand flash memory memory density height and storage data first read the feature run afterwards.

Continue to reduce ability additionally, the memory element that the present embodiment provides has good process.Meanwhile, each memory element is one and has the two grid device both sides of channel layer 415 (grid 437 simultaneously cover), has less cut-off current.Further, the forming method of described memory element and traditional F inFET process compatible, simplify technique, decrease process costs.

The embodiment of the present invention additionally provides a kind of nand flash memory memory cell array structure.Described nand flash memory memory cell array structure can adopt forming method embodiment corresponding for Figure 17 to be formed, and therefore, described nand flash memory memory cell array structure is referred to previous embodiment corresponding contents, it is possible to combines with reference to Figure 17.

Concrete, Figure 17 illustrates the stereochemical structure of described nand flash memory memory cell array structure.Described nand flash memory memory cell array structure includes Semiconductor substrate 400 and the fin being positioned in Semiconductor substrate 400, described fin includes the source layer 417 of stacking, channel layer 415 and drain electrode layer 413 on vertical, and channel layer 415 is positioned in the middle of source layer 417 and drain electrode layer 413.Tunneling medium layer 431, covers top and the both sides of part fin；Charge trapping layer 433, covers top and the both sides of tunneling medium layer 431；Gate dielectric layer 435, covers top and the both sides of charge trapping layer 433；Grid 437, covers top and the both sides of gate dielectric layer 435.Additionally, described nand flash memory memory cell array structure also includes the string source electrode 4431 connecting source layer 417 and the string drain electrode 4432 connecting drain electrode layer 413.

In the present embodiment, on direction, described fin length place, tunneling medium layer 431 is between string source electrode 4431 and string drain electrode 4432, and namely grid 437 is between string source electrode 4431 and string drain electrode 4432, that is described nand flash memory memory element is between string source electrode 4431 and string drain electrode 4432.

In the present embodiment, the material of string source electrode 4431 and string drain electrode 4432 can be carborundum or germanium silicon, and carborundum or germanium silicon can have light doping.

In the present embodiment, although each memory element has independent source electrode and drain electrode, but the source electrode of the memory element on a bit line and drain electrode are all that series connection is (because the source layer 417 as each source electrode is continuous structure, drain electrode layer 413 as each drain electrode is also continuous structure), so being still that nand flash memory, it still maintains, and nand flash memory memory density is high first reads, with storage data, the feature run afterwards.

The forming method of another nand flash memory memory cell array structure that further embodiment of this invention provides.

Refer to Figure 18, it is shown that the top view cross section structure of nand flash memory memory cell array structure.Described forming method includes: provides Semiconductor substrate (not shown), and forms fin (being not entirely shown) on the semiconductor substrate.Described fin includes stacking source layer 517, channel layer (not shown), drain electrode layer (not shown) and semiconductor layer 511 on vertical, and wherein said channel layer is positioned in the middle of source layer 517 and described drain electrode layer.Concrete, above-mentioned each structure that the present embodiment is formed is referred to Fig. 3 to Figure 16 and Figure 17 corresponding contents.

Described fin has certain length, the head-tail in direction, described fin length place is divided into the two ends (being shown as two ends, left and right in Figure 18) of described fin, the both sides that two edges are described fin (being shown as upper and lower both sides in Figure 18) in direction, described fin width place.

In the present embodiment, vertically referring to and the substantially vertical direction of wafer upper surface, wafer upper surface is usual that is described Semiconductor substrate upper surface, i.e. plane shown in Figure 18, is therefore vertically often referred to and is perpendicular to plane outwardly direction shown in Figure 18.Accordingly, laterally refer to and wafer upper surface direction that is substantially parallel.

In the present embodiment, at equally possible existence the first dielectric structure (not shown) of described fin and the second dielectric structure (not shown), they are not overlapping on vertical, and both lay respectively at two ends of fin, thus guarantee section source layer 517 on vertical with the first dielectric structure overlapping, the described drain electrode layer of part is overlapping with the second dielectric structure on vertical.

In the present embodiment, on the one hand, source layer 517 and described drain electrode layer partly overlap on vertical, thus ensureing that source layer 517 and described drain electrode layer can respectively as the source electrode of nand flash memory storage element and drain electrodes；On the other hand, source layer 517 and described drain electrode layer have nonoverlapping two ends on vertical, only is connected with both one of them thus ensureing that the string source electrode 5431 being subsequently formed and string drain electrode (not shown) can distinguish, i.e. the corresponding nand flash memory memory cell array structure of guarantee formation.

In the present embodiment, described Semiconductor substrate is silicon substrate.In other embodiments of the invention, described Semiconductor substrate can also be the substrate that germanium silicon substrate, III-group Ⅴ element compound substrate, silicon carbide substrates or their combination are formed, or be silicon-on-insulator substrate, or other suitable semiconductive material substrate being known to the skilled person.

In the present embodiment, form the step of described fin and may include that and form the first heavily doped layer on the semiconductor substrate；Described first heavily doped layer forms described channel layer；Described channel layer is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, described channel layer, the first heavily doped layer and described Semiconductor substrate, until forming described fin.After forming described fin, described hard mask layer can be removed, it is also possible to retains.

In the forming process of above-mentioned fin, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 517 and described drain electrode layer, and both are different.Namely in other embodiments of the invention, the position of source layer 517 and described drain electrode layer can be exchanged.

In the forming process of above-mentioned fin, it is possible to concurrently form the first dielectric structure described above and described second dielectric structure.

In the forming process of above-mentioned fin, described channel layer can be intrinsic semiconductor layer, for instance intrinsic silicon material layer, it is also possible to include described channel layer is gently adulterated, and the atomic concentration that described light doping is injected is 10E17atom/cm³, and the conduction type of the atom of described light doping injection is contrary with the conduction type of source layer 517 and described drain electrode layer.Namely, when source layer 517 and described drain electrode layer are n-type doping, the doping of described channel layer is P type atom.

It should be noted that in other embodiments, the step forming described fin can also for comprising the following steps: adulterates to form the first heavily doped layer to described Semiconductor substrate；Described first heavily doped layer forms described channel layer；Described channel layer is formed the second heavily doped layer；Described second heavily doped layer is formed the hard mask layer of patterning；With the hard mask layer of described patterning for mask, etch described second heavily doped layer, described channel layer, the first heavily doped layer and described Semiconductor substrate, until forming described fin.Wherein, one of them of described first heavily doped layer and the second heavily doped layer respectively source layer 517 and described drain electrode layer, and both are different.

Same, in the forming process of described fin, it is possible to adopt epitaxial growth method or vapour deposition process to form described second heavily doped layer, it is possible to described channel layer is gently adulterated, the atomic concentration that described light doping is injected is 10E17atom/cm³。

Please continue to refer to Figure 18, being upwardly formed tunneling medium layer 531 in described fin length place side, tunneling medium layer 531 covers top and the both sides of the described fin of part.Forming charge trapping layer 533, charge trapping layer 533 covers top and the both sides of tunneling medium layer 531.Forming gate dielectric layer 535, gate dielectric layer 535 covers top and the both sides of charge trapping layer 533.Forming grid 537, grid 537 covers top and both sides (grid 537 is in combinations with the grid 437 in reference Figure 17) of described gate dielectric layer 535.

In the present embodiment, form grid 537, gate dielectric layer 535, the process of charge trapping layer 533 and tunneling medium layer 531 can be: exposes described fin portion surface, to form gate dielectric layer 535 in whole described fin portion surface, charge trapping layer 533 and tunneling medium layer 531, and it is positioned at the gate material layer on described gate dielectric layer 535, then described gate material layer is etched, until forming the multiple grids 537 being intervally arranged, and gate dielectric layer 535 is the grid 537 that flood structure is corresponding different, same charge trapping layer 533 is the grid 537 that flood structure is corresponding different, tunneling medium layer 531 is the grid 537 that flood structure is corresponding different.

In the present embodiment, the material of charge trapping layer 533 can be silicon nitride.When adopting silicon nitride as charge trapping layer 533, when corresponding electric charge enters after trap layer, it is not susceptible to mobile, therefore, corresponding data stabilization, and also protect different grids 537 and corresponding can adopt one layer of integrally-built charge trapping layer 533.

In the present embodiment, the material of tunneling medium layer 531 and gate dielectric layer 535 can be all silicon oxide.Now tunneling medium layer 531, charge trapping layer 533 and gate dielectric layer 535 form ONO laminated construction.

In the present embodiment, the material of grid 537 can be polysilicon or metal.When the material of grid 537 is metal, corresponding gate dielectric layer 535 can be made for high K dielectric material.

Please continue to refer to Figure 18, two ends epitaxial growth carborundum or germanium silicon at described fin drain as string source electrode 5431 and described string, Figure 18 has only shown a part for described nand flash memory memory cell array structure, and show the part with string source electrode 5431, and the part with string drain electrode is not shown.But, in top view cross section structure, there is the part of described string drain electrode basic with the partial symmetry with string source electrode 5431.

In the present embodiment, the forming step of string source electrode 5431 and described string drain electrode may include that two ends epitaxial growth carborundum or germanium silicon, described carborundum or germanium silicon at described fin drain as described string source electrode 5431 and described string.In the process of epitaxial growth string source electrode 5431 and described string drain electrode, it is possible to described carborundum or germanium silicon are carried out original position doping, thus improving string source electrode 5431 and the electric conductivity of described string drain electrode.The conductivity of lightly doped carborundum or germanium silicon is higher, and string source electrode 5431 and the described string drain parasitic resistance worked it out are less.

In the present embodiment, on direction, described fin length place, string source electrode 5431 and described string drain electrode are formed on tunneling medium layer 531 both sides, namely tunneling medium layer 531 is formed between string source electrode 5431 and described string drain electrode, that is grid 537 is between string source electrode 5431 and described string drain electrode, and grid 537 and corresponding source layer 517, described channel layer, described drain electrode layer, tunneling medium layer 531, charge trapping layer 533 and gate dielectric layer 535 constitute nand flash memory memory element, therefore, that is, described nand flash memory memory element is between string source electrode 5431 and described string drain electrode.

In the present embodiment, string source electrode 5431 is grown in source layer 517 two sides, and therefore string source electrode 5431 electrically connects with source layer 517.Meanwhile, string source electrode 5431 is not grown in described drain electrode layer side, but is grown in above-mentioned second dielectric structure side, therefore, and mutually insulated between string source electrode 5431 and described drain electrode layer.Same, described string drain electrode is grown in described drain electrode layer two sides, and therefore described string drain electrode electrically connects with described drain electrode layer.Meanwhile, described string drain electrode is not grown in source layer 517 side, but is grown in the first dielectric structure side described above, therefore, and mutually insulated between described string drain electrode and source layer 517.

Please continue to refer to Figure 18, with previous embodiment the difference is that, in the present embodiment, on direction, described fin length place, string source electrode 5431 and each grid 537 between also make active selection transistor 560.

Source selects transistor 560 to be similarly formed on described fin, and source selects transistor 560 with a portion of described source layer 517 for channel region 561, namely has subregion to select the channel region 561 of transistor 560 as source in source layer 517, as shown in figure 18.The forming process of concrete channel region 561 can be: when described fin carrying out doping and forming source layer 517; mask layer is adopted to protect above channel region 561; thus adulterating in anti-region here, and it is left intrinsic semiconductor structure (such as intrinsic silicon structure).Further, this region can also be carried out the light doping contrary with source layer 517 doping type afterwards.Such as when source layer 517 carry out be N-type heavy doping time, it is possible to channel region 561 is carried out P type and gently adulterates.

Source selects in transistor 560, and channel region 561 both sides are covered by gate dielectric layer 563.In the present embodiment, gate dielectric layer 563 both can be when tunneling medium layer 531 and gate dielectric layer 535, is retained in the laminated construction of channel region 561 both sides, it is also possible to is the single layer structure individually made in channel region 561 both sides.

Source selects in transistor 560, and gate dielectric layer 563 is covered by grid 565, and grid 565 surrounds and covers channel region 561 both sides (grid 565 is in combinations with the grid 437 in reference Figure 17)

Though it is not shown in figure, but follow-up can also continue to of the present embodiment forms metal silicide (not shown) on string source electrode 5431, described string drain and gate 537, and form the contact plunger (not shown) each metal silicide of connection, and it is simultaneously connected with grid 537.

On direction, described fin length place, owing to source selects transistor 560 to be produced between string source electrode 5431 and grid 537, namely source selects transistor 560 to be produced between string source electrode 5431 and each nand flash memory memory element, therefore, source selects transistor 560 can control whether to turn between string source electrode 5431 and each nand flash memory memory element.

In the present embodiment, define multiple grid 537 (such as 4,8,16 or 32 grids), the corresponding multiple nand flash memory memory element of composition.These multiple nand flash memory memory element select transistor 560 to form nand flash memory memory cell array structure with string source electrode 5431, described string drain electrode and source.

It should be noted that, in other embodiments of the invention, on direction, described fin length place, and between described string drain electrode and described grid, can also being formed with Lou selection transistor, and described leakage selects a portion that transistor is also adopted by described drain electrode layer to be channel region, namely described leakage selects transistor fabrication between described string drain electrode and each nand flash memory memory element, therefore, described leakage selects transistor can control whether to turn between string drain electrode and each nand flash memory memory element.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, the described Semiconductor substrate provided defines fin, described fin includes on vertical the source layer 517 of stacking, described channel layer, described drain electrode layer and semiconductor layer 511 from top to bottom, then form the laminated construction being made up of tunneling medium layer 531, charge trapping layer 533 and gate dielectric layer 535 and cover top and the both sides of described fin, form grid 537 again and cover described laminated construction, thus defining nand flash memory memory element.In whole forming process, eliminate photoetching when forming multi-crystal silicon floating bar and etching technics, Simplified flowsheet step.

The nand flash memory memory element formed is by source layer 517 as source electrode, and channel region is formed in described channel layer, and by described drain electrode layer as drain electrode, therefore, size can significantly reduce.

In the nand flash memory memory element formed, the operating current direction of each memory element is parallel operation, namely carrier is all move from source layer 517 to described drain electrode layer, therefore, in reading the data, the drain electrode layer region of those incidental hot carrier in jection and the charge trapping layer region distance of consecutive storage unit are farther out, and the direction of electric field is generally by source layer 317 to drain electrode layer 313, prevent hot carrier in jection consecutive storage unit charge trap layer region, thus solving the problem that memory element reads interference from device architecture.

In the forming method of the nand flash memory memory cell array structure that the present embodiment provides, after defining above-mentioned nand flash memory memory element, continue again to define string source electrode 5431 and described string drain electrode at the two ends of described fin, thus forming memory cell array structure.The size of described array structure is equally possible significantly to be reduced, and the performance of memory cell array structure improves.

The embodiment of the present invention additionally provides a kind of nand flash memory memory element.Described nand flash memory memory element can adopt the forming method that previous embodiment provides to be formed, and (method that is namely previously formed is when forming nand flash memory memory cell array structure, described nand flash memory memory cell array structure includes nand flash memory memory element, therefore described forming method also form nand flash memory memory element simultaneously), therefore, described nand flash memory memory element is referred to previous embodiment corresponding contents, it is possible to combine with reference to Figure 18.

Concrete, Figure 18 illustrates the stereochemical structure of described nand flash memory memory element.Described nand flash memory memory element includes described Semiconductor substrate and the fin being positioned in described Semiconductor substrate, described fin includes the source layer 517 of stacking, described channel layer and described drain electrode layer on vertical, and described channel layer is positioned in the middle of source layer 517 and described drain electrode layer.Tunneling medium layer 531, covers top and the both sides of part fin；Charge trapping layer 533, covers top and the both sides of tunneling medium layer 531；Gate dielectric layer 535, covers top and the both sides of charge trapping layer 533；Grid 537, covers top and the both sides of gate dielectric layer.

In the present embodiment, the thickness range of described channel layer can be 50nm～70nm.In the nand flash memory memory element that the present embodiment provides, on the one hand, owing to the thickness of the vertical described channel layer of the electric current of described nand flash memory memory element flows, if the thickness of described channel layer is less than 50nm, then it is difficult to turn off corresponding channel current by grid 537；On the other hand, if the thickness of described channel layer is more than 70nm, corresponding channel resistance increases, and electric current is too little, affects the performance of nand flash memory memory element equally.

In the present embodiment, the thickness range of charge trapping layer 533 can be 15nm～50nm.Data charge storage position when charge trapping layer 533 is as nand flash memory storage unit stores data, need enough thickness to ensure that data charge can be stored therein on the one hand, on the other hand, its thickness needs less, to facilitate formation and the control of subsequent gate 537.

In the present embodiment, source layer 517 and described drain electrode layer and thickness range can be all 20nm～100nm, this is the result considered structure, if source layer 517 and described drain layer thickness are too little, less than 20nm, then electric current handling capacity is too low, and if source layer 517 and described drain layer thickness are too big, more than 100nm, now the height of described fin is too big, being difficult to be formed, even if defining, integrity problem also easily occurring.

Continue to reduce ability additionally, the memory element that the present embodiment provides has good process.Meanwhile, each memory element is one and has the two grid device both sides of described channel layer (grid 537 simultaneously cover), has less cut-off current.Further, the forming method of described memory element and traditional F inFET process compatible, simplify technique, decrease process costs.

The embodiment of the present invention additionally provides a kind of nand flash memory memory cell array structure.Described nand flash memory memory cell array structure can adopt forming method embodiment corresponding for Figure 18 to be formed, and therefore, described nand flash memory memory cell array structure is referred to previous embodiment corresponding contents, it is possible to combines with reference to Figure 18.

Concrete, Figure 18 illustrates the stereochemical structure of described nand flash memory memory cell array structure.Described nand flash memory memory cell array structure includes described Semiconductor substrate and the fin being positioned in described Semiconductor substrate, described fin includes the source layer 517 of stacking, described channel layer and described drain electrode layer on vertical, and described channel layer is positioned in the middle of source layer 517 and described drain electrode layer.Tunneling medium layer 531, covers top and the both sides of part fin；Charge trapping layer 533, covers top and the both sides of tunneling medium layer 531；Gate dielectric layer 535, covers top and the both sides of charge trapping layer 533；Grid 537, covers top and the both sides of gate dielectric layer 535.Additionally, described nand flash memory memory cell array structure also includes the string source electrode 5431 connecting source layer 517 and the described string drain electrode connecting described drain electrode layer.

In the present embodiment, on direction, described fin length place, tunneling medium layer 531 is between string source electrode 5431 and described string drain electrode, and namely grid 537 is between string source electrode 5431 and described string drain electrode, that is described nand flash memory memory element is between string source electrode 5431 and described string drain electrode.

In the present embodiment, the material of string source electrode 5431 and described string drain electrode can be carborundum or germanium silicon, and carborundum or germanium silicon can have light doping.

In the present embodiment, although each memory element has independent source electrode and drain electrode, but the source electrode of the memory element on a bit line and drain electrode are all that series connection is (because the source layer 517 as each source electrode is continuous structure, described drain electrode layer as each drain electrode is also continuous structure), so being still that nand flash memory, it still maintains, and nand flash memory memory density is high first reads, with storage data, the feature run afterwards.

Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims

1. a nand flash memory memory element, it is characterised in that including:

Semiconductor substrate；

Grid, covers top and the both sides of described gate dielectric layer.

2. nand flash memory memory element as claimed in claim 1, it is characterised in that the thickness range of described channel layer is 50nm～70nm.

3. nand flash memory memory element as claimed in claim 1, it is characterised in that the thickness range of described charge trapping layer is 15nm～40nm.

4. a nand flash memory memory cell array structure, it is characterised in that including:

Semiconductor substrate；

Cover the top of described gate dielectric layer and the grid of both sides

Connect the string source electrode of described source layer；

Connect the string drain electrode of described drain electrode layer.

5. nand flash memory memory cell array structure as claimed in claim 4, it is characterised in that on direction, described fin length place, whole described grids are between described string source electrode and described string drain.

6. nand flash memory memory cell array structure as claimed in claim 4, it is characterised in that the thickness range of described channel layer is 50nm～70nm.

7. nand flash memory memory cell array structure as claimed in claim 4, it is characterised in that the thickness range of described charge trapping layer is 15nm～40nm.

8. nand flash memory memory cell array structure as claimed in claim 4, it is characterised in that the material of described string source electrode and the drain electrode of described string is carborundum or germanium silicon.

9. nand flash memory memory cell array structure as claimed in claim 4, it is characterized in that, on direction, described fin length place, also there is between described string source electrode and grid source and select transistor, or also there is between described grid and string drain electrode leakage selection transistor.

10. the forming method of a nand flash memory memory cell array structure, it is characterised in that including: Semiconductor substrate is provided；

11. forming method as claimed in claim 10, it is characterised in that on direction, described fin length place, described tunneling medium layer is formed between described string source electrode and described string drain.

12. forming method as claimed in claim 10, it is characterised in that the step forming described fin includes:

Form the first heavily doped layer on a semiconductor substrate；

Described first heavily doped layer is formed channel layer；

Described channel layer is formed the second heavily doped layer；

13. forming method as claimed in claim 10, it is characterised in that the step forming described fin includes:

Adulterate Semiconductor substrate to form the first heavily doped layer；

Described first heavily doped layer is formed channel layer；

Described channel layer is formed the second heavily doped layer；

14. the forming method as described in claim 12 or 13, it is characterised in that adopt epitaxial growth method or vapour deposition process to form described second heavily doped layer.

15. forming method as claimed in claim 10, it is characterised in that also include described channel layer is gently adulterated, the atomic concentration that described light doping is injected is 10E17atom/cm³。

16. forming method as claimed in claim 10, it is characterised in that form described tunneling medium layer and include:

Form mask layer and cover described fin；

17. forming method as claimed in claim 16, it is characterised in that the process forming described string source electrode and string drain electrode includes:

18. forming method as claimed in claim 10, it is characterised in that form described tunneling medium layer, including:

Form Tunnel dielectric material layer and cover described fin；

Form gate material layer and cover described gate dielectric material layer；

19. forming method as claimed in claim 18, it is characterised in that the forming step of described string source electrode and string drain electrode includes: at two ends epitaxial growth carborundum or the germanium silicon of described fin, described carborundum or germanium silicon as described string source electrode and string drain electrode.