CN103681800B - Multi-time programmable semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a multi-time programmable semiconductor device, comprising: a plurality of fin-shaped structures located on a substrate and extending and distributed along a first direction parallel to the surface of the substrate, including a substrate implantation region, a buried oxide layer, and a top layer; a trench The channel region is located in the top layer of the plurality of fin structures; the source and drain regions are located at both ends of the channel region in the top layer of the plurality of fin structures; the gate insulating layer is located on the top and side of the channel region and is parallel to The substrate surface extends in the second direction; the floating gate is located on both sides of the plurality of fin structures in the second direction; the programming/erasing gate is formed by the substrate implantation region and is located under the buried oxide layer. According to the multi-time programmable semiconductor device and its manufacturing method of the present invention, the programming/erasing gate of the FinFET is formed by using the substrate implantation region, which simplifies the device structure, reduces the manufacturing process, improves the integration density of the device, and is suitable for Multiple times programmable memory.

Description

Multiple times programmable semiconductor device and manufacturing method thereof

technical field

The invention relates to a multi-time programmable semiconductor device and a manufacturing method thereof, in particular to a high-density multi-time programmable semiconductor device suitable for Fin Field Effect Transistor (FinFET) technology and a manufacturing method thereof.

Background technique

As the feature size of the CMOS process continues to shrink proportionally, the MOS memory structure develops rapidly, and various types of memory cell structures appear. Although DRAM has high integration and low power consumption, it cannot store information for a long time, while SRAM can store information for a long time, but it has a large area and low integration. Current technological developments are gradually focusing on ROMs, especially electrically erasable E ² PROMs.

In the existing E ² PROM unit, the FN tunneling effect of the thin oxide layer is used to realize electrical erasure, which usually includes an ultra-thin tunnel oxide layer, a floating gate of polysilicon, an interlayer dielectric, and a polysilicon layer stacked in sequence on the channel region. or metal control grid. However, due to the subthreshold leakage in conventional MOSFETs, the performance of this structure is greatly degraded in small-scale devices. Furthermore, variations in threshold voltage severely limit the drive strength and response speed.

An effective solution is to use FinFET to realize E ² PROM, and increase or decrease the threshold voltage of the transistor by changing the charge of the floating gate, thus providing higher performance and lower power consumption for the chip. However, the structure of the existing E ² PROM implemented by FinFET is too complex, the device area is large, the process cost is high, and the integration density is low, so it is difficult to be suitable for large-scale memory cell array manufacturing.

All in all, the current multi-time programmable semiconductor devices are complex in structure, high in cost and low in efficiency, and are in urgent need of improvement.

Contents of the invention

Therefore, the object of the present invention is to provide a high-density integrated multi-time programmable semiconductor device suitable for FinFET technology and a manufacturing method thereof.

The present invention provides a multiple-time programmable semiconductor device, comprising: a plurality of fin-shaped structures located on a substrate and extending along a first direction parallel to the surface of the substrate, including a substrate implantation region, a buried oxide layer, and a top layer The channel region is located in the top layer of the plurality of fin structures; the source and drain regions are located at both ends of the channel region in the top layer of the plurality of fin structures; the gate insulating layer is located on the top and sides of the channel region along the The distribution extends in the second direction parallel to the surface of the substrate; the floating gate is located on both sides of the plurality of fin structures in the second direction; the programming/erasing gate is formed by the substrate implantation region and is located under the buried oxide layer.

It further includes: an interlayer dielectric layer covering a plurality of fin structures, a gate insulating layer, a control gate, and a floating gate; source-drain contact holes and programming/erasing gate contact holes are formed in the interlayer dielectric layer to respectively expose source The drain region and the substrate implantation region as the programming/erasing gate; the metal silicide is formed in the source-drain contact hole and the programming/erasing gate contact hole; the connection line is used as the programming/erasing gate through the metal silicide and the source-drain region and as the programming/erasing gate The substrate implant region of the erase gate is electrically connected.

Wherein, the plurality of fin structures further include a capping layer on the top layer.

Wherein, the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials and combinations thereof. Wherein, the high-k material includes hafnium-based materials selected from HfO ₂ , HfSiO _x , HfSiON, HfAlO _x , HfTaO _x , HfLaO _x , HfAlSiO _x , HfLaSiO _x , or includes hafnium-based materials selected from ZrO ₂ , La ₂ O ₃ , LaAlO ₃ , TiO ₂ , Y ₂ O ₃ rare earth-based high-K dielectric material, or a composite layer including Al ₂ O ₃ and the above materials.

Wherein, the floating gate includes polysilicon, metals, alloys of the metals, nitrides of the metals and combinations thereof. Wherein, the metal includes Al, Ta, Ti and combinations thereof.

Among them, the metal silicide materials include Ni Si _2-y , PtS i _2-y , CoSi _2-y , Ni _1-x Pt _x Si _2-y , Ni _{1- x} Co _x Si _2-y , Pt _{1 -x} Co _x Si _2-y , Ni _2-xz Pt _x Co _z Si _3-y , where x and z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.

Wherein, the material of the connecting wire includes W, Cu, Al, Ti, Ta and combinations thereof.

The present invention also provides a manufacturing method of a multi-time programmable semiconductor device, comprising the steps of: forming a plurality of fin-shaped structures extending along a first direction parallel to the surface of the substrate on the substrate, including substrate implantation regions, buried Oxygen layer, top layer; form a gate insulating layer on the top and both sides of multiple fin structures; form a gate conductive layer on both sides of the gate insulating layer; photolithography/etch the gate conductive layer, only in the top layer Retain part of the gate conductive layer on both sides of the channel region as a floating gate; photolithography/etch multiple fin structures to expose part of the substrate implant region; form source and drain contacts, and form connections to the exposed substrate implant region’s program/erase gate contacts.

Wherein, the step of forming a plurality of fin structures further includes: performing dopant implantation on the substrate including the bottom layer, buried oxide layer and top layer, forming a substrate implantation region in the bottom layer below the buried oxide layer to form a programming/erasing gate ; Photolithography/etching the substrate until the undoped bottom layer is exposed, forming a plurality of fin-shaped structures extending and distributed along a first direction parallel to the substrate surface.

Wherein, the step of photolithography/etching the gate conductive layer further includes: forming a hard mask pattern extending along a second direction parallel to the substrate surface on the substrate, the gate conductive layer, and the gate insulating layer; The hard mask pattern is a mask, and the gate conductive layer is etched, leaving only a part of the gate conductive layer covered by the hard mask pattern, wherein the top layer below the hard mask pattern constitutes the channel region, and the top layer at both ends of the channel region form the source-drain region.

Wherein, the step of exposing part of the substrate implantation region further includes: forming a hard mask layer on the entire device; planarizing until the gate insulating layer is exposed; photolithography/etching part of the gate insulating layer, top layer, buried oxide layer , until the substrate implantation region is exposed, forming a programming/erasing gate contact hole, wherein the programming/erasing gate contact hole is located at one end of the source-drain region in the first direction.

Wherein, the steps of forming source-drain contacts and forming programming/erasing gate contact holes connected to exposed substrate implant regions further include: forming an interlayer dielectric layer on the entire device; photolithography/etching to form source-drain contact holes, And the programming/erasing gate contact hole connected to the exposed substrate implant region; metal silicide is formed in the source-drain contact hole and the programming/erasing gate contact hole; the source-drain contact hole and the programming/erasing gate contact hole Fill with conductive material to form connection lines.

Wherein, the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials and combinations thereof.

Wherein, the high-k material includes hafnium-based materials selected from HfO ₂ , HfSiO _x , HfSiON, HfAlO _x , HfTaO _x , HfLaO _x , HfAlSiO _x , HfLaSiO _x , or includes hafnium-based materials selected from ZrO ₂ , La ₂ O ₃ , LaAlO ₃ , TiO ₂ , Y ₂ O ₃ rare earth-based high-K dielectric material, or a composite layer including Al ₂ O ₃ and the above materials.

Wherein, the floating gate includes polysilicon, metals, alloys of the metals, nitrides of the metals and combinations thereof.

Wherein, the metal includes Al, Ta, Ti and combinations thereof.

Among them, the metal silicide materials include NiSi _2-y , PtSi _2-y , CoSi _2-y , Ni _1-x Pt _x Si _2-y , Ni _1-x Co _x Si _2-y , Pt _1-x Co _x Si _2-y , Ni _2-xz Pt _x Co _z Si _3-y , where x and z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1.

Wherein, the material of the connecting wire includes W, Cu, Al, Ti, Ta and combinations thereof.

According to the multi-time programmable semiconductor device and its manufacturing method of the present invention, the programming/erasing gate of the FinFET is formed by using the substrate implantation region, which simplifies the device structure, reduces the manufacturing process, improves the integration density of the device, and is suitable for Multiple times programmable memory.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

FIG. 1A shows a top view of step S1 of the method according to the present invention, wherein a fin-shaped structure extending along a first direction is formed on an SOI substrate;

Fig. 1 B is a cross-sectional view along line AA' among Fig. 1A;

FIG. 2A shows a top view of step S2 of the method according to the present invention, wherein a gate insulating layer and a gate conductive layer are formed on the fin structure and on the side;

Fig. 2B is a sectional view along line AA' of Fig. 2A;

Fig. 2 C is the sectional view of Fig. 2 A along line BB';

Fig. 2D is a sectional view along line CC' of Fig. 2A;

Figure 2E is a sectional view along line DD' of Figure 2A;

3A shows a top view of step S3 of the method according to the present invention, wherein a mask is formed along the second direction and the gate insulating layer and the gate conductive layer are etched;

Fig. 3B is a sectional view along line AA' of Fig. 3A;

Fig. 3 C is a cross-sectional view along line BB' of Fig. 3A;

Figure 3D is a sectional view along line CC' of Figure 3A;

Figure 3E is a sectional view along line DD' of Figure 3A;

FIG. 4A shows a top view of step S4 of the method according to the present invention, wherein etching forms programming/erasing gate contact holes;

Fig. 4B is a sectional view along line AA' of Fig. 4A;

Fig. 4C is a sectional view along line BB' of Fig. 4A;

Figure 4D is a sectional view along line CC' of Figure 4A;

Figure 4E is a sectional view along line DD' of Figure 4A;

Fig. 4F is a sectional view along line EE' of Fig. 4A;

FIG. 5A shows a top view of step S5 of the method according to the present invention, wherein source-drain contacts and program/erase gate contacts are formed;

Fig. 5B is a cross-sectional view along line AA' of Fig. 5A;

Figure 5C is a sectional view along line BB' of Figure 5A;

Figure 5D is a sectional view along line CC' of Figure 5A;

Figure 5E is a sectional view along line DD' of Figure 5A;

Figure 5F is a cross-sectional view along line EE' of Figure 5A; and

Figure 6 shows a flow chart of the method according to the invention.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments, disclosing a high-density integrated multi-time programmable semiconductor device suitable for FinFET technology and a manufacturing method thereof. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or process steps . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or process steps unless otherwise specified.

Referring to FIG. 6 and FIG. 1A and FIG. 1B , a method step S1 according to the present invention is shown, wherein a plurality of fin-shaped structures extending along a first direction are formed on a substrate. A semiconductor substrate is provided, which is made of silicon-on-insulator (SOI), and includes a bottom layer 1 , a buried oxide layer 2 and a top layer 3 . The material of the bottom layer 1 and the top layer 3 are both silicon (Si), and the thickness of the top layer 3 is smaller than that of the bottom layer 1 . The material of the buried oxide layer 2 is the corresponding oxide of the material of the top layer 3 , such as silicon oxide (SiO ₂ ), and the thickness of the buried oxide layer 2 is smaller than that of the top layer 3 . Doping implantation is performed on the semiconductor substrate, and different types of doping ions are implanted according to the different conductivity types of PMOS and NMOS. The peak of doped ion implantation is located below the buried oxide layer 2, for example, 1 to 10 nm away from the bottom surface of the buried oxide layer 2, so that a part of the bottom layer 1 has a higher n+ or p+ doping concentration, forming the bottom layer implantation region 1D, which is beneficial Later used as program/erase gate (or word line). At the same time, less dopant ions are also distributed in the top layer 3 , so that the top layer 3 has a lower n- or p- doping concentration, which is beneficial for later formation of source and drain regions. Deposit a cap layer 4 on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and its material is, for example, silicon nitride or silicon oxynitride, which is used to form a hard mask for fin structure etching and a barrier for subsequent etching layer. Lithographically and anisotropically etch the cap layer 4, the top layer 3, the buried oxide layer 2, and the bottom implant region 1D until the undoped bottom layer 1 is exposed, forming a layer on the bottom layer 1 along a first direction parallel to the surface of the bottom layer 1. Extended multiple fin structures. The interface where the etching stops is, for example, located 10-20 nm below the bottom surface of the buried oxide layer 2 . As shown in FIG. 1A, in a top view, a plurality of fin-shaped structures extend along a first direction parallel to the substrate surface, and a line AA' passes through the plurality of fin-shaped structures along a second direction parallel to the substrate surface. The section line of will serve as the position of the gate (floating gate) of the FinFET device, wherein the second direction intersects the first direction, and is optionally vertical. And below, if there is no explicit indication to the contrary, the spatial positions of all identically marked cross-lines are the same. 1B is a cross-sectional view of FIG. 1A taken along the section line AA', wherein the plurality of fin structures sequentially include a cap layer 4 , a top layer 3 , a buried oxide layer 2 and a bottom implant region 1D from top to bottom.

Referring to FIG. 6 and FIGS. 2A to 2E , step S2 of the method according to the present invention is shown, wherein a gate insulating layer extending along the first direction is formed on the sides and top surfaces of a plurality of fin structures, and the gate insulating layer A gate conductive layer extending along the first direction is formed on both sides. Deposit gate insulating material on the fin structure (4/3/2/1A) and the bottom layer 1 by LPCVD, PECVD, HDPCVD, ALD and other conventional methods, and perform photolithography/etching, leaving only the top and sides of the fin structure a gate insulating layer 5 extending along the first direction. The material of the gate insulating layer 5 includes silicon oxide, silicon nitride, silicon oxynitride, high-k materials and combinations thereof. Wherein, the high-k material includes hafnium-based materials selected from HfO ₂ , HfSiO _x , HfSiON, HfAlO _x , HfTaO _x , HfLaO _x , HfAlSiO _x , HfLaSiO _x , or includes hafnium-based materials selected from ZrO ₂ , La ₂ O ₃ , LaAlO ₃ , TiO ₂ , Y ₂ O ₃ rare earth-based high-K dielectric material, or a composite layer including Al ₂ O ₃ and the above materials. Preferably, a high-k material is selected as the gate insulating layer 5 so as to be suitable for small-sized devices, so that an ultra-thin gate insulating layer can be used as a tunnel oxide layer to realize electrical erasing by using FN tunneling effect. The thickness of the gate insulating layer 5 is, for example, 1 to 10 nm. Subsequently, on the gate insulating layer 5 and the bottom layer 1, the gate conductive material is deposited by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc., and photolithography/etching is performed. Only the substrate bottom layer on both sides of the gate insulating layer 5 1, leaving a gate conductive layer 6 extending in the first direction, which will be patterned later to be used as a floating gate. The material of the gate conductive layer 6 includes polysilicon, metal, metal alloy, metal nitride and combinations thereof, wherein the metal includes Al, Ta, Ti and combinations thereof. The thickness of the gate conductive layer 6 is, for example, 1 to 10 nm. Fig. 2A is a top view, wherein section line AA' is the same as section line AA' in Fig. 1A; The source and drain regions of the device; the section line CC' passes through the fin structure, and along the first direction, its position includes the later channel region and the connection area of the program/erase gate; the section line DD' does not pass through the fin Shaped structure and along the first direction are used to supplement the description of the spatial structure of the device. 2B and 2C are cross-sectional views of FIG. 2A along line AA' and line BB' respectively. It can be seen that the gate insulating layer 5 is distributed on the top and side surfaces of the fin structure (4/3/2/1A) on the substrate bottom layer 1; Electrode conductive layer 6 is distributed on both sides of gate insulating layer 5 on substrate bottom layer 1 , and its top is lower than the top of gate insulating layer 5 . FIG. 2D is a cross-sectional view along line CC′ in FIG. 2A , it can be seen that the gate insulating layer 5 is located on the top of the fin structure and also extends along the first direction. 2E is a cross-sectional view along the line DD' in FIG. 2A , it can be seen that there is no gate insulating layer 5 and gate conductive layer 6 outside the fin-shaped structure region on the substrate bottom layer 1 .

Referring to FIG. 6 and FIG. 3A to FIG. 3E, step S3 of the method according to the present invention is shown, wherein a mask is formed along the second direction and part of the gate insulating layer and the gate conductive layer are etched and removed, only in the area covered by the mask Parts of the gate insulating layer and the gate conductive layer are reserved. A first hard mask material is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, and ALD, and its material is, for example, silicon oxide, silicon nitride, and silicon oxynitride. Photolithography/etching of the hard mask material forms a plurality of first hard mask patterns 7 extending along the second direction, wherein at least one of the first hard mask patterns 7 passes through the section line AA' to retain the gate underneath it The insulating layer 5 and the gate conductive layer 6 are used as insulating layers and floating gates on both sides of the channel region of the device. Then, using the first hard mask pattern 7 as a mask, the gate conductive layer 6 is etched anisotropically so that only the gate conductive layer 6 under the first hard mask pattern 7 remains as a floating gate. FIG. 3A is a top view, it can be seen that the first hard mask pattern 7 extends along the second direction and at least passes through the section line AA'. 3B and 3C are cross-sectional views along the lines AA' and BB' of FIG. 3A respectively. It can be seen that the gate conductive layer 6 is removed on the area not covered by the first hard mask pattern 7 . Figure 3D and Figure 3E are cross-sectional views of Figure 3A along lines CC' and DD' respectively, where the top layer 3 part in the region through which the AA' line passes constitutes the channel region 3C, and the remaining top layer 3 parts constitute the source and drain regions 3S/3D , which will be used as the control part (or bit line) of the device in the future.

Referring to FIG. 6 and FIG. 4A to FIG. 4F , step S4 of the method according to the present invention is shown, wherein a control gate contact hole is formed by etching. The second hard mask layer 8 is deposited by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, etc. on the entire device, and its material is, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably the second hard mask layer 8 and the first A hard mask layer/pattern 7 is made of the same material. Then, the second hard mask layer 8 is planarized by CMP or other processes until the gate insulating layer 5 is exposed. Then photolithography/etching part of the second hard mask layer 8, gate insulating layer 5, capping layer 4, top layer 3, buried oxide layer 2, until the underlying implant region 1D is exposed, forming multiple programming/erasing gate contacts Hole 8H. FIG. 4A is a top view, wherein the line EE' passes through the position where the programming/erasing gate contact hole 8H is located, and extends along the second direction, and the programming/erasing gate contact hole 8H extends along the first direction. 4B and 4C are cross-sectional views along the lines AA' and BB' of FIG. 4A respectively. Similar to FIGS. 3B and 3C, it can be seen that the gate conductive layer 6 is removed in the area not covered by the original first hard mask pattern 7. , and the top of the second hard mask layer 8 is flush with the top of the gate insulating layer 5 . Fig. 4D is a cross-sectional view along line CC' of Fig. 4A. It can be seen that the programming/erasing gate contact hole 8H reaches directly to the underlying implanted region 1D, so that the doped underlying implanted region 1D used as the programming/erasing gate can be electrically connected to the outside. Fig. 4E is a cross-sectional view of Fig. 4A along line DD'. 4F is a cross-sectional view of FIG. 4A along section line EE'. It can be seen that in the programming/erasing gate contact hole 8H, a part of the top and side of the gate insulating layer 5 is removed, and only the implanted region 1D in the bottom layer remains. parts on both sides.

Referring to FIG. 6 and FIG. 5A to FIG. 5F , step S5 of the method according to the present invention is shown, wherein source-drain contacts and program/erase gate contacts are formed. The interlayer dielectric layer 9 is deposited on the entire device by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, and its material is, for example, silicon oxide, silicon nitride or silicon oxynitride, preferably with the first hard mask layer/pattern 7 and /or the materials of the second hard mask layer 8 are the same. Photolithography/etching the interlayer dielectric layer 9, forming the source-drain contact hole 9SD at the position corresponding to the source-drain region 3S/3D, and forming the programming/erasing gate at the position corresponding to the programming/erasing gate contact hole 8H Contact hole 9P. Metal silicide 10 is then formed in each contact hole to reduce contact resistance. The material of metal silicide 10 includes NiSi _2-y , PtSi _2-y , CoSi _2-y , Ni _1-x Pt _x Si _2-y , Ni _1-x Co _x Si _2-y , Pt _1-x Co _x Si _2-y , Ni _2-xz Pt _x Co _z Si _3-y , where x and z are greater than 0 and less than 1, and y is greater than or equal to 0 and less than or equal to 1. Then, each contact hole is filled with a conductive material 11 to form a contact plug and a connection line. The conductive material 11 is, for example, W, Cu, Al, Ti, Ta or a combination thereof. Figure 5A is a top view, in which the AA' line passes through the channel region and the gate insulating layer and the gate conductive layer on both sides of the channel region, and BB' passes through the source and drain regions and the gate insulating layer on both sides of the source and drain region , CC' passes through the source-drain region, channel region, programming/erasing gate contact holes, DD' only passes through the bottom layer 1 of the substrate, and EE' passes through the substrate implantation region 1D. 5B is a cross-sectional view along AA' of FIG. 5A , it can be seen that there are gate insulating layers 5 on both sides of the channel region 3C, and gate conductive layers 6 (floating gates) on both sides of the gate insulating layer 5 . Fig. 5C is a cross-sectional view along BB' of Fig. 5A. It can be seen that the source-drain connection line 11SD (as the bit line of the device unit) is electrically connected to the source-drain region 3S/3D through the metal silicide 10, and there is only gate insulation on both sides of the source-drain region Layer 5 without gate conductive layer 6. 5D and 5E are cross-sectional views of FIG. 5A along CC' and EE', respectively. It can be seen that the programming/erasing gate connection line 11C (word line as a device unit) is electrically connected to the substrate implantation region 1D through the metal silicide 10, And there are part of the gate insulating layer 5 on both sides of the substrate injection region 1D. FIG. 5E is a cross-sectional view along DD' of FIG. 5A .

The resulting multi-time programmable semiconductor device is shown in Figures 5A to 5F, including: a plurality of fin structures located on the substrate, including a substrate implant region 1D, a buried oxide layer 2, a top layer 3 and optionally a cap Layer 4, a plurality of fin-shaped structures extending along a first direction parallel to the substrate surface; channel region 3C, located in the top layer 3 of the plurality of fin-shaped structures; source and drain regions 3S/3D, located in the plurality of fin-shaped structures Both ends of the channel region 3C in the top layer 3; the gate insulating layer 5, located on the top and side of the channel region 3C, extends along a second direction parallel to the substrate surface, and the second direction intersects the first direction and Preferably vertical; the floating gate 6 is located on both sides of the fin structure in the second direction and is in contact with the gate insulating layer 5; the programming/erasing gate is formed by the substrate implantation region 1D and is located below the channel region 3C; The interlayer dielectric layer 9 covers a plurality of fin structures, gate insulating layers and floating gates; the source and drain contact holes 9SD and the programming/erasing gate contact holes 9P are formed in the interlayer dielectric layer 9, respectively exposing the source and drain regions 3S /3D and the substrate implantation region 1D as the programming/erasing gate; the metal silicide 10 is formed in the source-drain contact hole 9SD and the programming/erasing gate contact hole 9P; the connection line 11 passes through the metal silicide 10 and the source The drain region 3S/3D is electrically connected to the substrate implantation region 1D serving as a program/erase gate, wherein the source-drain region connection line 11SD extends along the second direction.

The specific material and geometric structure parameters of the above components have been described in detail in each step of the manufacturing method. In addition, subsequent manufacturing processes, such as the connection of word lines and bit lines, the manufacture of selection circuits, etc., are widely known to those skilled in the art. , so it will not be repeated here.

According to the multi-time programmable semiconductor device of the present invention, the substrate implantation region is used to form the programming/erasing gate of the FinFET, which simplifies the device structure, reduces the manufacturing process, improves the integration density of the device, and is suitable for multi-time programmable memory.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (20)

1. can a repeatedly programming semiconductor device, including:

Multiple fin structure, are positioned on substrate and extend distribution along the first direction being parallel to substrate surface, injecting including substrate District, oxygen buried layer, top layer；

Channel region, is positioned in the top layer of multiple fin structure；

Source-drain area, is positioned at channel region two ends in the top layer of multiple fin structure；

Gate insulator, is positioned at top and the sidepiece of channel region, extends distribution along the second direction being parallel to substrate surface；

Floating boom, is positioned at the both sides in the second direction of multiple fin structure；

Program/erase grid, are made up of substrate injection region, are positioned at below oxygen buried layer.

The most as claimed in claim 1 can repeatedly programming semiconductor device, farther include:

Interlayer dielectric layer, covers multiple fin structure, gate insulator, floating boom；

Source and drain contact hole and control gate contact hole, be formed in interlayer dielectric layer, respectively source of exposure drain region and conduct programming/wiping Substrate injection region except grid；

Metal silicide, is formed in source and drain contact hole and program/erase grid contact hole；

Connecting line, is electrically connected by the metal silicide substrate injection region with source-drain area and as program/erase grid.

3. as claim 1 can repeatedly programming semiconductor device, wherein, multiple fin structure also include the lid being positioned on top layer Layer.

The most as claimed in claim 1 can repeatedly programming semiconductor device, wherein, gate insulator includes silicon oxide, silicon nitride, nitrogen oxygen SiClx, high-g value and combinations thereof.

The most as claimed in claim 4 can repeatedly programming semiconductor device, wherein, high-g value includes selected from HfO₂、HfSiO_x、 HfSiON、HfAlO_x、HfTaO_x、HfLaO_x、HfAlSiO_x、HfLaSiO_xHafnio material, or include selected from ZrO₂、La₂O₃、 LaAlO₃、TiO₂、Y₂O₃Rare earth base high K dielectric material, or include Al₂O₃, or the composite bed of above-mentioned material.

The most as claimed in claim 1 can repeatedly programming semiconductor device, wherein, floating boom includes polysilicon, metal, the conjunction of described metal Nitride of metal golden, described and combinations thereof.

The most as claimed in claim 6 can repeatedly programming semiconductor device, wherein, described metal includes Al, Ta, Ti and combinations thereof.

The most as claimed in claim 2 can repeatedly programming semiconductor device, wherein, the material of metal silicide includes NiSi_2-y、 PtSi_2-y、CoSi_2-y、Ni_1-xPt_xSi_2-y、Ni_1-xCo_xSi_2-y、Pt_1-xCo_xSi_2-y、Ni_2-x-zPt_xCo_zSi_3-y, wherein x, z are more than 0 Less than 1, y is less than or equal to 1 more than or equal to 0.

The most as claimed in claim 2 can repeatedly programming semiconductor device, wherein, the material of connecting line include W, Cu, Al, Ti, Ta and A combination thereof.

10. can a repeatedly programming semiconductor device making method, including step:

Substrate is formed the multiple fin structure extending distribution along the first direction being parallel to substrate surface, injects including substrate District, oxygen buried layer, top layer；

Gate insulator is formed at multiple fin structure tops and both sides；

Grid conducting layer is formed in gate insulator both sides；

Photoetching/etching grid conductive layer, the only grid conducting layer of the channel region both sides member-retaining portion in being positioned at top layer, as floating Grid；

Photoetching/etch multiple fin structure, the substrate injection region of expose portion；

Formation source and drain contacts, and forms the program/erase grid contact of the substrate injection region being connected to exposure.

11. such as claim 10 can repeatedly programming semiconductor device making method, wherein, form the step of multiple fin structure Farther include: the substrate including bottom, oxygen buried layer and top layer is doped injection, the bottom below oxygen buried layer is formed Substrate injection region, constitutes program/erase grid；Photoetching/etched substrate, until exposing unadulterated bottom, is formed along being parallel to lining The first direction of basal surface extends multiple fin structure of distribution.

12. such as claim 10 can repeatedly programming semiconductor device making method, wherein, photoetching/etching grid conductive layer Step farther includes: forms the second direction along being parallel to substrate surface on substrate, grid conducting layer, gate insulator and prolongs The hard mask pattern that extending portion is divided；With hard mask pattern as mask, etching grid conductive layer, only stay and covered by hard mask pattern Part of grid pole conductive layer, wherein the top layer constituting channel district below hard mask pattern, the top layer at channel region two ends constitutes source-drain area.

13. such as claim 10 can repeatedly programming semiconductor device making method, wherein, the substrate injection region of expose portion Step farther includes: form hard mask layer on whole device；Planarization is until exposing gate insulator；Photoetching/etching portion Point gate insulator, top layer, oxygen buried layer, until expose substrate injection region, formed program/erase grid contact hole, wherein programming/ Erasing grid contact hole is positioned at one end of source-drain area on first direction.

14. such as claim 10 can repeatedly programming semiconductor device making method, wherein, form source and drain contact and the company of being formed The step of the program/erase grid contact hole receiving the substrate injection region of exposure farther includes: form interlayer on whole device Dielectric layer；Photoetching/etching forms source and drain contact hole, and is connected to the program/erase grid contact hole of the substrate injection region exposed； Metal silicide is formed in source and drain contact hole and program/erase grid contact hole；Contact with program/erase grid at source and drain contact hole Hole is filled conductive material, forms connecting line.

15. such as claim 10 can repeatedly programming semiconductor device making method, wherein, gate insulator include silicon oxide, Silicon nitride, silicon oxynitride, high-g value and combinations thereof.

16. such as claim 10 can repeatedly programming semiconductor device making method, wherein, high-g value includes selected from HfO₂、 HfSiO_x、HfSiON、HfAlO_x、HfTaO_x、HfLaO_x、HfAlSiO_x、HfLaSiO_xHafnio material, or include being selected from ZrO₂、La₂O₃、LaAlO₃、TiO₂、Y₂O₃Rare earth base high K dielectric material, or include Al₂O₃, or above-mentioned material is compound Layer.

17. such as claim 16 can repeatedly programming semiconductor device making method, wherein, floating boom includes polysilicon, metal, institute State nitride of the alloy of metal, described metal and combinations thereof.

18. such as claim 17 can repeatedly programming semiconductor device making method, wherein, described metal include Al, Ta, Ti and A combination thereof.

19. such as claim 14 can repeatedly programming semiconductor device making method, wherein, the material of metal silicide includes NiSi_2-y、PtSi_2-y、CoSi_2-y、Ni_1-xPt_xSi_2-y、Ni_1-xCo_xSi_2-y、Pt_1-xCo_xSi_2-y、Ni_2-x-zPt_xCo_zSi_3-y, wherein X, z are more than 0 less than 1, and y is less than or equal to 1 more than or equal to 0.

20. such as claim 14 can repeatedly programming semiconductor device making method, wherein, the material of connecting line include W, Cu, Al, Ti, Ta and combinations thereof.