CN103681800B - Multi-time programmable semiconductor device and manufacturing method thereof - Google Patents
Multi-time programmable semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103681800B CN103681800B CN201210326597.XA CN201210326597A CN103681800B CN 103681800 B CN103681800 B CN 103681800B CN 201210326597 A CN201210326597 A CN 201210326597A CN 103681800 B CN103681800 B CN 103681800B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 238000002347 injection Methods 0.000 claims abstract description 41
- 239000007924 injection Substances 0.000 claims abstract description 41
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 23
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 23
- 238000007667 floating Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 118
- 239000012212 insulator Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 16
- 238000009826 distribution Methods 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 10
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 229910002244 LaAlO3 Inorganic materials 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 229910052593 corundum Inorganic materials 0.000 claims description 5
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 5
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 claims description 5
- 229910052761 rare earth metal Inorganic materials 0.000 claims description 5
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 5
- 229910015468 Ni1-xCox Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- -1 bottom Substances 0.000 claims description 2
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 230000012447 hatching Effects 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000011435 rock Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910002065 alloy metal Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a multiple time programmable semiconductor device, comprising: the fin-shaped structures are positioned on the substrate and extend and are distributed along a first direction parallel to the surface of the substrate, and each fin-shaped structure comprises a substrate injection region, an oxygen burying layer and a top layer; a channel region in a top layer of the plurality of fin structures; the source and drain regions are positioned at two ends of the channel region in the top layer of the fin-shaped structures; the gate insulation layers are positioned at the top and the side parts of the channel region and extend and are distributed along a second direction parallel to the surface of the substrate; the floating gates are positioned on two sides of the fin-shaped structures in the second direction; and the programming/erasing gate is formed by a substrate injection region and is positioned below the buried oxide layer. According to the multiple-time programmable semiconductor device and the manufacturing method thereof, the programming/erasing gate of the FinFET is formed by utilizing the substrate injection region, the structure of the device is simplified, the manufacturing procedures are reduced, the integration density of the device is improved, and the multiple-time programmable semiconductor device is suitable for a multiple-time programmable memory.
Description
Technical field
The present invention relates to a kind of multiple programmable semiconductor device and manufacture method thereof, particularly relate to a kind of high density,
It is applicable to multiple programmable semiconductor device and the manufacture method thereof of fin-shaped field effect transistor (FinFET) technology.
Background technology
Along with CMOS technology characteristic size continues equal proportion reduction, metal-oxide-semiconductor memory structural development is rapid, occurs in that various types of
The memory unit of type.But although DRAM integrated level height is low in energy consumption cannot preserve information for a long time, although and SRAM is permissible
But it is low to preserve the big integrated level of information area for a long time.Current technology development is gradually conceived to ROM, particularly electric erasable
E2PROM。
Existing E2In prom cell, utilize the F-N tunnel-effect of thin oxide layer to realize electrically erasable, generally include channel region
On be sequentially stacked ultra-thin tunnel oxidation layer, the floating boom of polysilicon, interlayer dielectric, polysilicon or the control gate of metal.But
Because sub-threshold leakage in traditional MOSFET, this structure performance in small size device is substantially reduced.Additionally, threshold value is electric
The change of pressure seriously limits driving intensity and response speed.
It is to utilize FinFET to realize E that one efficiently solves scheme2PROM, by change floating boom electric charge improve or
Reduce the threshold voltage of transistor, thus provide higher performance and relatively low power consumption for chip.But, existing FinFET is real
Existing E2PROM structure is excessively complicated, device area is relatively big, and process costs is high, integration density is low, it is difficult to be applicable to extensive
Memory cell array manufacture.
Sum it up, current multiple programmable semiconductor device structure is complicated, with high costs, inefficient, needs badly and change
Enter.
Summary of the invention
Therefore, it is an object of the invention to provide a kind of superintegrated, be applicable to repeatedly can compiling of finfet technology
Journey semiconductor device and manufacture method thereof.
The invention provides a kind of multiple programmable semiconductor device, including: multiple fin structure, it is positioned on substrate and edge
The first direction being parallel to substrate surface extends distribution, including substrate injection region, oxygen buried layer, top layer；Channel region, is positioned at multiple fin
In the top layer of shape structure；Source-drain area, is positioned at channel region two ends in the top layer of multiple fin structure；Gate insulator, is positioned at raceway groove
The top in district and sidepiece, extend distribution along the second direction being parallel to substrate surface；Floating boom, is positioned at the of multiple fin structure
Both sides on two directions；Program/erase grid, are made up of substrate injection region, are positioned at below oxygen buried layer.
Farther include: interlayer dielectric layer, cover multiple fin structure, gate insulator, control gate, floating boom；Source and drain connects
Contact hole and program/erase grid contact hole, be formed in interlayer dielectric layer, distinguishes source of exposure drain region and as program/erase grid
Substrate injection region；Metal silicide, is formed in source and drain contact hole and program/erase grid contact hole；Connecting line, passes through metal
The silicide substrate injection region with source-drain area and as program/erase grid electrically connects.
Wherein, multiple fin structure also include the cap rock being positioned on top layer.
Wherein, gate insulator includes silicon oxide, silicon nitride, silicon oxynitride, high-g value and combinations thereof.Wherein, high k material
Material includes selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnio material,
Or include selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or include Al2O3, with on it
State the composite bed of material.
Wherein, floating boom includes nitride of polysilicon, metal, the alloy of described metal, described metal and combinations thereof.Its
In, described metal includes Al, Ta, Ti and combinations thereof.
Wherein, the material of metal silicide includes Ni S i2-y、PtS i2-y、CoSi2-y、Ni1-xPtxSi2-y、Ni1- xCoxSi2-y、Pt1-xCoxSi2-y、Ni2-x-zPtxCozSi3-y, wherein x, z are more than 0 less than 1, and y is less than or equal to 1 more than or equal to 0.
Wherein, the material of connecting line includes W, Cu, Al, Ti, Ta and combinations thereof.
Present invention also offers a kind of multiple programmable method, semi-conductor device manufacturing method, including step: formed on substrate
Multiple fin structure of distribution are extended, including substrate injection region, oxygen buried layer, top layer along the first direction being parallel to substrate surface；
Gate insulator is formed at multiple fin structure tops and both sides；Grid conducting layer is formed in gate insulator both sides；Photoetching/
Etching grid conductive layer, the only grid conducting layer of the channel region both sides member-retaining portion in being positioned at top layer, as floating boom；Photoetching/
Etch multiple fin structure, the substrate injection region of expose portion；Formation source and drain contacts, and forms the substrate note being connected to expose
Enter the program/erase grid contact in district.
Wherein, the step forming multiple fin structure farther includes: enter the substrate including bottom, oxygen buried layer and top layer
Row doping is injected, and forms substrate injection region, constitute program/erase grid in the bottom below oxygen buried layer；Photoetching/etched substrate,
Until exposing unadulterated bottom, form the multiple fin structure extending distribution along the first direction being parallel to substrate surface.
Wherein, the step of photoetching/etching grid conductive layer farther includes: at substrate, grid conducting layer, gate insulator
The upper hard mask pattern formed along the second direction extension being parallel to substrate surface；With hard mask pattern as mask, etching
Grid conducting layer, only leaves the part of grid pole conductive layer covered by hard mask pattern, wherein the top layer structure below hard mask pattern
Becoming channel region, the top layer at channel region two ends constitutes source-drain area.
Wherein, the step of the substrate injection region of expose portion farther includes: form hard mask layer on whole device；Flat
Smoothization is until exposing gate insulator；The gate insulator of photoetching/etched portions, top layer, oxygen buried layer, inject until exposing substrate
District, forms program/erase grid contact hole, and wherein program/erase grid contact hole is positioned at one end of source-drain area on first direction.
Wherein, formation source and drain contacts and is formed the program/erase grid contact hole of the substrate injection region being connected to exposure
Step farther includes: form interlayer dielectric layer on whole device；Photoetching/etching forms source and drain contact hole, and is connected to
The program/erase grid contact hole of the substrate injection region exposed；Metal is formed in source and drain contact hole and program/erase grid contact hole
Silicide；In source and drain contact hole and program/erase grid contact hole, fill conductive material, form connecting line.
Wherein, gate insulator includes silicon oxide, silicon nitride, silicon oxynitride, high-g value and combinations thereof.
Wherein, high-g value includes selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、
HfLaSiOxHafnio material, or include selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or
It is to include Al2O3, with the composite bed of its above-mentioned material.
Wherein, floating boom includes nitride of polysilicon, metal, the alloy of described metal, described metal and combinations thereof.
Wherein, described metal includes Al, Ta, Ti and combinations thereof.
Wherein, the material of metal silicide includes NiSi2-y、PtSi2-y、CoSi2-y、Ni1-xPtxSi2-y、Ni1-xCoxSi2-y、
Pt1-xCoxSi2-y、Ni2-x-zPtxCozSi3-y, wherein x, z are more than 0 less than 1, and y is less than or equal to 1 more than or equal to 0.
Wherein, the material of connecting line includes W, Cu, Al, Ti, Ta and combinations thereof.
According to multiple programmable semiconductor device and the manufacture method thereof of the present invention, utilize substrate injection region to form Fi
The program/erase grid of nFET, simplify device architecture, and reduce manufacturing process, improve the integration density of device, it is adaptable to
Time-after-time programmable memory.
Accompanying drawing explanation
Describe technical scheme referring to the drawings in detail, wherein:
Figure 1A shows the top view of the method step S 1 according to the present invention, is formed the most on soi substrates along first party
To the fin structure extended；
Figure 1B is the sectional view of AA ' along the line in Figure 1A；
Fig. 2 A shows the top view of the method step S2 according to the present invention, wherein in fin structure and side is formed
Gate insulator and grid conducting layer；
Fig. 2 B is the sectional view of Fig. 2 A AA ' along the line；
Fig. 2 C is the sectional view of Fig. 2 A BB ' along the line；
Fig. 2 D is the sectional view of Fig. 2 A CC ' along the line；
Fig. 2 E is the sectional view of Fig. 2 A DD ' along the line；
Fig. 3 A shows the top view of the method step S3 according to the present invention, forms mask the most in a second direction and etches
Gate insulator and grid conducting layer；
Fig. 3 B is the sectional view of Fig. 3 A AA ' along the line；
Fig. 3 C is the sectional view of Fig. 3 A BB ' along the line；
Fig. 3 D is the sectional view of Fig. 3 A CC ' along the line；
Fig. 3 E is the sectional view of Fig. 3 A DD ' along the line；
Fig. 4 A shows the top view of the method step S4 according to the present invention, and wherein etching forms the contact of program/erase grid
Hole；
Fig. 4 B is the sectional view of Fig. 4 A AA ' along the line；
Fig. 4 C is the sectional view of Fig. 4 A BB ' along the line；
Fig. 4 D is the sectional view of Fig. 4 A CC ' along the line；
Fig. 4 E is the sectional view of Fig. 4 A DD ' along the line；
Fig. 4 F is the sectional view of Fig. 4 A EE ' along the line；
Fig. 5 A shows the top view of the method step S5 according to the present invention, wherein forms source and drain contact and programming/wiping
Except grid contact；
Fig. 5 B is the sectional view of Fig. 5 A AA ' along the line；
Fig. 5 C is the sectional view of Fig. 5 A BB ' along the line；
Fig. 5 D is the sectional view of Fig. 5 A CC ' along the line；
Fig. 5 E is the sectional view of Fig. 5 A DD ' along the line；
Fig. 5 F is the sectional view of Fig. 5 A EE ' along the line；And
Fig. 6 shows the flow chart of the method according to the present invention.
Detailed description of the invention
Referring to the drawings and combine schematic embodiment to describe feature and the skill thereof of technical solution of the present invention in detail
Art effect, discloses superintegrated, to be applicable to finfet technology multiple programmable semiconductor device and manufacture method thereof.
It is pointed out that similar reference represents similar structure, term " first " use herein, " second ",
On " ", D score etc. can be used for modifying various device architecture or processing step.These modifications do not imply that institute unless stated otherwise
Modify device architecture or the space of processing step, order or hierarchical relationship.
With reference to Fig. 6 and Figure 1A, Figure 1B, it is shown that according to the method step S1 of the present invention, on substrate, wherein form edge
Multiple fin structure that first direction extends.There is provided Semiconductor substrate, its material is silicon-on-insulator (SOI), including bottom 1,
Oxygen buried layer 2 and top layer 3.Wherein bottom 1 be silicon (Si) identical with top layer 3 material, and top layer 3 thickness is less than the thickness of bottom 1
Degree.Oxygen buried layer 2 material is the corresponding oxide of top layer 3 material, for example, silicon oxide (SiO2), and oxygen buried layer 2 thickness is less than top
The thickness of layer 3.Semiconductor substrate is doped injection, injects different types of according to PMOS, NMOS conduction type difference
Dopant ion.The peak value that dopant ion injects is positioned at below oxygen buried layer 2, such as the bottom surface 1～10nm of distance oxygen buried layer 2 so that
A part in bottom 1 has the doping content of higher n+ or p+, constitutes bottom injection region 1D and is beneficial to later serve as volume
Journey/erasing grid (or referred to as wordline).Meanwhile, during smaller part of dopant ion is also distributed about top layer 3 so that top layer 3 has
There is the doping content of relatively low n-or p-, be beneficial to be formed after a while source-drain area.On whole device by LPCVD, PECVD,
The conventional method sedimentary covers 4 such as HDPCVD, ALD, its material for example, silicon nitride or silicon oxynitride, it is used for constituting fin structure and carves
The hard mask of erosion and the barrier layer of subsequent etching.Photoetching anisotropically etching cap 4, top layer 3, oxygen buried layer 2 and the end
Layer injection region 1D, until exposing unadulterated bottom 1, forming the first direction along being parallel to bottom 1 surface on bottom 1 and extending
Multiple fin structure.The interface of etching stopping is such as positioned at oxygen buried layer 2 subjacent 10～20nm.As shown in Figure 1A, on top
In view, multiple fin structure extend along the first direction being parallel to substrate surface, and line AA ' is the edge through multiple fin structure
It is parallel to the hatching line of the second direction of substrate surface, using grid (floating boom) position as FinFET, wherein second
Direction is intersected with first direction, is optionally vertical.And it is following without the most contrary instruction, cuing open of all same tag
The locus of line is the most identical.Figure 1B is the sectional view that Figure 1A intercepts along hatching line AA ', and plurality of fin structure from top to bottom depends on
Secondary include cap rock 4, top layer 3, oxygen buried layer 2 and bottom injection region 1D.
With reference to Fig. 6 and Fig. 2 A to 2E, it is shown that according to step S2 of the method for the present invention, wherein in multiple fin structure
Side and end face form the gate insulator that extends in a first direction, and formed along first party in gate insulator both sides
To the grid conducting layer extended.By the conventional methods such as LPCVD, PECVD, HDPCVD, ALD fin structure (4/3/2/1A) with
And on bottom 1, deposit gate dielectric materials, and photoetching/etching, only stay in the first direction at fin structure top and side
The gate insulator 5 extended.The material of gate insulator 5 includes silicon oxide, silicon nitride, silicon oxynitride, high-g value and group thereof
Close.Wherein, high-g value includes selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、
HfLaSiOxHafnio material, or include selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or
It is to include Al2O3, with the composite bed of its above-mentioned material.Preferably, select high-g value as gate insulator 5, in order to be applicable to
Small size device, enabling use ultra-thin gate insulator to utilize F-N tunnel-effect to realize electricity as tunnel oxidation layer
Erasing.The thickness of gate insulator 5 for example, 1～10nm.Subsequently, on gate insulator 5 and bottom 1 by LPCVD,
The conventional method deposition grid conducting materials such as PECVD, HDPCVD, ALD, and photoetching/etching, only in the both sides of gate insulator 5
Substrate bottom 1 on leave the grid conducting layer 6 extended in a first direction, after a while will be through graphical for use as floating boom.Grid
The material of conductive layer 6 includes nitride of polysilicon, metal, the alloy of metal, metal and combinations thereof, wherein, metal include Al,
Ta, Ti and combinations thereof.The thickness of grid conducting layer 6 for example, 1～10nm.Fig. 2 A is top view, in its Vertical Centre Line AA ' and Figure 1A
Hatching line AA ' is identical；Hatching line BB ' is parallel to hatching line AA ' and the most in a second direction, but has certain distance with it, and its position is slightly
It is used as the source-drain area of device afterwards；Hatching line CC ' through fin structure and in the first direction, its position include channel region after a while with
And the bonding pad of program/erase grid；Hatching line DD ' does not passes through fin structure and in the first direction, for the space structure to device
Remark additionally.Fig. 2 B, Fig. 2 C are respectively Fig. 2 A AA ' along the line and the sectional view of line BB ', it is seen that gate insulator 5 is distributed in
The top of fin structure (4/3/2/1A) and side on substrate bottom 1；Grid conducting layer 6 is distributed in grid on substrate bottom 1
The both sides of insulating barrier 5, and its top is less than the top of gate insulator 5.Fig. 2 D is the sectional view of Fig. 2 A CC ' along the line, it is seen that
Gate insulator 5 is positioned at fin structure top, also extends in a first direction distribution.Fig. 2 E is the sectional view of Fig. 2 A DD ' along the line, can
See outside fin structure region, there is no gate insulator 5 and grid conducting layer 6 on substrate bottom 1.
With reference to Fig. 6 and Fig. 3 A to Fig. 3 E, it is shown that according to step S3 of the method for the present invention, shape the most in a second direction
Become mask and etch removal part of grid pole insulating barrier and grid conducting layer, only at the gate insulator of mask overlay area member-retaining portion
Layer and grid conducting layer.By conventional method deposition the first hard masks such as LPCVD, PECVD, HDPCVD, ALD on whole device
Material, its material for example, silicon oxide, silicon nitride, silicon oxynitride.Photoetching/etching hard mask material is formed and extends in a second direction
Multiple first hard mask pattern 7 of distribution, the hard mask pattern of at least one of which first 7 is through hatching line AA ' with reservation below
Gate insulator 5 and grid conducting layer 6, as insulating barrier and the floating boom of both sides, device channel region.Then with the first hard mask
Pattern 7 as mask, anisotropically etching grid conductive layer 6 so that only retain be positioned at the grid below the first hard mask pattern 7
Pole conductive layer 6, as floating boom.Fig. 3 A is top view, it is seen that the first hard mask pattern 7 extends in a second direction, and at least across
Hatching line AA '.Fig. 3 B, Fig. 3 C are Fig. 3 A AA ' along the line, the sectional view of BB ' respectively, it is seen that do not covered by the first hard mask pattern 7
On region, grid conducting layer 6 is removed.Fig. 3 D, Fig. 3 E are Fig. 3 A CC ' along the line, the sectional view of DD ' respectively, and wherein AA ' line passes
Region in top layer 3 part constituting channel district 3C, remaining top layer 3 part then constitutes source-drain area 3S/3D, will act as device future
The control part (or referred to as bit line) of part.
With reference to Fig. 6 and Fig. 4 A to Fig. 4 F, it is shown that according to step S4 of the method for the present invention, wherein etching is formed and controls
Grid contact hole.Whole device deposits the second hard mask layer 8 by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, its
Material for example, silicon oxide, silicon nitride or silicon oxynitride, the preferably second hard mask layer 8 and the material of the first hard mask layer/pattern 7
Expect identical.Then the techniques such as CMP are used to planarize the second hard mask layer 8 until exposing gate insulator 5.Then photoetching/etching
Second hard mask layer 8 of part, gate insulator 5, cap rock 4, top layer 3, oxygen buried layer 2, until exposing bottom injection region 1D, are formed
Multiple program/erase grid contact hole 8H.Fig. 4 A is top view, and its Vertical Centre Line EE ' is through program/erase grid contact hole 8H place
Position and in a second direction, program/erase grid contact hole 8H extends in a first direction.Fig. 4 B, Fig. 4 C are that Fig. 4 A is along the line respectively
AA ', the sectional view of BB ', similar with Fig. 3 B, 3C, it is seen that on the region not covered by the former first hard mask pattern 7, grid is led
Electric layer 6 is removed, and the second hard mask layer 8 top flushes with gate insulator 5 top.Fig. 4 D is the section view of Fig. 4 A CC ' along the line
Figure, it is seen that program/erase grid contact hole 8H goes directly bottom injection region 1D, so that the end of the doping as program/erase grid
Layer injection region 1D energy and external electrical connections.Fig. 4 E is the sectional view of Fig. 4 A DD ' along the line.Fig. 4 F is Fig. 4 A section view along hatching line EE '
Figure, it is seen that in program/erase grid contact hole 8H, the top of gate insulator 5 and a part for sidepiece are removed, and only protect
Stay the part in 1D both sides, bottom injection region.
With reference to Fig. 6 and Fig. 5 A to Fig. 5 F, it is shown that according to step S5 of the method for the present invention, wherein form source and drain contact
And the contact of program/erase grid.By conventional method deposition interlayers such as LPCVD, PECVD, HDPCVD, ALD on whole device
Dielectric layer 9, its material for example, silicon oxide, silicon nitride or silicon oxynitride, preferably with the first hard mask layer/pattern 7 and/or
The material of two hard mask layers 8 is identical.Photoetching/etching interlayer dielectric layer 9, in the position formation source corresponding with source-drain area 3S/3D
Miss contact hole 9SD, and form program/erase grid contact hole 9P in the position corresponding with program/erase grid contact hole 8H.Then exist
Each contact hole forms metal silicide 10 to reduce contact resistance.The material of metal silicide 10 includes NiSi2-y、
PtSi2-y、CoSi2-y、Ni1-xPtxSi2-y、Ni1-xCoxSi2-y、Pt1-xCoxSi2-y、Ni2-x-zPtxCozSi3-y, wherein x, z are more than 0
Less than 1, y is less than or equal to 1 more than or equal to 0.Then in each contact hole, fill conductive material 11 form contact plug and connection
Line, conductive material 11 for example, W, Cu, Al, Ti, Ta and combinations thereof.Fig. 5 A is top view, wherein AA ' line through channel region and
The gate insulator of channel region both sides and grid conducting layer, BB ' passes source-drain area and the gate insulator of source-drain area both sides,
CC ' passes source-drain area, channel region, program/erase grid contact hole, and DD ' extends only through substrate bottom 1, EE ' through substrate injection region
1D.Fig. 5 B is Fig. 5 A sectional view along AA ', it is seen that have gate insulator 5, gate insulator 5 both sides in channel region 3C both sides
There is grid conducting layer 6 (floating boom).Fig. 5 C is Fig. 5 A sectional view along BB ', it is seen that source and drain connecting line 11SD is (as device cell
Bit line) electrically connected with source-drain area 3S/3D by metal silicide 10, source-drain area both sides only gate insulator 5 and there is no grid
Pole conductive layer 6.Fig. 5 D, Fig. 5 E are respectively Fig. 5 A along CC ', the sectional view of EE ', it is seen that program/erase grid connecting line 11C (as
The wordline of device cell) electrically connected with substrate injection region 1D by metal silicide 10, and 1D both sides, substrate injection region have
The gate insulator 5 of part.Fig. 5 E is Fig. 5 A sectional view along DD '.
The multiple programmable semiconductor device that finally gives, as shown in Fig. 5 A to Fig. 5 F, including multiple fin structure, is positioned at
On substrate, including substrate injection region 1D, oxygen buried layer 2, top layer 3 and cap rock 4 alternatively, multiple fin structure are along being parallel to substrate
The first direction on surface extends distribution；Channel region 3C, is positioned in the top layer 3 of multiple fin structure；Source-drain area 3S/3D, is positioned at many
Channel region 3C two ends in the top layer 3 of individual fin structure；Gate insulator 5, is positioned at top and the sidepiece of channel region 3C, along parallel
Second direction in substrate surface extends distribution, and second direction intersects with first direction and the most vertical；Floating boom 6, is positioned at fin
Both sides in the second direction of shape structure, contact with gate insulator 5；Program/erase grid, are made up of substrate injection region 1D, position
Below channel region 3C；Interlayer dielectric layer 9, covers multiple fin structure, gate insulator and floating boom；Source and drain contact hole 9SD
It is formed in interlayer dielectric layer 9 with program/erase grid contact hole 9P, distinguishes source of exposure drain region 3S/3D and as program/erase
The substrate injection region 1D of grid；Metal silicide 10, is formed in source and drain contact hole 9SD and program/erase grid contact hole 9P；Connect
Line 11, is electrically connected by the metal silicide 10 substrate injection region 1D with source-drain area 3S/3D and as program/erase grid, its
Middle source-drain area connecting line 11SD extends distribution in a second direction.
The concrete material of above-mentioned all parts and geometrical structure parameter describe in detail in each step of manufacture method, this
Outward, subsequent manufacturing procedures, the such as connection of wordline, bit line, manufacture of selection circuit etc., these the most widely technical staff institute ripe
Know, the most also repeat no more.
According to the multiple programmable semiconductor device of the present invention, utilize substrate injection region to form the programming/wiping of FinFET
Except grid, simplify device architecture, and reduce manufacturing process, improve the integration density of device, it is adaptable to multiple programmable is deposited
Reservoir.
Although with reference to one or more exemplary embodiments illustrate the present invention, those skilled in the art could be aware that without
Depart from the scope of the invention and device architecture is made various suitable change and equivalents.Additionally, can by disclosed teaching
Make many and can be adapted to the amendment of particular condition or material without deviating from the scope of the invention.Therefore, the purpose of the present invention does not exists
In being limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture
And manufacture method will include all embodiments fallen within the scope of the present invention.
Claims (20)
1. can a repeatedly programming semiconductor device, including:
Multiple fin structure, are positioned on substrate and extend distribution along the first direction being parallel to substrate surface, injecting including substrate
District, oxygen buried layer, top layer；
Channel region, is positioned in the top layer of multiple fin structure；
Source-drain area, is positioned at channel region two ends in the top layer of multiple fin structure；
Gate insulator, is positioned at top and the sidepiece of channel region, extends distribution along the second direction being parallel to substrate surface；
Floating boom, is positioned at the both sides in the second direction of multiple fin structure；
Program/erase grid, are made up of substrate injection region, are positioned at below oxygen buried layer.
The most as claimed in claim 1 can repeatedly programming semiconductor device, farther include:
Interlayer dielectric layer, covers multiple fin structure, gate insulator, floating boom；
Source and drain contact hole and control gate contact hole, be formed in interlayer dielectric layer, respectively source of exposure drain region and conduct programming/wiping
Substrate injection region except grid；
Metal silicide, is formed in source and drain contact hole and program/erase grid contact hole；
Connecting line, is electrically connected by the metal silicide substrate injection region with source-drain area and as program/erase grid.
3. as claim 1 can repeatedly programming semiconductor device, wherein, multiple fin structure also include the lid being positioned on top layer
Layer.
The most as claimed in claim 1 can repeatedly programming semiconductor device, wherein, gate insulator includes silicon oxide, silicon nitride, nitrogen oxygen
SiClx, high-g value and combinations thereof.
The most as claimed in claim 4 can repeatedly programming semiconductor device, wherein, high-g value includes selected from HfO2、HfSiOx、
HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnio material, or include selected from ZrO2、La2O3、
LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or include Al2O3, or the composite bed of above-mentioned material.
The most as claimed in claim 1 can repeatedly programming semiconductor device, wherein, floating boom includes polysilicon, metal, the conjunction of described metal
Nitride of metal golden, described and combinations thereof.
The most as claimed in claim 6 can repeatedly programming semiconductor device, wherein, described metal includes Al, Ta, Ti and combinations thereof.
The most as claimed in claim 2 can repeatedly programming semiconductor device, wherein, the material of metal silicide includes NiSi2-y、
PtSi2-y、CoSi2-y、Ni1-xPtxSi2-y、Ni1-xCoxSi2-y、Pt1-xCoxSi2-y、Ni2-x-zPtxCozSi3-y, wherein x, z are more than 0
Less than 1, y is less than or equal to 1 more than or equal to 0.
The most as claimed in claim 2 can repeatedly programming semiconductor device, wherein, the material of connecting line include W, Cu, Al, Ti, Ta and
A combination thereof.
10. can a repeatedly programming semiconductor device making method, including step:
Substrate is formed the multiple fin structure extending distribution along the first direction being parallel to substrate surface, injects including substrate
District, oxygen buried layer, top layer；
Gate insulator is formed at multiple fin structure tops and both sides；
Grid conducting layer is formed in gate insulator both sides；
Photoetching/etching grid conductive layer, the only grid conducting layer of the channel region both sides member-retaining portion in being positioned at top layer, as floating
Grid；
Photoetching/etch multiple fin structure, the substrate injection region of expose portion；
Formation source and drain contacts, and forms the program/erase grid contact of the substrate injection region being connected to exposure.
11. such as claim 10 can repeatedly programming semiconductor device making method, wherein, form the step of multiple fin structure
Farther include: the substrate including bottom, oxygen buried layer and top layer is doped injection, the bottom below oxygen buried layer is formed
Substrate injection region, constitutes program/erase grid；Photoetching/etched substrate, until exposing unadulterated bottom, is formed along being parallel to lining
The first direction of basal surface extends multiple fin structure of distribution.
12. such as claim 10 can repeatedly programming semiconductor device making method, wherein, photoetching/etching grid conductive layer
Step farther includes: forms the second direction along being parallel to substrate surface on substrate, grid conducting layer, gate insulator and prolongs
The hard mask pattern that extending portion is divided；With hard mask pattern as mask, etching grid conductive layer, only stay and covered by hard mask pattern
Part of grid pole conductive layer, wherein the top layer constituting channel district below hard mask pattern, the top layer at channel region two ends constitutes source-drain area.
13. such as claim 10 can repeatedly programming semiconductor device making method, wherein, the substrate injection region of expose portion
Step farther includes: form hard mask layer on whole device；Planarization is until exposing gate insulator；Photoetching/etching portion
Point gate insulator, top layer, oxygen buried layer, until expose substrate injection region, formed program/erase grid contact hole, wherein programming/
Erasing grid contact hole is positioned at one end of source-drain area on first direction.
14. such as claim 10 can repeatedly programming semiconductor device making method, wherein, form source and drain contact and the company of being formed
The step of the program/erase grid contact hole receiving the substrate injection region of exposure farther includes: form interlayer on whole device
Dielectric layer；Photoetching/etching forms source and drain contact hole, and is connected to the program/erase grid contact hole of the substrate injection region exposed；
Metal silicide is formed in source and drain contact hole and program/erase grid contact hole；Contact with program/erase grid at source and drain contact hole
Hole is filled conductive material, forms connecting line.
15. such as claim 10 can repeatedly programming semiconductor device making method, wherein, gate insulator include silicon oxide,
Silicon nitride, silicon oxynitride, high-g value and combinations thereof.
16. such as claim 10 can repeatedly programming semiconductor device making method, wherein, high-g value includes selected from HfO2、
HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnio material, or include being selected from
ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare earth base high K dielectric material, or include Al2O3, or above-mentioned material is compound
Layer.
17. such as claim 16 can repeatedly programming semiconductor device making method, wherein, floating boom includes polysilicon, metal, institute
State nitride of the alloy of metal, described metal and combinations thereof.
18. such as claim 17 can repeatedly programming semiconductor device making method, wherein, described metal include Al, Ta, Ti and
A combination thereof.
19. such as claim 14 can repeatedly programming semiconductor device making method, wherein, the material of metal silicide includes
NiSi2-y、PtSi2-y、CoSi2-y、Ni1-xPtxSi2-y、Ni1-xCoxSi2-y、Pt1-xCoxSi2-y、Ni2-x-zPtxCozSi3-y, wherein
X, z are more than 0 less than 1, and y is less than or equal to 1 more than or equal to 0.
20. such as claim 14 can repeatedly programming semiconductor device making method, wherein, the material of connecting line include W, Cu,
Al, Ti, Ta and combinations thereof.
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| CN201210326597.XA CN103681800B (en) | 2012-09-05 | 2012-09-05 | Multi-time programmable semiconductor device and manufacturing method thereof |
| PCT/CN2012/001536 WO2014036676A1 (en) | 2012-09-05 | 2012-11-13 | Multiple time programmable semiconductor device and manufacturing method thereof |
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| CN201210326597.XA CN103681800B (en) | 2012-09-05 | 2012-09-05 | Multi-time programmable semiconductor device and manufacturing method thereof |
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| CN104375429B (en) * | 2014-11-27 | 2017-02-22 | 无锡中感微电子股份有限公司 | Programming control circuit for programmable chip |
| TWI677077B (en) * | 2016-07-06 | 2019-11-11 | 聯華電子股份有限公司 | Non-volatile memory device and manufacturing method thereof |
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| US7091551B1 (en) * | 2005-04-13 | 2006-08-15 | International Business Machines Corporation | Four-bit FinFET NVRAM memory device |
| CN101093838A (en) * | 2006-06-23 | 2007-12-26 | 三星电子株式会社 | Non-volatile memory device and methods for operating same |
| CN101159270A (en) * | 2006-10-03 | 2008-04-09 | 旺宏电子股份有限公司 | Method of performing an operation on a flash memory cell device |
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| US8872247B2 (en) * | 2009-11-04 | 2014-10-28 | Micron Technology, Inc. | Memory cells having a folded digit line architecture |
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| US7091551B1 (en) * | 2005-04-13 | 2006-08-15 | International Business Machines Corporation | Four-bit FinFET NVRAM memory device |
| CN101093838A (en) * | 2006-06-23 | 2007-12-26 | 三星电子株式会社 | Non-volatile memory device and methods for operating same |
| CN101159270A (en) * | 2006-10-03 | 2008-04-09 | 旺宏电子股份有限公司 | Method of performing an operation on a flash memory cell device |
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