KR20110075398A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE: A non-volatile memory device is provided to improve an information removal characteristic by forming an oxide thin film transistor on one side thereof. CONSTITUTION: An active area(13) is formed on an area of a substrate(10) and includes an n-type or a p-type material. A source area(14) is formed at one side of the active area and is formed with a material which is different from an other type of the active area. A tunneling layer, an information store layer, a blocking layer, and a gate are sequentially formed on the active area. A second electrode is electrically connected a first electrode and the active area which are formed on the source area.

Description

Nonvolatile Memory Device

The disclosed embodiment relates to a nonvolatile memory device, and to a nonvolatile memory device having improved electrical characteristics by forming active and source regions of different types of materials.

The performance of semiconductor memory devices has been developed with a focus on increasing information storage capacity and the speed of writing and erasing the information. The conventional semiconductor memory array structure includes a large number of circuit-connected memory unit cells and volatile memory such as nonvolatile memory (DNA) and dynamic random access memory (DRAM), in which information remains intact even when the power is cut off. It is divided into Volatile Memory.

Various types of memory devices have been introduced as nonvolatile memories. For example, in order to use magnetoresistance characteristics, a semiconductor memory device in which a Giant Magneto-Resistance (GMR) or Tunneling Magneto-Resistance (TMR) structure is formed on a transistor is introduced. In addition, new structures such as Phase-Change Random Access Memory (PRAM), which utilizes phase transition material characteristics, and Sonos, which have a tunneling oxide layer, a charge storage layer, and a blocking oxide layer, are non-volatile. volatile) semiconductor memory devices have emerged.

Recently, studies on various devices using oxide thin film transistors have been conducted. This is due to various advantages of oxide thin film transistors compared to conventional Si technology, for example, stacking is possible. In addition, it is possible to implement a flexible and flexible device. However, when the oxide thin film transistor is applied to a memory device, there is a problem in its utilization due to the problem of the information erasing process.

In one aspect of the present invention, a nonvolatile memory device including an oxide thin film transistor is provided.

In another aspect of the present invention, a nonvolatile memory device including an oxide thin film transistor having improved information erasing characteristics is provided.

The disclosed embodiment includes an active region formed in one region on a substrate and including an n-type or p-type material;

A source region formed on one side of the active region and formed of a material different from the active region;

A tunneling layer, an information storage layer, a blocking layer, and a gate sequentially formed on the active region; And

It provides a non-volatile memory device comprising a first electrode formed on the source region and a second electrode electrically connected to the active region.

It may further include an oxide layer formed on the surface of the substrate.

The active region is formed of an n-type oxide, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag It may be formed by including at least one material selected from oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide or Ta oxide.

The active region may be formed of a p-type material, and may include at least one material selected from Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, or pentacene. .

The active region may be formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs or InGaAs.

The source region is formed of an n-type material, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag It may be formed by including at least one material of oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide or Ta oxide.

The source region is formed of a p-type material, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, DyCu oxide, It may be formed by including at least one material of ZnCu oxide or SrCu oxide.

The source region may be formed by doping an n-type dopant or a p-type dopant to at least one of SiC, GaN, GaAs, or InGaAs.

And a drain region formed between the active region and the second electrode and formed of a material of another type different from the active region.

In addition, the gate formed in one region on the substrate;

A tunneling layer, an information storage layer, and a blocking layer sequentially formed on the gate;

An active region formed on the blocking layer and including an n-type or p-type material;

A source region formed on one side of the active region and formed of a material different from the active region; And

It provides a non-volatile memory device comprising a first electrode formed on the source region and a second electrode electrically connected to the active region.

According to an embodiment of the present invention, the source region or the source region and the drain region are formed of a different type of material from the active region to improve electron tunneling and hole tunneling characteristics, thereby reducing temperature dependency when erasing information and improving information erasing characteristics. You can.

Hereinafter, a nonvolatile memory device according to an embodiment will be described in detail with reference to the accompanying drawings. For reference, the same reference numerals in the drawings refer to the same components, the size or thickness of each component may be exaggerated for clarity of description.

1 and 2 illustrate a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, an active region 13 is formed in one region on the substrate 10 and includes a source region 14 formed on one side of the active region 13. An insulating layer 12 may be formed on both sides of the active region 13 and the source region 14. The first electrode 15a is formed on the source region 14, and the second electrode 15b electrically connected to the active region 13 is formed in one region of the active region 13. The tunneling layer 16a, the information storage layer 16b, and the blocking layer 16c are sequentially formed on the active region 13 between the first electrode 15a and the second electrode 15b. Here, both sides of the information storage layer 16b have a structure buried between the tunneling layer 16a and the blocking layer 16c so as not to contact the first electrode 15a and the second electrode 15b. The gate 17 is formed on the blocking layer 16c. Optionally, an oxide layer 11 may be further formed on the surface of the substrate 10.

2 illustrates a structure in which source and drain regions 14a and 14b are formed on both sides of the active region 13. Referring to FIG. 2, the active region 13 is formed in one region on the substrate 10, and the source region 14a and the drain region 14b are formed at both sides of the active region 13. In addition, an insulating layer 12 may be formed on side portions of the source region 14a and the drain region 14b. The first electrode 15a is formed on the source region 14a, and the second electrode 15b is formed on the drain region 14b. The tunneling layer 16a, the information storage layer 16b, and the blocking layer 16c are sequentially formed on the active region 13 between the first electrode 15a and the second electrode 15b, and the information storage layer ( Both sides of the 16b have a structure buried between the tunneling layer 16a and the blocking layer 16c so as not to contact the first electrode 15a and the second electrode 15b. The gate 17 is formed on the blocking layer 16c. In addition, an oxide layer 11 may be further formed on the surface of the substrate 10.

Hereinafter, materials for forming each layer of the nonvolatile memory device illustrated in FIGS. 1 and 2 will be described. The substrate 10 may be formed of a substrate material commonly used in a semiconductor device, and may be formed of, for example, Si, Ge, C, SiC, GaN, GaAs, InGaAs, glass, or an organic material. The oxide layer 11 is selectively formed on the surface of the substrate 10 and may be, for example, SiO ₂ formed by thermal oxidation on the surface of the Si substrate. The insulating layer 12 is formed of an insulating material, and may be formed of Si oxide, Si nitride, Al oxide, Hf oxide, or the like.

The active region 13 may be formed using an n-type or p-type material. For example, it may be formed of a semiconductor oxide, specifically n-type semiconductor oxide, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxides, Nb oxides, Ag oxides, Ge oxides, Na oxides, Ln oxides, Al oxides, W oxides or Ta oxides and the like can be selectively used, a composite material thereof can be used. As the p-type semiconductor oxide, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, or SrCu oxide may be used, and a single material or a composite material thereof may be used. It is also possible to use organic polymer materials such as pentacene. In addition, an n-type dopant or a p-type dopant may be doped into a material such as SiC, GaN, GaAs, or InGaAs.

In the nonvolatile memory device according to an exemplary embodiment of the present invention, the source regions 14 and 14a and the drain region 14b may be formed of a different type of material from the active region 13. Here, the other type is, for example, when the active region 13 is formed of an n-type material, the source region 14, 14a and the drain region 14b are formed of a p-type material, and the active region 13 ) Is formed of a p-type material, it means that the source region (14, 14a) and drain region (14b) is formed of an n-type material.

For example, as the n-type oxide semiconductor, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag oxide , Ge oxides, Na oxides, Ln oxides, Al oxides, W oxides, or Ta oxides, and the like, or a single material or a composite material thereof may be used. As the p-type oxide semiconductor, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, DyCu oxide, ZnCu oxide or SrCu oxide and the like, and a single material or a composite material thereof can be used. In addition, an n-type dopant or a p-type dopant may be doped into a material such as SiC, GaN, GaAs, or InGaAs.

The tunneling layer 16a and the blocking layer 16c may be formed of an insulating material. Specifically, for example, Si and an n-type dopant or a p-type dopant may be doped in these materials. At least one of Si oxide, Si nitride, Al oxide, Hf oxide, Mg oxide, Sr oxide, Ba oxide, Ti oxide, Ta oxide, BaTi oxide BaZr oxide, Zr oxide, Y oxide, ZrSi oxide, HfSi oxide or LaAl oxide It may be formed to include.

The charge storage layer 16b is formed of a material capable of storing charge, and is formed of Si nitride, SiON, SiO _x , GeON, GeN, GeO poly-Silicon metal nitride, metal boron nitride, metal silicon nitride, metal aluminum nitride, or metal silicide. It may be formed including at least one.

The gate 17 is formed of a conductive material and is formed of a metal such as Au, Ag, Al, Ta, Ni, Ir, Pt, W, Nb, Ti, Mo, Ru, Zr, or Hf, or ITO, IZO (InZnO), or AZO ( AlZnO), or a conductive metal oxide.

The material of each layer as described above may also be used for the layers of the same name in FIGS. 3 to 6.

Hereinafter, the reason why the source 14, 14a and the drain 14b are formed of a different type of material from the active region 13 will be described.

The nonvolatile memory device according to the embodiment of the present invention records information in the information storage layer 16b by using a Fowler-Nordheim (FN) method and erases the information.

First, in order to record information, when a predetermined positive voltage is applied to the gate 17, an electric field is formed between the gate 17 and the active region 13, and an FN current across the tunneling layer 16a is generated. . The electrons traveling through the active region 13 between the source regions 14 and 14a and the drain region 14b by the FN current are stored in the information storage layer 16b by tunneling an energy barrier of the tunneling layer 16a. . Electrons e once stored in the information storage layer 16b are blocked by the energy barrier of the blocking layer 16c and trapped in the information storage layer 16b so that information is recorded.

The process of erasing the information will be described with reference to FIG. 7A. 7A illustrates an energy band gap in an information erasing process of a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 7A, the conduction band energy Ec and the balance band energy Ev of the tunneling layer Tu, the information storage layer Tr, and the blocking layer Bl are illustrated. In the case of erasing information, a predetermined negative voltage is applied to the gate 17 to form an electric field in the direction opposite to that of information recording. As a result, the FN current is generated in the opposite direction to the recording time, and the electrons are tunneled from the information storage layers 16b and Tr to the tunneling layers 16a and Tu by the FN current and moved toward the substrate 10 to erase the information. do. At this time, as a method of erasing electrons in the information storage layer 16b and Tu, as described above, electrons in the information storage layer 16b and Tu can be tunneled through the tunneling layer 16a and Tu, The electrons can be neutralized by tunneling to the information storage layer 16b and Tu, and the information erasing efficiency is greatly improved when electron and hole tunneling occurs at the same time.

7B and 7C show the change in the threshold voltage over time when the tunneling of the hole does not occur during information erasure, and shows data measured at 85 degrees Celsius and -10 degrees Celsius. 7B and 7C, when tunneling of holes to the information storage layers 16b and Tu occurs during information erasing, deviations according to temperature are not shown very much (FIG. 7C). By the way, when the tunneling of the hole does not occur, it can be seen that a large deviation occurs depending on the temperature (FIG. 7B).

This is especially true in the case where a material having a large energy band gap (Eg> 1.5 eV), for example, an oxide semiconductor-based material is used in the active region, the hole tunneling height is the electron barrier height. Can be caused because hole tunneling may not occur in situations where there is insufficient energy supply. Accordingly, hole tunneling may not occur when erasing information, and in particular, degradation of information erasure may occur while showing dependence on temperature. As a result, in the embodiment of the present invention, the source region or the source region and the drain region are formed of a material different from the active region, thereby improving electron tunneling and hole tunneling characteristics, thereby reducing temperature dependency when erasing information and improving information erasing characteristics. You can. The source region 14a and the drain region 14b may be formed in a different type from the active region 13. In particular, a junction that affects the threshold voltage (V _th ) of the transistor may be formed in the source region. Therefore, as shown in FIG. 1, only the source region 14 may be formed of a material different from that of the active region 13.

Referring to the manufacturing process of the nonvolatile memory device according to the embodiment of the present invention as follows.

1 and 2, an oxide layer 11 is selectively formed on the substrate 10. In this case, the oxide layer may be a SiO ₂ layer formed on the surface of the Si substrate by a thermal oxidation process. The active region 13, the source region 14, and the like are formed on the oxide layer 12. In this case, the active region 13 and the source region 14 may be formed in separate processes, and may be simultaneously formed by forming and doping one material layer. For example, an n-type oxide semiconductor such as Zn oxide is coated on the oxide layer 11 to form an active region 13, and a p-type dopant is doped on one or both sides of the source region 14, 14a and And / or the drain region 14b may be formed. After the tunneling layer 16a, the information storage layer 16b, and the blocking layer 16c are formed on the active region 13, the gate 17 may be formed on the blocking layer 16c. Next, the first electrode 15a may be formed by exposing the source regions 14 and 14a, and the second electrode 15b may be formed by exposing the active region 13 or the drain region 14b.

The structure of the nonvolatile memory device of FIGS. 1 and 2 may be modified in various forms. For example, as shown in FIGS. 3 and 4, the information storage layer 26b may be formed in a modified structure in order to enlarge an area. In addition, although the top gate structure is disclosed in FIGS. 1 and 2, the present invention is not limited thereto, and the top gate structure may be formed as shown in FIGS. 5 and 6.

3 and 4, the active region 23 is formed in one region on the substrate 20, and the insulating layer 22 is formed on both side surfaces of the active region 23. The tunneling layer 26a, the information storage layer 26b, and the blocking layer 26c are sequentially formed on the active region 23. The source region 24 and the first electrode 25a are formed on the insulating layer 22 on one side of the active region 23, and the second electrode (on the insulating layer 22 on the other side of the active region 23). 25b) may be formed, and optionally, the drain region 24b and the second electrode 25b may be sequentially formed. In this case, the source region 24 or the source and drain regions 24a and 24b may be in direct contact with the active region 23. Here, both sides of the information storage layer 26b have a structure buried between the tunneling layer 26a and the blocking layer 26c so as not to contact the first electrode 25a and the second electrode 25b. Optionally, an oxide layer 21 may be formed on the surface of the substrate 20.

For reference, FIGS. 3 and 4 disclose a configuration in which insulating layers 22 are formed at both sides of the active region 23, and source regions 24 or source and drain regions 24a and 24b are formed thereon. However, the insulating layer 22 may be formed such that the source region 24 or the source and drain regions 24a and 24b extend.

5 and 6 illustrate a nonvolatile memory device having a bottom gate structure.

5 and 6, the gate 32 is formed in one region on the substrate 30, and the tunneling layer 33a, the information storage layer 33b, and the blocking layer are formed on the substrate 30 and the gate 32. 33c is formed sequentially. Here, the information storage layer 33b may have a structure buried between the tunneling layer 33a and the blocking layer 33c. The active region 34 is formed on the blocking layer 33c. A source region 35 may be formed on one side of the active region 34, and a first electrode 36a may be formed on the source region 35. In addition, a second electrode 36b electrically connected to the active region 34 may be formed at the other side of the active region 34. A drain region 34b may be formed between the active region 34 and the second electrode 36b. Specifically, a source region 35a and a first electrode 36a are formed on one side of the active region 34. The drain region 35b and the second electrode 36b may be formed on the other side of the active region 34.

Although embodiments of the present invention have been described above, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

1 and 2 illustrate a nonvolatile memory device according to an embodiment of the present invention.

3 and 4 are diagrams illustrating modified examples in which an area of the information storage layer of FIGS. 1 and 2 is enlarged.

5 and 6 illustrate a top gate structure of a nonvolatile memory device according to an exemplary embodiment of the present invention.

7A illustrates an energy band gap in an information erasing process of a nonvolatile memory device according to an embodiment of the present invention.

7B and 7C are graphs illustrating changes in threshold voltages over time when tunneling of holes does not occur when information is erased.

<Description of Symbols for Main Parts of Drawings>

10, 20, 30 ... substrate 11, 21, 31 ... oxide layer

12, 22 ... insulation layer 13, 23, 34 ... active area

14, 14a, 24, 24a, 35, 35a ... source area

14b, 24b, 35b ... drain region 15a, 25a, 36a ... first electrode

15b, 25b, 36b ... second electrode 16a, 26b, 33a ... tunneling layer

16b, 26b, 33b ... information storage layer 16c, 26c, 33c ... blocking layer

17, 27, 32 ... gate

Claims (18)

An active region formed in one region on the substrate and including an n-type or p-type material; A source region formed on one side of the active region and formed of a material different from the active region; A tunneling layer, an information storage layer, a blocking layer, and a gate sequentially formed on the active region; And And a first electrode formed on the source region and a second electrode electrically connected to the active region. The method of claim 1, Non-volatile memory device comprising an oxide layer formed on the surface of the substrate. The method of claim 1, The active region is formed of an n-type oxide, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag A nonvolatile memory device including at least one material selected from oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide or Ta oxide. The method of claim 1, The active region is formed of a p-type material, and includes a nonvolatile memory formed of at least one material selected from Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, or pentacene. device. The method of claim 1, The active region is formed by doping an n-type dopant or a p-type dopant in at least one of SiC, GaN, GaAs or InGaAs material. The method of claim 1, The source region is formed of an n-type material, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag A nonvolatile memory device including at least one of oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide, or Ta oxide. The method of claim 1, The source region is formed of a p-type material, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, DyCu oxide, A nonvolatile memory device including at least one of ZnCu oxide and SrCu oxide. The method of claim 1, And the source region is formed by doping an n-type dopant or a p-type dopant in at least one of SiC, GaN, GaAs or InGaAs. The method of claim 1, And a drain region formed between the active region and the second electrode and formed of a material of a different type from the active region. A gate formed in one region on the substrate; A tunneling layer, an information storage layer, and a blocking layer sequentially formed on the gate; An active region formed on the blocking layer and including an n-type or p-type material; A source region formed on one side of the active region and formed of a material different from the active region; And And a first electrode formed on the source region and a second electrode electrically connected to the active region. The method of claim 10, Non-volatile memory device comprising an oxide layer formed on the surface of the substrate. The method of claim 10, The active region is formed of an n-type oxide, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag A nonvolatile memory device including at least one material selected from oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide or Ta oxide. The method of claim 10, The active region is formed of a p-type material, and includes a nonvolatile memory formed of at least one material selected from Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, ZnMn oxide, SrDy oxide, SrCu oxide, or pentacene. device. The method of claim 10, The active region is formed by doping an n-type dopant or a p-type dopant in at least one of SiC, GaN, GaAs or InGaAs material. The method of claim 10, The source region is formed of an n-type material, Zn oxide, Sn oxide, In oxide, Ga oxide, Ti oxide, Zr oxide, Hf oxide, Sr oxide, Cd, Sc oxide, Mn oxide, Mo oxide, Nb oxide, Ag A nonvolatile memory device including at least one of oxide, Ge oxide, Na oxide, Ln oxide, Al oxide, W oxide, or Ta oxide. The method of claim 10, The source region is formed of a p-type material, Cu oxide, CuAl oxide, CuGa oxide, Sn oxide, InSn oxide, Zn oxide, ZnMn oxide, SrDy oxide, SrSm oxide, SrGd oxide, GdCu oxide, SmCu oxide, DyCu oxide, A nonvolatile memory device including at least one of ZnCu oxide and SrCu oxide. The method of claim 10, And the source region is formed by doping an n-type dopant or a p-type dopant in at least one of SiC, GaN, GaAs or InGaAs. The method of claim 10, And a drain region formed between the active region and the second electrode, the drain region being formed of a material different from the active region.

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