JP2001313342A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reliable semiconductor device that can be easily manufactured. SOLUTION: On a p-type silicon substrate 1011, a fine particle diffusion region 1012, an SiO2 film 1015 functioning as an insulating film, and an n-type polycrystalline silicon electrode 1016 functioning as an upper electrode are provided in the order of lower part. Also in a charge retention region 1012, a silicon fine particle 1013 is diffused in the SiO2 film 1014 functioning as an insulator. In this manner, in the semiconductor device, by having the fine particle diffusion region 1012 where the silicon fine particle 1013 is diffused in the SiO2 film 1014 provided, the need for controlling the thickness of a tunnel oxide film and particle diameter of a particle body is eliminated as in a conventional semiconductor device, effectively inhibiting the spontaneous emission of accumulated electrons, and hence achieving a new semiconductor device of high reliability that can be manufactured easily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which electric charges are retained in fine particles or the like so that the semiconductor device can be used as a memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art A current ULSI has a memory section in which memory elements composed of a large number of MOS transistors are integrated. In recent years, there has been an increasing demand for faster operation, lower power consumption, and longer-time record retention in this memory element. Therefore, development of a MOS transistor that satisfies these requirements is being promoted.

In a memory element proposed so far and already manufactured as a trial, a very small number of electric charges are injected and held in fine particles such as a semiconductor when writing or erasing a memory. ing. An example of such a conventional technique is the study of a memory using a plurality of silicon fine particles (dots) by S. Tiwari et al. (Appl. Phys. Lett. 68 (1996) 1377).

[0004] FIG. 57 is a view showing the fineness of the conventional plurality of silicon.
A semiconductor memory device that functions as a memory using particles
FIG. In this semiconductor memory device,
SiO on a p-type silicon substrate 6201_Two Tons of membrane
Flannel oxide film 6202, SiO _Two The film 6204 is in order from the bottom
Deposited on top of n-type polysilicon
An electrode 6205 is provided. Tunnel oxide film 620
2 and SiO_Two Between the film 6204 and the silicon fine particles 6
203 is embedded. Also, a p-type silicon
N-type polycrystalline silicon electrode 6205 in control substrate 6201
The source / drain regions 6 are located on both sides of the
206 is provided.

In this semiconductor memory device, by applying a positive voltage to n-type polycrystalline silicon electrode 6205, silicon fine particles 6 pass through tunnel oxide film 6202.
Electrons can be injected into 203. When a negative voltage is applied to the n-type polycrystalline silicon electrode 6205, electrons in the silicon fine particles 6203 can be extracted. The threshold voltage of the memory element can be changed depending on the presence or absence of the electrons in the silicon microparticles 6203. The level of this threshold voltage is expressed as information H (high).
The information is written and read by associating with the information L (low).

Since the thickness of the tunnel oxide film 6202 is extremely small (about 1.5 to 4 nm), the electron injection process is not performed by the FN tunnel but by the direct tunnel.

[0007]

However, according to the study of the present inventors, in order to realize a semiconductor device having practically practical performance in this conventional semiconductor device, a very sophisticated and fine structure is required. Manufacturing technology is required.

For example, when the thickness of the tunnel oxide film 6202 is too large, it is difficult to inject charges by a tunnel process, so that low-voltage operation and high-speed operation are difficult. On the other hand, if the thickness of the tunnel oxide film 6202 is too small, the charge confinement during the charge holding becomes insufficient, and it becomes difficult to hold the charge for a long time, that is, to record information for a long time.

Further, in order to obtain practical characteristics in this conventional semiconductor device, a manufacturing technique capable of controlling the particle diameter and dispersion of the silicon fine particles 6203 to a high degree is required. In other words, the particle size of the silicon fine particles 6203 becomes too small or too large,
If the in-plane density of 03 is not sufficient, the charge holding period is too short or the amount of charge that can be held is too small, so that the reliability of the semiconductor element is also lowered.

Further, when the thermal energy increases due to a rise in temperature, etc., the charges accumulated in the silicon fine particles 6203 are spontaneously released by a tunnel process from the silicon fine particles 6203 to the p-type silicon substrate 6201.

That is, in this conventional semiconductor device, in order to obtain practical device characteristics, the tunnel oxide film 62 is required.
It is necessary to control the film quality and thickness of the silicon microparticles 02 with extremely high precision and uniformity. Further, while maintaining the particle diameter of the silicon microparticles 6203 constant, the silicon microparticles have a high in-plane density and a uniform dispersion state. 6203 must be created. However, to perform such control over the entire surface of the p-type silicon substrate 6201, a very advanced manufacturing technique is required. Therefore, even if this conventional semiconductor element is manufactured, it is unlikely that an element having practical characteristics can be obtained in the manufacturing process. Further, the reliability of the manufactured conventional semiconductor device is low. That is, according to the study of the present inventors, it is difficult to perform high-speed charge injection / extraction and hold charge for a long time in this conventional semiconductor device.

Therefore, the present invention is easy to manufacture, and
It is an object of the present invention to provide a highly reliable semiconductor element and a manufacturing method thereof.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate having a conductive layer; a barrier layer provided on the conductive layer and functioning as a barrier against movement of electric charges;
A charge holding region composed of a plurality of particles different from each other in a distance between the conductor layer and the conductor layer, wherein the capacitance of the plurality of particles is equal to that of the conductor layer. The smaller the distance, the larger.

Thus, the larger the capacitance, the smaller the rise in potential at the time of holding the charge and the easier the transfer of the charge. Therefore, the charge is held by particles far from the conductor layer, or the charge is released by applying a voltage. This makes it easy to use this charge holding state as information.

In the first semiconductor device, as the particles are dispersed at a higher dispersion density and as the average particle diameter of the particles increases, the capacitance of the particles increases and the charge transfer becomes easier. . Therefore, by changing these elements in accordance with the distance from the conductor layer, the first semiconductor element of the present invention effectively suppresses the spontaneous emission of the accumulated charges, and thereby the Since the charge can be held for a long time, the reliability is high.

In the first semiconductor device, since the particles are quantized, it becomes easy to control the injection and discharge of electric charges by voltage.

It is preferable that the plurality of particles are grouped into a plurality of particle groups including a plurality of particles having a common distance from the conductor layer.

An insulator layer provided on the barrier layer;
A MIS transistor further comprising a gate electrode provided on the insulator layer, and source / drain regions formed by introducing impurities into regions of the substrate located on both sides of the gate electrode. Thus, a semiconductor device functioning as a semiconductor device is obtained.

According to a second aspect of the present invention, there is provided a substrate having a conductor layer, a barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, and a barrier layer dispersed in the barrier layer. And a charge holding region composed of a plurality of particles whose distances from the conductor layer are different from each other, and a barrier height between the particles in the charge holding region is a distance from the conductor layer. The smaller is the smaller.

As a result, the smaller the barrier height is, the easier the charge transfer becomes. Therefore, it is easy to hold the charges in the particles far from the conductor layer or to discharge the charges by applying a voltage. The holding state can be used as information.

Each of the particles has a smaller electron affinity as the distance from the conductor layer becomes smaller, or has a larger electron affinity and a sum of the forbidden band width. The difference in barrier height between the particles can be easily realized.

Whether the barrier layer has a larger electron affinity as the distance from the conductor layer is smaller or has a smaller electron affinity and the sum of the forbidden band width, The difference in the barrier height between the particles can be easily realized.

It is preferable that the plurality of particles are grouped into a plurality of particle groups each including a plurality of particles having a common distance from the conductor layer.

An insulator layer provided on the barrier layer;
The MIS further includes a gate electrode formed on the insulator layer and source / drain regions formed by introducing impurities into regions on both sides of the gate electrode on the substrate. A semiconductor element functioning as a type transistor is obtained.

According to a third aspect of the present invention, there is provided a substrate having a conductive layer, a first tunnel barrier film provided on the conductive layer, and provided on the first tunnel barrier film;
A quantized semiconductor layer, a second tunnel barrier film provided on the first tunnel barrier film and the semiconductor layer, and a second tunnel barrier film provided on the second tunnel barrier film so as not to contact each other; The semiconductor device includes quantized semiconductor particles, and the second tunnel barrier film and an insulating film provided on the semiconductor particles.

Thus, by providing the quantized semiconductor layer, the electron transfer between the quantized semiconductor particle and the conductor layer can be controlled. That is, since charge transfer occurs only when the potential of the energy level of the semiconductor particles and the potential of the energy level of the semiconductor layer match, the spontaneous emission of the charges accumulated in the semiconductor particles can be effectively suppressed, Charges can be held in the semiconductor particles for a long time. Further, in the presence of an appropriate electric field, charges can be easily injected from the conductor layer into the semiconductor particles, and charges can be easily extracted from the semiconductor particles into the conductor layer. Therefore, injection of electrons into semiconductor particles
Since the holding / pulling-out can be reliably controlled, it can be said that this semiconductor element has high reliability in responding to the demand for long-term record holding while satisfying the demands for high-speed operation and reduction in power consumption in the element. .

The discrete energy width of the semiconductor layer is preferably smaller than the discrete energy width of the semiconductor particles.

The semiconductor layer may be a particle group consisting of a collection of particles in contact with each other.

By further including a gate electrode provided on the insulating film and source / drain regions provided on regions of the substrate located on both sides of the gate electrode, the device functions as a MIS transistor. A semiconductor device is obtained.

A fourth semiconductor device according to the present invention includes a substrate having a conductor layer, a first barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, A quantized first particle body provided on the barrier layer;
A second barrier layer provided on the first particle body and functioning as a barrier against movement of electric charges; and a second particle body provided on the second barrier layer. The particle diameter of the second particle is larger than the particle diameter of the first particle.

Thus, when a charge is retained in the particle, the charge retention ability of the particle having a large particle diameter is larger than that of the particle having a small particle diameter, and the release probability is reduced. This makes it possible to use the second particle as an information carrier.

The particle diameter ratio of the second particles to the first particles is 1.8 or more and 300 or less.
The charge holding function of the second particles and the function of the first particles as a charge transfer member can be appropriately adjusted.
The particle size of the first particle is 0.1 nm or more and 5
nm or less, and the particle diameter of the second particles is preferably 1 nm or more and 30 nm or less.

An insulator layer provided on the second particle body, a gate electrode provided on the insulator layer, and provided in regions of the conductor layer located on both sides of the gate electrode By further providing the source / drain regions, a semiconductor element functioning as a MIS transistor can be obtained.

A fifth semiconductor device according to the present invention includes a substrate having a conductive layer, a first barrier layer provided on the conductive layer and functioning as a barrier against movement of electric charges, A first particle body provided on the barrier layer, a second barrier layer provided on the first particle body and functioning as a barrier against the movement of electric charges, and the second barrier layer A second particle body provided thereon, wherein the potential of the second particle body with respect to the charge to be held and released is the first particle body.
Is lower than the potential of the particles.

With this, it is possible to utilize the second particle as an information carrier by utilizing the fact that the second particle having a lower potential has a higher charge holding ability than the first particle. Will be possible.

When the charge to be retained / released is an electron, the electron affinity of the second particle is preferably larger than the electron affinity of the first particle, and the conductor layer is a semiconductor layer. In some cases, it is preferable that the electron affinity of the second particle is larger than the electron affinity of the semiconductor layer.

When the charge to be retained and released is a hole, the sum of the electron affinity and the forbidden band width of the second particle is equal to the sum of the electron affinity and the forbidden band width of the first particle. It is preferable that the sum of the electron affinity and the forbidden band width of the second particle is equal to the electron affinity and the forbidden band width of the semiconductor substrate when the conductor layer is a semiconductor layer. Is preferably smaller than the sum of

An insulating layer provided on the second particle body, a gate electrode provided on the insulating layer, and provided in regions of the conductor layer located on both sides of the gate electrode. By further providing the source / drain regions, a semiconductor element functioning as a MIS transistor can be obtained.

The sixth semiconductor device of the present invention has a conductor layer.
And a first SiO provided on the conductor layer
_Two Layer and the first SiO_Two SiO provided on the layer
_x N _y Layer (0 ≦ x <2, 0 <y ≦ 4/3)
iO_x N_y A second SiO provided on the layer_Two Layers and above
The second SiO_Two With the particles provided on the layer
I have.

Thus, the SiO _x N _y layer and each SiO ₂
Utilizing the generation of a level at which charges can be transferred near the interface with the layer and in the SiO _x N _y layer, the particles can hold charges and be used as information carriers. Become.

An insulator layer provided on the particles,
A semiconductor functioning as a MIS transistor by further comprising a gate electrode provided on the insulator layer and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode An element is obtained.

According to a seventh aspect of the present invention, there is provided a semiconductor device having a substrate having a conductor layer, a first insulator layer provided on the conductor layer, and a first insulator layer provided on the first insulator layer. A first particle body, a first barrier layer provided on the first particle body, which functions as a barrier against movement of electric charges, and a second barrier layer provided on the first barrier layer. , A second barrier layer provided on the second particle body and functioning as a barrier against the movement of electric charges, and a third particle body provided on the second barrier layer Wherein the particle diameters of the first particle body and the third particle body are larger than the particle diameter of the second particle body.

Thus, as described above, the third and the first
Utilizing that the charge holding function of the particles of the second particle is higher than the charge holding function of the second particles, the second particles are charged between the first and the third particles. Since charges can be exchanged as a transfer member, the first and third particles can be used as information carriers.

The particle size ratio between the first and third particles and the second particles is 1.8 or more and 300 or less, respectively, so that the charge retention of the first and third particles is maintained. The function and the charge release function of the second particles can be adjusted as appropriate.

The particle diameter of the second particles is preferably 0.1 nm or more and 5 nm or less.
The particle size of the particles is preferably 1 nm or more and 30 nm or less.

An insulator layer provided on the third particle body, a gate electrode provided on the insulator layer, and provided in regions of the conductor layer located on both sides of the gate electrode. By further providing the source / drain regions, a semiconductor element functioning as a MIS transistor can be obtained.

An eighth semiconductor device according to the present invention includes a substrate having a conductor layer, a first insulator layer provided on the conductor layer, and a substrate provided on the first insulator layer. A first particle body, a first barrier layer provided on the first particle body, which functions as a barrier against movement of electric charges, and a second barrier layer provided on the first barrier layer. , A second barrier layer provided on the second particle body and functioning as a barrier against the movement of electric charges, and a third particle body provided on the second barrier layer And the potentials of the first and third particles for holding and releasing are lower than the potential of the second particles.

As described above, by utilizing the fact that the charge holding function of the first and third particles is higher than the charge holding function of the second particles, as described above, the first particles and the third particles are used. It is possible to exchange electric charges with the particles of the second particle as a charge transfer member, so that the first particles and the third particles can be used as information carriers. Become.

When the charge to be retained and released is an electron, it is preferable that the electron affinity of the first and third particles is larger than the electron affinity of the second particle. When the charge to be charged is a hole, the sum of the electron affinity and the forbidden band width of the first and third particles is calculated from the sum of the electron affinity and the forbidden band width of the second particle. Are also preferably small.

An insulator layer provided on the third particle body, a gate electrode provided on the insulator layer, and provided in regions of the conductor layer located on both sides of the gate electrode By further providing the source / drain regions, a semiconductor element functioning as a MIS transistor can be obtained.

A ninth semiconductor device according to the present invention has a conductor layer.
Substrate, and an insulator layer provided on the conductor layer,
A first particle body provided on the first insulator layer,
The first SiO provided on the first particle body_Two layer
And the first SiO_Two SiO provided on the layer_x N
_y Layer (0 ≦ x <2, 0 <y ≦ 4/3) layer and the SiO
_x N_y A second SiO provided on the layer_Two Layer and the first
2 SiO_Two A second particle body provided on the layer.
ing.

Thus, the SiO _x N _y layer and each SiO ₂
Utilizing the generation of a level capable of transferring charges in the vicinity of the interface with the layer and in the SiO _x N _y layer, the first and second particles hold the charges to serve as an information carrier. It can be used.

Another one provided on the second particle body
Further comprising one insulator layer, a gate electrode provided on the other insulator layer, and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode. Thereby, a semiconductor element functioning as a MIS transistor is obtained.

According to a tenth aspect of the present invention, there is provided a semiconductor device having a substrate having a conductor layer, a barrier layer provided on the conductor layer that functions as a barrier to the movement of electric charges, and a barrier layer provided on the barrier layer. A charge retention carrier; and a quantized particle body embedded in at least a part of the barrier layer.

This makes it possible to control the movement of charges while using the particles as a charge transfer member between the charge holding carrier and the conductor layer. In particular, the use of the quantized particles enables high-speed operation. A semiconductor element which can be used as a memory capable of writing and erasing data can be obtained.

An insulator layer provided on the particles,
A gate electrode provided on the insulator layer; and a source / drain region formed by introducing impurities into regions of the conductor layer located on both sides of the gate electrode, thereby providing non-volatile memory. A semiconductor element functioning as a memory cell of a memory is obtained.

An eleventh semiconductor device according to the present invention comprises a substrate having a conductive layer, and a first Si provided on the conductive layer.
O ₂ layer and Si provided on the first SiO ₂ layer
An O _x N _y layer (0 ≦ x <2, 0 <y ≦ 4/3) layer, a second SiO ₂ layer provided on the SiO _x N _y layer,
A charge holding carrier provided on the second SiO ₂ layer.

Thus, the SiO 2_x N_y Layer and each SiO_Two 
Near the interface with the layer and SiO_x N _y Charge transfer in layer
By utilizing the generation of functional levels,
That can be used as a memory that can write and erase data
An element is obtained.

Impurity is introduced into an insulator layer provided on the charge holding carrier, a gate electrode provided on the insulator layer, and regions of the conductor layer located on both sides of the gate electrode. And a source / drain region formed as described above, a semiconductor element functioning as a memory cell of the nonvolatile memory can be obtained.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment)-Structure of Semiconductor Device According to First Embodiment-FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.
You. In this semiconductor device, a p-type silicon substrate 101
1 includes several fine particle dispersion areas 1012a.
Charge holding region 1012 (about 20 nm thick), insulating film
SiO functioning as_Two Film 1015 (thickness 20 nm),
And n-type polycrystalline silicon electrode 1 functioning as upper electrode
016 are provided in order from the bottom. Also, for each fine particle
In the scattering region 1012a, silicon fine particles 1013 (particle size
5 nm) is the insulator SiO _Two Dispersed in 1014
Have been. The fine particles in the fine particle dispersion region 1012a have been removed.
The part (matrix) has a band gap larger than the fine particles.
A semiconductor having a pump may be used. Note that SiO_Two Membrane 1015
Thickness of 5-20 nm, particle size of silicon microparticles 1013
About 2 to 10 nm, the dispersion density of the silicon fine particles 1013
Degree 1 × 10¹⁷cm ^-3~ 1 × 10²⁰cm^-3About
Is preferred.

-Manufacturing Process of Semiconductor Device According to First Embodiment-FIGS. 13A, 13B, and 13C are cross-sectional views showing manufacturing processes of the semiconductor device according to the first embodiment. .

First, in the step shown in FIG. 13A, silicon tablets are arranged on SiO ₂ in a sputtering apparatus provided with a p-type silicon substrate 1011 and accelerated ions collide with the tablets. At this time, the atoms and molecules 1017 repelled by the impact are deposited on the p-type silicon substrate 1011.

Thereafter, the substrate is subjected to a heat treatment in the step shown in FIG. By these steps, on the p-type silicon substrate 1011, a film in which silicon fine particles 1013 are deposited in SiO ₂ 1014, that is, a charge holding region 1012 composed of several fine particle dispersed regions 1012 a
To form

Next, in the step shown in FIG.
Place the substrate on the susceptor in the chamber of the device,
After depositing the iO ₂ film 1015 on the fine particle dispersion region 1012a, an n-type polycrystalline silicon electrode 1016 is deposited on the SiO ₂ film 1015 in the same chamber.

—Electron Injection / Holding / Extraction Mechanism of Conventional Semiconductor Element— As described above, the conventional semiconductor element has a tunnel oxide formed of a SiO ₂ film on a p-type silicon substrate 6201 as shown in FIG. A film 6202 and a SiO ₂ film 6204 are sequentially deposited from the bottom, and an n-type polycrystalline silicon electrode 6205 is further provided thereon. Silicon fine particles 6203 are embedded between the tunnel oxide film 6202 and the SiO ₂ film 6204.

[0066] Figure 2, SiO ₂ film 6204 of the conventional semiconductor device shown in FIG. 57, the silicon microparticles 6203,
Tunnel oxide film 6202 and p-type silicon substrate 6201
FIG. 3 is a band diagram showing the energy band structure of FIG. In the silicon fine particles 6203, since the particle diameter of the silicon fine particles 6203 is extremely small, the energy state (energy level) that electrons in the silicon fine particles can take is quantized. In this conventional semiconductor device, electron injection / extraction to the silicon fine particles 6203 occurs by a tunnel process between the p-type silicon substrate 6201 and the silicon fine particles 6203.

FIGS. 3A and 3B are partial band diagrams respectively showing the energy band states when performing electron injection and electron holding in this conventional semiconductor device. In addition,
In FIGS. 3A and 3B, illustration of the valence band is omitted for easy understanding.

As shown in FIG. 3A, in this conventional device, when a positive voltage equal to or more than a certain value is applied to n-type polycrystalline silicon electrode 6205, an external electric field is generated, and the potential of silicon fine particles 6203 becomes The potential is higher than the potential of the p-type silicon substrate 6201. At this time, electrons are injected from the conduction band in the p-type silicon substrate 6201 to the silicon fine particles 6203 via the tunnel oxide film 6202 by a tunnel phenomenon.

On the other hand, as shown in FIG. 3B, when the application of the positive voltage to the n-type polycrystalline silicon electrode 6205 is stopped, the potential of the silicon particles 6203 itself is reduced by the electrons accumulated in the silicon particles 6203. To rise. Therefore, contrary to the time of electron injection, a force for spontaneously emitting electrons from the silicon fine particles 6203 to the p-type silicon substrate 6201 through the tunnel oxide film 6202 is generated by a tunneling process. If this potential rise is sufficiently small, electrons are held by the silicon fine particles 6203.

When a negative voltage is applied to n-type polycrystalline silicon electrode 6205,
Through the tunnel oxide film 6202, the p-type silicon substrate 62
It is pulled into the conduction band at 01.

The detailed mechanism of the tunnel process between the energy level in the semiconductor substrate and the energy level of the fine particles and the transition probability thereof have not been clarified. However, application of a voltage causes injection of electrons in the fine particles, retention of the electrons in the fine particles even when the application of the voltage is stopped, and gradual spontaneous emission of electrons from the fine particles at room temperature. It is clear that the existence of the tunnel process described above is clear.

—Electron Injection / Holding / Extraction Mechanism of Semiconductor Device According to First Embodiment— Next, an electron injection / holding / extraction mechanism of the semiconductor device according to the first embodiment will be described with reference to FIG. I will explain it.

When a certain positive voltage is applied to the n-type polycrystalline silicon electrode 1016, a tunnel process is performed from the p-type silicon substrate 1011 to the p-type silicon substrate 1011 through the SiO ₂ 1014 in the same manner as in a conventional semiconductor device. Electrons are injected into adjacent silicon microparticles 1013. However, unlike the conventional semiconductor device, the semiconductor device according to the first embodiment has the charge holding region 1012 in which the silicon fine particles 1013 are dispersed also in the thickness direction, so that the electrons are transferred to the p-type silicon substrate 1011. An attempt is made to move from the silicon particle 1013 at an adjacent position to the silicon particle 1013 on the n-type polycrystalline silicon electrode 1016 side (upper in FIG. 1).

Here, the space between the silicon particles 1013 is
Separated by SiO ₂ 1014. This SiO ₂
Due to 1014, electrons are difficult to be injected from the surrounding silicon microparticles 1013 into the silicon microparticles 1013 far away from and isolated from the surrounding silicon microparticles 1013. Electrons are easily injected into the 1013 from the surrounding silicon microparticles 1013.

The capacitance of silicon fine particles 1013 adjacent to p-type silicon substrate 1011 is larger than the capacitance of silicon fine particles 1013 distant from p-type silicon substrate 1011. Silicon fine particles 1 with large capacitance
In No. 013, since the potential rise due to the charge injection is small, the electron transfer is easy, and the silicon fine particles 1 having a small capacitance are used.
In 013, since the potential rise due to the charge injection is large, electron transfer due to the charge injection hardly occurs. That is, charge transfer to the silicon microparticles 1013 is easier as the distance from the p-type silicon substrate 1011 is smaller.

Therefore, in the silicon fine particles 1013 adjacent to the p-type silicon substrate 1011, electrons can easily move, and many electrons move further from the position adjacent to the p-type silicon substrate 1011 to the n-type polycrystalline silicon electrode 1016. . In this way, electrons move from the p-type silicon substrate 1011 side to the n-type polycrystalline silicon electrode 1016 side while selecting a path through which electron movement is easy, and finally, further electron movement occurs. It is accumulated in difficult relatively isolated silicon fine particles 1013.

The position where the electrons finally reach is
It depends on the voltage applied to the n-type polycrystalline silicon electrode 1016 layer. A larger voltage is applied to the n-type polycrystalline silicon electrode 10.
By applying the voltage to the 16 layers, more electrons pass through more paths, and more electrons are injected into the silicon fine particles 1013, which are more difficult to inject electrons, that is, the n-type polycrystalline silicon electrode 1013.
The particles are accumulated in the silicon microparticles 1013 closer to the 16 layers.

Next, the mechanism of electron injection, holding, and extraction in the semiconductor device according to the first embodiment will be described with reference to a band diagram.

FIG. 4 is a band diagram of the semiconductor device according to the first embodiment. In the charge holding region 1012,
Actually, there are many silicon fine particles 1013,
In FIG. 4, the respective energy levels of the silicon fine particles A adjacent to the p-type silicon substrate 1011 and the SiO ₂ film 1015 not adjacent to the p-type silicon substrate 1011
Are adjacent to each other, and only two of the energy levels of the silicon microparticles B that hold electric charge are shown for simplicity of explanation.

Here, for the sake of simplicity, a description will be given of a tunneling process between the silicon fine particles A and the silicon fine particles B. However, charge transfer is performed by the same principle even in charge transfer through a large number of silicon fine particles. .

In the silicon microparticles 1013, since the particle diameter of the silicon microparticles 1013 is extremely small, the energy state (energy level) that electrons in the silicon microparticles can take is quantized. Therefore, as shown in FIG.
The energy levels of both the silicon microparticles A and the silicon microparticles B are quantized.

The interval between the energy levels of the silicon fine particles 1013 (hereinafter referred to as “discrete energy width”) is large when the energy level is low.
It is small when the energy level is higher.

In the ordinary tunnel process, it is necessary that the potentials of the energy levels on both sides of the passing barrier layer are the same. Therefore, between the silicon microparticles B and the silicon microparticles A, when no voltage is applied, one of the energy levels of the silicon microparticles B both quantized on both sides of the second tunnel barrier film 1014 and the silicon microparticles Since tunneling occurs only when the potential of one of the energy levels of A matches each other, the probability of the occurrence of tunneling is very low. Therefore, between the silicon fine particle B and the silicon fine particle A, the electron transfer is efficiently performed by the resonance tunneling process only when a voltage is applied so that the potentials of the energy levels quantized between the silicon fine particle B and the silicon fine particle A become equal. On the other hand, in other cases, electron transfer is suppressed. That is,
The electron transfer between the silicon microparticles B and the silicon microparticles A can be controlled by an externally applied voltage, and the electrons once injected into the silicon microparticles B are held for a long time.

On the other hand, in the conduction band of the p-type silicon substrate 1011, energy levels, which are energy states that electrons can take, exist almost continuously, and the state density is high. Therefore, the energy level having the same potential is applied to the p-type silicon substrate 1011 for any of the quantized energy levels of the silicon microparticles A.
Therefore, the tunneling process between the silicon fine particle Ap-type silicon substrate 1011 is not prohibited at least in terms of energy. Further, since the area of the silicon fine particles A is sufficiently large, SiO ₂ 1014
The state function has a large spatial overlap between the levels of the silicon fine particles A and the p-type silicon substrate 1011 sandwiching the. Therefore, no matter how the voltage applied to the n-type polycrystalline silicon electrode 1016 is changed, a rapid tunneling process occurs between the silicon fine particle Ap and the p-type silicon substrate 1011.
And equipotential. That is, electron transfer between the silicon fine particle Ap-type silicon substrate 1011 is easy.

FIGS. 5 (a), 5 (b) and 5 (c) are partial band diagrams respectively showing the energy band states when performing electron injection and electron holding in the semiconductor device of the first embodiment. In FIGS. 5A, 5B and 5C, illustration of the energy band state of the valence band is omitted for easy understanding.

As shown in FIG. 5A, before the voltage is applied to the n-type polycrystalline silicon electrode 1016, the electron transfer between the p-type silicon substrate 1011 and the silicon fine particle A or the silicon fine particle B is performed. Does not happen.

However, as shown in FIG. 5B, when a certain positive voltage is applied to the n-type polycrystalline silicon electrode 1016, the empty energy of the silicon fine particles A from the p-type silicon substrate 1011 is increased as described above. Electron transfer to the level,
Electron transfer from the energy level of the silicon fine particle A to the empty energy level in the silicon fine particle B easily occurs. Here, the particle diameter of the plurality of silicon fine particles B is usually
Due to the variation, the potential of the quantized energy level of the silicon microparticles B also varies. Therefore, even if the voltage is not strictly controlled, some of the energy levels of the electrons of the silicon microparticles A and each of the energy levels of some of the silicon microparticles B become the same potential by the applied constant voltage. Becomes Therefore,
When a positive voltage is applied to the n-type polycrystalline silicon electrode 1016, electrons can be injected from the p-type silicon substrate 1011 to the plurality of silicon fine particles B via the silicon fine particles A.

Since the interval (discrete energy width) between the quantized energy levels becomes smaller as the potential increases, the higher the voltage applied, the more the silicon microparticles B and A are quantized. Higher-order dense portions of the energy level group have the same potential, and the density of states increases, so that more high-order silicon fine particles B are injected with electrons. Further, it is possible to inject more electrons into the silicon microparticles B by sweeping the applied voltage within a certain range or superimposing a high frequency.

As shown in FIG. 5C, after electron injection into a plurality of silicon fine particles B, the n-type polycrystalline silicon electrode 1
When the application of the voltage to 016 is stopped, the potential of the silicon fine particles B increases, and the potential of the conduction band of the p-type silicon substrate 1011 decreases. In other words, by eliminating the application of the voltage, the energy levels of the silicon microparticles A, the energy levels of the silicon microparticles B, and the relative potential of the conduction band of the p-type silicon substrate change. After the electron injection into the plurality of silicon microparticles B, the potential of the silicon microparticles B is higher than before the electron injection (FIG. 5A).

At this time, at the potential when the applied voltage is removed, the potential of the energy level of some silicon microparticles B coincides with the potential of the energy level of silicon microparticles A, and the tunnel process is started. Since it is allowed, the electrons injected into the silicon microparticles B may be lost. In this respect, it is similar to the conventional semiconductor device. However, in the semiconductor device according to the first embodiment, unlike the conventional semiconductor device, the potential of the energy level of many silicon fine particles B into which electrons are injected is different from the potential of the energy level of the silicon fine particles B. Therefore, the electron transfer due to the tunnel process between the silicon microparticles B and the silicon microparticles A is prohibited. Therefore, electrons are stably held in the majority of the silicon microparticles B, so that the semiconductor element according to the first embodiment can hold electrons for a long time.

Conversely, by applying a negative voltage to the n-type polycrystalline silicon electrode 1016, the charge can be erased. That is, the n-type polycrystalline silicon electrode 1
When a sufficiently large negative voltage is applied to 016, when the potential of the energy level of the silicon microparticles B matches the potential of the energy level of the silicon microparticles A,
Electrons are extracted from the silicon microparticles B to the silicon microparticles A. As at the time of injecting electrons into silicon fine particles B,
By relatively increasing the applied negative voltage, sweeping the applied voltage, or superimposing a high frequency, the charge can be more efficiently erased.

In the semiconductor device according to the first embodiment, since the silicon microparticles 1013 having a large capacitance exist between the silicon microparticles 1013 having a small capacitance and the p-type silicon substrate 1011, the electrostatic capacitance is increased. The transfer of electric charge between the silicon particles 1013 having a small capacitance and the p-type silicon substrate 1011 is easily performed via the silicon particles 1013 having a large capacitance. Therefore,
n-type polycrystalline silicon electrode 1016 and p-type silicon substrate 1
When a charge injection voltage is applied between the silicon fine particle 1013 and the gate electrode 011, the charge is easily injected into the upper silicon fine particles 1013 having a small capacitance.

In particular, in the semiconductor device according to the first embodiment, unlike the conventional semiconductor device using a plurality of silicon fine particles, a large number of quantized silicon having a large discrete energy width in the charge holding region 1012. By providing the fine particles 1013, spontaneous emission of accumulated electrons can be effectively suppressed, and electrons can be held in the silicon fine particles B for a long time. In addition, since the silicon microparticles 1013 are quantized, it becomes easy to control the injection and release of electric charges by voltage.

Therefore, the semiconductor device according to the first embodiment can hold electric charge in the electric charge holding region 1012 for a long time by effectively suppressing spontaneous emission of the accumulated electric charge. Becomes That is, the first
It can be said that the semiconductor device according to the embodiment is more reliable than the conventional semiconductor device in responding to a long-time recording and holding request.

In a conventional semiconductor device, in order to realize easy electron injection, the particle size of the silicon fine particles 6203 shown in FIG. In addition, it is necessary to control the thickness of the tunnel oxide film 6202 with high accuracy and uniformly. On the other hand, in the semiconductor device according to the first embodiment, since the silicon fine particles 13 having various particle diameters are randomly diffused in the SiO ₂ 1014, the silicon fine particles 101 which can easily inject electrons when a voltage is applied are applied.
3 automatically and selectively inject electrons, and
Electrons are held by the silicon microparticles 1013 which hold electrons most easily. Therefore, in the semiconductor device according to the first embodiment, it is not necessary to control the thickness of the tunnel oxide film and the particle size of the silicon microparticles 1013. The manufacturing process of such a semiconductor element is easier.

Further, in the semiconductor device according to the first embodiment, since the silicon fine particles 1013 having various capacitances exist in the charge holding region 1012, a certain electron holding period (recording time) is realized. It is also possible to perform electron injection with a minimum voltage required to perform electron injection. Also,
The charge erasing can also be performed with the minimum necessary voltage having the same magnitude.

In a conventional semiconductor device, FIG.
P-type silicon substrate 6201 shown in FIG.
Since the tunnel process only between the 203 is used, it is necessary to arrange the silicon fine particles 6203 on a single surface.
Therefore, the amount of electrons that can be held in the semiconductor element is limited by the number of silicon fine particles 6203 that can be manufactured on a single surface. On the other hand, in the semiconductor device according to the first embodiment, not only the tunnel process between the p-type silicon substrate 1011 and the silicon fine particles 1013 shown in FIG. The fine particles 1013 can also be arranged in the thickness direction. Therefore, the semiconductor device according to the first embodiment has an advantage that it can hold a larger amount of electrons than the conventional semiconductor device.

As described above, the semiconductor device having the novel structure according to the first embodiment and the method of manufacturing the semiconductor device according to the first embodiment have a simpler manufacturing process and a finer particle size than ever before. A semiconductor element having high reliability of charge injection / holding / erasing to a semiconductor device is provided.

It is needless to say that the semiconductor device according to the first embodiment can be applied to various semiconductor devices for controlling movement and accumulation of minute electric charges.

Second Embodiment Structure of Semiconductor Device According to Second Embodiment FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment. As shown in FIG. 6, the semiconductor device according to the second embodiment has a MIS transistor structure. In this semiconductor device, on a p-type silicon substrate 1071, a charge holding region 1073 composed of several fine particle dispersion regions 1073a and a gate insulating film 1 composed of an SiO ₂ film are provided.
076 and an n-type polycrystalline silicon electrode 1078 functioning as a gate electrode are sequentially stacked from the bottom. In each fine particle dispersion region 1073a, silicon fine particles 1074 are dispersed in SiO ₂ 1075 which is an insulator. Also, a p-type silicon substrate 1071 serving as a base
An n-type diffusion region (source / drain region) 10 is located in a region located on both sides of n-type polycrystalline silicon electrode 1077 in the middle.
72 are provided. Further, the n-type diffusion region 1072
On top, a metal electrode 1078 functioning as a source / drain electrode is provided. A portion (matrix) of the charge holding region 1073 other than the fine particles may be a semiconductor having a larger band gap than the fine particles.

—Process for Manufacturing Semiconductor Device According to Second Embodiment— Next, a process for manufacturing a semiconductor device according to the second embodiment will be described. After a semiconductor substrate similar to that of the first embodiment is formed, a charge holding region 1073, a gate insulating film 1076, and an n-type polycrystalline silicon electrode 1077 are formed on a p-type silicon substrate 1071 by forming respective films, photolithography, and etching. To form Next, after the n-type diffusion region 1072 is formed by ion implantation, a metal electrode 1079 is formed by sputtering and etching. Thereby, the semiconductor device according to the second embodiment can be manufactured.

<< Characteristics of Semiconductor Device According to Second Embodiment >> Also in the second embodiment, the capacitance of the silicon fine particles 1074 increases as the distance from the p-type silicon substrate 1071 decreases. Therefore, according to the same principle as in the first embodiment, it is possible to inject electrons into the silicon microparticles 1074, retain electrons in the silicon microparticles 1074, and extract electrons from the silicon microparticles 1074.
Further, as described above, the semiconductor device according to the second embodiment has an MIS transistor structure. further,
In the second embodiment, silicon fine particles 1074 for holding electrons are provided in SiO ₂ 1075 between a p-type silicon substrate 1071 and an n-type polycrystalline silicon electrode 1077. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon microparticles 1074. By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

In the semiconductor device according to the second embodiment, since the silicon microparticles 1074 having a large capacitance exist between the silicon microparticles 1074 having a small capacitance and the p-type silicon substrate 1071, static electricity is present. Silicon fine particles 1074 with small capacitance and p-type silicon substrate 1071
The transfer of the electric charge between the substrate and the substrate is easily performed through the silicon microparticles 1074 having a large capacitance.

In particular, also in the second embodiment, by providing a large number of quantized silicon fine particles 1074 having a large discrete energy width in the charge holding region 1073, spontaneous emission of accumulated electrons is effectively suppressed. In addition, electrons can be held in the silicon microparticles B for a long time. In addition, since the silicon microparticles 1074 are quantized, it is easy to control the injection and release of electric charges by voltage.

Therefore, the semiconductor device according to the second embodiment can hold charges in the charge holding region 1073 for a long time by effectively suppressing spontaneous emission of the stored charges, so that the semiconductor device has high reliability. Becomes Therefore, the second
The semiconductor device according to the embodiment can satisfy the demands for high-speed operation and low power consumption in the device, and can be highly reliable in response to the demand for long-term record keeping. Further, in the second embodiment, since a basic memory operation is realized by a single element, high-density integration is possible.

In the semiconductor device according to the second embodiment, like the semiconductor device according to the first embodiment,
Since it is not necessary to control the thickness of the tunnel oxide film, the manufacturing process of the semiconductor device according to the second embodiment is easier than the conventional semiconductor device manufacturing process.

In the second embodiment, it is preferable to provide a region in which silicon fine particles 1074 do not exist on or above at least one of n-type diffusion regions 1072. Thereby, the n-type diffusion region 1072
Can be prevented from flowing between the n-type diffusion regions 1072 when a voltage is applied to the n-type diffusion region 1072.

In the second embodiment, the layer made of silicon fine particles 1074 can be divided into several parts in a direction perpendicular to the cross section shown in FIG. With this, the current short-circuited through the silicon microparticles 1074 when a voltage is applied to the n-type diffusion region 1072 becomes n
Flow between the mold diffusion regions 1072 can be prevented.

Third Embodiment —Structure of Semiconductor Device According to Third Embodiment— FIG. 7 is a sectional view of a semiconductor device according to a third embodiment. In this semiconductor device, the p-type silicon substrate 108
1, a charge retention region 1082 (about 20 nm thick) composed of several fine particle dispersion areas 1082a, a SiO ₂ film 1086 (20 nm thick) functioning as an insulating film,
And n-type polycrystalline silicon electrode 1 functioning as upper electrode
087 are provided in order from the bottom. In each fine particle dispersion region 1082a, silicon fine particles 1084 (with a particle size of about 5 nm) are dispersed in SiO ₂ 1085, which is an insulator. A portion (matrix) of the charge holding region 1082 other than the fine particles may be a semiconductor having a band gap larger than the fine particles. The SiO ₂ film 1086
Is preferably 5 to 20 nm, and the particle size of the silicon fine particles 1084 is preferably about 2 to 10 nm.

As shown in FIG. 7, unlike the first embodiment, in the third embodiment, silicon fine particles 108
The dispersion density of No. 4 continuously decreases from the portion adjacent to the p-type silicon substrate 1081 to the portion adjacent to the SiO ₂ film 1086. Note that the charge holding region 108
2, the dispersion density of the silicon fine particles 1084 is 1 × 10 3 at a portion adjacent to the p-type silicon substrate 1081.
While it is ²⁰ cm ^-3, in a portion adjacent to the SiO ₂ film 1086, the dispersion density of 1 × 10 silicon microparticles 1084
¹⁵ cm ^-3 . In the charge holding region 1082, there is no interface.

—Process of Manufacturing Semiconductor Device According to Third Embodiment— Next, a process of manufacturing a semiconductor device according to the third embodiment will be described. First, in a sputtering apparatus provided with a p-type silicon substrate 1081, silicon tablets are arranged on SiO ₂ , and accelerated ions collide therewith. The atoms and molecules repelled by the impact at this time are deposited on the p-type silicon substrate 1081. Where Si
This sputtering is repeated while gradually reducing the amount of silicon tablets arranged on O ₂ . After that, heat treatment of the substrate is performed. By these steps, on the p-type silicon substrate 1081, the dispersion density of the silicon fine particles 1084 in the SiO ₂ 1085 is reduced.
1 continuously decreases from the portion adjacent to the SiO2 film 1086 to the portion adjacent to the SiO2 film 1086, that is, the charge holding region 10 including several fine particle dispersion regions 1082a.
82 is formed. Next, a substrate is placed on a susceptor in a chamber of the CVD apparatus, and an SiO ₂ film 1086 is deposited on the charge holding region 1082. Then, in the same chamber, the n-type polycrystalline silicon electrode 1087 is placed on the SiO ₂ film 10
86.

Here, by setting the dispersion density of the fine particles in the portion of the charge holding region 1082 close to the n-type polycrystalline silicon electrode 1087 to a sufficiently small value of 1 × 10 ¹⁷ cm ⁻³ or less, the charge holding region N out of 1082
A portion near the type polycrystalline silicon electrode 1087 can also have a function as an insulating film. In this case, in the third embodiment, it does not form part of the SiO ₂ film 1086, i.e., SiO ₂ film 1086
Can be made substantially zero.

—Electron Injection / Holding / Pull-Out Mechanism of Semiconductor Device According to Third Embodiment— In the third embodiment, the dispersion density of silicon fine particles 1084 decreases as the position increases above fine particle dispersion region 1082. Therefore, the average distance between the silicon microparticles 1084 increases. Therefore, the charge holding region 1082
, The capacitance of the silicon microparticles 1084 decreases. That is, the capacitance of the silicon microparticles 1084 increases as the distance from the p-type silicon substrate 1081 decreases. In addition, since the tunnel barrier is thicker, electron injection is less likely to occur in the silicon fine particles 1084 closer to the n-type polycrystalline silicon electrode 1087.

In the semiconductor device according to the third embodiment, unlike the conventional semiconductor device using a plurality of silicon fine particles, a large number of quantized silicon having a large discrete energy width in the charge holding region 1082. By providing the fine particles 1084, spontaneous emission of accumulated electrons can be effectively suppressed, and electrons can be held in the silicon fine particles 1084 for a long time. Also,
Since the silicon microparticles 1084 are quantized, it is easy to control the injection and release of electric charge by voltage.

Therefore, the semiconductor device according to the third embodiment is more reliable than the conventional semiconductor device in responding to the demand for long-term record keeping.

In the semiconductor device according to the third embodiment, like the semiconductor device according to the first embodiment,
Silicon fine particles 1084 having various particle sizes are made of SiO ₂
Since it is diffused in 1085, electrons are automatically and selectively injected from silicon fine particles 1084 which are easy to inject when applying voltage, and electrons are held by silicon fine particles 1084 in which electrons are most easily held. . Therefore, in the semiconductor device according to the third embodiment, the first
Since the thickness of the tunnel oxide film and the particle size of the silicon microparticles 1084 do not need to be controlled similarly to the semiconductor device according to the first embodiment, the third embodiment is more complicated than the conventional semiconductor device manufacturing process.
The manufacturing process of the semiconductor device according to the embodiment is easier.

Further, in the semiconductor device according to the third embodiment, similarly to the semiconductor device according to the first embodiment, silicon fine particles 1084 having various capacitances exist in the charge holding region 1082. Therefore, electron injection can be performed with a minimum voltage necessary to realize a certain electron holding period (recording time). In addition, charge erasing can be performed with a minimum necessary voltage having the same magnitude.

In the third embodiment, the dispersion density of the silicon fine particles 1084 depends on the p-type silicon substrate 10.
It decreases continuously from the portion adjacent to 81 to the portion adjacent to the SiO ₂ film 1086. In the charge holding region 1082, there is no interface. However, it is also possible to provide a portion in the charge holding region 1082 such that the dispersion density of the silicon fine particles 1084 does not change continuously. Also, in the charge holding region 1082, the surface where the composition of the portion excluding the fine particles of the charge holding region 1082 changes above and below the surface, and the silicon fine particles 1
It is also possible to provide a surface where the dispersion density or the composition of 084 changes or another interface. Note that there may be a plurality of interfaces. Further, the silicon fine particles 1084 may be divided into a plurality of fine particle groups including silicon fine particles 1084 having a common distance from the p-type silicon substrate 1081. Also in these cases, each silicon fine particle 1
Since the capacitance between the capacitors 084 is not constant, substantially the same effects as in the third embodiment can be obtained.

(Fourth Embodiment) —Structure of Semiconductor Device According to Fourth Embodiment— FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment. As shown in FIG. 8, the semiconductor device according to the fourth embodiment has a MIS transistor structure. In this semiconductor device, on a p-type silicon substrate 1091, a charge holding region 1093 composed of several fine particle dispersion regions 1093a, and a gate insulating film 1 composed of an SiO ₂ film.
097 and an n-type polycrystalline silicon electrode 1098 functioning as a gate electrode are sequentially stacked from the bottom. In each fine particle dispersion region 1093a, silicon fine particles 1095 are dispersed in SiO ₂ 1096 which is an insulator. The fourth embodiment is different from the second embodiment in that the dispersion density of the silicon microparticles 1095 decreases continuously from the portion adjacent to the p-type silicon substrate 1091 to the portion adjacent to the gate insulating film 1097. Is different from the embodiment. Also, a p-type silicon substrate 1091 serving as a base
In regions located on both sides of n-type polycrystalline silicon electrode 1098, n-type diffusion regions 1092 are provided. Further, a metal electrode 1099 functioning as a source / drain electrode is provided on the n-type diffusion region 1092. A portion (matrix) of the charge holding region 1093 excluding the fine particles may be a semiconductor having a band gap larger than the fine particles.

—Process for Manufacturing Semiconductor Device According to Fourth Embodiment— Next, a process for manufacturing a semiconductor device according to the fourth embodiment will be described. After a semiconductor substrate similar to that of the third embodiment is formed, a charge holding region 1093, a gate insulating film 1097, and an n-type polycrystalline silicon electrode 1098 are formed on a p-type silicon substrate 1091 by forming respective films, photolithography, and etching. To form Next, after an n-type diffusion region 1092 is formed by ion implantation, a metal electrode 1099 is formed by sputtering and etching. Thus, the semiconductor device according to the fourth embodiment can be manufactured.

<< Characteristics of Semiconductor Element According to Fourth Embodiment >> Also in the fourth embodiment, the capacitance of the silicon fine particles 1095 increases as the distance from the p-type silicon substrate 1091 decreases. Therefore, according to the same principle as that of the third embodiment, it is possible to inject electrons into the silicon microparticles 1095, retain electrons in the silicon microparticles 1095, and extract electrons from the silicon microparticles 1095.
As described above, the semiconductor device according to the fourth embodiment has a MIS transistor structure. further,
In the fourth embodiment, silicon microparticles 1095 for holding electrons are provided in SiO ₂ 1096 between a p-type silicon substrate 1091 and an n-type polycrystalline silicon electrode 1098. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon microparticles 1095. By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

In the semiconductor device according to the fourth embodiment, since the silicon microparticles 1095 having a large capacitance exist between the silicon microparticles 1095 having a small capacitance and the p-type silicon substrate 1091, the static electricity is reduced. Silicon fine particles 1095 with small capacitance and p-type silicon substrate 1091
The transfer of the electric charge between the silicon fine particles and the silicon oxide particles is easily performed via the silicon microparticles 1095 having a large capacitance.

In particular, also in the fourth embodiment, by providing a large number of quantized silicon fine particles 1095 having a large discrete energy width in the charge holding region 1093, spontaneous emission of accumulated electrons is effectively suppressed. In addition, electrons can be held in the silicon microparticles B for a long time. In addition, since the silicon microparticles 1095 are quantized, it is easy to control the injection and release of electric charge by voltage.

Therefore, the semiconductor device according to the fourth embodiment can hold the charge in the charge holding region 1093 for a long time by effectively suppressing the spontaneous emission of the stored charge. Becomes Therefore, the fourth
The semiconductor device according to the embodiment can satisfy the demands for high-speed operation and low power consumption in the device, and can be highly reliable in response to the demand for long-term record keeping. Furthermore, in the fourth embodiment, since a basic memory operation is realized by a single element, high-density integration becomes possible.

In the semiconductor device according to the fourth embodiment, like the semiconductor device according to the third embodiment,
Since it is not necessary to control the thickness of the tunnel oxide film, the manufacturing process of the semiconductor device according to the fourth embodiment is easier than the conventional semiconductor device manufacturing process.

In the fourth embodiment, a region where the silicon fine particles 1095 do not exist may be provided on or above at least one of the n-type diffusion regions 1092. This can prevent a current short-circuited through the silicon fine particles 1095 from flowing between the n-type diffusion regions 1092 when a voltage is applied to the n-type diffusion region 1092.

In the fourth embodiment, the layer made of silicon fine particles 1095 can be divided into several parts in a direction perpendicular to the cross section shown in FIG. With this, the current short-circuited through the silicon microparticles 1095 when a voltage is applied to the n-type diffusion region 1092 becomes n
Flow between the mold diffusion regions 1092 can be prevented.

(Fifth Embodiment) —Structure of Semiconductor Device According to Fifth Embodiment— FIG. 9 is a sectional view of a semiconductor device according to a fifth embodiment.
You. In this semiconductor device, a p-type silicon substrate 110
1 includes several fine particle dispersion areas 1102a.
Charge holding region 1102 (about 30 nm thick), insulating film
SiO2 film 1106 (thickness: 20 nm) functioning as
And n-type polycrystalline silicon electrode 1 functioning as upper electrode
107 are provided in order from the bottom. Also, for each fine particle
In the scattering region 1102a, silicon fine particles 1104 are
SiO as an edge_Two 1105. charge
Portion (matrix) of the holding region 1102 excluding fine particles
Is a semiconductor with a larger band gap than fine particles
Is also good. Note that SiO_Two The thickness of the film 1106 is 5 to 20 n.
m, the dispersion density of the silicon fine particles 1104 is 1 × 10 ^Fifteenc
m^-3~ 1 × 10²⁰cm^-3It is preferable to set the degree.

As shown in FIG. 9, unlike the first embodiment, in the fifth embodiment, silicon fine particles 110
The grain size of No. 4 continuously decreases from the portion adjacent to the p-type silicon substrate 1101 to the portion adjacent to the SiO ₂ film 1106. In the charge holding region 1102, the particle size of the silicon fine particles 1104 is about 20 nm at a position adjacent to the p-type silicon substrate 1101, while the particle size of the silicon fine particles 1104 is at a position adjacent to the SiO ₂ film 1106. Preferably, the thickness is about 1 nm. In the charge holding region 1102, there is no interface.

—Process of Manufacturing Semiconductor Device According to Fifth Embodiment— Next, a process of manufacturing a semiconductor device according to the fifth embodiment will be described. First, in a sputtering apparatus provided with a p-type silicon substrate 1101, silicon tablets are arranged on SiO ₂ , and accelerated ions collide with the tablets. The atoms and molecules repelled by the impact at this time are deposited on the p-type silicon substrate 1101. After that, heat treatment of the substrate is performed. Next, after the amount of the silicon tablet on SiO ₂ is reduced and sputtering is performed, the substrate is heat-treated at a temperature lower than the substrate temperature in the previous heat treatment.
Thereafter, in the same manner, deposition by sputtering and growth of silicon fine particles 1104 by heat treatment are repeated. By these steps, the particle size of the silicon fine particles 1104 in the SiO ₂ 1105 on the p-type silicon substrate 1101 is reduced from the position adjacent to the p-type silicon substrate 1101 by S
The film continuously reduced toward a portion adjacent to the iO ₂ film 1106, that is, several fine particle dispersion regions 110.
The charge holding region 1102 made of 2a is formed. next,
After setting the substrate on the susceptor in the chamber of the CVD apparatus and depositing the SiO ₂ film 1106 on the charge holding region 1102, the n-type polycrystalline silicon electrode 1107 is deposited on the SiO ₂ film 1106 in the same chamber. I do.

Note that the charge holding region 1102 is stored in one CV
Even if the charge holding region 1102 is formed by the D method,
The particle size of the silicon fine particles 1104 in the iO ₂ 1105 is
SiO ₂ from a portion adjacent to the p-type silicon substrate 1101
A film that continuously decreases toward a portion adjacent to the film 1106 can be used.

The particle diameter of the portion of the charge holding region 1102 close to the n-type polycrystalline silicon electrode 1107 is set to 3
nm or less so that the n-type polycrystalline silicon electrode 11
A portion near 07 can also have a function as an insulating film. In this case, in the third embodiment, it does not form part of the SiO ₂ film 1106, i.e., a portion of the thickness of the SiO ₂ film 1106 substantially 0
It is also possible to use

—Electron Injection / Holding / Pull-Out Mechanism of Semiconductor Device According to Fifth Embodiment—In the fifth embodiment, the particle size of silicon fine particles 1104 decreases as the position increases above fine particle dispersion region 1102. Therefore, the average distance between the silicon microparticles 1104 increases. Therefore, the capacitance of the silicon fine particles 1104 decreases as the position increases above the charge holding region 1102. That is,
The capacitance of the silicon microparticles 1104 increases as the distance from the p-type silicon substrate 1101 decreases. Therefore, since the tunnel barrier is thicker, electron injection is less likely to occur in the silicon fine particles 1104 closer to the n-type polycrystalline silicon electrode 1107.

In particular, in the semiconductor device according to the fifth embodiment, unlike the conventional semiconductor device using a plurality of silicon fine particles, a large number of quantized silicon having a large discrete energy width in the charge holding region 1102. By providing the fine particles 1104, spontaneous emission of accumulated electrons can be effectively suppressed, and electrons can be held in the silicon fine particles 1104 for a long time. Also,
Since the silicon microparticles 1104 are quantized, it is easy to control the injection and emission of electric charges by voltage.

Therefore, the semiconductor device according to the fifth embodiment is more reliable than the conventional semiconductor device and the semiconductor device according to the first embodiment in responding to a demand for long-term record keeping.

In the semiconductor device according to the fifth embodiment, like the semiconductor device according to the first embodiment,
Silicon fine particles 1104 having various particle sizes are made of SiO ₂
Since it is diffused in 1105, electrons are automatically and selectively injected from silicon microparticles 1104 which are easy to inject when voltage is applied, and electrons are held by silicon microparticles 1104 in which electrons are most easily held. . Therefore, in the semiconductor device according to the fifth embodiment, the first
Since it is not necessary to control the thickness of the tunnel oxide film and the particle size of the silicon fine particles 1104 similarly to the semiconductor device according to the first embodiment, the fifth embodiment is more effective than the conventional semiconductor device manufacturing process.
The manufacturing process of the semiconductor device according to the embodiment is easier.

Further, in the semiconductor device according to the fifth embodiment, similarly to the semiconductor device according to the first embodiment, silicon fine particles 1104 having various capacitances exist in the charge holding region 1102. Therefore, electron injection can be performed with a minimum voltage necessary to realize a certain electron holding period (recording time). In addition, charge erasing can be performed with a minimum necessary voltage having the same magnitude.

In the fifth embodiment, the particle size of the silicon fine particles 1104 is different from that of the p-type silicon substrate 1101.
From the portion adjacent to the SiO ₂ film 1106 to the portion adjacent to the SiO ₂ film 1106. In the charge holding region 1102, there is no interface. However, it is also possible to provide a portion in the charge holding region 1102 such that the particle size of the silicon fine particles 1104 does not change continuously. Further, in the charge holding region 1102, the surface where the composition of the portion excluding the fine particles of the charge holding region 1102 changes above and below the surface, the surface where the particle size, dispersion density, or composition of the silicon fine particles 1104 changes above and below the surface, etc. Can be provided. Note that there may be a plurality of interfaces. Further, the silicon fine particles 1104 may be divided into a plurality of fine particle groups each including the silicon fine particles 1104 having a common distance from the p-type silicon substrate 1101. Also in these cases, each silicon fine particle 11
Since the capacitance between the elements 04 is not constant, substantially the same effects as in the fifth embodiment can be obtained.

Sixth Embodiment Structure of Semiconductor Device According to Sixth Embodiment FIG. 10 is a sectional view showing a semiconductor device according to a sixth embodiment. As shown in FIG. 10, the semiconductor device according to the sixth embodiment has a MIS transistor structure. In this semiconductor device, a p-type silicon substrate 111
1, a charge holding region 1113 composed of several fine particle dispersion regions 1113a, a gate insulating film 1117 composed of a SiO ₂ film, and an n-type polycrystalline silicon electrode 1118 functioning as a gate electrode are sequentially stacked from below. In each fine particle dispersion region 1113a, silicon fine particles 1115 are dispersed in SiO ₂ 1116 which is an insulator. In the sixth embodiment, the second embodiment is different from the sixth embodiment in that the particle size of the silicon fine particles 1115 continuously decreases from a portion adjacent to the p-type silicon substrate 1111 to a portion adjacent to the gate insulating film 1117. Is different from the embodiment. Also, a p-type silicon substrate 111 serving as a base
An n-type diffusion region 1112 is provided in a region located on both sides of the n-type polycrystalline silicon electrode 1118 in 1.
Further, a metal electrode 1119 functioning as a source / drain electrode is provided on the n-type diffusion region 1112. A portion (matrix) of the charge holding region 1113 excluding the fine particles may be a semiconductor having a larger band gap than the fine particles.

—Process of Manufacturing Semiconductor Device According to Sixth Embodiment— Next, a process of manufacturing a semiconductor device according to the sixth embodiment will be described. After a semiconductor substrate similar to that of the fifth embodiment is formed, a charge holding region 1113, a gate insulating film 1117, and an n-type polycrystalline silicon electrode 1118 are formed on a p-type silicon substrate 1111 by formation of respective films, photolithography, and etching. To form Next, after an n-type diffusion region 1112 is formed by ion implantation, a metal electrode 1119 is formed by sputtering and etching. Thus, the semiconductor device according to the sixth embodiment can be manufactured.

<< Characteristics of Semiconductor Device According to Sixth Embodiment >> Also in the sixth embodiment, the capacitance of the silicon fine particles 1115 decreases as the distance from the p-type silicon substrate 1111 decreases. Therefore, according to the same principle as in the fifth embodiment, it is possible to inject electrons into the silicon fine particles 1115, hold electrons in the silicon fine particles 1115, and extract electrons from the silicon fine particles 1115.
As described above, the semiconductor device according to the sixth embodiment has a MIS transistor structure. further,
In the sixth embodiment, silicon fine particles 1115 for retaining electrons are provided in SiO ₂ 1116 between a p-type silicon substrate 1111 and an n-type polycrystalline silicon electrode 1118. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon fine particles 1115. By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

In particular, also in the sixth embodiment, by providing a large number of quantized silicon fine particles 1115 having a large discrete energy width in the charge holding region 1113, spontaneous emission of accumulated electrons is effectively suppressed. In addition, electrons can be held in the silicon microparticles B for a long time. In addition, since the silicon microparticles 1115 are quantized, it is easy to control the injection and release of electric charges by voltage.

Therefore, the semiconductor device according to the sixth embodiment can hold charges in the charge holding region 113 for a long time by effectively suppressing the spontaneous emission of the stored charges, so that the semiconductor device having high reliability can be obtained. Becomes Therefore, the semiconductor device according to the sixth embodiment can be highly reliable in meeting the demand for long-term record keeping while satisfying the demand for high-speed operation and reduction in operation power consumption in the device.
Furthermore, in the sixth embodiment, since a basic memory operation is realized by a single element, high-density integration is possible.

In the semiconductor device according to the sixth embodiment, like the semiconductor device according to the fifth embodiment,
Since it is not necessary to control the thickness of the tunnel oxide film, the manufacturing process of the semiconductor device according to the sixth embodiment is easier than the conventional semiconductor device manufacturing process.

In the sixth embodiment, a region where the silicon fine particles 1115 do not exist may be provided on or above at least one of the n-type diffusion regions 1112. This can prevent a current short-circuited through the silicon fine particles 1115 from flowing between the n-type diffusion regions 1112 when a voltage is applied to the n-type diffusion region 1112.

In the sixth embodiment, a layer made of silicon fine particles 1115 is added to some portions in FIG.
Can be divided in a direction perpendicular to the section shown in FIG.
This also allows the current short-circuited through the silicon fine particles 1115 when a voltage is applied to the n-type diffusion region 1112 to be increased.
Flow between the n-type diffusion regions 1112 can be prevented.

(Seventh Embodiment) —Structure of Semiconductor Device According to Seventh Embodiment— FIG. 11 is a cross-sectional view of a semiconductor device according to a seventh embodiment. In this semiconductor device, the p-type silicon substrate 11
21, a charge retention region 1122 (about 30 nm thick) composed of several fine particle dispersion regions 1122 a, a SiO ₂ film 1126 (20 nm thick) functioning as an insulating film
m) and an n-type polycrystalline silicon electrode 1127 functioning as an upper electrode are provided in order from the bottom. A portion (matrix) of the charge holding region 1122 other than the fine particles may be a semiconductor having a larger band gap than the fine particles. Note that the thickness of the SiO ₂ film 1126 is preferably 5 to 20 nm.

As shown in FIG. 11, unlike the first, third, and fifth embodiments, in the seventh embodiment, the SiGe fine particles 1124 (particle diameters 1 to 2)
About 0 nm, dispersion density 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ c
m ⁻³ ) is dispersed in SiO ₂ 1125 which is an insulator. The proportion of Ge in the composition of the SiGe fine particles 1124 continuously increases from the portion adjacent to the p-type silicon substrate 1121 to the portion adjacent to the SiO ₂ film 1126. In the charge holding region 1122, at a position adjacent to the p-type silicon substrate 1121, the proportion of Ge in the composition of the SiGe fine particles 1124 is almost 0%, while the proportion of Ge in the composition of the SiGe fine particles 1124 is almost zero. 10
0%. In the charge holding region 1122,
There is no interface.

—Manufacturing Process of Semiconductor Device According to Seventh Embodiment— Next, a manufacturing process of a semiconductor device according to the seventh embodiment will be described. First, in a sputtering apparatus provided with a p-type silicon substrate 1121, SiO ₂ , Si, and G
Accelerated ions collide with each of e. However, the ratio of the amount of deposited SiO _2, Si, and Ge, in the sputtering apparatus is adjusted by opening and closing of the shutter provided for the SiO _2, Si, and Ge, respectively.
Using these shutters, while increasing the ratio of the amount of Ge deposited to Si, the atoms and molecules repelled by the impact at this time are deposited on the p-type silicon substrate 1121. After that, heat treatment of the substrate is performed. By these steps, the proportion of Ge in the composition of the SiGe fine particles 1124 on the p-type silicon substrate 1121 is changed from the position adjacent to the p-type silicon substrate 1121 to the SiO ₂ film 1
A charge holding region 1122 composed of several fine particle dispersion regions 1122a is formed so as to increase continuously toward a portion adjacent to 126. Then, the substrate was placed on a susceptor in a chamber of a CVD apparatus, after depositing a SiO ₂ film 1126 on the charge holding region 1122, in the same chamber, n-type polycrystalline silicon electrodes 1127 a SiO ₂ film 1126 Deposit on top.

—Electron Injection / Hold / Extraction Mechanism of Semiconductor Device According to Seventh Embodiment— In the semiconductor device according to the seventh embodiment, SiGe
Ratio of Ge in composition of fine particles 1124 (Ge
The content) decreases as the distance from the p-type silicon substrate 1121 decreases, and its electron affinity is small, and the sum of the electron affinity and the band gap is large. Thereby, the barrier height of the surrounding SiO ₂ 1125 for electrons and holes decreases as the distance from the silicon substrate decreases. This relationship will be described in an embodiment described later. Therefore, SiGe fine particles 1 having a large Ge content
Since the SiGe fine particles 1124 having a small Ge content exist between the SiGe fine particles 1124 and the p-type silicon substrate 1121, the charge transfer between the SiGe fine particles 1124 having a large Ge content and the p-type silicon substrate 1121 is: This is easily performed via the SiGe fine particles 1124 having a small Ge content.

In particular, in the semiconductor device according to the seventh embodiment, unlike the conventional semiconductor device using a plurality of silicon fine particles, many quantized SiGe having a large discrete energy width in the charge holding region 1122. By providing the fine particles 1124, spontaneous emission of accumulated electrons can be effectively suppressed, and electrons can be retained in the SiGe fine particles 1124 for a long time. Also,
Since the SiGe fine particles 1124 are quantized, it is easy to control the injection and release of electric charges by voltage.

Therefore, in the semiconductor device according to the seventh embodiment, as in the first embodiment, spontaneous emission of accumulated electrons is effectively suppressed, and SiGe fine particles 1124 are prevented.
Inside, electrons can be held for a long time.

FIG. 14 is a band diagram of a semiconductor device according to the seventh embodiment. Here, the fine particle dispersion region 1
In 125, actually, many SiGe fine particles 11
24, but for the sake of simplicity, the SiGe fine particles 1124 are moved from a portion adjacent to the p-type silicon substrate 1121 to a portion adjacent to the SiO ₂ film 1126.
In this order, silicon microparticles A, silicon microparticles B, silicon microparticles C, and silicon microparticles D are used. Therefore, in FIG. 14, the regions of silicon fine particles A, B, C, D, Si
The band structure in the region of O ₂ 1125 is shown.

In general, in SiGe, as the proportion of Ge in the SiGe composition increases, the band gap, which is the forbidden band width between the valence band and the conduction band, becomes smaller. Here, as described above, SiGe
The proportion of Ge in the composition of the fine particles 1124 is p
It increases continuously from the portion adjacent to the mold silicon substrate 1121 to the portion adjacent to the SiO ₂ film 1126. Therefore, as shown in FIG. 14, the band gap becomes smaller in the order of silicon fine particles A, silicon fine particles B, silicon fine particles C, and silicon fine particles D. At the same time, the electron affinity increases, and the sum of the electron affinity and the band gap decreases. Therefore, the tunnel barrier (barrier height) for electrons and holes increases in this order. Therefore, in this order, it becomes difficult to inject electrons due to the tunnel process, but the ability to retain electrons increases.

Therefore, the semiconductor device according to the seventh embodiment is more reliable than the conventional semiconductor device and the semiconductor device according to the first embodiment in responding to a demand for long-term record keeping.

In the semiconductor device according to the seventh embodiment, like the semiconductor device according to the first embodiment,
SiGe fine particles 1124 having various particle sizes are made of SiO ₂
Electrons are automatically and selectively injected from SiGe fine particles 1124 which are easy to inject when voltage is applied because they are diffused in 1125, and electrons are held by SiGe fine particles 1124 in which electrons are most easily held. . Therefore, in the semiconductor device according to the seventh embodiment, the first
Since the thickness of the tunnel oxide film and the particle size of the SiGe fine particles 1124 do not need to be controlled in the same manner as the semiconductor device according to the first embodiment, the seventh embodiment has a seventh step compared to the conventional semiconductor device manufacturing process.
The manufacturing process of the semiconductor device according to the embodiment is easier.

Further, in the semiconductor device according to the seventh embodiment, similarly to the semiconductor device according to the first embodiment, various capacitances of Si are stored in the charge holding region 1122.
The presence of the Ge microparticles 1124 makes it possible to perform electron injection with a minimum voltage required to realize a certain electron holding period (recording time). In addition, charge erasing can be performed with a minimum necessary voltage having the same magnitude.

In order to control the height of the tunnel barrier by changing the energy level of the fine particles, the Ge composition is changed using SiGe fine particles, and the Cd composition or the Te content is changed using a mixed crystal such as ZnCdS or ZnSTe. Other material systems can be used, such as changing the composition.

[0159] In addition, in place of the SiO ₂ 1125 Si _x O
_y N _z or the like to vary the N composition with (4x = 2y + 3z), it is also possible to control the barrier height by altering the electron affinity or-conduction band energy of the material of the surrounding particles. That is, by increasing the value of y in Si _x O _y N _z, the greater the band gap, electron affinity smaller, also because the sum increases the electron affinity and band gap, the greater the barrier height . Thereby, the same effect as described above can be obtained.

Further, the dispersion density of the fine particles near the n-type polycrystalline silicon electrode 1127 in the charge holding region 1122 is set to a sufficiently small value of 1 × 10 ¹⁷ cm ⁻³ or less, or By making the diameter sufficiently small, that is, 3 nm or less, a portion near the n-type polycrystalline silicon electrode 1127 in the charge holding region 1122 can also have a function as an insulating film. In this case, in the third embodiment, S
not forming a part of the iO ₂ film 1126,
It is also possible to make the thickness of a part of the SiO ₂ film 1126 substantially zero.

Note that, in the charge holding region 1122,
There is no interface. However, it is also possible to provide a portion in the charge holding region 1122 where the band gap does not change continuously. Further, in the charge holding region 1122, the surface where the composition of the portion excluding the fine particles of the charge holding region 1122 changes above and below the surface, and the fine particles 112
It is also possible to provide a surface where the particle diameter, dispersion density or composition changes, a surface where the band gap of the fine particle dispersion region changes, and other interfaces. Note that there may be a plurality of interfaces. Further, the silicon fine particles 1124 have a common distance from the p-type silicon substrate 1121.
The fine particles may be grouped into a plurality of fine particle bodies composed of 124. Also in these cases, since the capacitance between the fine particles 1124 is not constant, substantially the same effects as in the seventh embodiment can be obtained.

As an example of a semiconductor device having an interface, FIG. 15 shows a semiconductor device having a plurality of SiGe fine particles 1124 and a plurality of fine particle groups 1128 arranged in the charge holding region 1122 in order from below the substrate. FIG. In this semiconductor device, since the proportion of Ge in the SiGe composition increases for each fine particle group 1128 in order from below the substrate, the tunnel barrier (barrier height) increases in this order. .

(Eighth Embodiment)-Structure of Semiconductor Device According to Eighth Embodiment-FIG. 12 is a sectional view showing a semiconductor device according to an eighth embodiment. As shown in FIG. 12, the semiconductor device according to the eighth embodiment has a MIS transistor structure. In this semiconductor device, the p-type silicon substrate 113
1, a charge retention region 1133 composed of several fine particle dispersion regions 1133a, a gate insulating film 1137 composed of a SiO ₂ film, and an n-type polycrystalline silicon electrode 1138 functioning as a gate electrode are sequentially stacked from below. Unlike the second, fourth, and sixth embodiments, in the eighth embodiment, each of the fine particle dispersion regions 1133a uses SiG
e fine particles 1135 are dispersed in SiO ₂ 1136 which is an insulator. The proportion of Ge in the composition of the SiGe fine particles 1135 is determined by the p-type silicon substrate 11.
It continuously increases from a portion adjacent to the portion 31 to a portion adjacent to the SiO ₂ film 1137. An n-type diffusion region 1132 is provided in a region located on both sides of n-type polycrystalline silicon electrode 1138 in p-type silicon substrate 1131 serving as a base. Further, the n-type diffusion region 11
On 32, a metal electrode 1139 functioning as a source / drain electrode is provided. Charge holding region 1133
The portion (matrix) excluding the fine particles may be a semiconductor having a band gap larger than the fine particles.

-Manufacturing Process of Semiconductor Device According to Eighth Embodiment-Next, a manufacturing process of the semiconductor device according to the eighth embodiment will be described. After the same semiconductor substrate as that of the seventh embodiment is formed, the charge holding region 1133, the gate insulating film 1137, and the n-type polycrystalline silicon electrode 1138 are formed on the p-type silicon substrate 1131 by forming each film, photolithography, and etching. To form Next, after an n-type diffusion region 1132 is formed by ion implantation, a metal electrode 1139 is formed by sputtering and etching. Thus, the semiconductor device according to the eighth embodiment can be manufactured.

{Characteristics of Semiconductor Device According to Eighth Embodiment} In the eighth embodiment as well, the Ge content of SiGe fine particles 1135 decreases as the distance from p-type silicon substrate 131 decreases. Therefore, according to the same principle as in the seventh embodiment, injection of electrons into the SiGe fine particles 1135
The retention of electrons in the iGe fine particles 1135 and the extraction of electrons from the SiGe fine particles 1135 can be performed.
As described above, the semiconductor device according to the eighth embodiment has a MIS transistor structure. further,
In the eighth embodiment, SiGe fine particles 1 holding electrons
135 is provided in the SiO ₂ 1136 between the p-type silicon substrate 1131 and the n-type polycrystalline silicon electrode 1127. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the SiGe fine particles 1135.
By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

In particular, also in the eighth embodiment, by providing a large number of quantized SiGe fine particles 1135 having a large discrete energy width in the charge holding region 1133, spontaneous emission of accumulated electrons is effectively suppressed. In addition, electrons can be held in the silicon microparticles B for a long time. Further, since the SiGe fine particles 1135 are quantized, it is easy to control the injection and release of electric charges by the voltage.

Therefore, the semiconductor device according to the eighth embodiment can hold charges in the charge holding region 1133 for a long time by effectively suppressing spontaneous emission of the stored charges, so that the semiconductor device has high reliability. Becomes Therefore, the eighth
The semiconductor device according to the embodiment can satisfy the demands for high-speed operation and low power consumption in the device, and can be highly reliable in response to the demand for long-term record keeping. Furthermore, in the eighth embodiment, since a basic memory operation is realized by a single element, high-density integration is possible.

In the semiconductor device according to the eighth embodiment, like the semiconductor device according to the seventh embodiment,
Since it is not necessary to control the thickness of the tunnel oxide film, the manufacturing process of the semiconductor device according to the eighth embodiment is easier than the conventional semiconductor device manufacturing process.

In the eighth embodiment, a region where SiGe fine particles 1135 do not exist may be provided on or above at least one of n-type diffusion regions 1132. This can prevent a current short-circuited through SiGe fine particles 1135 from flowing between n-type diffusion regions 1132 when a voltage is applied to n-type diffusion region 1132.

In the eighth embodiment, the SiG
The layer composed of e-particles 1135 was
Can be divided in a direction perpendicular to the section shown in FIG.
With this, the current that has been short-circuited through the SiGe fine particles 1135 when a voltage is applied to the n-type diffusion region 1132,
Flow between the n-type diffusion regions 1132 can be prevented.

(Modifications of First to Eighth Embodiments) In the first to eighth embodiments, electrons have been described as an example of charges injected and accumulated in silicon fine particles. Then, holes can be injected and accumulated.

Further, in the first to eighth embodiments, the insulator sidewalls are formed on the sides of the gate electrode and the gate insulating film by utilizing the so-called LDD structure generally employed in the fine MISFET. For example, by forming a source / drain region after forming a silicon oxide film) to secure a wide space between the source / drain region and the fine particles, it is possible to change the fine particles from the source / drain regions when not desired. Leakage of charges can be reliably prevented.

—Substrate— In the above-described embodiment, a p-type silicon substrate is used as the substrate.
A substrate using an s substrate or another semiconductor material can also be used.

In the above-described embodiment, since a p-type silicon substrate is used as the substrate, a high-precision silicon-based process technology can be used, and high-density integration of semiconductor elements can be achieved.

Further, at least one of a silicon oxide film, a silicon nitride film and a silicon oxynitride film may be provided on the substrate. These films will function as tunnel films.

{Particles around the Particles (Matrix) and Gate Insulating Film} In the above embodiments, SiO ₂ is used as the members around the particles (matrix) and the gate insulating film. Any material that can function as a tunnel barrier between and between a plurality of fine particles can be used instead of SiO ₂ . This member functioning as a tunnel barrier has a property of blocking a thermal diffusion current but transmitting a tunnel current, and has a barrier height of at least 100 meV or more as compared with a semiconductor substrate and fine particles. It is preferable that

Here, the insulator material is SiO ₂ , S
i ₃ N ₄ , Al ₂ O ₃ , CeO _{2 and the} like are particularly suitable.
Further, a film having a composition and that mixed a combination of these insulating films, for _{example, Si x O y N z (} 4x = 2y
+ 3z) can also be used. As a semiconductor material, C (diamond), AlN, Ga
N, AlP, GaP, ZnO, ZnS, MgO, MgS
And mixed crystals thereof are suitable.

The members (matrix) around the fine particles
The material of the gate insulating film is not uniform, and may differ depending on the position.

Fine Particles In the first to eighth embodiments, silicon fine particles or SiGe fine particles are used as fine particles. However, silicon microcrystals, SiGe microcrystals, amorphous silicon, single crystal silicon, and other materials are used. The semiconductor or metal can be used as fine particles.

When silicon particles are used as the fine particles, the silicon particles can be used at a high temperature during the manufacturing process.
Since it is stable and hard to be contaminated, a highly accurate silicon process technology can be easily applied. When metal particles are used as fine particles, high-quality fine particles having a uniform particle size can be easily and uniformly formed with a high in-plane density.

When metal particles are used as the fine particles,
Although the quantization does not occur as described above, the potential rise according to the capacitance, the charge transfer and the change in the charge holding characteristic according to the barrier height occur, and the same effect as the above-described embodiment is obtained. can get.

When a plurality of fine particles are a semiconductor having a band gap of 2.0 eV or more, the difference between the energy levels of the fine particles increases, thereby increasing the effect of confining charges. Furthermore, when an insulator such as SiO ₂ is used as a member around the fine particles, and the plurality of fine particles are a semiconductor having a band gap of 2.0 eV or more, the height of the tunnel barrier is reduced. Therefore,
At this time, the interval between the fine particles can be increased while securing the tunnel current. Therefore, the capacity of the fine particles holding the electric charge is reduced.

Here, semiconductors having a band gap of 2.0 eV or more include GaN, GaP, GaAs,
AlAs, ZnO, ZnS, ZnSe, CdS, ZnT
e, SiC and the like and mixed crystals of these semiconductors.

In the above embodiment, the fine particles
Degree 1 × 10^Fifteencm^-3From 1 × 10 ²⁰cm^-3Is between
In this way, the charge can be effectively retained in the fine particles,
In addition, detection of the presence or absence of charges is also easy, which is preferable.

Further, in the above embodiment, the shape of the fine particles may be flat. In particular, when fine particles are formed not only by sputtering but also by CVD,
The element manufacturing process can be facilitated. When the shape of the fine particles is flat, the capacitance of the fine particles can be increased. In this case, the fine particles are more likely to be present near the straight line connecting the fine particles for holding the electric charge and the p-type silicon substrate. Charge transfer via the intervening fine particles is more likely to occur.

Furthermore, the fine particles may overlap to form a plurality of layers.

-Applications of Semiconductor Devices According to First to Eighth Embodiments- Various applications of the semiconductor devices according to the first to eighth embodiments described above for controlling movement and accumulation of minute electric charges are provided. it can. For example, a scanning probe microscope (SPM),
It is conceivable to use the distribution map as a memory by creating a distribution map of charges in each semiconductor element according to the first to sixth embodiments using the principle of an atomic force microscope (AFM). In this case, the semiconductor element may not have the n-type polycrystalline silicon electrode. Further, from among the above-described embodiments, a semiconductor element having a configuration having features of a plurality of embodiments may be used.

In addition, various modifications can be made without departing from the gist of the present invention.

Ninth Embodiment -Structure of Semiconductor Device According to Ninth Embodiment- FIG. 16 is a sectional view of a semiconductor device according to a ninth embodiment. In this semiconductor device, the p-type silicon substrate 20
11, a first tunnel barrier film 2012 (2 nm thick) made of a silicon oxynitride film, a semiconductor film 2013 (5 nm thick) made of a polycrystalline silicon film, and a second tunnel barrier film made of a SiO ₂ film 2014 (2 nm thick)
Insulating film 2016 made of SiO ₂ film (thickness: 20 nm)
And n-type polycrystalline silicon electrode 2 functioning as an upper electrode
017 are provided in order from the bottom. This semiconductor film 20
13 is quantized. A plurality of quantized silicon microparticles 2015 (particle diameter: 5 nm) are embedded between the second tunnel barrier film 2014 and the insulating film 2016. The thickness of the first tunnel barrier film 2012 made of a silicon oxynitride film is 2 to 3 nm, the thickness of the semiconductor film 2013 made of a polycrystalline silicon film is 2 to 8 nm,
The thickness of the second tunnel barrier film 2014 made of an O ₂ film is 2 to 3 nm, the thickness of the insulating film 2016 made of a SiO ₂ film is 5 to ₂₀ nm, and the particle size of the silicon fine particles 2015 is 2 to 3 nm.
8 nm, the in-plane density of the silicon fine particles 2015 is 1 × 10
^It is preferable that the ^{thickness be} about ¹² cm ⁻² to 3 × 10 ¹² cm ⁻² .

-Manufacturing Process of Semiconductor Device According to Ninth Embodiment-Next, a manufacturing process of the semiconductor device according to the present embodiment will be described. First, a first tunnel barrier film 2012 made of a silicon oxynitride film is formed on the p-type silicon substrate 2011 by oxynitriding the p-type silicon substrate 2011 (at a substrate temperature of 800 ° C.) in the presence of a nitrogen compound. Next, a substrate is placed on a susceptor in a chamber of a CVD apparatus, and a semiconductor film 20 made of a polycrystalline silicon film is formed.
13 is deposited on the first tunnel barrier film 2012,
In the same chamber, a second tunnel barrier film 2014 made of a SiO ₂ film is successively deposited on the semiconductor film 2013. Next, with the substrate (substrate temperature: 580 ° C.) placed on the same susceptor in the same chamber, SiH ₄ as a material gas is introduced into the chamber in the CVD apparatus for a short time. As a result, a plurality of silicon microparticles 2015 are formed on the second tunnel barrier film 2014. After that, the p-type silicon substrate 2011 is exposed for a short time in the presence of oxygen or water vapor to oxidize the surface of each silicon microparticle 2015 by a thickness of about 1 nm, thereby insulating each silicon microparticle 2015 with SiO ₂ . . Next, in the same chamber, an insulating film 2016, which is a SiO ₂ film, is deposited on the second tunnel barrier film 2014 and the silicon fine particles 2015.
An n-type polycrystalline silicon electrode 2017 is deposited on the substrate 16. The first silicon fine particles 201 formed by the CVD method are used.
By repeating the formation of 5 and the subsequent oxidation of the surface of the silicon microparticles 2015, the in-plane density of the silicon microparticles 2015 can be increased to an appropriate value.

Next, the semiconductor device of this embodiment and FIG.
The differences in the electron injection / holding / pulling-out mechanism in the conventional semiconductor device shown in FIG.

—Electron Injection / Hold / Extract Mechanism of Semiconductor Device According to Ninth Embodiment— The structure of a conventional semiconductor device and the electron injection / hold / extract mechanism of the semiconductor device are as described in the first embodiment. .

Therefore, the mechanism of electron injection and electron holding in the semiconductor device according to the present embodiment will be described in terms of differences from the conventional semiconductor device.

FIG. 17 is a band diagram of a semiconductor device according to the ninth embodiment. In the silicon microparticles 2015, since the particle diameter of the silicon microparticles 2015 is extremely small, an energy state (energy level) that electrons in the silicon microparticles can take is quantized. Further, since the thickness of the semiconductor film 2013 is extremely small, the energy level of the semiconductor film 13 is quantized and discrete. Therefore, as shown in FIG.
In both 015 and the semiconductor film 2013, the energy level is quantized.

Since the state density of the silicon microparticles 2015 increases as the energy becomes higher, the interval between the energy levels (hereinafter referred to as “discrete energy width”) is generally lower in the energy level. Large in the case, and small when the energy level is higher. Also,
Due to the high state density, the electron transition probability is also high. On the other hand, the discrete energy width of the semiconductor film 2013 is also large when the energy level is low, and is small when the energy level is high. However, the discrete energy width of the semiconductor film 2013 is smaller than the discrete energy width of the silicon microparticles 2015. Therefore, the potential of the portion where the discrete energy width of the semiconductor film 2013 is dense is smaller than the potential of the portion where the discrete energy width of the silicon microparticle 2015 is dense.

In the ordinary tunnel process, it is necessary that the potentials of the energy levels on both sides of the passing barrier layer are the same. Therefore, between the silicon fine particle 2015 and the semiconductor film 2013, when no voltage is applied, the energy level of the silicon fine particle 2015, which is quantized on both sides of the second tunnel barrier film 2014, is one.
Since tunneling occurs only when the potential of one of the semiconductor layers 2013 and one of the energy levels of the semiconductor film 2013 coincide with each other, the probability of the occurrence of tunneling is extremely low. If the capacitance of the silicon fine particles 2015 is sufficiently small, the silicon fine particles 2015-the semiconductor film 201
Only when a voltage is applied such that the potentials of the energy levels quantized between the two become equal, the electron transfer is efficiently performed by the resonance tunneling process, while the electrons in the other cases are not efficiently performed. Movement is suppressed. That is, the silicon fine particles 2015-the semiconductor film 201
The electron transfer between the three can be controlled by an externally applied voltage, and the electrons once injected into the silicon microparticles 2015 are held for a long time.

On the other hand, in the conduction band of the p-type silicon substrate 2011, energy levels, which are energy states that electrons can take, exist almost continuously, and the state density is high. Therefore, the energy level having the same potential is applied to the p-type silicon substrate 2011 for any of the quantized energy levels of the semiconductor film 2013.
Therefore, the tunnel process between the semiconductor film 2013 and the p-type silicon substrate 2011 is not prohibited at least in terms of energy. In addition, since the area of the semiconductor film 2013 is sufficiently large, spatial overlap of state functions is large between the levels of the semiconductor film 2013 and the p-type silicon substrate 2011 with the first tunnel barrier film 2012 interposed therebetween. Therefore, no matter how the voltage applied to the n-type polycrystalline silicon electrode 2017 is changed,
Since a rapid tunneling process occurs between the 13-p-type silicon substrate 2011, the semiconductor film 2013 has the same potential as the p-type silicon substrate 2011. That is, the semiconductor film 2013
-Electron transfer between the p-type silicon substrates 2011 is easy.

FIGS. 18A, 18B and 18C are partial band diagrams respectively showing the energy band states when performing electron injection and electron holding in the semiconductor device of the ninth embodiment. 18 (a), 18 (b) and 18 (c), the illustration of the energy band state of the valence band is omitted for easy understanding.

As shown in FIG. 18A, before a voltage is applied to the n-type polycrystalline silicon electrode 2017, electron transfer between the p-type silicon substrate 2011 and the semiconductor film 2013 or the silicon fine particles 2015 is performed. Does not happen.

However, as shown in FIG. 18B, when a certain positive voltage is applied to the n-type polycrystalline silicon electrode 2017, the empty energy of the semiconductor film 2013 from the p-type silicon substrate 2011 is changed as described above. Electron transfer to a level and electron transfer from the energy level of the semiconductor film 2013 to the empty energy level in the silicon microparticles 2015 easily occur. Here, usually, a plurality of silicon fine particles 2
Since the particle size of 015 varies, silicon fine particles 2
The potential of the quantized energy level of 015 also varies. Therefore, the semiconductor film 2013 can be controlled by the applied constant voltage without strictly controlling the voltage.
Some of the energy levels of the electrons and the energy levels of some of the silicon microparticles 2015 have the same potential. Therefore, the n-type polycrystalline silicon electrode 20
17, a positive voltage is applied to the p-type silicon substrate 2011.
Through the semiconductor film 2013 to form a plurality of silicon fine particles 20
15 can be injected.

Further, the interval between the quantized energy levels (discrete energy width) becomes smaller as the potential becomes larger. Since the high-order dense portions of the energy level group have the same potential and the state density also increases, the silicon fine particles 2 having more higher-order levels can be obtained.
Electron injection into 015 occurs. Further, by sweeping the applied voltage in a certain range or superimposing a high frequency, more electrons can be injected into the silicon microparticles 2015.

As shown in FIG. 18C, when the application of the voltage to the n-type polycrystalline silicon electrode 2017 is stopped after the electron injection into the plurality of silicon fine particles 2015, the potential of the silicon fine particles 2015 rises. The potential of the conduction band of the p-type silicon substrate 2011 decreases. That is, by eliminating the application of the voltage, each energy level of the silicon fine particles, each energy level of the semiconductor film, p
The upper and lower relation of the relative potential of the conduction band of the silicon substrate changes. Note that a plurality of silicon microparticles 2015
After the electron injection into the semiconductor device 2015, the potential of the silicon microparticles 2015 is higher than that before the electron injection (FIG. 18A).

At this time, at the potential when the applied voltage is removed, the potential of the energy level of some of the silicon fine particles 2015 happens to coincide with the potential of the energy level of the semiconductor film 2013, so that the tunnel process is performed. Silicon particles 2015
In some cases, the electrons injected into the semiconductor may be lost. In this respect, it is similar to the conventional semiconductor device. However, in the semiconductor device according to the present embodiment, unlike the conventional semiconductor device, many silicon fine particles 2015 into which electrons are injected.
Does not match the potential of the energy level of the semiconductor film, the electron transfer by the tunnel process between the silicon microparticles 2015 and the semiconductor film 2013 is prohibited. Therefore, electrons are stably held in the majority of the silicon microparticles 2015, so that the semiconductor device according to the present embodiment can hold electrons for a long time.

Contrary to the above, by applying a negative voltage to the n-type polycrystalline silicon electrode 2017, the charge can be erased. That is, the n-type polycrystalline silicon electrode 2
When a sufficiently large voltage at which the potential on the 017 side is negative is applied, when the potential of the energy level of the silicon fine particles 2015 matches the potential of the energy level of the semiconductor film 2013, the semiconductor fine particles 2015
Electrons are extracted to 13. Silicon fine particles 2015
As in the case of electron injection into the semiconductor device, the charge can be erased more efficiently by increasing the applied negative voltage relatively, sweeping the applied voltage, or superimposing a high frequency.

That is, in the semiconductor device according to the present embodiment, unlike the conventional semiconductor device using a plurality of silicon fine particles, the semiconductor film 2013 in which the energy level is quantized is provided in the tunnel barrier film. ,
Electron transfer between the silicon fine particles 2015 and the p-type silicon substrate 2011 can be controlled. Therefore, in the semiconductor device according to the present embodiment, even when the thickness of the second tunnel barrier film 2014 is reduced, unlike the conventional semiconductor device using a plurality of silicon fine particles, spontaneous emission of accumulated electrons is performed. To effectively suppress silicon fine particles 201
5, the electrons can be held for a long time. In addition, since the injection, holding, and extraction of electrons into the fine particles can be reliably controlled by utilizing the above-described effects, the semiconductor device according to the present embodiment requires a high-speed operation of the device and a reduction in power consumption. It can be said that it is a highly reliable one that satisfies the condition and meets the demand for long-term record keeping.

(Tenth Embodiment) —Structure of Semiconductor Element According to Tenth Embodiment— FIG. 19 is a sectional view showing a semiconductor element according to a tenth embodiment. As shown in FIG. 19, the semiconductor device according to the tenth embodiment has a MIS transistor structure using the semiconductor device according to the ninth embodiment. In this semiconductor device, the first tunnel barrier film 20 which is a silicon oxynitride film is formed on the p-type silicon substrate 2071.
73, a semiconductor film 2074 made of a polycrystalline silicon film, S
a _second tunnel barrier film 2075 made of an SiO 2 film, Si
A gate insulating film 2077 made of an O ₂ film and an n-type polycrystalline silicon electrode 2078 functioning as a gate electrode are sequentially stacked from below. The semiconductor film 2074 is quantized. Also, a p-type silicon substrate 2071 serving as a base
An n-type diffusion region (source / drain region) 20 is located in a region located on both sides of n-type polycrystalline silicon electrode 2078 in the middle.
72 are provided. Further, the n-type diffusion region 2072
On top, a metal electrode 2079 functioning as a source / drain electrode is provided. Further, a plurality of quantized silicon fine particles 2076 are embedded between the second tunnel barrier film 2075 and the gate insulating film 2077.

—Manufacturing Process of Semiconductor Device According to Tenth Embodiment— Next, a manufacturing process of the semiconductor device according to the tenth embodiment will be described. After forming the same semiconductor substrate as in the ninth embodiment, the first film is formed on the p-type silicon substrate 2071 by forming each film, photolithography and etching.
Barrier film 2073, semiconductor film 2074, second tunnel barrier film 2075, fine silicon particles 2076, gate insulating film 2077 and n-type polycrystalline silicon electrode 207
8 is formed. Next, after an n-type diffusion region 2072 is formed by ion implantation, a metal electrode 2079 is formed by sputtering and etching. Thereby, the semiconductor device according to the tenth embodiment can be manufactured.

{Characteristics of Semiconductor Device According to Tenth Embodiment} In this embodiment, in accordance with the same principle as in the ninth embodiment, the injection of electrons into silicon fine particles 2076 and the internal , And control of extraction of electrons from the silicon microparticles 2076 can be performed. As described above, the semiconductor device according to the tenth embodiment has a MIS transistor structure. Further, in this embodiment, silicon fine particles 2076 for retaining electrons are provided between the second tunnel barrier film 2075 and the gate insulating film 2077. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon microparticles 2076. Information H (high) and information L (low)
In this case, writing and reading of information can be performed.

Also in this embodiment, as in the ninth embodiment, even if the thickness of the second tunnel barrier film 7205 is reduced, electrons can be retained in the silicon fine particles 2076 for a long time. Becomes possible. Therefore, it can be said that the semiconductor element according to the present embodiment has high reliability in responding to the demand for long-time record keeping while satisfying the demand for high-speed operation and reduction in power consumption in the element. Furthermore, in the present embodiment, since a basic memory operation is realized by a single element, high-density integration is possible.

In this embodiment, a region where the semiconductor film 2074 does not exist may be provided on or above at least one of the n-type diffusion regions 2072. As a result, when a voltage is applied to the n-type diffusion region 2072, the current short-circuited through the semiconductor film 2074 becomes n
Flow between the mold diffusion regions 2072 can be prevented.

In this embodiment, the semiconductor film 2
074 may be divided into several parts in a direction perpendicular to the cross section shown in FIG. In this way, when a voltage is applied to the n-type diffusion region 2072,
4 can be prevented from flowing between the n-type diffusion regions 2072.

(Eleventh Embodiment) —Structure of Semiconductor Device According to Eleventh Embodiment— FIG. 20 is a sectional view of a semiconductor device according to an eleventh embodiment.
It is. In this semiconductor device, the p-type silicon substrate 8
On top of 201_Two First tunnel barrier made of film
Film 2082 (1.5 nm thick), SiO_Two The first consisting of a membrane
2 tunnel barrier film 2084 (2 nm thick), SiO_Two 
Film 2086 (thickness 20 nm) made of and upper electrode
N-type polycrystalline silicon electrode 2087 functioning as
Are provided in order. Also, the first tunnel barrier film 2
082 and the second tunnel barrier film 2084.
Particles consisting of a large number of silicon particles in contact
2083 (particle size: 5 nm) is embedded. This fine grain
Each fine particle of the child group 2083 is quantized. Further
Then, the second tunnel barrier film 2084, the insulating film 2086,
In between, the quantized silicon fine particles 2085 (particle size
5 nm). In addition, each silicon fine
Between the particles 2083, the first and second tunnel barrier films 20
SiO made of the same material as 82, 2084_Two Separated by
Have been. Note that SiO_Two First tunnel consisting of a membrane
The thickness of the barrier film 2082 is 1-2 nm,_Two From the membrane
The thickness of the second tunnel barrier film 2084 is
m, SiO _Two The thickness of the insulating film 2086 is set to 5 to 2
0 nm, the particle size of the silicon fine particles in the fine particle group 2083
3 to 10 nm, the size of silicon microparticles in microparticle group 2083
1 × 10 in-plane density¹³cm^-2From 1 × 10¹⁴cm^-2About
The particle size of the silicon fine particles 2085 is 2 to 5 nm,
The in-plane density of the cone fine particles 2085 is 1 × 10¹²cm^-2From
1 × 10¹³cm^-2It is preferable to set the degree.

—Manufacturing Process of Semiconductor Device According to Eleventh Embodiment— Next, a manufacturing process of the semiconductor device according to the eleventh embodiment will be described. First, a first tunnel barrier film 2082 made of an SiO ₂ film is formed on the p-type silicon substrate 2081 by thermal oxidation (at a substrate temperature of 800 ° C.). Next, SiH ₄ as a material gas is introduced into a chamber in the CVD apparatus at a substrate temperature of 580 ° C. for a short time. Thereby, the first tunnel barrier film 2
082, a fine particle group 2083 is formed. afterwards,
By exposing the p-type silicon substrate 2081 in the presence of oxygen or water vapor for a short time to oxidize the surface of each silicon microparticle 2083 by a thickness of about 1 nm, the silicon microparticles 2083 are insulated from each other by SiO ₂ . Next, in the same chamber, a second tunnel barrier film 2084 made of a SiO ₂ film is continuously formed with the fine particle group 2083.
And deposited on the first tunnel barrier film 2082. Next, with a substrate (substrate temperature: 580 ° C.) placed on the same susceptor in the same chamber, SiH ₄ was used as a material gas.
Is introduced into the chamber in the CVD apparatus for a short time. Thereby, a plurality of silicon fine particles 2085 are formed on the second tunnel barrier film 2084. Thereafter, the p-type silicon substrate 2081 is exposed to oxygen or water vapor for a short time to oxidize the surface of each silicon microparticle 2085 by a thickness of about 1 nm, thereby insulating the silicon microparticles 2085 from each other with SiO ₂ . . Next, in the same chamber, the insulating film 2086 made of the SiO ₂ film is formed into the second tunnel barrier film 2084 and the silicon fine particles 20.
After the deposition on 85, an n-type polycrystalline silicon electrode 2087 is deposited in the same chamber. The formation of the fine particle group 2083 by the CVD method and the subsequent fine particle group 2
By repeating the oxidation of the surface of No. 083, the in-plane density of the fine particle group 2083 can be increased to an appropriate value. The same applies to the in-plane density of the silicon microparticles 2085.

—Electron Injection / Hold / Extraction Mechanism for Semiconductor Device According to Eleventh Embodiment— In the eleventh embodiment, the same principle as that of the first embodiment is used to inject / inject electrons into the silicon microparticles 2085.
Electrons can be held in the silicon fine particles 2085 and electrons can be extracted from the silicon fine particles 2085. This is because, in the present embodiment, the fine particle group 2083 plays a role similar to that of the semiconductor film 2013 in the first embodiment. Therefore, the semiconductor device according to the present embodiment also satisfies the demands for high-speed operation and reduced power consumption, as well as the demands for long-term record keeping, similarly to the semiconductor device device according to the ninth embodiment. It can be said that it is highly reliable.

In this embodiment, silicon fine particles 2085
The silicon fine particles of the fine particle group 2083 are made of the same material. Also, their particle sizes are approximately equal. Therefore, the silicon fine particles 2 for retaining electrons
Since the energy levels of 085 and the energy levels of the silicon microparticles in the microparticle group 2083 are quantized in a quantum box shape under the same conditions, their band structures are similar. Therefore, in the present embodiment, electron injection and electron extraction are more likely to occur due to the tunnel process between the silicon microparticle 2085 and the microparticle group 2083, and therefore, compared to the ninth embodiment, control of electron injection and electron extraction is performed. Becomes easier. On the other hand, silicon fine particles 2
After the electron injection into 085, silicon microparticles 2085
Is higher than before electron injection.
Therefore, even if the silicon microparticles and the silicon microparticles 2085 in the microparticle group 2083 are exactly the same,
Since the potentials of the energy levels are different, spontaneous emission of electrons from the silicon microparticles 2085 is suppressed. However, the configuration of the fine particles of the fine particle group 2083 may be different from the configuration of the fine particles 2085. For example, the fine particles of the fine particle group 2083 may be made of amorphous silicon, and the fine particles 2085 may be made of single crystal silicon.

By changing the energy levels of the silicon microparticles 2085 and the energy levels of the silicon microparticles of the microparticle group 2083, the conditions for injecting electrons, retaining electrons, and extracting electrons are determined. For adjustment, the particle diameter of the silicon fine particles 2085 can be made different from the particle diameter of the silicon fine particles in the fine particle group 2083.

Further, the present embodiment has an advantage over the ninth embodiment in that it is easy to control the fine shape in element fabrication. That is, compared to the quantum well formed by the semiconductor film 2013 in the ninth embodiment, the degree of discretization of each energy level is larger in the quantum box formed by the particle group 2083 in the present embodiment. Therefore, in the present embodiment, even if the size of the silicon fine particles in the fine particle body group 2083 is relatively large, the effect of the quantization is large, so that electrons can be held for a long time. Therefore, in the present embodiment, higher precision is not required in element fabrication than in the ninth embodiment.

In the process of manufacturing a semiconductor device,
The variation in the thickness of the semiconductor film 2013 in the ninth embodiment is easier to suppress than the variation in the particle size of the silicon fine particles in the fine particle group 2083 in the present embodiment. Therefore, the semiconductor device according to the ninth embodiment is more advantageous than the semiconductor device according to the present embodiment in uniformity of characteristics.

In this embodiment, the fine particle group 208
Since the silicon fine particles of No. 3 are in contact with each other, rapid electron transfer between the fine particles in the fine particle group 2083 and the silicon fine particles 2085 and the p-type silicon substrate 2081 is not hindered.

In this embodiment, since the thickness of the first tunnel barrier film 2082 is smaller than the thickness of the second tunnel barrier film 2084, the fine particle group 2083 and the p-type silicon Transfer of electrons between them becomes easier.

In this embodiment, the fine particle group 208
The silicon fine particles 2085
May be larger than the particle size. In this case, since the silicon fine particles of the fine particle body group 2083 are more likely to be present near the straight line connecting the silicon fine particles 2085 and the p-type silicon substrate 2081, the p-type silicon substrate 2081 -the silicon fine particles 2085 Electron transfer via the fine particle body group 2083 between them becomes more likely to occur.

In the present embodiment, the fine particle group 208
By making the in-plane density of the silicon fine particles 3 larger than the in-plane density of the second silicon fine particles 2085, the distance between the silicon fine particles in the fine particle group 2083 is reduced. Also in this case, the fine particle group 20 is located near a straight line connecting the silicon fine particles 2085 and the p-type silicon substrate 2081.
Since 83 silicon microparticles are more likely to be present, electron transfer between the p-type silicon substrate 2081 and the silicon microparticles 2085 via the microparticle group 2083 is more likely to occur.

Twelfth Embodiment -Structure of Semiconductor Device According to Twelfth Embodiment- FIG. 21 is a sectional view showing a semiconductor device according to a twelfth embodiment. As shown in FIG. 21, the semiconductor device according to the present embodiment has an MIS transistor structure.
In this semiconductor device, on a p-type silicon substrate 2091, a first consisting of SiO ₂ film, a second tunnel barrier film 2093,2095, n-type functions as a gate insulating film 2097 and a gate electrode made of SiO ₂ film multi Crystal silicon electrodes 2098 are sequentially stacked from below. Also, n-type polycrystalline silicon electrodes 2098 in the p-type silicon substrate 2091 serving as an underlayer have n
A mold diffusion region 2092 is provided. Further, a metal electrode 2099 functioning as a source / drain electrode is provided on the n-type diffusion region 2092. Also, the first
Tunnel barrier film 2093 and second tunnel barrier film 20
A fine particle group 2094 composed of a large number of silicon fine particles that are in contact with each other is embedded between the fine particle body 95 and the silicon fine particles 95. Each fine particle of the fine particle group 2094 is quantized. Further, the second tunnel barrier film 2095 and the gate insulating film 2
097, the quantized silicon fine particles 209
6 are embedded. The fine particle group 2094
The silicon fine particles may overlap to form a plurality of layers as shown in FIG. In addition, the fine particle group 20
Between the silicon fine particles 94, SiO 2 made of the same material as the first and second tunnel barrier films 2093 and 2095 is used.
Separated by _two membranes.

The structure of the fine particles of the fine particle body group 2094 may be different from the structure of the fine particles 2096.
For example, the fine particles of the fine particle group 2094 may be formed of amorphous silicon, and the fine particles 2096 may be formed of single crystal silicon.

—Manufacturing Process of Semiconductor Device According to Twelfth Embodiment— Next, a manufacturing process of the semiconductor device according to the present embodiment will be described. After forming a semiconductor substrate similar to that of the eleventh embodiment, a first tunnel barrier film 2093, a fine particle group 2094, and a second tunnel are formed on a p-type silicon substrate 2091 by forming respective films, photolithography, and etching. Barrier film 2095, silicon fine particles 2096, gate insulating film 2097, and n-type polycrystalline silicon electrode 2098
To form Next, after forming an n-type diffusion region 2092 by ion implantation, a metal electrode 2099 is formed by sputtering and etching. Thereby, the semiconductor device according to the present embodiment can be manufactured.

<< Characteristics of Semiconductor Device According to Twelfth Embodiment >> In the present embodiment, the same principle as that of the eleventh embodiment is used to inject electrons into silicon microparticles 2096 and to generate electrons in silicon microparticles 2096. Electrons can be extracted from the holding / silicon fine particles 2096. In addition, as described above, the semiconductor device according to the present embodiment has M
It has an IS type transistor structure. Further, in this embodiment, the silicon fine particles 209 for holding electrons are used.
6 is the first and second tunnel barrier films 2093, 2095
And the gate insulating film 2097. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon microparticles 2096. By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

Further, the semiconductor device according to the present embodiment has a high reliability that meets the demand for long-time record holding while satisfying the demand for high-speed operation and reduction in power consumption in the device. Furthermore, in the fourth embodiment, since a basic memory operation is realized by a single element, high-density integration becomes possible.

In this embodiment, a region in which the fine particle group 2094 does not exist may be provided on or above at least one of the n-type diffusion regions 2092. This can prevent a current short-circuited through the fine particle group 2094 from flowing between the n-type diffusion regions 2092 when a voltage is applied to the n-type diffusion region 2092.

In the present embodiment, the layer composed of the fine particle group 2094 can be divided into several portions in a direction perpendicular to the cross section shown in FIG. This also allows the current that has been short-circuited through the layer composed of the fine particle group 2094 when a voltage is applied to the n-type diffusion region 2092 to be n
Flow between the mold diffusion regions 2092 can be prevented.

(Thirteenth Embodiment) —Structure of Semiconductor Device According to Thirteenth Embodiment— FIG. 22 is a sectional view of a semiconductor device according to a thirteenth embodiment. In this semiconductor device, the p-type silicon substrate 2
On 101, a first tunnel barrier film 2102 made of SiO ₂ film (thickness: 1.5 nm), a second tunnel barrier film 2104 made of SiO ₂ film (thickness: 2 nm), SiO ₂
An insulating film 2106 (thickness: 20 nm) made of a film and an n-type polycrystalline silicon electrode 2107 functioning as an upper electrode are provided in this order from the bottom. Further, between the first tunnel barrier film 2102 and the second tunnel barrier film 2104,
A plurality of fine wires 2103 (5 nm in height, 10 nm in width, and 100 nm in length) made of polycrystalline silicon are embedded.
This thin line 2103 is quantized. Further, between the second tunnel barrier film 2104 and the insulating film 2106,
A plurality of quantized silicon fine particles 2105 (particle diameter 5 nm) are embedded. Also, between each thin line 2103,
The first and second tunnel barrier films 2102 and 2104 are separated by an SiO ₂ film made of the same material. The thickness of the insulating film 2106 made 1~2nm the thickness of the first tunnel barrier film 2102 made of SiO _2, the thickness of the second tunnel barrier film 2104 made of SiO ₂ 2 to 3 nm, of SiO ₂ 5-20 nm, silicon fine particles 2
Preferably, the particle diameter of the particles 105 is 2 to 8 nm, and the in-plane density of the silicon fine particles 2105 is about 2 × 10 ¹² cm ⁻² to 6 × 10 ¹² cm ⁻² .

-Manufacturing Process of Semiconductor Device According to Thirteenth Embodiment-Next, a manufacturing process of the semiconductor device according to the present embodiment will be described. First, a first tunnel barrier film 2102 made of SiO ₂ is formed on a p-type silicon substrate 2101 by thermal oxidation (a substrate temperature of 800 ° C.). Next, CVD
After setting a substrate on a susceptor in a chamber of the apparatus and depositing a polycrystalline silicon film having a thickness of 5 nm, a plurality of polycrystalline silicon films are formed on the first tunnel barrier film 2102 by electron beam lithography and dry etching. Is formed. Next, a second tunnel barrier film 2104 made of SiO ₂ is deposited on the thin wire 2103 and the first tunnel barrier film 2102 in the same chamber. Next, with a substrate (substrate temperature: 580 ° C.) placed on the same susceptor in the same chamber, SiH ₄ as a material gas is introduced into the chamber in the CVD apparatus for a short time. Thus, a plurality of silicon fine particles 2105 are formed on the second tunnel barrier film 2104. Thereafter, the p-type silicon substrate 2101 is exposed for a short time in the presence of oxygen or water vapor to oxidize the surface of each silicon fine particle 2105 by a thickness of about 1 nm, thereby insulating the silicon fine particles 2105 from each other with a SiO ₂ film. I do. Next, after an insulating film 2106 made of a SiO ₂ film is deposited on the second tunnel barrier film 2104 and the silicon fine particles 2105 in the same chamber, an n-type polycrystalline silicon electrode 2107 is deposited in the same chamber. I do.
The formation of the silicon fine particles 2105 by the CVD method,
By repeating the subsequent oxidation of the surface of the silicon fine particles 2105, the in-plane density of the silicon fine particles 2105 can be increased to an appropriate value.

—Electron Injection / Holding / Pull-Out Mechanism of Semiconductor Device According to Thirteenth Embodiment— In this embodiment, the same principle as that of the ninth embodiment is used to inject electrons into the silicon microparticles 2105 and silicon microparticles. Retention of electrons in 2105-Silicon fine particles 2
Electrons can be extracted from 105. This is because, in the present embodiment, the thin wire 2103 plays a role similar to that of the semiconductor film 2013 in the ninth embodiment.
Therefore, the semiconductor device according to the present embodiment also includes the ninth semiconductor device.
Like the semiconductor device according to the embodiment, it can be said that the semiconductor device has high reliability in responding to a request for long-time record keeping while satisfying a request for high-speed operation and a reduction in power consumption.

Further, this embodiment has an advantage that the fine shape can be easily controlled in the device fabrication as compared with the ninth embodiment. That is, compared to the quantum well formed by the semiconductor film 2013 in the ninth embodiment, in the quantum wire formed by the thin wire 2103 in the present embodiment, the degree of discretization of each energy level is larger. Therefore, in this embodiment,
Even if the size of the thin wire 2103 is relatively large, the effect of quantization is large, so that electrons can be held for a long time. Therefore, in the present embodiment, higher precision is not required in element fabrication than in the ninth embodiment.

(Fourteenth Embodiment) —Structure of Semiconductor Element According to Fourteenth Embodiment— FIG. 23 is a sectional view showing a semiconductor element according to a fourteenth embodiment. As shown in FIG. 23, the semiconductor device according to the present embodiment has a MIS transistor structure.
In this semiconductor device, the first and second tunnel barrier films 2 made of SiO ₂ are formed on a p-type silicon substrate 2111.
113, 2115, gate insulating film 21 made of SiO ₂
17 and an n-type polycrystalline silicon electrode 2118 functioning as a gate electrode are sequentially stacked from the bottom. Also,
In a region located on both sides of an n-type polycrystalline silicon electrode 2118 in a p-type silicon substrate 2111 serving as a base, n
A mold diffusion region 2112 is provided. Further, a metal electrode 2119 functioning as a source / drain electrode is provided on the n-type diffusion region 2112. Also, the first
Tunnel barrier film 2113 and second tunnel barrier film 21
15, a thin wire 2114 made of polycrystalline silicon
Are embedded multiple times. Although this thin line 2114 is quantized. Further, a plurality of quantized silicon fine particles 2116 are embedded between the second tunnel barrier film 2115 and the gate insulating film 2117. The first and second tunnel barrier films 211 are located between the thin wires 2114.
3, 2115 are separated by an SiO ₂ film made of the same material. Note that the thin wires 2114 may overlap to form a plurality of layers. The direction of each thin line 2114 may not be the same, and may be arbitrary.

—Manufacturing Process of Semiconductor Device According to Fourteenth Embodiment— Next, a manufacturing process of the semiconductor device according to the fourteenth embodiment will be described. After a semiconductor substrate similar to that of the thirteenth embodiment is formed, a first tunnel barrier film 2113, a thin wire 2114, and a second tunnel barrier film are formed on a p-type silicon substrate 2111 by formation of respective films, photolithography, and etching. 2115, silicon fine particles 2116, gate insulating film 2117, and n-type polycrystalline silicon electrode 2118
To form Next, after an n-type diffusion region 2112 is formed by ion implantation, a metal electrode 21119 is formed by sputtering and etching. Thereby, the semiconductor device according to the present embodiment can be manufactured.

{Characteristics of Semiconductor Device According to Fourteenth Embodiment} In the present embodiment, injection of electrons into the silicon fine particles 2116 and electron injection within the silicon fine particles 2116 are performed according to the same principle as in the thirteenth embodiment. Electrons can be extracted from the holding / silicon fine particles 2116. Further, as described above, the semiconductor device according to the fourteenth embodiment has an MIS transistor structure. further,
In the fourteenth embodiment, the silicon fine particles 2116 for holding electrons are formed by the first and second tunnel barrier films 211.
3, 2115 and the gate insulating film 2117. Therefore, the threshold voltage of the element changes depending on the presence or absence of electrons in the silicon fine particles 2116.
By making the level of the threshold voltage correspond to the information H (high) and the information L (low), writing and reading of information can be performed.

Further, the semiconductor device according to the present embodiment has high reliability in responding to the requirement for long-time recording and holding while satisfying the requirement for high-speed operation and reduction in power consumption in the device. Furthermore, in the present embodiment, since a basic memory operation is realized by a single element, high-density integration is possible.

In the present embodiment, a region where no thin line 2114 exists may be provided on or above at least one of the n-type diffusion regions 2112. This can prevent a current short-circuited through the thin wire 2114 from flowing between the n-type diffusion regions 2112 when a voltage is applied to the n-type diffusion region 2112.

Also, in the present embodiment, the thin line 211
The layer made of 4 may be divided into several parts in a direction perpendicular to the cross section shown in FIG. In this case, when a voltage is applied to the n-type diffusion
The current short-circuited through the layer consisting of 114 consists of n
Flow between the mold diffusion regions 2112 can be prevented.

(Fifteenth Embodiment) —Structure of Semiconductor Device According to Fifteenth Embodiment— FIG. 24 is a sectional view of a semiconductor device according to a fifteenth embodiment. In this semiconductor device, the p-type silicon substrate 2
A first tunnel barrier film 2132 (thickness 2 nm) made of a silicon oxynitride film, a semiconductor film 2133 (thickness 5 nm) made of a polycrystalline silicon film, and a second tunnel barrier film 2134 made of SiO ₂ (2 nm thick), S
an insulating film 2136 (20 nm thick) made of iO ₂ and an n-type polycrystalline silicon electrode 2137 functioning as an upper electrode
Are provided in order from the bottom. The semiconductor film 2133 is quantized. A plurality of quantized thin wires 2135 (5 nm in height, 10 nm in width, and 100 nm in length) made of polycrystalline silicon are embedded between the second tunnel barrier film 2134 and the insulating film 2136. The thickness of the first tunnel barrier film 2132 made of silicon oxynitride is set to 2 to 3 nm, and the thickness of the semiconductor film 213 made of polycrystalline silicon is increased.
Preferably, the thickness of 3 is ₂ to 8 nm, the thickness of the second tunnel barrier film 2134 made of SiO _{2 is 2} to 3 nm, and the thickness of the insulating film 2136 made of SiO ₂ is 5 to 20 nm.

Manufacturing of the semiconductor device according to the fifteenth embodiment
Manufacturing Process— Next, the manufacturing process of the semiconductor device according to the present embodiment will be described.
explain. First, in the presence of a nitrogen compound, a p-type silicon
Oxynitriding (substrate temperature 800 ° C.)
, Silicon oxynitride on the p-type silicon substrate 2131
A first tunnel barrier film 2132 made of silicon is formed.
Next, the substrate is placed on the susceptor in the chamber of the CVD device.
And a semiconductor film 2133 made of polycrystalline silicon is formed.
After being deposited on the first tunnel barrier film 2132, the same
In the chamber, continuously SiO _Two The second ton consisting of
A tunnel barrier film 2134 is deposited on the semiconductor film 2133.
Next, in the same chamber, a polycrystalline silicon having a thickness of 5 nm is used.
Electron beam lithography and dry
On the first tunnel barrier film 2102 by etching
To form a plurality of fine wires 2103 made of polycrystalline silicon
I do. Next, in the same chamber, the SiO 2_Two Consists of
The insulating film 2136 is formed with the second tunnel barrier film 2134 and the thin film.
After being deposited on the line 2135, the insulating film 2136
Then, an n-type polycrystalline silicon electrode 2137 is deposited.

—Characteristics of Semiconductor Element According to Fifteenth Embodiment— In this embodiment, as in the above-described embodiment, the semiconductor film 2133 made of a polycrystalline silicon film and the thin wire 2135 made of a polycrystalline silicon are , Has been quantized.
Therefore, electron transfer between the fine wire 2135 @ p-type silicon substrate 2131 can be controlled. That is, the thin wire 21
35 and the semiconductor film 213
Since the electron transfer occurs only when the potential of the energy level 3 matches the potential, the spontaneous emission of the electrons accumulated in the fine wire 2135 can be effectively suppressed, and the electrons are retained in the fine wire 2135 for a long time. It becomes possible. Therefore, in the presence of an appropriate electric field, the p-type silicon substrate 2131
Electrons can be easily injected from the thin wire 2135 to the p-type silicon substrate 2131. Therefore, the injection, holding, and extraction of electrons into and from the fine wire 2135 can be reliably controlled by utilizing the above-described effects. Therefore, the semiconductor element according to the present embodiment can operate at high speed and reduce power consumption. This can be said to be a highly reliable one that satisfies the request for long-term record keeping while satisfying the request.

(Modification of Ninth to Fifteenth Embodiments) Ninth
In the fifteenth to fifteenth embodiments, electrons have been described as an example of charges injected and stored in silicon fine particles. However, holes can be injected and stored in the same manner.

—Substrate— In the ninth to fifteenth embodiments, a p-type silicon substrate is used as a substrate. In addition, an n-type silicon substrate, a GaAs substrate, or a substrate using another semiconductor material is used. Can also.

In the first to seventh embodiments, since a p-type silicon substrate is used as a substrate, a high-precision silicon-based process technology can be used, and high-density integration of semiconductor elements is possible. Become.

[0246] - a tunnel barrier film - In the ninth to fifteenth embodiments, the material of the tunnel barrier film, and as the material of the insulating film SiO ₂ is used, etc., Si ₃ N _4, Si _x O _y N _z (4x = 2y
+ 3z), CeO ₂ , ZnS, ZnO, Al ₂ O _{3, and} other insulator materials can also be used.

Here, the tunnel barrier film according to the ninth to fifteenth embodiments refers to a barrier film having a property of blocking a thermal diffusion current but transmitting a tunnel current.

The first and second tunnel barrier films usually have a barrier height of at least 1 eV and a thickness of 50 nm as compared with the upper and lower films sandwiching the tunnel barrier film.
It is desirable that: Further, the thickness of the first and second tunnel barrier films is 1 nm or more and 6 nm or less, and those materials are insulator materials, or the thickness of the first and second tunnel barrier films is Is 3 nm or more 5
It is preferable that the semiconductor material has a band gap of 0 nm or less and has a band gap larger than that of a semiconductor substrate, a plurality of fine particles, a semiconductor film, or a fine wire. This is to make it function as a good tunnel barrier film.

Here, as the insulator material, SiO ₂ , S
i ₃ N ₄ , Al ₂ O ₃ , CeO _{2 and the} like are particularly suitable.
Further, a film having a composition and that mixed a combination of these insulating films, for _{example, Si x O y N z (} 4x = 2y
+ 3z) can also be used. Amorphous S
When using iO ₂ , its thickness is 1 nm to 3 nm.
In particular, good tunnel characteristics can be obtained. S
When i ₃ N ₄ is used, particularly good tunnel characteristics can be obtained if the thickness is between 2 nm and 6 nm. As a semiconductor material, C (diamond), Al
N, GaN, AlP, GaP, ZnO, ZnS, Mg
O, MgS and the like and mixed crystals thereof are suitable.

At this time, the first tunnel barrier film does not directly participate in charge confinement. Therefore, as the material of the first tunnel barrier _{film, Si 3 N 4, Si x} O y N z, CeO
It is preferable to use a material having a higher dielectric constant than SiO ₂ , such as an insulator such as ₂ or a semiconductor material. For the same reason, the thickness of the first tunnel barrier film may be smaller than the thickness of the second tunnel barrier film. When the material of the first tunnel barrier film is an insulator, its thickness is 1 n
m or more and 4 nm or less, or when the material of the first tunnel barrier film is a semiconductor, the thickness is 3 nm or more and 2 nm or less.
It is particularly suitable that the thickness be 0 nm or less.

On the other hand, since the second tunnel barrier film contributes to confinement of electric charges, a material having a relatively low dielectric constant, such as SiO ₂ or C (diamond), is particularly preferable as the material of the second tunnel barrier film. . For the same reason, it is preferable that the thickness of the second tunnel barrier film is larger than the thickness of the first tunnel barrier film. When the material of the second tunnel barrier film is an insulator, its thickness is 1.5
When the material of the second tunnel barrier film is a semiconductor from nm to 6 nm or less, the thickness is particularly suitable from 4 nm to 40 nm.

In the eleventh to fourteenth embodiments, the thickness of a part of the first tunnel barrier film is substantially zero, that is, the semiconductor element is provided without providing a part of the first tunnel barrier film. It can also be provided. This simplifies the manufacturing process of the semiconductor element, and can further increase the capacitance of the silicon fine particles in the fine particle group, the capacitance of the fine wire, or the capacitance of the fine wire. At this time, charge transfer in the semiconductor element is promoted.

—Particles— In the ninth to fourteenth embodiments, as the particles, silicon microcrystals, amorphous silicon, single crystal silicon, and semiconductors of other materials can be used. Further, it may be constituted by any one of them.

When silicon particles are used as the fine particles, the silicon particles can be used at a high temperature during the manufacturing process.
Since it is stable and hard to be contaminated, a highly accurate silicon process technology can be easily applied. When metal particles are used as fine particles, high-quality fine particles having a uniform particle size can be easily and uniformly formed with a high in-plane density.

In the case where the material of the plurality of fine particles is a semiconductor having a band gap of 2.0 eV or more, the difference between the energy levels of the fine particles is increased.
The effect of charge confinement increases. Further, when an insulator such as SiO ₂ is used as the tunnel barrier film, and the material of the plurality of fine particles is a semiconductor having a band gap of 2.0 eV or more, the height of the tunnel barrier is reduced.
Therefore, at this time, the second
The thickness of the tunnel barrier film can be increased. Therefore, the capacity of the fine particles holding the electric charge is reduced.

In the ninth to fourteenth embodiments, the silicon fine particles may have a flat shape. In particular,
When silicon microparticles are formed by sputtering, the process for manufacturing the element can be facilitated. In particular, in the eleventh and twelfth embodiments, when the shape of the silicon fine particles in the fine particle group is a flat shape,
The capacitance of the fine particle group can be increased. In this case, the silicon fine particles of the group of fine particles are more likely to be present in the vicinity of a straight line connecting the silicon fine particles for holding electric charge and the p-type silicon substrate. Is more likely to occur between the silicon microparticles for retaining the charge through the microparticle group.

Furthermore, in the ninth to fourteenth embodiments, the silicon fine particles may overlap to form a plurality of layers.

—Semiconductor Film— In the ninth, tenth, and fifteenth embodiments, a polycrystalline silicon film is used as a semiconductor film. However, a semiconductor made of amorphous silicon, single crystal silicon, or another material may be used. Can also be used. Further, it may be constituted by any one of them. When the semiconductor film is made of an amorphous silicon film or a polycrystalline silicon film, the silicon semiconductor film is stable and hard to be contaminated even at a high temperature in the manufacturing process. Easy to apply.

In the case where the material of the semiconductor film is a semiconductor film having a band gap of 2.0 eV or more, the effect of confining charges is increased by increasing the difference between the energy levels of the fine particles. Furthermore, when an insulator such as SiO ₂ is used as the tunnel barrier film, and the material of the semiconductor film is a semiconductor film having a band gap of 2.0 eV or more, the height of the tunnel barrier is reduced. Therefore, at this time, the thickness of the second tunnel barrier film can be increased while securing the tunnel current, and the manufacturing becomes easy.

—Thin Wires— In the thirteenth and fourteenth embodiments, polycrystalline silicon is used as the thin wires, but amorphous silicon, single crystal silicon, a carbon nanotube, or another material semiconductor may be used as the thin wires. Further, it may be constituted by any one of them. When the fine wire is made of amorphous silicon or polycrystalline silicon, the silicon fine wire is stable and hardly contaminated even at a high temperature in the manufacturing process, so that a high-precision silicon process technology can be easily applied. .

In the case where the material of the fine wire is a semiconductor having a band gap of 2.0 eV or more, the effect of confining charges is increased by increasing the difference between the energy levels of the fine particles. Further, when an insulator such as SiO ₂ is used as the tunnel barrier film and the material of the semiconductor film is a semiconductor having a band gap of 2.0 eV or more, the height of the tunnel barrier is reduced. Therefore, at this time, the thickness of the second tunnel barrier film can be increased while securing the tunnel current. Therefore, the capacity of the fine particles holding the electric charge is reduced.

In the thirteenth and fourteenth embodiments, the thin wires may overlap to form a plurality of layers. Further, the direction of each thin line may not be the same, and may be arbitrary.

Here, semiconductors having a band gap of 2.0 eV or more include GaN, GaP, GaAs,
AlAs, ZnO, ZnS, ZnSe, CdS, ZnT
e, SiC and the like and mixed crystals of these semiconductors.

—In-Plane Density of Fine Particles— In the ninth to fourteenth embodiments, the in-plane density of fine particles is preferably between 1 × 10 ¹¹ cm ⁻² and 1 × 10 ¹³ cm ⁻² . This is because charges can be held effectively and the detection of the presence or absence of charges becomes easy.

In the eleventh and twelfth embodiments,
Is the difference between the first tunnel barrier film and the second tunnel barrier film.
The in-plane density of the first fine particles embedded between them is 1 × 10¹²
cm ^-2And the second tunnel barrier film and the
Port) In-plane of second fine particles embedded between insulating film
More preferably, the density is higher than the density. 2nd particle-1st
This is because charge transfer between fine particles becomes easier.

-Application of Semiconductor Elements According to Ninth to Fifteenth Embodiments- The semiconductor elements according to the ninth to fifteenth embodiments can be applied in various ways to control the movement and accumulation of minute electric charges.
For example, by using a principle of a scanning probe microscope (SPM), in particular, an atomic force microscope (AFM), a distribution diagram of electric charges in each of the semiconductor elements according to the first to seventh embodiments is created, thereby obtaining the distribution. It is conceivable to use the figure as a memory. In this case, n
The type polycrystalline silicon electrode may not be provided. Further, from among the above-described embodiments, a semiconductor element having a configuration having features of a plurality of embodiments may be used.

In addition, various modifications can be made without departing from the gist of the present invention.

(Sixteenth Embodiment) FIG.
It is sectional drawing of the semiconductor element in 16th Embodiment.
As shown in the figure, a p-type silicon base as a semiconductor substrate
On the plate 3011, first act as a barrier against the movement of charges.
Thermally oxidized Si having a thickness of about 2 nm, which is a functional first barrier layer
O_Two A membrane 3012 is provided. Also, the first barrier
Thermally oxidized SiO layer_Two A first fine particle on the film 3012
Silicon fine particles 3013 having a diameter of 2 nm are provided as a body.
Have been. Silicon fine particles as the first fine particles
Acts as a barrier against charge transfer, on top of child 3013
SiO 2 having a thickness of about 2 nm as a second barrier layer_Two Membrane 3
014 are provided. Further, the second barrier layer is provided.
SiO _Two On the membrane 3014, the diameter of the second fine particle
Gold fine particles 3015 of 5 to 8 nm are provided. Also
Insulation is performed on the gold fine particles 3015 as the second fine particles.
10 nm thick SiO as body layer_Two Provided with a film 3016
N-type polycrystalline silicon at the top is the electrode layer
An electrode 3017 is provided.

Here, the diameter of the gold fine particle 3015 as the second fine particle is at least 2.5 times the diameter of the silicon fine particle 3013 as the first fine particle, and the capacitance thereof is the same as that of the silicon fine particle 3013. Larger than the fine particles of No. 1. The electron affinity of the second fine particles is larger than that of the first fine particles, and the sum of the electron affinity and the forbidden band width is smaller than that of the first fine particles.

The silicon fine particles 13 are produced by chemical vapor synthesis.
1 × 10 by (CVD) method¹¹cm ^-2~ 1 × 10¹³c
m^-2Gold particles 3015 are formed with an in-plane density of about
1 × 10 by wafer immersion in gold colloid solution^Tencm^-2
~ 1 × 10¹²cm^-2The in-plane density is fixed.

In the conventional semiconductor device shown in FIG. 57, the number of charges of the fine particles (silicon fine particles 6203) and the semiconductor substrate of the fine particles (p-type silicon The same fine particles (silicon fine particles 6203) / tunnel barrier film (tunnel oxide film 6) are different only in the potential with respect to the substrate 6201).
202) / the tunnel phenomenon in the semiconductor substrate (p-type silicon substrate 6201) system is used. Therefore, it is not easy to greatly change the tunnel current of this system with a low external voltage (upper electrode voltage) to the upper electrode (n-type polycrystalline silicon electrode 6205). For example, if the height or thickness of the tunnel barrier is increased in order to suppress the leak current, the write / erase current also decreases, and the write / erase speed decreases. Although the magnitude of the leak current also depends on the number of charges held in each fine particle, it is considered that the leak current is the smallest when one electron (or hole) is used, and there is little room for improvement.

The potential of the fine particles at the time of writing (or erasing) is determined by the positional relationship between the device structure and the fine particles. Here, the fine particles (silicon fine particles 620)
If the distance between 3) and the upper electrode (the n-type polycrystalline silicon electrode 6205) is reduced, the potential rise of the fine particles during writing increases, so that the writing current can be increased in principle. However, if the particulate matter is brought too close to the upper electrode side, the gate voltage shift at the time of device reading becomes small, and the sensitivity is lowered too much.

In addition, if the capacitance of the fine particles is increased, the potential rise of the fine particles at the time of holding the electric charge can be suppressed, so that there is an effect of suppressing the leak current. However, in practice, if the particle size of the fine particles is increased in order to increase the capacitance of the fine particles, or if the distance between the fine particles and the semiconductor is reduced, the tunnel probability between the fine particles and the semiconductor substrate is increased. As a result, the leakage current increases. In principle, increasing the particle size of the microparticles and increasing the thickness of the tunnel barrier film at the same time may reduce only the leakage current to some extent, but if the size of the microparticles is too large, the in-plane density of the microparticles will decrease. And can no longer hold the required amount of charge to support the sensitivity of the device. Further, if the barrier thickness is too large, the structure becomes close to a flash EEPROM,
Since a large voltage is applied to the barrier film, a problem occurs in that film quality is degraded due to charge transfer. Also, in the manufacturing process, high precision is required for controlling the particle size, the distribution state of the particles, and the barrier thickness in order to obtain a device having a long life.

As described above, with the conventional semiconductor device shown in FIG. 57, it is difficult to realize a device capable of performing a high-speed write / erase operation and capable of recording with a long life. On the other hand, according to the configuration of the semiconductor device of the present embodiment, the leak current at the time of retaining charges can be significantly reduced without lowering the writing / erasing speed as described below.

In this embodiment, the charge transfer between the semiconductor substrate and the first fine particles (silicon fine particles 3013) via the first barrier layer (thermally oxidized SiO ₂ film 3012) and the second barrier First through a layer (SiO ₂ film 3014)
There is a charge transfer between the microparticle (silicon microparticle 3013) and the second microparticle (gold microparticle 3015). The probability of charge transfer through the first barrier layer is determined by the wave function of the state occupied by the electrons of the semiconductor substrate and the density and spatial overlap of the wave function of the empty state of the fine particles. In the semiconductor substrate and the first fine particles, the first fine particles have a much lower density of states and a smaller spread of the wave function.
The charge transfer is substantially controlled by the first fine particles.
Further, since the first fine particles have a smaller particle size than the second fine particles, the state density and the spread of the wave function are small, and the charge transfer between the first fine particles and the second fine particles is also the first fine particles. The particulate matter will dominate. As a result, the charge transfer between the semiconductor substrate and the second fine particle via the first fine particle is mainly governed by the state of the first fine particle. If the particle size of the fine particle 1 is small, the tunnel probability is suppressed and becomes low.

A specific charge injection and charge holding operation of the device of the present invention will be described below. In the writing process at the time of charge injection, a writing voltage is applied to the upper electrode 3017 from the outside to firstly form the first barrier layer (the thermally oxidized SiO ₂ film 301).
The charge is extracted from the semiconductor substrate 3011 by tunneling through 2), and the first fine particles (silicon fine particles 3) are removed.
013). In this process, the potential of the first fine particles and the relationship between the first fine particles and the semiconductor surface are almost the same as those in the writing process of the prior art, and therefore, the first fine particles ( Charge transfer to the silicon fine particles 3013) is possible.

In the present invention, the charge on the first fine particles (silicon fine particles 3013) is further transferred to the second barrier layer (SiO 2
_{The second} fine particles (gold fine particles 3015) move through the _second film 3014). Here, when the particle diameter of the second microparticle is large, the tunnel transition between the first microparticle and the second microparticle is substantially equal to the tunnel transition between the first microparticle and the surface of the semiconductor substrate. Under equivalent conditions. Therefore, when the potential difference is the same, the charge transfer speed from the surface of the semiconductor substrate to the first fine particles (silicon fine particles 3013) and the charge transfer speed from the first fine particles to the second fine particles (gold fine particles 3015) Is about the same. However, in the present embodiment, the potential increase of the first fine particle due to the electric charge is applied between the first fine particle having the electric charge and the second fine particle having no electric charge in addition to the external writing voltage. (ΔV1 = Δq / Cdot1) (Δq is the charge amount, C
In dot1, an electric field is generated due to the capacitance of the first fine particles. The effect of increasing the potential due to the electric charge of the first fine particles (silicon fine particles 3013) having a small capacitance is large, and the first fine particles (silicon fine particles 3013) change from the first fine particles to the second fine particles (gold fine particles 3013).
The charge transfer to 15) will be further accelerated. In the writing process of the present invention, it is necessary to go through two tunnel processes. However, charge transfer from the first fine particles (silicon fine particles 3013) to the second fine particles (gold fine particles 3015) is performed from the semiconductor substrate to the first fine particles. Since the transfer is performed at a speed equal to or higher than the transfer of the charges to the fine particles, the entire charge transfer speed can realize a writing speed equivalent to that of the device according to the prior art. Although the writing process has been described here, the upper electrode 3017
The same applies to the erasing process in which a voltage opposite to the writing voltage is applied to the microparticles to release the accumulated charges from the microparticles.

When the writing voltage is removed from above after the writing is completed, the first fine particles (silicon fine particles 3013)
And the second fine particles (gold fine particles 3015) have potentials corresponding to the respective charges and capacitances. Some of the first fine particles have extra charge, but the first fine particle is adjacent to the semiconductor substrate and has a small capacitance and a large potential rise per charge. Quickly returns to the semiconductor substrate. On the other hand, the second fine particles have a large electrostatic capacitance Cdot2, and therefore have a potential rise (ΔV2 = ΔV2).
q / Cdot2) is suppressed low. On the other hand, the second fine particle itself has a large particle diameter and a large
The low state density of the fine particles of
The probability of charge transfer from the fine particles to the first fine particles is suppressed low, and as a result, the charges accumulated in the second fine particles are held for a long time.

Even if the fine particles are provided in a plurality of layers, if the second fine particles have the same particle diameter as the first fine particles, the second fine particles are more easily removed from the semiconductor substrate. Since they are separated, the capacitance with respect to the semiconductor substrate is reduced, and the above-described effects cannot be obtained.

In the above description, the writing / erasing speed of the device according to the present invention is equal to that of the conventional semiconductor device. However, the effect of suppressing the leak current and stabilizing the charge retention is further utilized to further improve the barrier layer. By reducing the thickness, it is possible to realize a higher writing / erasing speed and a lower writing / erasing voltage.

The state of the first fine particles is quantized, and the energy interval between the quantum levels is equal to the heat energy at room temperature and the second energy.
When the potential is larger than the potential rise of the fine particles, the charge retention can be further stabilized as described below. FIG.
(A)-(c) are schematic diagrams of a band structure near a conduction band when electrons are used as injected charges. FIG. 26 (a)
As shown in (1), the first fine particles (silicon fine particles 3013) are quantized in a state where there is no charge in the fine particles, the ground level 3031 is occupied by electrons, and the first excitation level 3032
Is empty and the energy interval between them is sufficiently larger than the heat energy. When an electric field is applied for writing from the outside, the first excitation level 303 is removed from the semiconductor substrate as shown in FIG.
Electrons are injected into the second fine particles (gold fine particles 3015) by a tunneling process 3033 through 2. Thereafter, when the particle diameter of the second fine particles is large when the external electric field is removed, the Fermi level of the second fine particles is 3 as shown in FIG.
034 is lower than the first excitation level 3032. If the difference between the two is greater than the thermal energy, it becomes difficult to release the charges, and the charges in the second fine particles are stably held. Here, the case where electrons are used as injected charges has been described, but the same effect can be obtained when holes are used.

-Relationship Between Band Structure of Fine Particles and Transfer / Hold of Electric Charge- FIGS. 27A to 27C show a semiconductor substrate (or a semiconductor layer on the substrate) when electrons are used as electric charges. A semiconductor substrate, a first barrier layer, and the like for explaining a more preferable relationship between the voltage level between the fine particles and the charge transfer characteristics.
FIG. 4 is a band diagram showing only conduction band edges of a first fine particle, a second barrier layer, and a second fine particle. FIG. 27A is a diagram showing a state when no voltage is applied. As shown in the figure, in this example, the electron affinity Δe2 of the second fine particle is larger than the electron affinity Δe1 of the first fine particle. As a result, as shown in FIG. 27B, when an electric field is applied between the second fine particle and the semiconductor substrate so that the second fine particle has a higher potential, the first fine particle is removed from the semiconductor substrate. Electrons easily flow through the body to the second particulate body. On the other hand, as shown in FIG. 27 (c), when charges are accumulated in the second fine particles, and as a result, a weak electric field is generated in which the second fine particles have a lower potential, the first fine particles It is difficult to transfer electrons from the particles to the second fine particles.
That is, unless a predetermined high electric field is applied to the semiconductor substrate, it becomes difficult for electrons to move from the first fine particles to the semiconductor substrate via the second fine particles. In other words,
It is easy to hold the electric charge in the second fine particles. Further, since the magnitude of the electron affinity χe2 of the second fine particles is larger than the electron affinity χsm of the semiconductor substrate, the second
It can be suppressed that the potential at the conduction band edge of the fine particles becomes higher than the potential at the conduction band edge of the semiconductor substrate, and the charge retention power is further improved. In particular, since the first fine particles are made of a semiconductor material and the second fine particles are made of a metal material, the effect of suppressing the increase in the potential at the conduction band edge of the second fine particles is large.

On the other hand, when the charges are holes,
As can be easily analogized from (a) to (c), the sum of the electron affinity χe2 of the second fine particle and the forbidden band width gy2 (χe2 +
gy2) is smaller than the sum (χe1 + gy1) of the electron affinity χe1 and the forbidden band width gy1 of the first fine particles, so that the potential increase at the valence band edge of the second fine particles can be suppressed, so that the electric charge is retained. Becomes easier. Also, the sum (の e2 + gy) of the electron affinity χe2 of the second fine particle and the forbidden band width gy2
2) is smaller than the sum of the electron affinity ｇsm of the semiconductor substrate and the forbidden band width gsm (χsm + gsm), so that the effect of suppressing the increase in the potential at the valence band edge of the second fine particles is large.

-Relationship between Particle Size and Ratio of First Fine Particle and Charge Transfer / Retention- Next, the particle size of the first fine particle, and the particle size of the first and second fine particles The effect of the ratio on the charge retention characteristics will be described.

As shown in FIG. 28, the distance between the upper electrode and the conductive layer on the substrate (semiconductor substrate) is tg, the distance between the first and second fine particles in contact with each other is d, Let r1 be the radius of the fine particle, r2 be the radius of the second fine particle, ε be the dielectric constant of the insulator and the barrier layer, and e be the unit charge.

Here, the potential of the conductive layer of the semiconductor substrate is set to 0 V
At the time of charge retention, the potential V of the upper electrode
g is set to 0 V, and charge injection and release are performed by controlling Vg.

First, Vg =
In order to maintain a state without charge as 0, it is necessary that charge is not naturally injected from the semiconductor substrate side to the fine particles by diffusion.

From the conductive layer on the substrate, the first
In the process of injecting the electric charge into the fine particles, the charging energy ΔE1 of the first fine particles is expressed by the following equation: ΔE1 = (e ² / 8πε) · (1 / r 1).

Here, when Vg = 0, the state in which charge is injected into the second fine particle is higher in energy than the state in which no charge is present in the second fine particle. Most of the charge transferred to the body returns to the substrate,
The probability of moving to the fine particles is not high. However, since the semiconductor substrate is not quantized, its state density is high, and charge transfer between the semiconductor substrate and the first fine particles adjacent to the semiconductor substrate is relatively easy to occur.

Therefore, the above-mentioned charging energy ΔE 1 is converted into thermal energy kT (k: Boltzmann constant, T: absolute temperature)
By setting it higher (ΔE1> kT), injection of thermally excited charges can be suppressed. In this case, if the particle size of the first fine particles is 5 nm or less, the charging energy ΔE1 becomes sufficiently larger than the thermal energy kT, and spontaneous injection of electric charges can be prevented. Also,
In the case where long-term charge retention is required, if the particle size of the first fine particles is 2 nm or less, the charging energy ΔE1 becomes 7 times or more the thermal energy kT. At this time, the excitation probability of electrons is 1/1000 or less of the normal value, which is preferable in that the information holding state of the element can be further stabilized.

Next, at the time of writing information in the memory element or the like, an electric field is applied by applying a positive voltage Vg (charge) to the upper electrode, and charges are injected from the substrate side into the second fine particles. . At this time, an electric field is applied to the first microparticles by applying an electric field against the charging energy ΔE1.
It is necessary to move to the second fine particle. Therefore, if the particle size of the first fine particles is too small, the charging energy ΔE1 becomes excessively large, and there is a possibility that the injection of charges is hindered. However, as described above, since the state density of the semiconductor substrate is high, charge transfer between the semiconductor substrate and the first fine particles is relatively easy to occur. Further, by applying Vg (charge), the energy state of the second fine particles is shifted to the first fine particles since the potential is lower in the state where the charges are injected than before the injection of the charges. The charged charges are immediately injected into the second fine particles. As a result, in practice, the lower limit of the particle diameter of the first fine particles is loose, and if the particle diameter is 0.1 nm or more on the order of atomic size, charge injection is possible. It is also possible to use the atom and the level resulting therefrom as the first fine particles. That is, the lower limit of the particle size of the first fine particles is about 0.1 nm.

In particular, in applications requiring high-speed operation, by setting the particle size of the first fine particles to 0.5 nm or more, the charging energy ΔE1 of the first fine particles is prevented from becoming excessive. This is desirable because it allows quick charge injection.

Next, in the case where a single charge is accumulated in the second fine particles and the charge is held at Vg = 0, the charges may not be spontaneously released from the fine particles toward the substrate. is necessary. In the present invention, the release of the charge is the second
Is determined in the process of charge transfer from the fine particle of the above to the first fine particle adjacent thereto. If the electron energy changes associated with charge transfer (ΔE1 -ΔE2) is the particle size ratio of the first particulate matter and the second particle body (r2 / r1) is is f, the following formula ΔE1 -ΔE2 = {e ² ( f-1) It is represented by｝ / 8π · f · r1. Here, since the state density of the first fine particles is lower than that of the substrate surface, the second fine particles
The charge transfer to the fine particles or vice versa is less likely to occur than the charge transfer between the first fine particles and the surface of the semiconductor substrate. However, when the band energy of the second fine particles is increased by the thermal excitation, the first fine particles move with a certain probability. Once the electric charge is retained in the first fine particles, the electric field moves more easily between the first fine particles and the semiconductor substrate than between the fine particles as described above. Most of the electric charges of the semiconductor substrate move to the semiconductor substrate. Therefore,
In order to suppress such a transition and stably hold the charge, it is desirable that the energy change is heat ΔE1−ΔE2> kT. For example, if the particle size of the first fine particles is 5
If the particle diameter ratio f of the first fine particles to the second fine particles is 1.8 times or more, the energy change (Δ
E1 -.DELTA.E2) is larger than the thermal energy kT, so that spontaneous release of electric charges can be prevented. In addition, when charge retention for a longer period is required, it is preferable that the particle size ratio f be 4 times or more, since the charge retention can be further stabilized.

When a voltage of Vg (discharge) is applied to the upper electrode to apply an electric field from the outside and discharge the electric charge accumulated in the second fine particle, the electric charge on the second fine particle is reduced. It is necessary to move quickly to the substrate side. At this time, it is necessary to apply an electric field against the energy change (ΔE1−ΔE2) to inject electric charges from the second fine particles to the first fine particles, and move the electric charges to the semiconductor substrate. Here, by the application of the voltage Vg (discharge), the state in which the charge is transferred from the second fine particle to the semiconductor substrate is more energetically compared to the state before the charge is released from the second fine particle. In this case, the probability that charges move from the second fine particles to the first fine particles increases. In addition, most of the charge transferred to the first fine particles is discharged to the semiconductor substrate as described above.
However, since the state density of the fine particles is lower than that of the semiconductor substrate surface, the charge transfer between the fine particles is less likely to occur than the charge transfer between the fine particles and the semiconductor substrate surface.

Therefore, the energy change (ΔΔ) of the electrons due to the charge transfer from the second fine particles to the first fine particles described above.
E1−ΔE2) is equal to or less than the energy change ΔE ′ ΔE ′ = eVg (discharge) · (d / tg) due to the potential difference between the two fine particles due to an external electric field.
The charges on the second fine particles can be easily released. Here, when the particle size of the first fine particles is 0.1 nm or more, the energy change (ΔE1−ΔE2) can be easily made.
Can be made equal to ΔE ′, and quick charge erasure can be performed.

Further, the particle size of the first fine particles is set to 0.1.
By making the thickness 5 nm or more, the energy change (ΔE1
−ΔE2) can be made sufficiently lower than ΔE ', and high-speed operation is possible.

-Relationship between Particle Size and Particle Size Ratio of Second Fine Particle and Transfer / Hold of Charge-Next, the particle size of the second fine particle and the particle size of the first and second fine particles The upper limit of the ratio will be described.

As a typical semiconductor device utilizing the present invention, a device having a charge accumulation region of about 0.4 μm square will be considered. This corresponds to, for example, the gate width and gate length of the MIS transistor element being 0.4 μm. Here, since a large number of the second fine particles are dispersed, resistance to a leak current due to a defect or the like of the barrier layer can be improved. Therefore, by setting the particle diameter of the second fine particles to 30 nm or less, it is possible to provide a large number of the second fine particles as an average of 40 or more in the charge storage region in the semiconductor element.

For a further miniaturized element,
By setting the particle diameter of the second fine particles to 10 nm or less, a large number of second fine particles can be similarly provided in the charge accumulation region of, for example, 0.13 μm square.

As described above, since the particle diameter of the first fine particles is 0.1 nm or more, the particle diameter r2 of the second fine particles
The ratio f between the particle diameter r1 of the first fine particles and the particle diameter r1 is preferably 300 times or less. Further, it is more preferable to make the particle diameter ratio 100 times or less especially for a miniaturized element.

On the other hand, when the particle size of the second fine particles is made too small, the potential rise ΔE2 when the electric charge represented by the following formula ΔE2 = (e ² / 8πε) · (1 / r2) is injected becomes large. , The accumulated charge becomes unstable. here,
By setting the particle size of the second fine particles to 1 nm or more,
Excessive rise in potential is suppressed, and charge retention is facilitated. In particular, when the particle diameter of the second fine particles is 3 nm or more, long-term charge retention becomes easy.

From the above, the particle diameter r2 of the second fine particles is:
1.8 times or more 300 times the particle diameter r1 of the first fine particles
It is preferable to set it to twice or less. In order to further stabilize charge retention in a miniaturized semiconductor device, the second
The particle size r2 of the fine particles is more preferably 4 times or more and 100 times or less the particle size r1 of the first fine particles.

[0303] The particle diameter r1 of the first fine particles is set at 0.1.
The thickness is preferably 1 nm or more and 5 nm or less. In order to operate at a high speed and stabilize the charge retention, the particle diameter r1 of the first fine particles is more preferably 0.5 nm or more and 2 nm or less.

The particle diameter r2 of the second fine particles is 1n
It is preferably at least m and at most 30 nm. In order to further stabilize charge retention in a miniaturized semiconductor device, the particle size r2 of the second fine particles should be 3 nm or more and 10 nm or more.
It is more preferable to set it to nm or less.

As described above, in the semiconductor device of this embodiment, the fine particles for holding the charges and the fine particles for controlling the charge transfer are independently provided, and the functions thereof are specialized, so that writing / erasing can be performed at high speed. In addition, there is provided means for injecting, holding, and erasing charge into the fine particles, which can hold charges for a longer time than ever before and has high reliability.

In the present embodiment, both electrons and holes can be used as the electric charge injected and accumulated in the fine particles.

In this embodiment, the semiconductor substrate is p
Although a silicon substrate of a type is used, an n-type semiconductor substrate or a semiconductor substrate of another material can be used in the same manner. When using electrons as the injected charges, an n-type semiconductor substrate is used.
In the case where holes are used as the injected charges, the use of a p-type semiconductor substrate makes it easier to suppress the release of accumulated charges, which is more preferable.

In this embodiment, silicon fine particles and gold fine particles are used as fine particles, but metals and other semiconductor materials can be used in the same manner.

In the present embodiment, only one layer of the first fine particles sandwiched between the first barrier layer and the second barrier layer is provided between the second fine particles and the semiconductor substrate. The structure in which a plurality of first fine particles are provided and a barrier layer is further interposed between the layers can further stabilize the charge retention in the second fine particles.

(Seventeenth Embodiment) FIG.
FIG. 21 is a sectional view of a semiconductor memory device according to a seventeenth embodiment.
is there. As shown in FIG.
A source formed in a p-type silicon substrate 3041 as a substrate
N-type region functioning as source region or drain region
3042 and a metal electrode 30 which is a source / drain electrode
49 and SiO having a thickness of 7 nm as a gate insulating film._Two Get
A gate insulating layer 3047 and an n-type polycrystalline silicon
And a recon electrode 3048 and a MIS transistor structure.
It has structure. In addition, the MIS transistor structure
Between the gate insulating film 3047 and the semiconductor substrate 3041
The following members are provided. Charge transfer on the semiconductor substrate
As a first barrier layer that functions as a barrier against movement,
Thermally oxidized SiO of about 1.9 nm_Two Provided with a film 3043
Have been. In addition, the thermally oxidized SiO, which is the first barrier layer,
_Two On the film 3043, a first fine particle having a diameter of 2.5
nm silicon fine particles 3044 are provided. Ma
In addition, silicon fine particles 3044 as the first fine particles
On top of a second that acts as a barrier to charge transfer
SiO having a thickness of about 1.8 nm as a barrier layer_Two Membrane 3045
Is provided. Further, the second barrier layer SiO 2
_Two On the film 3045, as a second fine particle, a diameter of 6 nm
Gold particles 3046 are provided. Where silico
The in-plane density of the fine particles is 1 × 10¹¹cm ^-2~ 1 × 10¹³c
m^-2The in-plane density of the gold fine particles is 1 × 10^Tencm^-2~ 1 × 1
0¹²cm^-2It is about.

In the present embodiment, a structure capable of controlling the injection, holding, and release of electric charge to the fine particles can be realized by the same principle as in the sixteenth embodiment. Further, in the present embodiment, since the structure for holding the charge is formed in the gate region of the MIS transistor structure, M is different between the state where the charge is held in the second fine particle and the state where the charge is not present.
The threshold voltage of the IS transistor characteristic changes. Thereby, it operates as a non-volatile semiconductor memory element capable of low-voltage, high-speed and long-term recording. Furthermore, since a basic memory operation is realized by a single element, high-density integration is possible.

In the present embodiment, as shown in FIG. 29, fine particles are present at least in the gate region above the source region and in contact with the source region, or in the drain region and in contact with the source region. Since the portion not provided is provided, it is possible to prevent a short-circuited current from flowing through the fine particles when a voltage is applied from the source region to the drain region.

In the present embodiment, since the region provided with the fine particles is divided into a plurality of regions at least in a direction in which a short-circuit current between the source and the drain is prevented, a voltage is applied from the source region to the drain region. When short-circuiting is applied, the short-circuited current can be prevented from flowing through the fine particles.

(Eighteenth Embodiment) FIG. 30 is a sectional view of a semiconductor device according to an eighteenth embodiment of the present invention.
As shown in the figure, a thermally oxidized SiO ₂ film 3 having a thickness of about 1 nm, which is a surface barrier layer functioning as a barrier against the movement of electric charges, is formed on a p-type silicon substrate 3051 which is a semiconductor substrate.
052a is provided. Further, on the thermal oxide SiO ₂ film 3052a is a surface barrier layer, the SiO ₂ film is provided serves as a barrier to the movement of charge, the SiO
_An SiO _x layer (1.5 <x <) as a fine particle dispersion layer in which silicon fine particles 3054 as the first fine particles are dispersed in _two films.
The silicon excessive oxide film 3053 of 2) is provided. A deposited SiO ₂ film 3052b functioning as a barrier layer is provided on a silicon rich oxide film 3053 which is a fine particle dispersion layer.
Then, gold fine particles 3055 having a diameter of 2 nm, which are second fine particles, are provided on the deposited SiO ₂ film 2052b. Further, the gold fine particles 305 as the second fine particles are used.
8, an SiO ₂ film 305 having a thickness of 8 nm as an insulator layer
6 is provided, and an n-type polycrystalline silicon electrode 3057 which is an electrode layer is provided on the uppermost portion. Gold particles 30
55 has a diameter of 2 by immersion of the wafer in a gold colloid solution.
Fine particles of up to 5 nm are 1 × 10 ¹⁰ cm ⁻² to 1 × 10 ¹² cm
It is fixed at an in-plane density of about ^-2 .

In the sixteenth embodiment, since the first fine particles are formed as a fine structure on the first barrier layer, the particle size distribution, the in-plane dispersion state, and the like of the first fine particles are obtained. Need to be controlled. However, in the present embodiment, SiO _x
Silicon-rich oxide film 30 composed of layers (1.5 <x <2)
53 (fine particle dispersion layer) can easily cause minute silicon fine particles 3054 in the SiO ₂ film as the barrier layer.
Can be realized. That is, since the minute silicon islands in the SiO _x film function as fine particles, there is no need to particularly control the fine structure. As a result,
The manufacture of the semiconductor device becomes easy, and the reproducibility of the device characteristics is high. The SiO _x layer can easily produce a high-quality film by a CVD method, but can also be produced by another method such as a sputtering method. In addition, when the oxygen content ratio x in the SiO _x layer (1.5 <x <2) is in the range of 1.8 <x <2, a finer silicon island can be formed, which is preferable. The thickness of the SiO _x layer (1.5 <x <2) is 3 to 10
By being in the range of nm, element operation at a low voltage becomes possible. In the present embodiment uses a SiO _{1. 9} thick layer of 6 nm. Here, silicon fine particles 30 in the SiO _x layer (1.5 <x <2) functioning as the first fine particles
The diameter of the gold fine particles 3055 (second fine particles) is smaller than the silicon fine particles 3054.
Is at least twice the diameter of

In particular, a deposited SiO ₂ film 3052b functioning as a barrier layer between the gold fine particles 3055 (second fine particles) and the silicon-rich oxide film 3053 (fine particle dispersion layer).
Is provided, there is an advantage that it is possible to reliably prevent the electric charge held in the gold fine particles 3055 from moving to the silicon fine particles (first fine particles) in the silicon-rich oxide film 3053 when it is not desired.

In this embodiment, the manufactured SiO _x
As it is used without particular heat treatment of the layer, SiO _x
Although fine silicon islands in the layer are used as fine particles, heat treatment of the SiO _x layer at about 1000 ° C. can grow silicon fine particles and control the particle size.

Further, in the present embodiment, the SiO _x layer is used as the fine particle dispersion layer. However, the semiconductor fine particle dispersion layer is formed by injecting semiconductor ions or metal ions into the insulator layer. A structure having the same charge control function as the fine particle dispersion layer of the embodiment can be formed more easily. Although the insulator layer into which semiconductor or metal ions are implanted is different from the structure in which fine particles are dispersed,
The level formed by a semiconductor or a metal atom in the insulator can achieve substantially the same function as the first fine particle having a small particle diameter in the present embodiment, and is used as a fine particle dispersion layer in the present embodiment. be able to. Examples of such semiconductor ions and metal ions include Si ions and W ions. By using a SiO ₂ film or the like into which these ions are implanted as a fine particle dispersion layer, the same function as that of the semiconductor element of the present embodiment is obtained. Can be obtained.

In the present embodiment, injection, holding, and injection of electric charges into fine particles are performed according to the same principle as in the sixteenth embodiment.
Emissions can be controlled efficiently. Furthermore, in this embodiment, as described above, there is no need to manufacture the first fine particles as a fine structure, so that there is an advantage that the manufacture is easy and the reproducibility of element characteristics is high.

Further, in the present embodiment, unlike the sixteenth embodiment, the electric charge transfer between the semiconductor substrate and the second fine particles is usually performed not only by a single first fine particle but also by a plurality of first fine particles. It is carried out through fine particles. In such a tunnel process through a plurality of fine particles, the tunnel current is reduced as compared with the process through a single fine particle, but the reduction rate is smaller than that in a relatively strong electric field such as during writing. It is larger under a weak electric field such as during holding. As a result, the ratio of the tunnel current (write / erase current) at the time of writing / erasing to the tunnel current (leakage current) at the time of charge retention is further increased, and a high-speed and long-life element can be realized.

Note that the first fine particles were not provided, and the first fine particles were simply provided.
In the structure in which only the fine particle dispersion layer is provided, the charge retention is performed by the first fine particles having a high capacitance, and the charge is held adjacent to the semiconductor substrate having the higher capacitance in the first fine particle dispersion layer during the charge retention. Therefore, it is difficult to maintain the charge for a long period of time because the particles flow back to the fine particles. Further, in this case, since the charges are easily dispersed in the first fine particle dispersion layer in the lateral direction, a large amount of accumulated charges may be lost due to a part of leak current, and it is difficult to realize a highly reliable semiconductor element.

Also, the second embodiment described in the later-described x-th embodiment will be described.
Even in a structure in which a single floating conductor is provided instead of the fine particles, all the charges are lost due to a part of the leakage current. In the present embodiment, only the second fine particles just above the leak position lose their electric charges, and the other second fine particles are not affected, so that high reliability is provided.

In the semiconductor device of this embodiment,
Since the second barrier layer is provided between the fine particle dispersion layer and the second fine particles, the leak current can be further suppressed.

In the semiconductor device of this embodiment, the surface barrier layer is provided between the semiconductor substrate and the fine particle dispersion layer. However, this is omitted when the fine particle density of the fine particle dispersion layer is not so high. A fine particle dispersion layer can be provided directly on the semiconductor substrate.

By utilizing the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the seventeenth embodiment can be formed.

FIG. 31 is a sectional view of a semiconductor memory device formed using the semiconductor device of this embodiment. On a p-type silicon substrate 3061 which is a semiconductor substrate, a source
Drain region 3062 and thermally oxidized Si as a surface barrier layer
The first O ₂ film 3063a and the first SiO ₂ film
Excessive silicon oxide film 3064 in which silicon fine particles 3065, which are fine particles, are dispersed, and deposited SiO
₂ film 3063b and gold fine particles 30 as second fine particles
66, a gate insulating film 3067 made of a SiO ₂ film,
An n-type polycrystalline silicon electrode 3068 serving as an electrode layer and a source / drain electrode 3069 are provided. That is, a MIS transistor structure similar to that of the seventeenth embodiment is formed, and a fine particle dispersion layer (SiO _x layer) is interposed between the gate insulating film 3067 and the semiconductor substrate 3061. As a result, the threshold voltage of the MIS transistor characteristics changes between the state where the electric charge is held in the gold fine particle 3066 as the second fine particle and the state where there is no electric charge. It operates as a possible non-volatile semiconductor memory device.

In the semiconductor memory device of this embodiment, at least one of or both of the gate region and the region in contact with the source region and the upper portion of the source region and the region in contact with the source region. In the region, at least a portion in which the fine particle dispersion layer and the fine particles are not present is provided, so that when a voltage is applied from the source region to the drain region, the short-circuited current flows through the fine particles more effectively. Can be prevented.

(Nineteenth Embodiment) FIG.
It is sectional drawing of the semiconductor element in 19th Embodiment.
An electrode is placed on a p-type silicon substrate 3071 which is a semiconductor substrate.
A surface barrier layer that functions as a barrier to the movement of loads
And a thermally oxidized SiO having a thickness of about 1.2 nm_Two Membrane 3072a
Is provided. In addition, thermal oxidation,
SiO_Two On the film 3072a, a barrier against charge transfer
SiO functioning as_Two The first fine particles in the film
A first fine particle dispersion layer in which recon fine particles 3074 are dispersed;
First SiO having a thickness of about 3 nm_x Layer (1.5 <x <
2) a silicon-rich oxide film 3073 comprising
I have. In addition, a silicon-rich acid as the first fine particle dispersion layer
Deposited on the oxide film 3073 to function as a barrier layer
_Two The film 3073b serves as a barrier layer against the movement of electric charges.
Working SiO_Two Silicon fine particles, which are second fine particles, are contained in the film.
Thickness of second fine particle dispersion layer in which particles 3076 are dispersed
Second SiO of about 5 nm _x From the layer (1.5 <x <2)
And a silicon excessive oxide film 3075 are sequentially provided.
You. In addition, the second fine particle dispersion layer, silicon excess,
On the oxide film 3075, a 10-nm-thick S serving as an insulator layer is formed.
iO_Two A film 3077 is provided, and an uppermost electrode layer
A certain n-type polycrystalline silicon electrode 3078 is provided.
You.

[0329] While the first particulate matter 3074 second microparticles body 3076 is a silicon particles dispersed in both SiO _x layer (1.5 <x <2), heat treatment and composition control of SiO _x film Thereby, the particle diameter of the fine particles can be controlled. Any of the layers, SiO _x layer using a CVD apparatus (1.5 <x
After depositing <2), the silicon fine particles are grown by heat treatment at about 1100 ° C., and the Si content ratio of the second fine particle dispersion layer (silicon-rich oxide film 3075) is adjusted to the first fine particle dispersion layer ( By increasing the Si composition ratio in the silicon-rich oxide film 3073), it is possible to increase the particle size of the silicon fine particles that grow in the second fine particle dispersion layer. In this embodiment, the composition of the first fine particle dispersion layer (silicon-rich oxide film 3073) is SiO _1.9
On the other hand, the composition of the second fine particle dispersion layer (silicon-rich oxide film 3075) is SiO _1.7 . Here, the particle diameter of the second fine particles is 1.7 nm or more. The particle size of the first fine particles is about 0.8 nm or less. The particle diameter of the second fine particles is about 1.8 times or more the particle diameter of the first fine particles. As a result, as described above, the second
The fine particles can exhibit good charge injection / holding characteristics.

In this embodiment, the SiO _x layer is used as the first and second fine particle dispersion layers. However, by implanting semiconductor ions or metal ions into the insulator layer, the fine particle dispersion layer is formed. By forming the layer, a structure having a charge control function equivalent to those of the first and second fine particle dispersion layers of the present embodiment can be more easily formed.

In the present embodiment, the injection, holding, and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the eighteenth embodiment. In the eighteenth embodiment, the second fine particles need to be formed as a fine structure on the first fine particle dispersion layer. In the present embodiment, however, the second fine particles are formed in the second barrier layer. By using a decentralized structure,
Further, there is an advantage that the fabrication of the semiconductor device is facilitated and the reproducibility of the device characteristics is high.

In the structure in which the second fine particle dispersion layer is not provided and the first fine particle dispersion layer is simply provided, the charge is retained by the first fine particles having a small capacitance. In the first fine particle dispersion layer, the backflow to the fine particles adjacent to the semiconductor substrate having a higher capacitance is difficult, so that it is difficult to hold the charge for a long time.

In the semiconductor device of this embodiment,
Between the first fine particle dispersion layer and the second fine particle dispersion layer, the second
The leakage current can be further suppressed by the provision of the barrier layer described above.

In the semiconductor device of this embodiment, the surface barrier layer is provided between the semiconductor substrate and the first fine particle dispersion layer. However, when the fine particle density of the first fine particle dispersion layer is not so high, Can be omitted and the first fine particle dispersion layer can be provided directly on the semiconductor substrate.

In this embodiment, there is a clear interface between the first fine particle dispersion layer and the second fine particle dispersion layer, but the first fine particle dispersion layer and the second fine particle dispersion layer have a continuous fine particle density. It is also possible to adopt a configuration having a distribution and no clear interface between them. In this case, substantially the same effects as in the present embodiment can be obtained.

By utilizing the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the seventeenth embodiment can be formed.

FIG. 33 is a sectional view of a semiconductor memory device formed using the semiconductor device of this embodiment. On a p-type silicon substrate 3081 which is a semiconductor substrate, a source
Drain region 3082 and thermally oxidized Si as a surface barrier layer
The first in the O ₂ film 3083a and the SiO ₂ film as the barrier layer
Silicon oxide film 3084 which is a first fine particle dispersion layer in which silicon fine particles 3085 which are fine particles of
And a deposited SiO ₂ film 3083b functioning as a barrier layer
A silicon-rich oxide film 3086 serving as a second fine particle dispersion layer in which gold fine particles 3087 serving as second fine particles are dispersed in an SiO ₂ film serving as a barrier layer, and a gate insulating film 3088 formed of a SiO ₂ film. An n-type polycrystalline silicon electrode 3089 serving as an electrode layer and a source / drain electrode 3080 are provided. That is, the same M as in the seventeenth embodiment is used.
An IS type transistor structure is formed, and two fine particle dispersion layers (a layer in which SiO _x layers and gold fine particles are dispersed in SiO ₂ ) are interposed between the gate insulating film 3088 and the semiconductor substrate 3081. As a result, the threshold voltage of the MIS transistor characteristics changes between the state where the electric charge is held in the gold fine particles 3087 as the second fine particle body and the state where there is no electric charge, and low-voltage, high-speed and long-term recording can be performed. It operates as a possible non-volatile semiconductor memory device.

In the semiconductor memory device of this embodiment, at least one or both of the gate region, a region in contact with the source region and the upper portion of the source region, or a region in contact with the source region and the drain region. Since at least a portion where the fine particle dispersion layer does not exist is provided in the region, it is possible to prevent a short-circuit current from flowing through the fine particles when a voltage is applied from the source region to the drain region.

(Twentieth Embodiment) FIG. 34 is a sectional view of a semiconductor device according to a twentieth embodiment of the present invention.
On a p-type silicon substrate 3091 which is a semiconductor substrate, a thermally oxidized SiO ₂ film 3092 having a thickness of about 1.3 nm which is a surface barrier layer functioning as a barrier against movement of electric charges is provided. Further, on the surface barrier layer, silicon fine particles 3094 as the first fine particles and ions as the second fine particles were ion-implanted into the SiO ₂ film as the barrier layer functioning as a barrier against the movement of electric charges. Tungsten atom 309
And a fine particle dispersion layer 3093 having a thickness of about 5 nm dispersed therein.
Is provided. Further, a 6 nm thick SiO ₂ film 3096 is provided as an insulator layer on the fine particle dispersion layer 3093, and an n-type polycrystalline silicon electrode 3097 as an electrode layer is provided on the uppermost portion.

Here, the first fine particles 94 and the second fine particles 3095 are both fine particles dispersed in a SiO ₂ film serving as a barrier layer, and the particle diameter of the second fine particles 3095 is 2 μm. 0.6 nm or more and a substantial particle size of about 0.5 nm
It is 1.8 times or more of the following first fine particle 3094.

The above-mentioned fine particle dispersion layer is formed by depositing a SiO _x (1.5 <x <2) film using a CVD apparatus and then performing a heat treatment at about 1100 ° C. to grow silicon fine particles, and further to form a tungsten atom. Can be produced by ion implantation. In the present embodiment, tungsten atoms implanted into the insulator layer as the first fine particles are used. However, other semiconductor atoms or metal atoms introduced by ion implantation, or other semiconductor fine particles or metal are introduced. Fine particles can also be used.

In this embodiment, the injection, holding and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the eighteenth embodiment. Further, in the eighteenth embodiment, it is necessary to control the thickness of the first fine particle dispersion layer in order to obtain an appropriate element operation speed and a recording retention period. And the device is easy to manufacture. That is, although the dispersed first and second fine particles have various positional relationships, the charge extracted from the semiconductor surface at the time of writing selects a path for easier charge transfer, and the relatively small amount of charge is injected. The second fine particles are easily injected. At the time of holding the charge, the charge is quickly released from the second fine particles adjacent to the semiconductor surface or the like, but the charge is held for a long time at a position where the charge is more difficult to release. In the present embodiment, the ratio of the retained electric charge to the injected electric charge is smaller than that of the eighteenth embodiment. However, since the element configuration is simpler, there is an advantage that a semiconductor element having high reproducibility can be easily manufactured. Have.

In this embodiment, the first fine particles and the second fine particles have a clear distinction. However, even if the same material is used, the fine particles having various particle diameters over a sufficiently wide range can be continuously formed. It is also possible to provide fine particles having a specific particle size distribution so that the fine particles having a small particle diameter function as the first fine particles and the fine particles having a large particle diameter function as the second fine particles. In this case, a clear distinction cannot be made between the first microparticles and the second microparticles, but the injected charge is selectively retained by the microparticles having a large particle diameter and a large capacitance. The fine particles selected by the electric charge function as the second fine particles. In order to prevent the backflow of charges to the fine particles near the semiconductor surface, the particle size distribution of the fine particles has a distribution at least wider than the range of 0.7 to 1.4 times that of the fine particles having an intermediate particle size. There is a need. For long-term charge retention, it is desirable to have a particle size distribution of at least 0.4 times to 1.6 times or more.

The particle size distribution of the fine particles is preferably a shape having a valley in the center and two peaks on both sides.

In the semiconductor device of this embodiment, the surface barrier layer is provided between the semiconductor substrate and the fine particle dispersion layer. However, when the fine particle density of the fine particle dispersion layer is not so high, this is omitted. A fine particle dispersion layer can be provided directly on the semiconductor substrate.

By utilizing the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the seventeenth embodiment can be formed.

FIG. 35 is a sectional view of a semiconductor memory device formed by using the semiconductor device of this embodiment. On a p-type silicon substrate 3101 which is a semiconductor substrate, a source / drain region 3102 and thermal oxidation S which is a surface barrier layer are formed.
The first in the SiO ₂ film 3103 and the SiO ₂ film as the barrier layer
A fine particle dispersion layer 3104 in which silicon fine particles 3105 as a fine particle and tungsten fine particles 3106 as a second fine particle are dispersed, a gate insulating film 3107 made of a SiO ₂ film, and an n-type polycrystalline silicon electrode as an electrode layer 3
108 and a source / drain electrode 3109 are provided. As a result, the threshold voltage of the MIS transistor characteristics changes between the state in which the electric charge is held in the second fine particle body and the state in which the electric charge is not present. It operates as a semiconductor memory element.

In the semiconductor memory device of this embodiment,
At least a portion where the fine particle dispersion layer does not exist is provided in at least one of the region above the source region and the source region, or the region above the drain region and the region contacting the source region in the gate region. Accordingly, when a voltage is applied from the source region to the drain region, a short-circuited current can be prevented from flowing through the fine particles.

(Twenty-First Embodiment) FIG. 36 is a sectional view of a semiconductor device according to a twenty-first embodiment of the present invention.
First, on a p-type silicon substrate 3111 which is a semiconductor substrate, a thermally oxidized SiO having a thickness of about 1 nm as a first SiO ₂ layer is formed.
_Two films 3112 are provided. In addition, the first Si
SiO _x on O ₂ layer on N _y layer (0 ≦ x <2,0 <y ≦ 4 /
3) a Si ₃ N ₄ layer 3113 having a thickness of about 1.2 nm
Is provided, and a second SiO ₂ layer 3114 having a thickness of about 1.8 nm is provided on the SiO _x N _y layer. On the second SiO ₂ layer 3114, fine gold particles 3115 having a diameter of 2 nm are provided. In addition, an insulating layer having a thickness of 1
A 0 nm SiO ₂ film 3116 is provided, and an n-type polycrystalline silicon electrode 3117 as an electrode layer is provided on the uppermost portion. The in-plane density of the gold fine particles 3115 is 1 × 10 ¹⁰
cm ⁻² to 1 × 10 ¹² cm ⁻² .

This embodiment is different from the sixteenth embodiment.
In addition, two types of fine particles having different particle sizes are not provided. I
However, in the present embodiment, SiO 2_x N_y Layer (0 ≦ x <2,
0 <y ≦ 4/3) is the first SiO_Two Layer and second SiO_Two 
Since the structure is sandwiched between layers,_x N_y layer
And the second SiO_Two Near the interface between the layers and SiO_x N _y 
Level at which charge can be transferred inside the layer (interface level)
Occurs. Energy between levels at this interface level
The gap is large, and the
Large rise in position, so it is effective
Similar functions can be provided. That is, this implementation
In the form of SiO_x N_yLayer and second SiO _Two Interface between layers
Level is equivalent to that of the first microparticle in the sixteenth embodiment.
Function. As a result, the fine
In the particulate matter, the second particulate matter in the sixteenth embodiment is used.
As well as stably hold the accumulated charge
You. Therefore, also in this embodiment, the sixteenth embodiment and
Injection, retention, and release of charge into microparticles based on the same principle
Can be controlled efficiently.

In the sixteenth embodiment, the first fine particles need to be formed as a fine structure on the first barrier layer. However, in the present embodiment, since the SiO _x N _y layer is used, the first fine particles are used. There is no need to particularly control the fine structure of the fine particles. As a result, there is an advantage that the manufacture of the semiconductor device becomes easy and the reproducibility of the device characteristics is high. SiO _x N _y layer is CVD
A high quality film can be easily manufactured by the method.

In this embodiment, SiO_x N_y Layer (0 ≦ x
<2, 0 <y ≦ 4/3) Si _Three N_Four Using layers
However, besides this, the general formula SiO_x N_y (0 <x <2, 0 <y
A silicon oxynitride film having a composition represented by <4/3)
Can also be used.

Note that no fine particles were provided, and only SiO _x N
_{With only the} structure in which the _y layer is sandwiched between the first SiO ₂ layer and the second SiO ₂ layer, it is difficult to hold the charge for a long time because the charge is held at the interface state having a high capacitance. . Further, since the horizontal charge dispersion cannot be ignored between the interface states where the charge is held, all the stored charges may be lost due to a part of the leak current, and the reliability of the semiconductor element is low.

By using the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the seventeenth embodiment can be formed.

FIG. 37 is a sectional view of a semiconductor memory device formed by using the semiconductor device of this embodiment. On a p-type silicon substrate 3121 which is a semiconductor substrate, a source / drain region 3122, a thermally oxidized SiO ₂ film 3123 which is a first SiO ₂ layer, and a SiO _x N _y layer (0 ≦ x <
2,0 <y ≦ 4/3) SiO _1.5 N _3.5 layer 312
4, a second SiO ₂ layer 3125, fine gold particles 3126 as fine particles, an SiO ₂ film 3127, an n-type polycrystalline silicon electrode 3128, and a source / drain electrode 312.
9 are provided. Thus, the state where the electric charge is held in the second fine particle body and the state where the electric charge is not present are M
The threshold voltage of the characteristics of the IS transistor changes,
It operates as a nonvolatile semiconductor memory element capable of high-speed and long-term recording.

In the semiconductor memory device of this embodiment, at least one of or both of the gate region and the region in contact with the source region and the upper portion of the source region and the region in contact with the source region. At least in the region of
_{Since the xNy} layer and the portion where the fine particles are not present are provided, it is possible to prevent a short-circuited current from flowing through the fine particles when a voltage is applied from the source region to the drain region.

(Twenty-second Embodiment) FIG. 38 is a sectional view of a semiconductor device according to a twenty-second embodiment of the present invention.
On a p-type silicon substrate 3131 as a semiconductor substrate, a first
Thermally oxidized SiO ₂ layer of about 1.3 nm thick
_Two films 3132 are provided. In addition, the first Si
On the O ₂ layer, a SiO _x N _y layer having a thickness of about 1.8 nm (0 ≦
SiO _0.5 N layer 313 where x <2, 0 <y ≦ 4/3)
3 is further provided on the SiO _0.5 N layer, which is a barrier layer functioning as a barrier against the movement of electric charges.
SiO _x layer silicon microparticles 3135 is particulate material in ₂ is the first fine particle dispersion layer dispersed (1.5 <x <
A silicon excessive oxide film 3134 made of 2) is provided. Further, a 10-nm-thick SiO ₂ film 3136 which is an insulator layer is provided on the first fine particle dispersion layer,
An n-type polycrystalline silicon electrode 3137 which is an electrode layer at the top
Is provided. In this embodiment, the thickness of the SiO _x layer is about 5 nm, and its composition is SiO _1.8 .

Also in the present embodiment, the injection, holding and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the twenty-first embodiment. In addition, in the twenty-first embodiment, it is necessary to produce the fine particles as a fine structure by controlling the particle size distribution and the in-plane dispersion state. In the present embodiment, the structure in which the fine particles are dispersed in the barrier layer is used. The use thereof has an advantage that the production of the element is easy and the reproducibility is high.

In this embodiment, the SiO _x N _y layer (0 ≦ x
Although the SiO _0.5 N layer is used for <2, 0 <y ≦ 4/3), a Si ₃ N ₄ layer or a silicon oxynitride film having another composition may be used.

Further, in the present embodiment, SiO _x N _y
Since the second SiO ₂ layer is provided between the layer (0 ≦ x <2, 0 <y ≦ 4/3) and the fine particle dispersion layer, the leak current can be further suppressed.

By using the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the seventeenth embodiment can be formed.

FIG. 39 is a sectional view of a semiconductor memory device formed using the semiconductor device of this embodiment. A source / drain region 3142 and a thermally oxidized SiO ₂ film 3143 are formed on a p-type silicon substrate 3141 which is a semiconductor substrate.
, Si ₃ N ₄ layer 3144, silicon fine particles 3146 as fine particles, silicon excessive oxide film 3145,
iO ₂ film 3147 and n-type polycrystalline silicon electrode 3148
And a source / drain electrode 3149. As a result, the threshold voltage of the MIS transistor characteristics changes between the state in which the electric charge is held in the fine particle and the state in which the electric charge is not present, and the nonvolatile semiconductor memory element capable of performing low-voltage, high-speed, and long-term recording Works as

In the semiconductor memory device of this embodiment, at least one of the gate region and the region in contact with the source region and the drain region and / or the region in contact with the source region. , At least SiO _x N
_{Since a} portion where the _y layer and the fine particle dispersion layer are not provided is provided, it is possible to prevent a short-circuited current from flowing through the fine particles when a voltage is applied from the source region to the drain region.

(Twenty-third Embodiment) FIG.
FIG. 37 is a sectional view of a semiconductor device according to a twenty-third embodiment.
As shown in the figure, a p-type silicon base as a semiconductor substrate
The plate 3151 acts as a barrier against charge transfer.
Thermally oxidized Si having a thickness of about 2 nm, which is a functional first barrier layer
O_Two A membrane 3152 is provided. Also, the first barrier
Thermally oxidized SiO layer_Two A first fine particle on the film 3152
Silicon fine particles 3153 having a diameter of 2 nm are provided as a body.
Have been. Silicon fine particles as the first fine particles
Acts as a barrier to charge transfer
SiO 2 having a thickness of about 2 nm as a second barrier layer_Two Membrane 3
154 are provided. Further, the second barrier layer is provided.
SiO _Two On the film 3154, the diameter of the second fine particle
2 nm SiGe fine particles 3155 are provided. Ma
Of the SiGe fine particles 3155 as the second fine particles
SiO 2 having a thickness of 10 nm as an insulator layer thereon_Two Membrane 3156
Is provided, and an n-type polycrystal serving as an electrode layer is provided on the uppermost portion.
A silicon electrode 3157 is provided.

Here, the second fine particles SiG
The diameter of the e microparticles 3155 is the same as the diameter of the silicon microparticles 3153 as the first microparticles, but the electron affinity of both is different. That is, the electron affinity of the silicon microparticles 3153 as the first microparticles is smaller than the electron affinity of the SiGe microparticles 3155 as the second microparticles. Also, in this case, the sum of the electron affinity and the forbidden band width of the silicon fine particles 3153 as the first fine particles is calculated from the sum of the electron affinity and the forbidden band width of the second SiGe fine particles 3155. Is also big. Therefore,
The structure of the present embodiment is a structure in which the SiGe fine particles 3155 as the second fine particles can hold and use both electrons and holes as electric charges as an information medium.

As described above, the semiconductor device having the novel structure of the present invention can be easily manufactured, has high reliability, and can inject electric charge into fine particles capable of retaining electric charge for a long time.
Means for retention and erasure are provided.

FIG. 41 is a sectional view of a semiconductor memory device obtained by using the semiconductor device according to the twenty-third embodiment of the present invention. As shown in the figure, the semiconductor memory device includes an n-type region 3162 functioning as a source region or a drain region formed in a p-type silicon substrate 3161 which is a semiconductor substrate, and a thermal oxidation S having a thickness of about 1.9 nm.
iO ₂ film 3043, silicon fine particles 3164 as first fine particles, and SiO ₂ film 316 as _second barrier layer
5 and SiGe fine particles 3046 as the second fine particles
And a SiO ₂ gate insulating layer 3167 which is a gate insulating film
And an n-type polysilicon electrode 3168 serving as a gate electrode
And a metal electrode 3169 which is a source / drain electrode, and has a MIS transistor structure.

According to this structure, it is also possible to realize a structure capable of controlling the injection, holding and release of electric charges into the fine particles according to the same principle as that of the twenty-third embodiment. Further, in the present embodiment, since the structure for holding the electric charge is formed in the gate region of the MIS transistor structure, the MIS type in the state where the electric charge is held in the second microparticle and the state where there is no electric charge are provided. The threshold voltage of the transistor characteristics changes. Thereby, it operates as a non-volatile semiconductor memory element capable of low-voltage, high-speed and long-term recording. Furthermore, since a basic memory operation is realized by a single element, high-density integration is possible.

In this embodiment, as shown in FIG. 40, fine particles exist at least in the gate region above the source region and the region in contact with the source region, or in the drain region and the region in contact with the source region. Since the portion not provided is provided, it is possible to prevent a short-circuited current from flowing through the fine particles when a voltage is applied from the source region to the drain region.

In the sixteenth to twenty-third embodiments, a p-type silicon substrate is used as a semiconductor substrate. However, in the present invention, an n-type silicon substrate, GaAs
A substrate using another semiconductor material such as a substrate can also be used.

[0371] Further, in Embodiment 16 23, but using SiO ₂ as the material constituting the insulating layer, as described _{above, Si 3 N 4, Si x} O y N z (4x
= 2y + 3z), CeO ₂ , ZnS, ZnO, Al ₂ O
Other insulator materials such as ₃ can also be used.

In the sixteenth to twenty-third embodiments, silicon fine particles, gold fine particles, tungsten atoms, SiGe fine particles, or the like are used as fine particles, but other semiconductor materials or metals may be used as described above. Can also.

(Twenty-fourth Embodiment) FIG. 42 is a sectional view of a semiconductor device according to a twenty-fourth embodiment of the present invention. A 4 nm-thick SiO ₂ film 4012 as a first insulating layer is provided over a p-type silicon substrate 4011 as a semiconductor substrate.
Gold fine particles 4 as first fine particles on the first insulator layer
013 is provided. A thermally oxidized SiO ₂ film 4014 having a thickness of about 2 nm, which is a first barrier layer functioning as a barrier against the movement of electric charges, is provided on the first fine particles. Further, silicon fine particles 4015 having a diameter of about 1 nm, which are second fine particles, are provided on the first barrier layer. In addition, a SiO 2 layer having a thickness of about 2 nm functioning as a barrier against the movement of electric charges is formed on the second fine particles.
_Two films 4016 (second barrier layers) are provided. Further, gold fine particles 4017 as third fine particles are provided on the second barrier layer. Further, a 10-nm-thick SiO ₂ film 401 as a _second insulator layer is formed on the third fine particles.
8 is provided, and an n-type polycrystalline silicon electrode 4019 which is an electrode layer is provided on the uppermost portion. Each of the fine gold particles has a height of about 1 nm and a diameter in the lateral direction of 5 to 8 nm. Here, the effective particle diameters of the first fine particles and the third fine particles are 1.8 times or more of the second fine particles, and their capacitances are larger than those of the second fine particles. Big. The electron affinity of the first and third fine particles is the second.
And the sum of the electron affinity and the forbidden band width of the first and third fine particles is smaller than that of the second fine particle.

[0374] Silicon fine particles are produced by chemical vapor synthesis (CV).
By D) ^{method, 1 × 10 11 cm -2 ~1} × 10 13 are formed in plane density of the order cm ^-2, gold microparticles, the wafer immersion into a gold colloid solution, 1 × ^{10 10} cm ^{- 2} to 1 ×
It is fixed at an in-plane density of about 10 ¹² cm ^-2 .

In the conventional semiconductor device shown in FIG. 57, as described above, the charge amount on the fine particles gradually changes according to the electric field state on the semiconductor surface. Was difficult. On the other hand, according to the configuration of the present invention, the reliability of the element can be greatly improved as described below.

In the present embodiment, information is recorded by charge transfer between the first fine particle and the third fine particle via the second fine particle. Recording (writing / erasing) of information is performed by applying a writing (erasing) electric field between the upper electrode and the semiconductor substrate from the outside to give an electric field gradient between the first fine particle and the third fine particle. This is performed by moving the charge between the two and changing the distribution state of the charge.

In this embodiment, an insulator layer is provided between the first fine particles and the surface of the semiconductor substrate, and normally, no charge transfer occurs between the semiconductor substrate and the fine particles. Since the fine particles holding the charges are provided at positions separated from the semiconductor surface, the influence of the state of the semiconductor surface is suppressed to an indirect one. For example, even if the semiconductor surface is in an accumulation state or a strong inversion state during charge retention and a large number of holes or electrons are present on the surface, they do not directly participate in the charge transfer between the fine particles. When the surface state of the semiconductor substrate changes, a corresponding change in the electric field gradient also occurs between the first fine particles and the third fine particles, and this electric field gradient is caused by an external electric field during writing / erasing. It can be suppressed sufficiently smaller than the electric field gradient.

With the above effects, the semiconductor device according to the present embodiment can realize a highly reliable semiconductor device with little change in the state of holding the fine particles due to the influence of the surface state of the semiconductor substrate.

The specific charge injection and charge holding operations of the device of this embodiment are described below.

When a positive voltage, for example, as a write voltage is applied to the n-type polycrystalline silicon electrode 4019 from the outside, electrons are extracted from the first fine particles (gold fine particles 4013) and the second fine particles (silicon fine particles) are drawn. Move to 4015). Here, since the particle size of the second fine particles is smaller than the particle size of the first fine particles or the third fine particles (gold fine particles 4017), the capacitance thereof is small, and The charge is unstable. For this reason, the surplus electrons move quickly from the second fine particles to the third fine particles. Due to this charge transfer, + e charges are accumulated in the first fine particles and -e charges are stored in the third fine particles. Since the capacitances of the first fine particle and the third fine particle are larger than the capacitance of the second fine particle, the electric field generated by the accumulated charge is sufficiently smaller than the external electric field at the time of writing. Then, the charge once accumulated is held without being discharged for a long time. In particular, when the particle diameter of the second fine particles is 5 nm or less, the potential rise due to the single electric charge is larger than the electric field gradient or the thermal energy due to the accumulated electric charges, and thus the charge transfer through the second fine particles is not increased. It becomes difficult and long-term charge retention becomes possible. Note that at the time of erasing, the accumulated electric charge can be easily discharged by applying an external electric field of the same magnitude in the direction opposite to the writing.

The state of the second fine particles is quantized, and the energy interval between the quantum levels is set to the thermal energy at room temperature and the third energy.
When the potential is larger than the potential rise of the fine particles, the charge retention can be further stabilized as described below.

FIGS. 43 (a) and 43 (b) are band diagrams schematically showing a band structure near a conduction band edge during charge transfer by electrons. As shown in FIG. 43 (a), first to third
The second fine particle is quantized in a state where no electric charge is present in the fine particles, and the ground level 4032 is occupied by electrons, the first excited level 4031 is empty, and the energy interval between the two is sufficiently larger than the thermal energy. I do. When an electric field is applied for writing from the outside, as shown in FIG. 43 (b), electrons are generated from the first fine particle by the tunneling process 4035 via the first excitation level 4031 of the second fine particle, and the third electron is generated. Injected into fine particles. When the particle diameter of the third microparticle is large, the Fermi level 4034 of the third microparticle is lower than the first excitation level 4031 as shown in FIG. If the difference between the two is smaller than the heat energy, it becomes difficult to release the charge, and the third fine particles and the first
Thus, the electric charge of the fine particles is stably held. Here, the case where electrons are used as the injected charges has been described, but holes can be used in the same manner.

By utilizing the effect that the leakage current is suppressed and the charge retention is stabilized, the thickness of the barrier layer is reduced to increase the writing / erasing speed or to lower the writing / erasing voltage. Voltage can also be used.

In the case where electrons are used as charges, the electron affinity of the first fine particles and the third fine particles is larger than that of the second fine particles, and in the case where holes are used as the charges, Since the sum of the electron affinity and the forbidden band width of the first fine particle and the third fine particle is smaller than that of the second fine particle, the charge leakage through the second fine particle can be suppressed, so that the charge is retained. Becomes easier. In particular, the second fine particles are made of a semiconductor material,
Since the fine particles and the third fine particles are made of a metal material, long-term charge retention becomes stable.

Further, a large electric field is applied to the upper electrode (polycrystalline silicon layer) 4019 in advance compared to the time of writing / erasing, and the first or third fine particles are applied to the p-type silicon substrate 4011 or the upper electrode. Excess initial charge can be accumulated from a certain n-type polycrystalline silicon electrode 4019. As an initial charge, for example, when an average of one single charge is given to each of the first fine particles (gold fine particles 4013) or the third fine particles (gold fine particles 4017), this single charge is applied to the first fine particles. Information can be recorded by distinguishing between a certain state and a state in the third microparticle. The electric field gradient generated by the movement of a single charge when there is no initial charge is about 2q / (C × d) (where q is the elementary charge, C: static between the first fine particle and the third fine particle) Capacitance, d: effective distance between the first microparticle and the third microparticle pair), the single initial charge exists in the first microparticle or the third microparticle. In this case, the electric field gradient becomes as small as about q / (C × d). This further suppresses the movement of charges during information retention, making it easier to retain information for a long period of time.

As described above, the semiconductor device according to the present embodiment provides a highly reliable information recording, retaining, and erasing means capable of retaining electric charges for a longer time than ever before.

In the present embodiment, both electrons and holes can be used as the electric charge injected and accumulated in the fine particles.

In this embodiment, a p-type silicon substrate is used as a semiconductor substrate. However, an n-type silicon substrate or a semiconductor substrate made of another material may be used.

In this embodiment, silicon fine particles and gold fine particles are used as the fine particles, but similarly, metal or other semiconductor materials can be used.

In this embodiment, the first fine particles (gold fine particles 4013) and the third fine particles (gold fine particles 401) are used.
7), a first barrier layer (thermally oxidized SiO ₂ film 401)
Although only one layer of the second fine particles (silicon fine particles 4015) sandwiched between 4) and the second barrier layer (SiO ₂ film 4016) is provided, a plurality of layers of the second fine particles are provided.
The structure in which a barrier layer is further interposed between the layers can further stabilize the charge retention in the first and third fine particles.

In the present embodiment, since the periphery of the region where the fine particles are provided is covered with an insulator,
Desirably, the accumulated charge does not disappear due to a short circuit from the periphery. In particular, in the case where initial charges are accumulated, it is necessary to cover the periphery with an insulator to prevent the charges from being released to the outside.

(Twenty-Fifth Embodiment) FIG. 44 is a sectional view of a semiconductor memory device according to a twenty-fifth embodiment of the present invention. An n-type conduction region 4042 functioning as a source region or a drain region is provided in a p-type silicon substrate 4041 which is a semiconductor substrate, a metal electrode 4411 which is a source / drain electrode, and a Si which is a gate insulating film.
An MIS transistor structure is formed in combination with the O ₂ gate insulating layer 4049 and the n-type polycrystalline silicon electrode 4410 serving as a gate electrode. The gate insulating film 4049 having the MIS transistor structure and the p-type silicon substrate 4
041, the following structure is provided.

On a p-type silicon substrate 4041, a 4 nm thick SiO ₂ film 4043 as an insulating layer is provided, and on the insulating layer, gold fine particles 4044 as first fine particles are provided. A thermally oxidized SiO ₂ film 4 having a thickness of about 2 nm, which functions as a barrier against the movement of electric charges, on the first fine particles.
045 (first barrier layer). On the first barrier layer, silicon fine particles 4046 having a diameter of 1 nm, which are second fine particles, are provided. On the second fine particle,
An SiO ₂ film 4047 (second barrier layer) having a thickness of about 2 nm which functions as a barrier against the movement of electric charges is provided. On the second barrier layer, gold fine particles 4048 as third fine particles are provided. Further, the SiO ₂ film 404
3, gold fine particles 4044, thermally oxidized SiO ₂ film 4045, silicon fine particles 4046, SiO ₂ film 4047, and SiO ₂ side walls 441 on the side surfaces of gold fine particles 4048
2 are provided. Here, gold fine particles 4044, 40
48 have a height of about 1 nm and a lateral diameter of 5 to 5 nm.
8 nm.

Here, the first fine particles (gold fine particles 404)
The effective particle size of 4) and the third fine particle (gold fine particle 4048) is the second fine particle (silicon fine particle 404).
6), which is 1.8 times or more, and their capacitances are larger than those of the second fine particles. Here, the in-plane density of the silicon fine particles 4044 and 4048 is 1 × 10 ¹¹
cm ⁻² to 1 × 10 ¹³ cm ⁻² , and the in-plane density of the fine gold particles is about 1 × 10 ¹⁰ cm ⁻² to 1 × 10 ¹² cm ⁻² . In addition, an SiO ₂ side wall 4412 made of an insulator is provided around the region where the fine particles are provided.
In this manner, since the periphery of the region where the fine particles are provided is covered with the insulator sidewall, the accumulated charge can be reliably prevented from disappearing due to a short circuit from the periphery. Also, even if the initial charge is accumulated in the fine particles,
Emission of charges to the outside can be effectively suppressed.

In the semiconductor memory device of this embodiment, at least one of the gate region and the region in contact with the source region and the drain region and / or the region in contact with the drain region. In the region, by providing at least a portion where the fine particle dispersion layer does not exist,
When a voltage is applied from the source region to the drain region, a short-circuited current can be prevented from flowing through the fine particles.

In this embodiment, the injection, holding, and injection of electric charges into the fine particles are performed according to the same principle as in the twenty-fourth embodiment.
A structure capable of controlling release can be realized. Further, in the present embodiment, since the structure for holding the charge is formed in the gate region of the MIS transistor structure, the MIS is changed in accordance with the change in the distribution of the charge in the first and third fine particles. The threshold voltage of the type transistor characteristic changes. As a result, the device operates as a high-speed and highly reliable nonvolatile semiconductor memory device.

Further, in the present embodiment, the region where the fine particles of the gate region are provided has a shape divided into a plurality of regions at least in a direction in which a short-circuit current between the source and the drain is obstructed. It is also possible to prevent a short-circuited current from flowing through the fine particles when a voltage is applied to the region.

(Twenty-Sixth Embodiment) FIG. 45 is a sectional view of a semiconductor device according to a twenty-sixth embodiment of the present invention.
On a p-type silicon substrate 4051 which is a semiconductor substrate, a first
An SiO ₂ film 4052 having a thickness of 4 nm is provided as an insulator layer, and silicon fine particles 4053 having a diameter of 5 nm are provided as first fine particles on the first insulator layer. On the first fine particles, a first fine particle dispersion layer in which silicon fine particles 4055 as second fine particles are dispersed in SiO ₂ as a barrier layer functioning as a barrier against the movement of electric charges, that is, SiO _x deposited using CVD equipment
(1.5 <x <2) silicon-rich oxide film 405
4 are provided. In addition, a second
Silicon fine particles 4056 having a diameter of 5 nm
Is provided.

Here, the surfaces of the first fine particles and the silicon fine particles 4053 and 4056 which are the third fine particles are both oxidized, and the periphery of the silicon fine particles 4053 and 4056 functions as a barrier against the movement of electric charges. Thickness 1n
It is covered by about m m of SiO ₂ film (barrier layer). On the third fine particles, a second insulator layer having a thickness of 10 n
An m ₂ SiO ₂ film 4057 is provided, and an n-type polycrystalline silicon electrode 4058 as an electrode layer is provided on the uppermost portion.

Silicon fine particles as first and third fine particles
The elements 4053 and 4056 are formed by the CVD method.
The in-plane density was 1 × 10^Tencm^-2~ 1 × 10¹²
cm ^-2It is about.

In the twenty-fourth embodiment, since the second fine particles are formed as a fine structure on the first barrier layer, it is necessary to control the particle size distribution, the in-plane dispersion state, and the like. However, in the present embodiment, the SiO _x layer (1.5 <x <2)
By using the (silicon-rich oxide film 4054), a structure in which fine silicon particles 4055 are dispersed in SiO _{2 as a} barrier layer can be easily realized. That is,
Since the fine silicon islands (silicon fine particles 4055) in the SiO _x layer function as the second fine particles,
In particular, there is no need to control the microstructure. As a result, the manufacture of the semiconductor device is facilitated and the reproducibility of the device characteristics is high. Si
The O _x layer (silicon-rich oxide film 4054) can be easily produced by a CVD method, but can also be produced by a sputtering method or the like. The SiO _x layer (1.5 <
When the oxygen content ratio x of x <2) is in the range of 1.8 <x <2, a finer silicon island can be formed, which is preferable. SiO _x layer (1.5 <x <2)
Has a thickness in the range of 5 to 20 nm, so that the device can operate at a low voltage. In this embodiment, the thickness is 10 n
m of SiO _1.9 is used.

Here, S functioning as a second fine particle
Silicon fine particles 405 in iO _x layer (1.5 <x <2)
The particle diameter of No. 5 is 1 nm or less, and the diameters of the silicon fine particles 4053 and 4056, which are the first and third fine particles, are 1.8 times or more thereof.

In this embodiment, the fabricated SiO_x 
The layer is used without any special heat treatment,
Recon Island is used as fine particles.
iO _x The layer is heat treated at about 1000 ° C.
It is also possible to control the particle size by growing
You.

In this embodiment, the SiO _x film is used as the fine particle dispersion layer. However, a layer formed by implanting semiconductor ions or metal ions into the insulator is used instead of the fine particle dispersion layer of the present embodiment. By using
Further, a structure having a charge control function equivalent to that of the fine particle dispersion layer of the present embodiment can be easily produced. Although an insulator into which semiconductor ions or metal ions are implanted has a structure different from a structure in which silicon microcrystals or the like are dispersed, the level formed by a semiconductor or a metal atom in the insulator is the first fine particle having a small particle diameter according to the present invention. Since it exerts substantially the same function as the body, it can be used as a fine particle dispersion layer in the present invention. For example, S implanted with Si ions or W ions, etc.
By using an iO ₂ film or the like as the fine particle dispersion layer, the same effect as in the present embodiment can be exhibited.

In this embodiment, the injection, holding, and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the twenty-fourth embodiment. Furthermore, in the present embodiment, as described above, there is no need to manufacture the second fine particles as a fine structure, so that there is an advantage that manufacturing is easy and reproducibility of element characteristics is high.

Further, in the present embodiment, unlike the twenty-fourth embodiment, the charge transfer between the first fine particle and the third fine particle is usually performed not only by the single second fine particle but also by the single second fine particle. , Through a plurality of second fine particles. In the tunnel process through a plurality of fine particles, the tunnel current under a weak electric field at the time of charge retention is reduced as compared with the process through a single fine particle, so that a longer-term charge retention becomes easier.

In the semiconductor device of this embodiment, the silicon fine particles 405 as the first and third fine particles are used.
The surface of 3,4056 is oxidized, and its periphery is covered with a barrier layer functioning as a barrier against the movement of electric charges. The structure without the barrier layer can also simplify the element manufacturing process. .

Further, in the semiconductor device of this embodiment,
The provision of the barrier layer between the first fine particle or the third fine particle and the fine particle dispersion layer can further suppress the leak current.

Further, in the semiconductor device of this embodiment,
The first fine particles and the third fine particles are also dispersed in the inside of the barrier layer functioning as a barrier against the movement of the electric charges, so that the device can be easily manufactured.

By using the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the twenty-fifth embodiment can be formed.

FIG. 46 is a sectional view of a semiconductor memory device formed by using the semiconductor device of this embodiment. As shown in the figure, a p-type silicon substrate 406 which is a semiconductor substrate
1, an n-type conductive region 4062 functioning as a source region or a drain region, an SiO ₂ film 4063, gold fine particles 4064 as first fine particles, and thermally oxidized SiO 2.
_{A second} film 4065, silicon fine particles 4067 as _second fine particles, an SiO ₂ film 4068, and an n-type polycrystalline silicon electrode 4069 are provided. Furthermore, SiO ₂
Film 4063, gold fine particles 4064, thermally oxidized SiO ₂ film 40
65, silicon fine particles 4067 and SiO ₂ film 4068
Are provided with SiO ₂ side walls. Further, a metal electrode 4610 which is a source / drain electrode is provided on the n-type conductive region 4062, and an MIS transistor structure is formed as a whole.

Thus, it is possible to prevent the threshold voltage of the MIS transistor characteristic from changing according to the change in the distribution state of the charges in the first fine particles (silicon fine particles 4064) and the third fine particles (silicon fine particles 4067). Use
This semiconductor element can be operated as a high-speed and highly reliable nonvolatile semiconductor memory element.

[0413] In the semiconductor memory device of this embodiment, as in the twenty-fifth embodiment, the periphery of the region where the fine particle dispersion layer and the like are provided is covered with an insulator.
It is desirable that the accumulated charge distribution does not disappear due to a short circuit from the periphery. Further, even if the initial charge is accumulated in the fine particles, the charge is not released to the outside, which is desirable.

In the semiconductor memory device of this embodiment, at least one of or both of a region of the gate region above the source region and the source region and a region above the drain region and the region of the drain region. In the region, by providing at least a portion where the fine particle dispersion layer does not exist,
When a voltage is applied from the source region to the drain region, a short-circuited current can be prevented from flowing through the fine particles.

(Twenty-Seventh Embodiment) FIG. 47 is a sectional view of a semiconductor device according to a twenty-seventh embodiment of the present invention.
On a p-type silicon substrate 4071 which is a semiconductor substrate, a 4 nm thick SiO ₂ film 4072 which is a first insulator layer
And silicon fine particles 4075 as the first fine particles and ion-implanted tungsten atoms 4074 as the second fine particles are dispersed in the SiO ₂ layer which functions as a barrier against the movement of electric charges. And a fine particle dispersion layer 4073 having a thickness of about 5 nm. On the fine particle dispersion layer 4073, a 10-nm-thick S
An iO ₂ film 4076 is provided, and an n-type polycrystalline silicon electrode 4077 as an electrode layer is provided on the uppermost portion.

Here, the first fine particles (silicon fine particles 4075) and the second fine particles (tungsten atoms 407) are used.
4) are fine particles dispersed in the SiO ₂ layer serving as a barrier layer, and the particle diameter of the second fine particles (tungsten atom 4074) is 2.6 nm or more, and It is at least 1.8 times as large as the first fine particles (silicon fine particles 4075) having a diameter of about 0.5 nm or less.

The fine particle dispersion layer 4073 as described above is
After depositing a SiO _x film (1.5 <x <2) using a VD apparatus, heat treatment is performed at about 1100 ° C. to grow silicon microparticles 4075 and further ion-implant tungsten atoms 4074. can do.

In the present embodiment, as the second fine particles,
Although tungsten atoms 4074 implanted in the insulator are used, other semiconductor particles or metal atoms introduced by ion implantation, or semiconductor particles or metal fine particles introduced by other methods can also be used.

[0419] In the present embodiment, similarly to the twenty-fourth embodiment, charge transfer and retention between fine particles can be performed. The first microparticles in the present embodiment have a function of either the first microparticles and the third microparticles in the twenty-fourth embodiment, or a function of both. For example, when a positive voltage is applied to the upper electrode at the time of writing, electrons are extracted from the first fine particles relatively on the substrate side, and charge transfer through some second fine particles causes the first fine particles closer to the upper electrode to move. It is injected and accumulated in one particle. The first fine particles and the second fine particles have various positional relationships in the fine particle dispersion layer, and the extraction and accumulation of the electric charges are selectively caused between the fine particles in which the electric charge transfer is easier. Further, in some cases, electrons are further extracted from the accumulated first fine particles, and move to higher first fine particles.

[0420] Thus, the first fine particles and the second
Even if the positional relationship of the fine particles is not controlled, the charge transfer occurs from an easy place in a self-selective manner, and finally, the first lower fine particles have a positive charge, and the upper fine particles have a negative charge. Many charges are distributed. When the write voltage is removed, this charge distribution is somewhat reduced, but much is retained for a long time without disappearing.

It should be noted that a certain amount of extra charge (for example, electrons) is externally injected and accumulated in the fine particle dispersion layer by applying a high voltage to the upper electrode initially, and the distribution of the extra charge is made by the external voltage. It is also possible to record information by changing.

As described above, also in the present embodiment, the injection, holding, and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the twenty-fourth embodiment. Also, the second
In the fourth embodiment, it is necessary to control the thickness of the fine particle dispersion layer in order to obtain an appropriate element operation speed and a recording retention period. In the present embodiment, however, the charge transfer is selectively performed from a place where the charge transfer is easy. Therefore, the allowable thickness range is wide and the device can be easily manufactured.

In this embodiment, there is a clear distinction between the first fine particles and the second fine particles. However, continuous fine particles having the same material and having various particle diameters over a sufficiently wide range are produced. It is also possible to provide fine particles having an appropriate particle size distribution, and make the fine particles having a large particle diameter function as the first fine particles, and the fine particles having a small particle diameter function as the second fine particles. In this case, a clear distinction cannot be made between the first microparticles and the second microparticles, but the injected charge is selectively retained by the microparticles having a large particle diameter and a large capacitance. The fine particle selected by the electric charge functions as the first fine particle. In order to maintain the charge distribution, the particle size distribution of the fine particles is at least 0.7 times to 1.4 that of the fine particles having an intermediate particle size.
It is necessary to have a distribution in a wider range than the double range. For long-term charge retention, at least 0.4 to 1.6 times.
It is desirable to have a particle size distribution in the range of twice or more.

A semiconductor memory device similar to that of the twenty-fifth embodiment can be constructed by utilizing the structure of the semiconductor device of this embodiment.

FIG. 48 is a sectional view of a semiconductor memory device formed by using the semiconductor device of this embodiment. As shown in the figure, a p-type silicon substrate 408 which is a semiconductor substrate
On 1, and n-type conduction region 4082 functioning as a source region or a drain region, a SiO ₂ film 4083, and the SiO ₂ film 4083 which is a first insulator layer, the SiO ₂ layer in a barrier layer 1 A fine particle dispersion layer 4084 having a thickness of about 5 nm in which silicon fine particles 4086, which are fine particles, and ion-implanted tungsten atoms 4085, which are second fine particles, are dispersed, an SiO ₂ film 4087, and n-type polycrystalline silicon. An electrode 4088 is provided. Further, the SiO ₂ film 4083, the fine particle dispersion layer 4084, and the S
_On the side surface of the iO ₂ film 4087, a SiO ₂ sidewall 4810 is provided. Also, the n-type conduction region 408
2, a metal electrode 408 serving as a source / drain electrode
9, an MIS transistor structure is formed as a whole.

Thus, the threshold voltage of the MIS transistor characteristic changes between the state where the electric charge is held in the second fine particle body and the state where there is no electric charge, so that low-voltage, high-speed and long-term recording is possible. It operates as a nonvolatile semiconductor memory element.

In addition, since the SiO ₂ side wall 4810 as an insulator is provided around the fine particle dispersion layer 4084, it is desirable that the accumulated charge does not disappear due to a short circuit from the periphery. It is also preferable that even if the initial charge is accumulated in the fine particles, the charge is not released to the outside.

In the semiconductor memory device of this embodiment, at least one of the gate region and the region in contact with the source region and the drain region and / or the region in contact with the drain region. In the region, by providing at least a portion where the fine particle dispersion layer does not exist,
When a voltage is applied from the source region to the drain region, a short-circuited current can be prevented from flowing through the fine particles.

(Twenty-eighth Embodiment) FIG. 49 is a sectional view of a semiconductor device according to a twenty-eighth embodiment of the present invention.
On a p-type silicon substrate 4091 which is a semiconductor substrate, a first
An SiO ₂ film 4092 having a thickness of 5 nm is provided as an insulator layer, and silicon fine particles 4093 having a diameter of 3 nm as a first fine particle are provided on the first insulator layer. On the first fine particles, a first SiO ₂ layer having a thickness of 1.
An SiO ₂ film 4094 of about 8 nm is provided. On the first SiO ₂ layer, an SiO _x N _y layer (0 ≦ x <2,
0 <y ≦ 4/3), a Si ₃ N ₄ layer 4095 having a thickness of about 8 nm is provided, and a second SiO ₂ layer 4096 having a thickness of about 1.8 nm is provided on the SiO _x N _y layer. Is provided. On the second SiO ₂ layer, silicon fine particles 4097 having a diameter of 3 nm, which are second fine particles, are provided. A 12-nm-thick SiO ₂ film 4098, which is a second insulator layer, is provided on the second fine particles.
At the top is an n-type polycrystalline silicon electrode 409 which is an electrode layer
9 are provided.

Here, the first fine particles and the second fine particles
The silicon fine particles are formed by a CVD method.
The in-plane density was 1 × 10^Tencm^-2~ 1 × 10¹²
cm ^-2It is about.

In this embodiment, unlike the twenty-fourth embodiment, no two kinds of fine particles having different particle diameters are provided. However, in the present embodiment, the SiO _x N _y layer (0 ≦ x <2,
0 <y ≦ 4/3) is the first SiO ₂ layer and the second SiO ₂
Since it has a configuration which is sandwiched between the layers, SiO _x
Near the interface between the N _y layer and each SiO ₂ layer and the SiO _x N _y
A level at which charges can be transferred (interface level) is generated inside the layer. Since the interface level has a large energy interval between levels and a large potential increase upon receiving charges, the same function as a fine particle having a small particle size can be provided effectively.

That is, in the present embodiment, SiO _x N _y
Near the interface between the layer and each SiO ₂ layer and the SiO _x N _y
The interface state inside the layer has a function equivalent to that of the second fine particles in the twenty-fourth embodiment. As a result, in the semiconductor device of this embodiment, the first fine particles (silicon fine particles 4093) and the second fine particles (silicon fine particles 493) are formed.
097) can be stably held. Therefore, also in the present embodiment, the injection, holding, and release of electric charges into the fine particles can be efficiently controlled by the same principle as in the twenty-fourth embodiment.

Also, in the twenty-fourth embodiment, it is necessary to form the second fine particles as a fine structure on the first barrier layer. However, in this embodiment, since the SiO _x N _y layer is used, this is In this respect, there is no need to particularly control the microstructure. As a result, there is an advantage that the manufacture of the semiconductor device is easy and the reproducibility of the device characteristics is high. For the SiO _x N _y layer, a high quality film can be easily manufactured by the CVD method.

In this embodiment, SiO_x N_y Layer (0 ≦ x
<2, 0 <y ≦ 4/3) Si _Three N_Four Using layers
However, besides this, SiO_x N_y Layer (0 <x <2, 0 <y <4
/ 3) a silicon oxynitride film having a composition expressed as
Can also be used.

Using the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the twenty-fifth embodiment can be formed.

FIG. 50 is a sectional view of a semiconductor memory device formed using the semiconductor device of this embodiment. As shown in the figure, a p-type silicon substrate 410 which is a semiconductor substrate
1, an n-type conductive region 4102 functioning as a source region or a drain region, and Si as a first insulator layer.
O ₂ film 4103, silicon fine particles 4104 as first fine particles, and SiO ₂ film 41 as first SiO ₂ layer
05 and a SiO _x N _y layer (0 ≦ x <2, 0 <y ≦ 4 /
3) Si ₃ N ₄ layer 4106, second SiO ₂ layer 4107, and silicon fine particles 41 as second fine particles
08, a SiO ₂ film 4109 as a _second insulator layer,
An n-type polycrystalline silicon electrode 4110 serving as an electrode layer is provided. Further, the SiO ₂ film 4103, the silicon fine particles 4104, the SiO ₂ film 4105, the Si ₃ N ₄ layer 41
06, second SiO ₂ layer 4107, silicon fine particles 41
08 and the SiO ₂ film 4109 are provided with side walls of SiO ₂ . Also, the n-type conduction region 41
02, a metal electrode 41 serving as a source / drain electrode
11 are provided, and an MIS transistor structure is formed as a whole.

As a result, the threshold voltage of the MIS transistor characteristics changes in accordance with the change in the distribution of charges in the first fine particles and the second fine particles. Operates as an element.

In the semiconductor memory device of this embodiment,
A portion where at least the fine particle dispersion layer and the fine particles do not exist in at least one of the region above the source region and the above-mentioned source region, or the region above the drain region and the above-mentioned drain region in the gate region, or both. Is provided, when a voltage is applied from the source region to the drain region, it is possible to prevent a short-circuited current from flowing through the fine particles.

[0439] It is preferable that the periphery of the region where the fine particles and the like are provided is covered with an insulator, so that the accumulated charge distribution does not disappear due to a short circuit from the periphery. Further, this is a preferable structure in that even if the initial charge is accumulated in the fine particles, the charge is not released to the outside.

As described above, the semiconductor device having the novel structure of the present invention has a higher reliability than ever before, means for injecting, holding, and erasing charges into fine particles that can be easily manufactured and can hold charges for a long time. Is provided.

In the twenty-fourth to twenty-eighth embodiments, a p-type silicon substrate is used as a semiconductor substrate. In the present invention, a substrate using another semiconductor material such as an n-type silicon substrate or a GaAs substrate is used. You can also.

[0442] Further, in Embodiment 24 to 28, but the insulating layer is constituted by SiO _2, as described _{above, Si 3 N 4, Si x} O y N z (4x = 2y + 3
z), the insulating layer may be formed of another insulating material such as CeO ₂ , ZnS, ZnO, Al ₂ O ₃ .

In the twenty-fourth to twenty-eighth embodiments, silicon fine particles, gold fine particles, tungsten atoms and the like are used as fine particles, but other semiconductor materials and metals can be used as described above.

(Twenty-Ninth Embodiment) FIG. 51 is a sectional view of a semiconductor device according to a twenty-ninth embodiment of the present invention.
P-type silicon layer 50 which is a semiconductor layer provided on a substrate
An SiO ₂ film 5012 having a thickness of about 4 nm, which is a barrier layer functioning as a barrier against the movement of electric charges, is provided on the substrate 11. On the barrier layer, a 9 n-thick charge carrier
m of metal tungsten 5014 is provided, and a 10 nm thick SiO ₂ film 5 serving as an insulator layer is provided on the charge holding carrier.
015 is provided, and the uppermost portion is an electrode layer n
A type polycrystalline silicon electrode 5016 is provided. Further, between the semiconductor layer and the charge retaining carrier, silicon fine particles 5013 having a diameter of 2 nm, which are fine particles, are provided inside the barrier layer. In the present embodiment, the region where the fine particles are provided is limited to a part of the region between the semiconductor layer and the charge carrier, and the silicon fine particles 5013 are 1 × 10 ¹¹ cm 3 by a chemical vapor deposition (CVD) method. ^-2 to 1
It is formed with an in-plane density of about × 10 ¹³ cm ⁻² .

In order to explain the function of this structure, first, the configuration according to the prior art and the charge injection / holding mechanism will be described.

FIG. 52 is a cross-sectional view showing a conventional semiconductor device using a plurality of silicon fine particles described in the above-mentioned document. In this semiconductor memory device, a tunnel oxide film 5022 made of SiO ₂ film on the p-type silicon substrate 5021, a SiO ₂ film 5024 are deposited in this order from the bottom, more n-type polycrystalline silicon electrode 5025 thereon Is provided. Silicon fine particles 5203, which are fine particles, are embedded between the tunnel oxide film 5022 and the SiO ₂ film 5024.

In this semiconductor device, by applying a positive voltage to n-type polycrystalline silicon electrode 5025, silicon fine particles 5023 are passed through tunnel oxide film 5022.
Can be injected into the device. In addition, by applying a negative voltage to the n-type polycrystalline silicon electrode 5025, electrons in the silicon fine particles 5023 can be extracted. The threshold voltage of a memory element using a semiconductor element can be changed depending on the presence or absence of the electrons in the silicon microparticle 5023. Information is written and read by associating the level of the threshold voltage with information H (high) and information L (low).

According to the conventional semiconductor device shown in FIG. 52, it has been found that it is difficult to fabricate a practical semiconductor memory device which enables high-speed charge injection / discharge and ensures long-term charge retention. . In this type of semiconductor device, both the speed of writing / erasing and the retention characteristics during charge retention are governed by the tunnel transition probability between the fine particles passing through the barrier and the semiconductor substrate. Therefore, in order to realize a high-speed and long-life element, it is necessary to sufficiently increase the ratio of the tunnel current (write / erase current) during writing / erasing to the tunnel current (leakage current) during charge retention. .

However, in the conventional semiconductor device shown in FIG. 52, only the number of charges of the fine particles and the potential of the fine particles with respect to the semiconductor substrate are different at the time of writing, erasing, and holding of electric charges. / Tunnel barrier / Semiconductor substrate
Reduce the tunnel current of this system to a low external voltage (upper electrode voltage)
It is not easy to make a big change with. For example, if the height or thickness of the tunnel barrier is increased in order to suppress the leak current, the write / erase current also decreases, and the write / erase speed decreases.

Also, the potential of the fine particles at the time of writing (or at the time of erasing) is determined by the positional relationship between the device structure and the fine particles. Here, when the fine particles are brought closer to the upper electrode (the n-type polycrystalline silicon electrode 5025 in FIG. 52), the potential rise of the fine particles at the time of writing increases, so that the writing current can be increased in principle. However, if the particulate matter is brought too close to the upper electrode side, the gate voltage shift at the time of device reading becomes small, and the sensitivity is lowered too much.

If the electrostatic capacity of the fine particles is increased, the rise in the potential of the fine particles at the time of holding the electric charges can be suppressed. However, since the capacitance of the fine particles actually increases, if the particle size of the fine particles is increased or the distance between the fine particles and the semiconductor substrate is reduced, the tunnel probability between the fine particles and the semiconductor substrate increases. On the contrary, the leakage current increases. In principle, increasing the particle size of the microparticles and increasing the thickness of the tunnel barrier at the same time may reduce only the leakage current to some extent, but if the particle size is too large, the in-plane density of the microparticles will decrease. And can no longer hold the required amount of charge to support the sensitivity of the device. further,
If the barrier thickness is too large, the structure becomes close to that of a flash EEPROM, and a large voltage is applied to the barrier film, so that a problem occurs in that the film quality is deteriorated due to charge transfer. Also,
Even in the manufacturing process, high precision is required for controlling the particle size, the distribution state of the particles, and the barrier thickness in order to obtain a device with a long life.

As described above, it is difficult to realize an element capable of performing a high-speed write / erase operation and capable of long-life recording by the conventional technique. On the other hand, according to the configuration of the present invention, it is possible to greatly reduce the leak current at the time of holding the charges without lowering the writing / erasing speed as described below.

The specific operation of charge injection and charge holding of the device of the present invention will be described below. In the writing process at the time of charge injection, a writing voltage is applied to the upper electrode (n-type polycrystalline silicon electrode 5016) from the outside, so that the barrier layer (S
Charges are extracted from the semiconductor substrate by the tunnel current through the iO ₂ film 5012), and fine particles (silicon fine particles 5
013). Since the potential of the fine particles and the relationship between the fine particles and the semiconductor surface in this process are almost the same as in the writing process of the prior art, the charge transfer speed is also equal.

In the present invention, the charges on the fine particles move to the adjacent charge carrier (metal tungsten 5015) via the barrier layer. Here, the tunnel transition between the fine particle and the charge retaining carrier is under substantially the same conditions as the tunnel transition between the fine particle and the semiconductor surface. Therefore, when the potential difference is the same, the speed of charge transfer from the semiconductor surface to the fine particles and the speed of charge transfer from the fine particles to the charge holding carrier are almost the same. However, in the present embodiment, the potential rise (ΔV = Δq / Cdot) of the fine particles due to the electric charges in addition to the externally applied write voltage between the already charged fine particles and the non-charged charge holding carrier. Here, q is the elementary charge, and Cdot is the silicon fine particle 5013.
An electric field is generated due to the capacitance. The effect of the potential increase due to the electric charge of the fine particles having a small capacitance is great, and the electric charge transfer from the fine particles to the charge holding carrier is further accelerated. In the writing process of the present invention, it is necessary to go through two tunneling processes. However, since the charge transfer from the fine particles to the charge holding carrier is performed at a speed equal to or higher than the charge transfer from the semiconductor substrate to the fine particles, the entire process is performed. Can achieve a writing speed equivalent to that of the device according to the prior art. Although the writing process has been described here, the same applies to the erasing process in which a negative voltage is used to release accumulated charges from the fine particles.

Next, when the writing is completed and the writing voltage from above is removed, the fine particles and the charge holding carrier are set to the potentials corresponding to the respective charges and capacitances. Some of the fine particles have surplus charge, but the fine particles are adjacent to the semiconductor layer, and the capacitance is small and the potential rise per charge is large. Return. On the other hand, since the charge holding carrier has a large capacitance,
The rise in the potential is suppressed low. Although the charge holding carrier itself has a large state density, the state density of the adjacent fine particles is low, so that the probability of charge transfer from the charge holding carrier having a low potential rise to the fine particles is low. In addition, during the charge transfer, the fine particles consume energy corresponding to half of the potential rise (ΔV / 2). Therefore, when the fine particles are sufficiently small, the transition of the charge having a lower energy level is suppressed. As a result, the charges accumulated on the charge holding carrier are held for a long time.

In the above description, the writing / erasing speed of the device according to the present invention is made equal to that of the device according to the prior art. However, the effect of suppressing the leak current and stabilizing the charge retention is further utilized to further increase the barrier. Writing by reducing the thickness of the layer
It is also possible to realize a higher erasing speed and a lower writing / erasing voltage.

When the electron affinity of the fine particles is smaller than that of the charge carrier, the accumulated electrons are further stabilized.

The semiconductor substrate, the first barrier layer, the first fine particles, the second barrier layer, and the fine particles in the band state at the conduction band edge of the second fine particles in this embodiment have no charge, Changes in the injection state and the charge holding state are as shown in FIGS.

That is, the Fermi level of the second fine particle in the charge holding state (see FIG. 27C) is higher than that in the state without charge (see FIG. 27A). Since the potential is lower than the energy level at the conduction band edge of the body, the charge can be stably held for a long time. When electrons are used as charges, the electron affinity of the second fine particles is larger than the electron affinity of the first fine particles, and when holes are used as the charges, the forbidden band of the second fine particles is used. Since the sum of the width and the electron affinity is smaller than that of the second fine particles, the charge is stably held in each of the second fine particles. In addition, when electrons are used as charges, the electron affinity of the fine particles is smaller than that of the semiconductor layer, and when holes are used as charges, the sum of the electron affinity and the forbidden band width of the fine particles is larger than the semiconductor layer. Thereby, the electric charge is stably held in the second fine particles.

When the state of the fine particles is quantized and the energy interval between the quantum levels is larger than the thermal energy at room temperature and the potential rise of the charge holding carrier, the charge holding can be stabilized by the quantum effect.

FIGS. 53A to 53C are diagrams schematically showing a band structure near the conduction band edge when electrons are used as injected charges. As shown in FIG. 53 (a), the fine particles are quantized in a state where there is no charge in the first fine particles, and the ground level 5042 is occupied by electrons, and the first excitation level 504 is obtained.
1 is empty, and the energy interval between them is sufficiently larger than the heat energy. When an electric field is applied for writing from outside,
As shown in FIG. 53B, electrons are injected from the semiconductor substrate into the charge holding carrier by a tunneling process 5043 through the first excitation level 5041. Thereafter, excluding the external electric field, when the particle diameter of the charge carrier is large, the Fermi level 5044 of the charge carrier becomes lower than the first excitation level 5041 as shown in FIG. If the difference between the two is smaller than the heat energy, it becomes difficult to release the charge, and the charge in the charge holding carrier is stably held. Here, the case where electrons are used as the injected charges has been described, but the same effect can be obtained when holes are used.

As described above, in the semiconductor device according to the present invention, by independently providing the charge holding carrier and the fine particles for controlling the charge transfer, writing and erasing can be performed at a high speed, and charge holding can be performed for a longer time than ever before. A possible and reliable means of injecting, holding and erasing charges into the particulate matter is provided.

(Thirtieth Embodiment) FIG. 54 is a sectional view of a semiconductor memory device according to a thirtieth embodiment of the present invention.
In the p-type silicon layer 5051 which is a semiconductor layer, a functioning n-type conduction region 5 which is a source region or a drain region is provided.
052 is provided. Further, the p-type silicon layer 50
41, a metal electrode 5 serving as a source / drain electrode
058 and SiO ₂ gate insulating layer 5 as a gate insulating film
056 and an n-type polycrystalline silicon electrode 5 serving as a gate electrode
057 is provided. That is, the semiconductor device of the present embodiment is a semiconductor memory device having a MIS transistor structure.

The following structure is provided between the gate insulating layer 5056 and the p-type silicon layer 5051 of the MIS transistor structure. p-type silicon layer 505
1, a 3.5-nm-thick SiO ₂ film 53 is provided as a barrier layer functioning as a barrier against the movement of electric charges. Further, a metal iron 5055 having a thickness of 8 nm as a charge holding carrier is provided on the barrier layer.

Further, the semiconductor layer and the charge carrier
In the meantime, a fine particle having a diameter of 1 nm is formed inside the barrier layer.
Of silicon fine particles 5054 are provided. This embodiment
In the state, the region provided with the fine particles is an MIS type transistor.
Above and above the source region of the transistor
The silicon fine particles 5054
Is 1 × 10 by chemical vapor synthesis (CVD).¹¹c
m^-2~ 1 × 10¹³cm ^-2It is formed with about the in-plane density
You.

Also in the present embodiment, a structure capable of controlling the injection, holding and release of charges into the charge holding carrier can be realized by the same principle as in the twenty-ninth embodiment. Further, in the present embodiment, the structure for holding the charge is formed in the gate region of the MIS transistor structure, so that the characteristics of the MIS transistor are different between the state where the charge is held on the charge holding carrier and the state where the charge is not present. The threshold voltage changes.
Thereby, it operates as a non-volatile semiconductor memory element capable of low-voltage, high-speed and long-term recording. Furthermore, since a basic memory operation is realized by a single element, high-density integration is possible.

In the present embodiment, the region where the fine particles are provided is limited to the region above the source region of the MIS transistor and the region in contact with the source region. Even if it fluctuates, if the potential of the source region is kept constant, it is possible to suppress charge transfer between the charge holding carrier and the read operation. At the time of writing / erasing of the element, injection / release of charges can be controlled by applying a larger potential difference between the source electrode and the gate electrode than at the time of reading.

Note that, depending on the circuit system for driving the semiconductor element, the region where the fine particles are provided is M
In some cases, the charge control can be more appropriately performed by limiting the region to the upper portion of the drain region of the IS transistor and the region in contact with the drain region, or to the region in contact with the channel region.

Further, the area where the fine particles are provided is not limited.
If a configuration in which the fine particles are provided on the entire surface between the semiconductor layer and the charge retaining carrier is used, the process of manufacturing the element can be simplified.

As described above, the semiconductor device having the novel structure of the present invention provides a charge injection, holding, and erasing means which is easier to manufacture than ever before, has high reliability, and can hold charge for a long time. You.

(Thirty-First Embodiment) FIG. 55 is a sectional view of a semiconductor device according to a thirty-first embodiment of the present invention.
P-type silicon layer 50 which is a semiconductor layer provided on a substrate
An SiO ₂ film 5062 having a thickness of about 4 nm, which is a barrier layer functioning as a barrier against the movement of electric charges, is provided on 61. On the barrier layer, a 9 n-thick charge carrier
m metal tungsten 5064 is provided, and a 10 nm thick SiO ₂ film 5 serving as an insulator layer is provided on the charge holding carrier.
065, and the uppermost portion is an electrode layer n
A type polycrystalline silicon electrode 5066 is provided. Further, between the semiconductor layer and the charge holding carrier, the 29th
Instead of the fine particles in the embodiment, the SiO _x N _y layer 5063 (0 ≦ x <2, 0 <y ≦ 4/3) (Si ₃ N ₄ )
Film or SiON film). In the present embodiment, the region where the SiO _x N _y layer 5063 is provided is limited to a part of the region between the semiconductor layer and the charge holding carrier.
The iO _x N _y layer 5063 is easily formed by the CVD method.

In this embodiment, the SiO _x N _y layer 5
063 and the vicinity of the interface between the SiO ₂ film 5065 or SiO _x
The interface state formed inside the N _y layer 5063 has the same charge transfer function as the fine particles in the twenty-ninth embodiment. Therefore, the same effect as in the twenty-ninth embodiment can be exerted.

In addition, since the SiO _x N _y layer 5063 can be easily formed by CVD as compared with the case of forming silicon fine particles, manufacturing can be facilitated.

By using the structure of the semiconductor device of this embodiment, a semiconductor memory device similar to that of the twenty-ninth embodiment can be formed.

FIG. 56 is a sectional view of a semiconductor memory device formed using the semiconductor device of the thirty-first embodiment.
As shown in the figure, an n-type conduction region 5072 functioning as a source region or a drain region and a silicon layer serving as an insulator layer are formed on a p-type silicon substrate 5071 which is a semiconductor substrate.
O ₂ film 5073 and SiO _x N _y layer 5074 (0 ≦ x <
2,0 <y ≦ 4/3), metal tungsten 5075 as a charge holding carrier, SiO ₂ film 5076, and n-type polycrystalline silicon electrode 5077 are provided. Also, n
A metal electrode 5078, which is a source / drain electrode, is provided on the mold conduction region 5072, forming an MIS transistor structure as a whole.

As a result, the device operates as a non-volatile semiconductor memory device capable of low-voltage, high-speed and long-term recording. Furthermore, since a basic memory operation is realized by a single element, high-density integration is possible.

In the above embodiments, injection and injection into the fine particles are performed.
As the stored charge, both electrons and holes can be used.

In the twenty-ninth to thirty-first embodiments, a p-type silicon layer is used as a semiconductor layer.
Other semiconductor material films such as a mold silicon layer, a polysilicon thin film, and a GaAs layer can also be used.

In the twenty-ninth to thirty-first embodiments, silicon fine particles are used as fine particles, but fine particles made of other semiconductor materials or metals may be used.

In the twenty-ninth to thirty-first embodiments, tungsten and iron are used as charge holding carriers. However, a similar effect can be obtained by using a metal or another semiconductor material.

In the twenty-ninth to thirty-first embodiments, only one layer of fine particles is provided inside the barrier layer between the charge holding carrier and the semiconductor substrate. A structure in which dispersed regions are provided can also be employed.

[0482] Further, in the first 29 to second 31 embodiments, although the insulating layer is constituted by SiO _2, as described _{above, Si 3 N 4, Si x} O y N z (4x = 2y + 3
The insulating layer may be made of other insulating materials such as z), CeO ₂ , ZnS, ZnO, Al ₂ O ₃ and the like.

In the first to thirty first embodiments, the semiconductor substrate may be formed by forming an epitaxial semiconductor layer on an insulator substrate or using a so-called SOI substrate having an insulating layer formed in a semiconductor substrate. The same effects as the above embodiments can be exerted.

Also, in some of the above embodiments, the SiO 2 layer may be formed on the side surface of the layer containing the fine particles.
_{Although two} sidewalls are provided, it is not always necessary to provide SiO ₂ sidewalls. That is, even in a structure in which fine particles are present on both or one of the source and drain regions, it is possible to prevent the occurrence of a leak current or the like by other means.

[0485]

According to the present invention, in a semiconductor device,
By providing a charge holding region configured by dispersing fine particles in an insulator or the like, there is no need to control the thickness of the tunnel oxide film and the particle size of the fine particles unlike a conventional semiconductor device, and Since spontaneous emission of accumulated electrons can be effectively suppressed, a novel semiconductor element which is easy to manufacture and has high reliability, and a method for manufacturing the same can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a band diagram showing an energy band structure of a SiO ₂ film, silicon fine particles, a tunnel oxide film, and a p-type silicon substrate in a conventional semiconductor device.

FIG. 3 is a partial band diagram showing an energy band state when performing electron injection and electron holding in a conventional semiconductor device.

FIG. 4 is a band diagram of the semiconductor device according to the first embodiment.

FIG. 5 is a partial band diagram illustrating an energy band state when performing electron injection and electron holding in the semiconductor element of the first embodiment.

FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second embodiment.

FIG. 7 is a cross-sectional view of a semiconductor device according to a third embodiment.

FIG. 8 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment.

FIG. 9 is a sectional view of a semiconductor device according to a fifth embodiment.

FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a sixth embodiment.

FIG. 11 is a sectional view of a semiconductor device according to a seventh embodiment.

FIG. 12 is a sectional view showing a semiconductor device according to an eighth embodiment.

FIG. 13 is a sectional view illustrating a manufacturing step of the semiconductor element according to the first embodiment;

FIG. 14 is a band diagram of a semiconductor device according to a seventh embodiment.

FIG. 15 is a cross-sectional view of a semiconductor device having a plurality of SiGe fine particles and including a plurality of fine particle groups arranged in a charge holding region in order from below the substrate.

FIG. 16 is a sectional view of a semiconductor device according to a ninth embodiment.

FIG. 17 is a band diagram of the semiconductor device according to the ninth embodiment.

FIGS. 18 (a), (b), and (c) are partial band diagrams respectively showing energy band states when performing electron injection and electron holding in the semiconductor device of the ninth embodiment.

FIG. 19 is a sectional view showing a semiconductor device according to a tenth embodiment.

FIG. 20 is a sectional view of a semiconductor device according to an eleventh embodiment.

FIG. 21 is a sectional view showing a semiconductor device according to a twelfth embodiment.

FIG. 22 is a sectional view of a semiconductor device according to a thirteenth embodiment.

FIG. 23 is a sectional view showing a semiconductor device according to a fourteenth embodiment.

FIG. 24 is a sectional view of a semiconductor device according to a fifteenth embodiment.

FIG. 25 is a sectional view of a semiconductor device according to a sixteenth embodiment of the present invention.

FIGS. 26A to 26C are band diagrams showing schematic diagrams of a band structure near a conduction band when electrons are used as injected charges.

FIGS. 27A to 27C are band diagrams for explaining a more preferable relationship between a voltage level between a semiconductor substrate and a second fine particle and a charge transfer characteristic when electrons are used as charges; It is.

FIG. 28 is a diagram for explaining the effect of the particle size of the first fine particles and the particle size ratio of the first and second fine particles on the charge retention characteristics.

FIG. 29 is a sectional view of a semiconductor memory device according to a seventeenth embodiment;

FIG. 30 is a sectional view of a semiconductor device in an eighteenth embodiment.

FIG. 31 is a sectional view of a semiconductor memory device formed using the semiconductor device of the eighteenth embodiment.

FIG. 32 is a sectional view of a semiconductor device according to a nineteenth embodiment;

FIG. 33 is a sectional view of a semiconductor memory device formed by using the semiconductor device of the nineteenth embodiment.

FIG. 34 is a cross-sectional view of a semiconductor device according to a twentieth embodiment.

FIG. 35 is a sectional view of a semiconductor memory device formed using the semiconductor device of the twentieth embodiment.

FIG. 36 is a sectional view of a semiconductor device in a twenty-first embodiment.

FIG. 37 is a sectional view of a semiconductor memory device formed using the semiconductor device of the twenty-first embodiment.

FIG. 38 is a sectional view of a semiconductor device according to a twenty-second embodiment.

FIG. 39 is a cross-sectional view of a semiconductor memory device formed using the semiconductor device of the twenty-second embodiment.

FIG. 40 is a sectional view of a semiconductor element in a twenty-third embodiment;

FIG. 41 is a sectional view of a semiconductor memory device obtained by using the semiconductor device according to the twenty-third embodiment.

FIG. 42 is a sectional view of a semiconductor device according to a twenty-fourth embodiment;

43 (a) and (b) are band diagrams schematically showing a band structure near a conduction band edge during charge transfer by electrons.

FIG. 44 is a sectional view of a semiconductor memory device in a twenty-fifth embodiment;

FIG. 45 is a sectional view of a semiconductor element in a twenty-sixth embodiment.

FIG. 46 is a sectional view of a semiconductor memory device formed using the semiconductor device of the twenty-sixth embodiment.

FIG. 47 is a sectional view of a semiconductor element in a twenty-seventh embodiment.

FIG. 48 is a sectional view of a semiconductor memory device formed using the semiconductor device of the twenty-seventh embodiment;

FIG. 49 is a sectional view of a semiconductor element in a twenty-eighth embodiment;

FIG. 50 is a sectional view of a semiconductor memory device formed using the semiconductor device of the twenty-eighth embodiment;

FIG. 51 is a sectional view of a semiconductor element in a twenty-ninth embodiment;

FIG. 52 is a cross-sectional view showing a conventional semiconductor device using a plurality of silicon fine particles described in a conventional document.

FIGS. 53A to 53C are diagrams schematically showing a band structure near a conduction band edge when electrons are used as injected charges.

FIG. 54 is a sectional view of a semiconductor memory device according to a thirtieth embodiment;

FIG. 55 is a sectional view of a semiconductor device in a thirty-first embodiment;

FIG. 56 is a sectional view of a semiconductor memory device formed using the semiconductor device of the thirty-first embodiment.

FIG. 57 is a cross-sectional view showing a conventional semiconductor memory element functioning as a memory using a plurality of silicon fine particles.

[Explanation of symbols]

1011 p-type silicon substrate 1012 charge holding region 1012a particle dispersion region 1013 silicon microparticles 1014 SiO ₂ 1015 SiO ₂ film 1016 n-type polycrystalline silicon electrode 1017 bombarded by flicked atoms, molecules

 ──────────────────────────────────────────────────続 き Continued on front page (31) Priority claim number Japanese Patent Application 2000-25930 (P2000-25930) (32) Priority date February 3, 2000 (2000.2.3) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 2000-48820 (P2000-48820) (32) Priority date February 25, 2000 (2000.2.25) (33) Priority claim country Japan (JP) (72) Inventor Kiyoyuki Morita 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 4M104 AA01 AA05 BB01 BB40 CC05 DD82 EE03 EE12 EE14 EE16 GG16 5F001 AA13 AA15 AA19 AA72 AC01 AD12 AD70 AE02 AE08 AF06 AG01 AG22 AG30 5F083 EP17 EP30 EP42 GA27 HA02 HA06 JA01 JA02 BA05 BA21 BA01 PR05 BF02 BH01 BH04 BH16

Claims (44)

[Claims] 1. A substrate having a conductor layer, a barrier layer provided on the conductor layer and functioning as a barrier to movement of electric charges, and a barrier layer dispersedly arranged in the barrier layer, And a charge holding region formed of a plurality of particles having different distances from each other, wherein the capacitance of the plurality of particles increases as the distance from the conductor layer decreases. 2. The semiconductor device according to claim 1, wherein the particles are dispersed at a higher dispersion density as the distance from the conductor layer decreases. 3. The semiconductor device according to claim 1, wherein the average particle size of the particles increases as the distance from the conductor layer decreases. 4. The semiconductor device according to claim 1, wherein the particles are quantized. 5. The semiconductor device according to claim 1, wherein the plurality of particles are grouped into a plurality of particle groups including a plurality of particles having a common distance from the conductor layer. A semiconductor element characterized by the following. 6. The semiconductor device according to claim 1, wherein: an insulator layer provided on the barrier layer; and a gate electrode provided on the insulator layer. A source / drain region formed by introducing impurities into regions on both sides of the gate electrode on the substrate, the semiconductor device functioning as a MIS transistor. 7. A substrate having a conductor layer, a barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, and a barrier layer dispersedly arranged in the barrier layer, And a charge holding region composed of a plurality of particles different in distance from each other, wherein the barrier height between the particles in the charge holding region is smaller as the distance from the conductor layer is smaller. Semiconductor element. 8. The semiconductor device according to claim 7, wherein the particle body has a smaller electron affinity as the distance from the conductor layer is smaller, or the particle body has a larger electron affinity and the sum of the forbidden band width. A semiconductor element, which has any of the following. 9. The semiconductor device according to claim 7, wherein the barrier layer has a larger electron affinity as the distance from the conductor layer is smaller, or the sum of the smaller electron affinity and the forbidden band width. And a semiconductor device comprising: 10. The semiconductor device according to claim 7, wherein the particles are quantized. 11. The semiconductor element according to claim 7, wherein the plurality of particles are a plurality of particles having a common distance from the conductor layer. A semiconductor element characterized by being divided into groups. 12. The semiconductor device according to claim 7, wherein: an insulator layer provided on the barrier layer; and a gate electrode formed on the insulator layer. A source / drain region formed by introducing impurities into regions on both sides of the gate electrode on the substrate, the semiconductor device functioning as a MIS transistor. 13. A substrate having a conductor layer, a first tunnel barrier film provided on the conductor layer, a quantized semiconductor layer provided on the first tunnel barrier film, and A second tunnel barrier film provided on the first tunnel barrier film and the semiconductor layer; a semiconductor particle which is provided on the second tunnel barrier film so as not to contact with each other and is quantized; A semiconductor device comprising: a second tunnel barrier film; and an insulating film provided on the semiconductor particles. 14. The semiconductor device according to claim 13, wherein a discrete energy width of the semiconductor layer is smaller than a discrete energy width of the semiconductor particles. 15. The semiconductor device according to claim 13, wherein the semiconductor layer is a particle group including a group of particles that are in contact with each other. 16. The semiconductor device according to claim 13, wherein a gate electrode provided on the insulating film and a region on both sides of the gate electrode on the substrate. A semiconductor element further comprising a source / drain region provided, and functioning as a MIS transistor. 17. A substrate having a conductor layer, a first barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, and a first barrier layer provided on the first barrier layer; A quantized first particle body, a second barrier layer provided on the first particle body and functioning as a barrier against movement of electric charge, and a second barrier layer provided on the second barrier layer A second particle body, wherein the particle diameter of the second particle body is larger than the particle diameter of the first particle body. 18. The semiconductor device according to claim 17, wherein a particle size ratio between the second particle and the first particle is:
A semiconductor element characterized by being 1.8 or more and 300 or less. 19. The semiconductor device according to claim 17, wherein the first particles have a particle size of 0.1 nm or more and 5 nm or less. 20. The semiconductor device according to claim 17, wherein the particle size of the second particles is 1 nm or more and 30 nm or less. 21. The semiconductor device according to claim 17, wherein the insulator layer is provided on the second particle, and the insulator layer is provided on the insulator layer. A semiconductor element further comprising a gate electrode, and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode, and functioning as a MIS transistor. 22. A substrate having a conductor layer, a first barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, and a first barrier layer provided on the first barrier layer A first particle body, a second barrier layer provided on the first particle body and functioning as a barrier against movement of electric charges, and a second barrier layer provided on the second barrier layer. A semiconductor device comprising: a particle; wherein a potential of the second particle for a charge to be held and released is lower than a potential of the first particle. 23. The semiconductor device according to claim 22, wherein the charge to be retained and released is an electron, and the electron affinity of the second particle is larger than the electron affinity of the first particle. A semiconductor element characterized by the above-mentioned. 24. The semiconductor device according to claim 23, wherein the conductor layer is a semiconductor layer, and wherein the second particles have an electron affinity greater than that of the semiconductor layer. . 25. The semiconductor device according to claim 22, wherein the charge to be held / released is a hole, and the sum of the electron affinity and the forbidden band width of the second particle is equal to the first bandgap. A semiconductor device characterized by being smaller than the sum of the electron affinity of the particles and the forbidden band width. 26. The semiconductor device according to claim 25, wherein the conductor layer is a semiconductor layer, and the sum of the electron affinity and the forbidden band width of the second particles is equal to the electron affinity of the semiconductor substrate. A semiconductor element characterized by being smaller than the sum of the band width. 27. The semiconductor device according to claim 22, wherein the insulating layer is provided on the second particle, and the insulating layer is provided on the insulating layer. A semiconductor element further comprising a gate electrode, and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode, and functioning as a MIS transistor. 28. A substrate having a conductor layer, a first SiO ₂ layer provided on the conductor layer, and a SiO _x N _y layer provided on the first SiO ₂ layer (0 ≦ 0) x <2,0 <y ≦ 4/3) layer, a second SiO ₂ layer provided on the SiO _x N _y layer, and a particle provided on the second SiO ₂ layer A semiconductor element comprising: 29. The semiconductor device according to claim 28, wherein: an insulator layer provided on the particles; a gate electrode provided on the insulator layer; and the gate electrode in the conductor layer And a source / drain region provided in regions located on both sides of the semiconductor device, and functioning as a MIS transistor. 30. A substrate having a conductor layer, a first insulator layer provided on the conductor layer, a first particle body provided on the first insulator layer, A first barrier layer provided on the first particle body and functioning as a barrier against the movement of electric charges; a second particle body provided on the first barrier layer; A second barrier layer provided on the particle body of the above, and functioning as a barrier against the movement of electric charges; and a third particle body provided on the second barrier layer, A semiconductor device, wherein the particle size of the particle and the third particle is larger than the particle size of the second particle. 31. The semiconductor device according to claim 30, wherein a particle diameter ratio between the first and third particles and the second particles is 1.8 or more and 300 or less, respectively. Characteristic semiconductor element. 32. The semiconductor device according to claim 30, wherein a particle diameter of the second particle is 0.1 nm or more and 5 nm or less. 33. The semiconductor device according to claim 30, wherein the particle diameter of the first and third particles is 1 nm or more and 30 n.
m or less. 34. The semiconductor device according to claim 30, wherein the insulating layer is provided on the third particle, and the insulating layer is provided on the insulating layer. A semiconductor element further comprising a gate electrode, and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode, and functioning as a MIS transistor. 35. A substrate having a conductor layer, a first insulator layer provided on the conductor layer, a first particle body provided on the first insulator layer, A first barrier layer provided on the first particle body and functioning as a barrier against the movement of electric charges; a second particle body provided on the first barrier layer; A second barrier layer provided on the particle body of the above, and functioning as a barrier against the movement of electric charges; and a third particle body provided on the second barrier layer, A semiconductor element, wherein the potential of the particles and the potential of the third particles for holding and releasing is lower than the potential of the second particles. 36. The semiconductor device according to claim 35, wherein the charge to be retained and released is an electron, and the electron affinity of the first and third particles is the electron affinity of the second particle. A semiconductor element characterized by being larger than each other. 37. The semiconductor device according to claim 35, wherein the charge to be retained and released is a hole,
A semiconductor device, wherein the sum of the electron affinity and the forbidden band width of the third particle is smaller than the sum of the electron affinity and the forbidden band width of the second particle. 38. The semiconductor element according to claim 35, wherein the insulating layer is provided on the third particle body, and the semiconductor layer is provided on the insulating layer. A semiconductor element further comprising a gate electrode, and source / drain regions provided in regions of the conductor layer located on both sides of the gate electrode, and functioning as a MIS transistor. 39. A substrate having a conductor layer, an insulator layer provided on the conductor layer, a first particle body provided on the first insulator layer, A first SiO ₂ layer provided on the particle body, and a SiO _x N _y layer (0 ≦ x <2, 0 <y ≦ 4/3) layer provided on the first SiO ₂ layer And a second SiO ₂ layer provided on the SiO _x N _y layer, and a second particle body provided on the second SiO ₂ layer. Semiconductor element. 40. The semiconductor device according to claim 39, wherein another insulator layer provided on said second particle body, and a gate electrode provided on said another insulator layer. And a source / drain region provided in regions of the conductor layer located on both sides of the gate electrode, and function as a MIS transistor. 41. A substrate having a conductor layer, a barrier layer provided on the conductor layer and functioning as a barrier against movement of electric charges, a charge holding carrier provided on the barrier layer, and the barrier layer And a quantized particle body embedded in at least a part of the semiconductor element. 42. The semiconductor device according to claim 41, wherein an insulator layer provided on the particle body, a gate electrode provided on the insulator layer, and the gate electrode in the conductor layer And a source / drain region formed by introducing impurities into regions located on both sides of the semiconductor device, and functioning as a memory cell of the nonvolatile memory. 43. A substrate having a conductive layer, a first SiO ₂ layer provided on the conductive layer, and a SiO _x N _y layer provided on the first SiO ₂ layer (0 ≦ x <2, 0 <y ≦ 4/3) layer, a second SiO ₂ layer provided on the SiO _x N _y layer, and a charge retention provided on the second SiO ₂ layer A semiconductor device comprising a carrier. 44. The semiconductor device according to claim 43, wherein: an insulator layer provided on the charge carrier; a gate electrode provided on the insulator layer; and the gate in the conductor layer. A semiconductor element further comprising source / drain regions formed by introducing impurities into regions located on both sides of an electrode, and functioning as a memory cell of a nonvolatile memory.