KR20070022682A - Nonvolatile semiconductor storage element having high charge holding characteristics and method for fabricating the same - Google Patents

Abstract

Conventional floating gate type nonvolatile semiconductor memory devices have low charge retention characteristics, and as a countermeasure for replenishing them, a method of sufficiently thickening the thickness of the tunnel insulating film and the gate oxide film has been taken. As a result, however, there has been a problem that it is difficult to realize such an increase in the operating speed or a higher density of the storage capacity.

In order to solve the above problems, in the nonvolatile semiconductor memory device, a material having a high work function or a high electron affinity or a material having a small work function difference between a semiconductor substrate or a control gate is used as a floating gate for holding charge. As the mother insulator, an amorphous material having a small electron affinity is used. In addition, the supply ratio of the ultrafine particle material and the parent insulator material at the time of forming the charge holding layer film, for example, the material mixing ratio of the aspect of the target in the sputtering method is adjusted to optimize the outer interval distance of the ultrafine particles. As a result, the charge retention characteristics of the floating gate type nonvolatile semiconductor memory element at room temperature and high temperature can be improved, and the rewrite characteristics and multi-value memory operation can be stabilized. The problem can be solved.

Charge retention characteristics, semiconductors, memory devices

Description

Nonvolatile semiconductor memory device having high charge retention characteristics and manufacturing method {NONVOLATILE SEMICONDUCTOR STORAGE ELEMENT HAVING HIGH CHARGE HOLDING CHARACTERISTICS AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method, and more particularly, to a structure in which ultra-fine particles composed of at least one single element material or compound are dispersed at high density in a mother-like insulator. And a nonvolatile semiconductor memory device having a charge holding layer having excellent retention characteristics in optimizing the work function or electron affinity between the ultrafine particles and the parent insulator, or optimizing the outer gap distance of adjacent ultrafine particles; The present invention relates to a method for manufacturing the device, which is cheap and has good reproducibility.

Conventionally, as a recording medium capable of storing and rewriting a large amount of data, there is a storage element using a semiconductor such as DRAM or SRAM, or a rotating disk type recording medium such as a hard disk, magneto-optical disk, or optical disk. It has been developed and used. Among them, DRAMs having characteristics such as fast data writing and reading speeds and easy high integration have been widely used as temporary storage elements such as PCs. However, since the memory has the disadvantage of volatility of fatal data (points held by extinguishing power supply from the outside), power supply from the outside is required for recording and thus power consumption. Is increased. This disadvantage is particularly disadvantageous when using a portable information terminal apparatus that relies on a power source for a battery or the like.

On the other hand, in a hard disk system or the like, the data is not volatile, but the writing and reading speed is slow and the power consumption is relatively large. In addition, there is a drawback in that the structure of the device is weak to mechanical vibration and impact. These drawbacks are also very unsuitable for use in portable terminal devices.

With the recent expansion of the portable electronic information terminal device market, it is nonvolatile as a storage medium used in this portable terminal device, and has a high memory density, a high speed recording, a high speed reading, or a mechanical vibration or shock when carrying. The emergence of a storage medium that is convenient to use, such as stable operation, low power consumption, and which can be manufactured easily and inexpensively using conventional semiconductor manufacturing techniques is expected.

Nonvolatile semiconductor memory devices such as flash memory, ferroelectric memory, magnetic random access memory (MRAM), phase change memory, and the like are expected as storage media that satisfy the above requirements, and these are currently in a development stage to some practical stages.

Each of these nonvolatile memories has advantages and disadvantages. For example, MRAM has many advantages, such as a fast writing speed and a large number of rewritable times, and is said to be one of the most promising candidates for DRAM replacement memory. However, the basic structure of the memory element is a complicated structure consisting of two transistors and a magnetoresistive element, the demand for variation in the thickness of the tunnel insulation layer of the magnetoresistive element is difficult, and the finer the magnetoresistive element, the more the reversal of the magnetic field. The problem is that the required external magnetic field is increased and a large rewrite current is required.

On the other hand, the memory cell of the flash memory is basically composed of one transistor, and since the structure is simple, the cell size can be reduced, and the highly integrated memory can be manufactured relatively inexpensively using the conventional DRAM process technology. For this reason, flash memory has already formed a large market as a memory for portable information terminal devices at present. In recent years, high speed and high integration of semiconductor devices have been promoted, but researches for high performance, such as miniaturization, high speed, and improvement of charge retention characteristics, have been actively conducted in flash memories.

In the flash memory which is already widely distributed in the market now, of which NOR type flash memory is taken as an example, this means that the read operation of the maintenance data of a designated memory cell is performed at a high speed in a relatively short time of about 100 ns (nanoseconds) or less. Is carried out.

On the other hand, data recording is performed by channel hot electron (CHE) injection from the channel to the floating gate, and data erasing is caused by discharge of charge by Fowler-Nordheim (FN) tunnel current from the floating gate to the channel forming region or source region. Is done by. The CHE implantation takes time for the rewrite operation because the charge transfer rate is fast but the charge injection efficiency (the ratio of the injection current to the supply current) is low, and the charge release by the FN tunnel current is slow.

Specifically, a relatively long time is required for recording of 1 ms (microseconds) and erasing for several hundred ms (milliseconds) to several s (seconds). For this reason, the use of the flash memory is relatively easy, but the use thereof is limited, and replacement of a high speed memory such as DRAM is difficult.

In order to overcome this drawback and to shorten the rewriting time, a method of thinning the physical thickness of the tunnel insulating film, which greatly affects the time required for rewriting, for example, can be considered. However, when the oxide film serving as the tunnel insulating film is thinned, a very strong electric field inversely proportional to the film thickness is applied to the tunnel insulating film during charging of the floating gate, so that the stress caused by the passage of the charge through the oxide film many times is caused by the rewriting operation. The oxide film is likely to cause dielectric breakdown.

If dielectric breakdown occurs at any one point of the tunnel insulating film, most of the charge held in the floating gate is leaked, and then the memory cell loses the data holding capability. Therefore, in the present situation, the tunnel insulating film must be thickened in order to maintain the reliability of charge retention, and it is difficult to shorten the rewrite time. Moreover, since there is a law that the oxide film thickness and the dimension of the whole element are similarly reduced, it hinders the miniaturization of the whole element.

In addition, by increasing the density of the memory elements, the distance between the floating gates of adjacent elements becomes narrower, and the capacitive coupling between adjacent floating gates becomes stronger. Accordingly, it has been pointed out that malfunctions are likely to occur during each operation of reading and writing. The effect of this capacitive coupling is especially noticeable for NAND type flash memories.

From this, it is said that the miniaturization and densification of the bulk floating gate type flash memory device of development are rapidly difficult in the future, and the miniaturization will reach a limit as early as 2007.

As a means of preventing the degradation of charge holding ability due to dielectric breakdown while maintaining high speed operation and reducing the influence of parasitic capacitance between floating gates of adjacent devices, there is a method of spatially distributing charge and holding it. MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory in volatile semiconductor memory, or SONOS (In the case of MONOS memory, the material of gate electrode is substituted from metal to semiconductor; specifically, for example, polycrystalline Si Is used).

For example, Figure 4 described as a tunnel insulating film (2) and, above the charge holding layer (3) in place of the floating gate shown in the SiN _x film and is in the laminated structure, the interface state (3a3) that exist in the interface, and It is a memory for keeping charge at a trap level 3a4 distributed discretely in a SiN _x film. 4, 1 is a p-type semiconductor substrate, 4 is a gate insulating film, 5 is a control gate electrode, 6 is a source region, and 7 is a drain region.

Since the interface levels 3a3 and trap levels 3a4 holding charges are distributed discretely in space, even if dielectric breakdown occurs in any one of the above-described tunnel insulating films 2, the charge leakage due to them is local. Only occurs, and the charge retention capability of the memory cell does not change significantly before or after occurrence of dielectric breakdown.

For this reason, the MONOS memory is advantageous in terms of miniaturization of the memory cell, which is superior in terms of the number of rewrites to the developed bulk floating gate type flash memory, and that the physical thickness of the tunnel insulating film can be relatively thin. However, the charge trapped once due to the fact that the depth of the trap level of the SiN _x film (the energy difference at the bottom of the conduction band for electrons and the energy difference at the top of the valence band for holes) is not necessarily sufficient. Is easy to escape, and the absolute charge holding ability (that is, the charge holding ability of a device in a normal state in which no dielectric breakdown occurs at all) is low.

On the other hand, by maintaining charge discretely in the same way as MONOS memory, it is possible to cope with the problem of dielectric breakdown of the oxide film and the capacitive coupling problem between adjacent floating gates, and to increase the absolute charge retention capability of MONOS memory. As a result, a form in which a large number of the Si ultrafine particles are dispersed in the gate insulating film can be considered. 5 shows an example of a semiconductor memory device having Si ultrafine particles. 5, the same code | symbol as FIG. 4 as another code | symbol in an element other than Si ultrafine particle 3a1 shows the same element as FIG. This type of memory is described, for example, in Japanese Patent Application Laid-Open No. 11-186421. In this publication, as shown in Fig. 5, a large number of Si ultrafine particles formed on the tunnel insulating film 2 by the CVD method ( The structure which forms the floating gate which consists of 3a1), and covers the circumference | surroundings with the gate insulating film 4 is described.

If the floating gate is an Si ultrafine particle which is an intrinsic semiconductor (contains no impurities), the injected electrons are trapped at the conduction band level of Si, and the height of the potential barrier seen from the electron is the oxide film surrounding the ultrafine particle, for example, The difference between the lower end and the lower end of the conduction band of Si, that is, the difference between the electron affinity between Si and the oxide film. Since this potential barrier is usually deeper than the barrier in which the traps in the SiN _x film of the MONOS memory are formed, trapped electrons are less likely to escape to the semiconductor substrate or control gate electrode, i.e., the charge retention capability is higher than that of the MONOS memory.

However, from the viewpoint of the potential barrier height, Si is not the best material as the material constituting the ultrafine particles. FIG.1 (a) is a schematic diagram of the energy level in the state in which the ultrafine particle of Si hold | maintained the electron. Where 1 is a p-type semiconductor substrate, 2 is a tunnel insulating film, 3a1 is a Si ultrafine particle, 4 is a gate insulating film, 5 is a control gate, 9 is an electron, 10a and 10b are the Si ultrafine particles and the lower level of the conduction band of the tunnel insulating film, respectively, 12 is It is a potential barrier. The injected electrons 9 are trapped in the conduction band bottom level 10a of the Si ultrafine particles. The potential barrier 12 seen from the electron 9 in this case is the conduction band bottom level 10b of the tunnel insulation film and the conduction band bottom level of the Si ultrafine particles at the interface between the Si ultrafine particles 3a1 and the tunnel insulating film 2 ( The difference of 10a), that is, the difference between the electron affinity of the oxide film and the electron affinity of the ultrafine Si particles. On the other hand, the energy level schematic diagram in the case where an ultrafine particle is a metal is shown in FIG.1 (b). 11a is the Fermi level of the ultrafine metal particles, and the other symbols indicate the same elements as in FIG. 1 (a). In this case, the electrons are trapped in the Fermi level 11a of the ultrafine metal particles, and the height of the potential barrier 12 in this case is the conduction band lower level 10b of the tunnel insulating film and the metal at the interface between the ultrafine metal particles and the tunnel insulating film. The difference between the Fermi level 11a of the ultrafine particles, that is, the difference between the work function of the metal and the electron affinity of the oxide film. Since the work function of most metals is higher than the electron affinity of Si, the potential barrier formed by Si in the oxide film is lower than that of metal. FIG. 6 is a diagram showing a result of theoretically calculating the probability that the electrons held in the floating gate of each material tunneled through the SiO ₂ film, which is a potential barrier, in the case of using Si, W, and Co as floating gates. In addition, the electron affinity of Si was 4.1 eV, the work functions of W and Co were calculated as 4.6 eV, 5.0 eV, and SiO ₂ as 1.0 eV, respectively. Thus, the heights of the potential barriers for the electrons held in the floating gate, in which the floating gate is Si, W, and Co, are 3.1 eV, 3.6 eV, and 4.0 eV, respectively. The horizontal axis of the graph represents the thickness of the insulating layer is SiO ₂ film tunnel that electrons are transmitted. According to this result, the tunneling probability in the case of using the Si floating gate is about 2 to 5 orders of magnitude higher than in the case of using the metal floating gate of W or Co. In other words, it can be seen that the leakage current from the Si floating gate becomes 100 to 100,000 times larger than that of the metal floating gate. This result is explained from the difference of the height of the potential barrier in each case of Si, W, and Co, and shows that the charge holding | maintenance capability becomes high by using the metal material which has work function higher than the electron affinity of Si. This effect can be similarly obtained even in a high temperature environment. As described above, for the purpose of obtaining high charge retention characteristics, a method of using a metal other than Si as the material of the floating gate is disclosed in, for example, Japanese Patent Laid-Open No. H16-055969.

However, in the nonvolatile semiconductor memory device disclosed in the above patent document, the density of the floating gate becomes too high and the adjacent ultrafine particles may approach too much. This state may not always be the best state in the case of performing a multi-value memory operation, etc., and there exists room for improvement, such as optimizing the space | interval of the ultrafine particle which acts as a floating gate.

Disclosure of the Invention

The problem to be solved by the present invention is that the above problem to be solved in the conventional flash memory, that is, bulk floating gate type flash memory, MONOS memory, SONOS memory, or Si ultra-fine particle floating gate type flash memory, that is, low charge retention characteristics will be. This problem is hindered in solving other problems on the various characteristics of the nonvolatile memory device, for example, difficulty in speeding up the data write operation or erase operation, and difficulty in miniaturization and high density of the device. It is becoming. Therefore, according to the present invention, these various problems can be solved simultaneously by improving the charge retention characteristics in the environment at room temperature and high temperature.

In other words, an object of the present invention is to provide a floating gate type nonvolatile semiconductor memory device having high charge retention characteristics in an environment at room temperature and high temperature, and furthermore, a nonvolatile semiconductor memory device capable of miniaturization, high density, and high speed operation of the device. And a method of manufacturing the nonvolatile semiconductor memory device with good reproducibility.

In view of the above, this invention has the following summary.

1. a source region and a drain region formed on a surface of a semiconductor substrate, a channel formation region formed so as to connect the source region and the drain region or between the source region and the drain region, and a tunnel formed in contact with the channel formation region. A nonvolatile semiconductor memory device comprising an insulating film, a charge holding layer formed adjacent to the tunnel insulating film, a gate insulating film formed adjacent to the charge holding layer, and a control gate formed adjacent to the gate insulating film, wherein the charge holding layer is provided. The ultrafine particles of a good conductor consisting of at least one single element material or compound having a particle diameter of 5 nm or less, functioning as a floating gate, are contained per nonvolatile semiconductor memory device or 10 ⁺¹² per square centimeter of the charge holding layer. To It is composed of a mother-like insulator which is dispersed in 10 ⁺¹⁴ density independently and contains a plurality, wherein the mother-like insulator is amorphous, its electron affinity is 1.0 eV or less, and the work function of ultrafine particles of the good conductor is 4.2 eV or more. Volatile semiconductor memory device.

By this configuration, the dispersion density and particle diameter of the ultrafine particles are optimized, the yield of the device is improved, and the energy barrier height against the charge trapped in the ultrafine particles by the selection of the material constituting the ultrafine particles and the parent insulator is optimized. Can be achieved, and the ability to retain charge in an environment at room temperature and high temperature can be improved compared to a conventional device. Alternatively, the data writing and erasing operation can be performed by optimizing the energy barrier so that the physical thickness of the tunnel insulating film and the gate insulating film can be made thin while maintaining the charge retention characteristics in the environment at room temperature and high temperature at the same level as the conventional device. It is possible to obtain a nonvolatile semiconductor memory device which achieves high speed, finer device and higher integration.

2. The nonvolatile semiconductor memory device according to 1, wherein a difference between the work function of the ultrafine particles and the work function of the semiconductor substrate is 0.5 eV or less.

3. The nonvolatile semiconductor memory device according to 1 or 2, wherein a difference between the work function of the ultrafine particles and the work function of the control gate is 0.5 eV or less.

4. The nonvolatile semiconductor memory device according to 1, 2 or 3, wherein the mutual outer space distances adjacent to the ultrafine particles are 1 to 5 nm.

In addition, the outer shell referred to here refers to the surface of the ultrafine particles or, in other words, the interface between the ultrafine particles and the mother insulating layer. The outer gap distance means the shortest distance between the surface of the ultrafine particles and the surface of the ultrafine particles closest to the ultrafine particles.

5. The nonvolatile semiconductor memory device according to any one of 1 to 4, wherein the ultrafine particles have a melting point of 1400 ° C or higher.

6. The nonvolatile semiconductor according to any one of 1 to 5, wherein the absolute value of the difference between the ionization energy level of the atom constituting the ultrafine particles in the semiconductor substrate and the center level of the gold band of the semiconductor substrate is 0.1 eV or more. Memory elements.

7. The ultrafine particles described in any one of 1 to 6 above, wherein the ultrafine particles are a single group or a compound composed of at least one of an element group of W, Mo, Ti, Pt, Pd, Ni, Ta, Cr, Os, Nb, Ru, and Rh. Nonvolatile Semiconductor Memory.

By this structure, when the Si single crystal is used as the semiconductor substrate, it is possible to obtain ultrafine particles satisfying all of the above physical properties 1, 5, and 6, and excellent in charge retention characteristics, and at the time of manufacturing process or use. Even in a high temperature environment, when the ultrafine particles are not dissolved or diffused, and when the atoms constituting the ultrafine particles are diffused onto the semiconductor substrate, the device can be obtained without becoming a recombination center of the carrier and stable operation characteristics of the device.

8. The nonvolatile semiconductor memory according to any one of 1 to 7 above, wherein the mother insulator constituting the charge holding layer is formed of at least one compound selected from the group consisting of oxides, carbides, nitrides, borides, silicides, and fluorides. device.

9. The nonvolatile semiconductor memory device according to any one of 1 to 8, wherein the ultrafine particles constituting the charge holding layer are dispersed two-dimensionally or three-dimensionally in the mother insulator.

10. A method for manufacturing a nonvolatile semiconductor memory device having a charge holding layer in which ultra-fine particles are dispersed two-dimensionally or three-dimensionally in a mother-shaped insulator according to 9, wherein the charge holding layer constitutes the ultra-fine particles and the mother-shaped insulator. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that each material is formed by self-organization by physical vapor deposition.

11. The method for producing a nonvolatile semiconductor memory device according to 10, wherein the physical vapor deposition method is a sputtering method.

12. A source region and a drain region formed on the surface of the semiconductor substrate, a channel forming region formed to connect the source region and the drain region or between the source region and the drain region, and a tunnel formed in contact with the channel forming region. A nonvolatile semiconductor memory device comprising an insulating film, a charge holding layer formed adjacent to the tunnel insulating film, a gate insulating film formed adjacent to the charge holding layer, and a control gate formed adjacent to the gate insulating film. The layer contains one or more ultrafine particles of a semiconductor or insulator composed of one or more single element materials or compounds having a particle diameter of 5 nm or less that functions as a floating gate per nonvolatile semiconductor memory element or per square centimeter of the charge holding layer. 10 ^{+12 +14} to 10 minutes a density as an independent subsidiary Formed of a matrix containing a plurality of insulator, and the electron affinity of 1.0eV or less is the parent phase is an amorphous insulator, and a non-volatile semiconductor memory device, characterized in that not less than the electron affinity of the ultrafine particles is 4.2eV.

By this configuration, the dispersion density, particle diameter, etc. of the ultrafine particles are optimized, the yield of the device is improved, and the height of the energy barrier against the charge trapped in the ultrafine particles by the selection of the material constituting the ultrafine particles and the parent insulator. Optimalization can be achieved, and the ability to maintain charge in an environment at room temperature and high temperature can be improved compared to a conventional device. Alternatively, by appropriately optimizing the energy barrier, it is possible to reduce the physical thicknesses of the tunnel insulating film and the gate insulating film while maintaining the charge retention characteristics in the environment at room temperature and high temperature at the same level as that of a conventional device. A nonvolatile semiconductor memory device capable of speeding up operation and miniaturization and high integration of the device can be obtained. In addition, the selection range of the ultrafine particle material can be widened not only to a semiconductor but also to a range including a semiconductor and an insulator.

13. The nonvolatile semiconductor memory device according to 12, wherein a difference between the work function of the ultrafine particles and the work function of the semiconductor substrate is 0.5 eV or less.

With this configuration, in addition to the effect obtained when the invention according to 2 or 13 described above is carried out, that is, the yield of the device and the effect of improving the charge retention characteristics in the environment at room temperature and high temperature, the work function of the ultrafine particles and the semiconductor substrate By further limiting the difference to 0.5 eV or less, it is possible to prevent spontaneous inflow of charges from the semiconductor substrate into the ultrafine particles before the write operation, thereby suppressing the lowering of the effective energy barrier.

14. The nonvolatile semiconductor memory device according to 12 or 13, wherein a difference between the work function of the ultrafine particles and the work function of the control gate is 0.5 eV or less.

With this configuration, in addition to the effect obtained when the invention according to 3 or 14 described above is carried out, that is, the yield of the device and the effect of improving the charge retention characteristics under the environment at room temperature and high temperature, the work function of the ultrafine particles and the control gate By further limiting the difference to 0.5 eV or less, it is possible to prevent spontaneous inflow of charges into the ultrafine particles in the control gate before the write operation, thereby suppressing the lowering of the effective energy barrier.

15. The nonvolatile semiconductor memory device according to 12, 13 or 14, wherein the mutual outer space distances adjacent to the ultrafine particles are 1 to 5 nm.

With this arrangement, when the inventions related to 4 or 15 are implemented, the distance between the ultrafine particles can be optimized, so that the insulation between adjacent ultrafine particles can be improved, and the movement of electric charges between adjacent ultrafine particles can be suppressed. As a result, in addition to the above-mentioned effects, namely, the ability to maintain charge in an environment at room temperature and high temperature, high speed operation, and high integration, a nonvolatile semiconductor memory device capable of realizing reliability of data rewriting and multi-value operation can be obtained. have.

16. The nonvolatile semiconductor memory device according to any one of 12 to 15, wherein the ultrafine particles have a melting point of 1400 ° C or higher.

By this structure, when the invention according to the above 5 or 16 is carried out, even in a high-temperature environment during the manufacturing process or use of the device, dissolution of the ultrafine particles is prevented and diffusion dissipation of atoms constituting the ultrafine particles is suppressed. can do. As a result, a nonvolatile semiconductor memory device capable of improving the yield of the device, stabilizing operation under room temperature and high temperature environment, and the like can be obtained.

17. The nonvolatile semiconductor memory according to any one of 12 to 16, wherein an absolute value of the difference between the ionization energy of the atoms constituting the ultrafine particles in the semiconductor substrate and the energy of the center level of the gold band of the semiconductor substrate is 0.1 eV or more. device.

With this configuration, in the case of carrying out the invention according to 6 or 17, even when atoms constituting the ultrafine particles diffuse into the semiconductor substrate to form an impurity level as the recombination center of the carrier, the carrier probability of trapping is low, so The influence can be suppressed. As a result, a nonvolatile semiconductor memory device capable of improving the yield of the device and stabilizing operation under room temperature and high temperature environment can be obtained.

18. The nonvolatile semiconductor memory device according to any one of 12 to 17, wherein the parent insulator constituting the charge holding layer is made of at least one compound selected from the group consisting of oxides, carbides, nitrides, borides, silicides, and fluorides. .

With this configuration, when the invention according to the above 8 or 18 is carried out, it is possible to select from the group consisting of oxides, carbides, nitrides, borides, silicides and fluorides as the material of the mother insulator, and the energy barrier is high and the insulating property is high. It is possible to realize a nonvolatile semiconductor memory device which is high in terms of high heat resistance and the like.

19. The nonvolatile semiconductor memory device according to any one of 12 to 18, wherein the ultrafine particles constituting the charge holding layer are dispersed two-dimensionally or three-dimensionally in the mother insulator.

With this configuration, in the case where 9 or 19 is carried out, when the dispersion of the ultrafine particles is two-dimensional, since the thickness of the charge holding layer becomes thin, the capacitive coupling between the semiconductor substrate and the control gate electrode is strengthened, resulting in a MOSFET. The short channel effect in (metal-oxide-semiconductor field effect transistor) can be suppressed. In addition, when the dispersion is three-dimensional, multi-valued operation by controlling the distance between the center of the distribution of the sustained charge and the semiconductor substrate becomes possible, or the charge can be trapped by the quantization effect of the ultrafine particles. A nonvolatile semiconductor memory device having these characteristics can be realized.

20. The method for manufacturing a nonvolatile semiconductor memory device having a charge holding layer in which ultra-fine particles are dispersed two-dimensionally or three-dimensionally in a mother-shaped insulator according to the above-mentioned 19, wherein the charge holding layer constitutes the ultra-fine particles and the mother-shaped insulator. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that each material is formed by self-organization using physical vapor deposition.

According to this configuration, when the invention relating to the above 10 or 20 is carried out, the physical vapor deposition method has characteristics such as a thermodynamic situation in which the parent insulator and the ultrafine particles tend to self-organize phase separation, and the like. It is suitable for formation of the charge holding layer of the nonvolatile semiconductor memory element to have, and a nonvolatile semiconductor memory element having the above characteristics can be realized.

21. A method for manufacturing a nonvolatile semiconductor memory device according to 20, wherein the physical vapor deposition method is a sputtering method.

With this configuration, in the case of performing the above 11 or 21, the sputtering method is particularly excellent in adhesion with the base substrate among physical vapor deposition methods, and can form a dense film in which the atoms constituting the film are strongly bonded. A nonvolatile semiconductor memory device capable of forming a charge holding layer of the nonvolatile semiconductor memory device having the above characteristics is preferable because it has a wide selection, excellent mass productivity, and low cost manufacturing. It can be realized.

Fig. 1 is a schematic diagram of the energy level explaining the charge retention characteristics of the nonvolatile semiconductor memory device of the present invention, (a) is the case where the ultrafine particles are Si, and (b) is the case where the ultrafine particles are a metal.

Fig. 2 is a cross-sectional schematic diagram showing a nonvolatile semiconductor memory device of the present invention in the first embodiment.

3 is a schematic cross-sectional view showing a nonvolatile semiconductor memory device of the present invention in Example 2. FIG.

4 is a cross-sectional schematic diagram showing an example of a conventional MONOS memory.

5 is a cross-sectional schematic diagram showing an example of a semiconductor memory device containing conventional Si ultrafine particles.

FIG. 6 is a diagram showing a result of theoretically calculating the probability that electrons held in the floating gate of each material tunnel through the Si0 ₂ film, which is a potential barrier, when Si, W, and Co are used as floating gates.

To practice the invention  Best form for

2 is a schematic cross-sectional view of an example of the nonvolatile semiconductor memory device of the present invention. In Fig. 2, 1 is a p-type semiconductor substrate, 2 is a tunnel insulating film, 3 is a charge holding layer, and ultrafine metal particles 3a2 serving as floating gates are contained in a dispersed state in the mother-like insulator 3b. 4 is a gate insulating film, 5 is a control gate. 6 represents a source region and 7 represents a drain region.

The p-type semiconductor substrate 1 may be a semiconductor as a whole, or a semiconductor layer may be formed on an insulator such as an SOI substrate. The tunnel insulating film 2 is a material having a high dielectric constant, for example, SiO, for the purpose of enhancing capacitive coupling between the p-type semiconductor substrate 1 and the silicon oxide film having a relatively good interfacial bonding property or the semiconductor substrate by the control gate voltage. _x N _y (0 ≦ x <2, 0 < _y ≦ 4/3; more preferably x, y satisfies 2x + 3y = 4) or a high dielectric material such as HfO ₂ . Can be.

In the case where heavy metal is used as the floating gate material or the control gate, the heavy metal element passes through the tunnel insulating film and diffuses to the semiconductor substrate, thereby preventing the threshold voltage of the MOSFET from changing. In this reason, preferable that for the purpose of preventing diffusion of a metal element toward the semiconductor substrate using the _{SiN x (0 <x≤4 / 3} ) nitrogen-based compounds such as an insulating film or HfO ₂ or LaO _x, such as non-Si-based oxide Do.

In addition, in order to make data write / erase operations at a high speed, the film thickness of the tunnel insulating film is preferably as thin as possible, preferably 8 nm or less. In addition, it is very preferable to set it as 5 nm or less for speed-up.

The metal ultrafine particles 3a2 constituting the charge holding layer 3 are designed to suppress the influence of the loss of the accumulated charge due to the dielectric breakdown of the tunnel insulating film 2 as much as possible, and also by the presence or absence of the accumulated charge to the ultrafine particles. In order to suppress the variation between the elements in the shift amount of the threshold voltage (ΔV _th , also referred to as a memory window), the ultrafine particles are dispersed in a high density at high density, specifically, one per nonvolatile semiconductor memory element, or 10 ⁺¹² It is preferably present at a density of from 10 ⁺¹⁴ / cm 2. At the same time, in order to increase the insulation of the adjacent ultrafine particles, the outer space of the ultrafine particles is preferably large, and preferably 1 nm or more apart. However, when the interval is too wide, high density dispersion is not obtained, so it is preferable to set 5 nm as the upper limit of the outer interval distance. Moreover, in order to make high-density dispersion of ultrafine particles and insulation between adjacent particles compatible, the size of ultrafine particles is 5 nm or less, More preferably, 3 nm or less is preferable. In addition, the magnitude | size of the ultrafine particle here is an average value, and this average value shall mean the arithmetic mean at the time of removing the ultrafine particle by 10% in the large and small part of particle diameter distribution, respectively.

The material constituting the charge holding layer 3 is basically a material forming the metal ultrafine particles 3a2 in the charge holding layer 3 and a material for obtaining the parent insulator 3b causing phase separation at the time of film formation. It is assumed that the material of the combination is selected.

As the material of the ultra-fine particle dispersed phase, any of metals, semiconductors, and insulators can be selected, but from the viewpoint of obtaining a high charge retention capability, a material having a work function or an electron affinity as large as possible is preferable, and therefore, according to 3a2 of FIG. As shown, it is preferred to use a metal. Theoretically, as shown in FIG. 6, the tunneling probability when exiting the insulator surrounding the electron from the ultrafine particles trapping the electrons depends on the material constituting the ultrafine particles, and the work function or electron affinity of the material is different. It is explained from the fact that the larger the lower the probability of tunneling.

In addition, the difference in the work function of the material used for the floating gate also affects the charge holding ability of the device under a high temperature environment. Here, a high temperature environment means the environment of the temperature range whose upper limit temperature is about 250 degreeC-about 300 degreeC from about 40 degreeC. Under high temperature environments, the potential barrier is effective because the thermal energy of the sustained charge (which is proportional to kT; where k is Boltzmann's constant and T is absolute temperature) is higher than at room temperature. Is lowered. In addition, there is a relatively strong temperature dependency on the energy bandgap of the insulator surrounding the floating gate. In Si0 _{2 or the} like which is most frequently used as an insulator, the band gap tends to be small due to the increase in temperature, and the influence of the gap reduction accompanying the temperature rise cannot be ignored.

Due to the influence of the thermal energy of the holding charge, the gap shrinkage accompanying the temperature rise, and the like, the potential barrier under a high temperature environment is insignificantly lowered compared with that under a room temperature environment, and it is a factor that degrades the charge holding ability at a high temperature. It is becoming. At this time, by using a metal having a large work function for the floating gate, it is possible to sufficiently compensate for the potential barrier effectively lowered under a high temperature environment, and lower the tunneling probability even when Si is used for the floating gate even in a high temperature environment. It can be suppressed.

From this, the use of a high work function material for the floating gate is more effective than the use of a low work function material or a semiconductor in which the potential barrier is substantially lowered with temperature rise, such as Si. Can be made higher. Specifically, a material having a work function of 4.2 eV or more for a metal material may be a material having an electron affinity of 4.2 eV or more for a semiconductor and an insulator material.

In addition, as the material of the ultra-fine particle dispersed phase, the work function of the semiconductor substrate or the control gate electrode is used in view of suppressing the introduction of charge into the ultra-fine particles before the write operation, increasing the effective height of the potential barrier, and obtaining a high charge retention capability. Materials as close as possible are very suitable. Specifically, it is preferable that the absolute value of the difference between the work function of the material of the ultrafine particle dispersed phase and the material of the semiconductor substrate or the absolute value of the difference between the work function of the material of the ultrafine particle dispersed phase and the material of the control gate is preferably 0.5 eV or less. It is more preferable that it is 0.1 eV or less.

This is for the following reason. When materials of different work functions are joined to reach a thermal equilibrium state, electrons move from one material to another so that the Fermi levels of each material coincide with each other. For this reason, for example, when the work function of the ultrafine particles is excessively high, the action of moving electrons from the semiconductor substrate or the control gate to the ultrafine particles acts strongly, and before the operation of injecting electrons into the ultrafine particles, the electrons spontaneously enter the ultrafine particles. Is injected. In this state, if you try to inject electrons to record data, the ultrafine particles are injected with the second or later electrons. For convenience of explanation, hereinafter, electrons spontaneously injected before the above recording operation are referred to as "thermal balance electrons", and electrons injected by the subsequent recording operation are referred to as "injection electrons".

At this time, since the injected electrons are subjected to the coulomb blockade by the thermal equilibrium electrons, it is difficult to be injected into the ultrafine particles by the amount of electrostatic energy of ΔE _c = e ² / (2C). In addition, the injection electron is the ΔE _c Because of its high energy, the potential barrier seen by this implanted electron is equal to this ΔE _c As low as it will. Artificially operated due to the operation of recording and erasing, and having a function as the person in charge of the stored information is mainly equivalent to that of the injected electrons, so that the effective potential barrier is lowered.

In addition, since the size of the ultrafine particles is nanometer order, the energy level that electrons trapped in the ultrafine particles can take is quantized. The energy level below is occupied by the thermal equilibrium electrons, and the injection electrons are ΔE _Q. When enough that capture the high-energy level, electrons are injected to become further from the energy level of the thermal equilibrium e ΔE _Q Requires as high energy as possible, and the height of the potential barrier seen from the implanted electron after capture is the same as in the case of the chromium blockcade, ΔE _Q. As low as it will.

In practice, since these chromium blockcade effects and two quantization effects coexist, the height of the potential barrier seen in the injection electron is simply the sum of these, ΔE _c + ΔE _Q , ignoring the interaction of these two effects. Is lowered. Since the lowering of the effective barrier is caused by pre-injecting the first electrons into the ultrafine particles, it is important to suppress spontaneous injection of thermally balanced electrons. It is desirable to be close.

In the manufacturing process of the nonvolatile semiconductor memory device of the present invention, when the charge holding layer is subjected to a high temperature treatment, in order to suppress aggregation of the ultrafine particles by heating, the melting point of the ultrafine particles is preferably higher, specifically, the melting point It is preferable that it is 1400 degreeC or more.

In addition, when the constituent elements of the ultrafine particles diffuse to reach the semiconductor substrate, an impurity level is formed in the semiconductor substrate depending on the elements. If the substrate is an indirect transition type semiconductor, it becomes a recombination center to reduce the carrier's lifespan and further affect the MOSFET's ON current or threshold voltage. The closer the impurity level is to the center level (gap center) of the gold band of the semiconductor substrate, the higher the probability of recombination. Therefore, an element forming an impurity level close to the gap center is not preferable as an element constituting ultrafine particles. On the other hand, as the impurity level moves away from the gap center, the probability of recombination decreases exponentially, so if the level is some distance away from the gap center, the effect on the operation of the MOSFET becomes smaller even if the impurity level is formed. . Therefore, the element constituting the ultrafine particles is 0.1 eV or more from the gap center of the semiconductor substrate (the upper limit is not particularly limited, but is about 0.56 eV when the semiconductor substrate is Si, for example, and this value depends on the material of the semiconductor substrate). An element which forms an impurity level at a level separated by) is preferable.

The material of the ultrafine particles is preferably selected in consideration of the above viewpoints, work function, melting point, and impurity level. In the case where the semiconductor substrate is Si, as the ultrafine metal particles, W, Mo, Ti, Pt, Pd, Ni, Ta, Cr and the like are preferable, but Os, Re, Nb, Ru, and Rh may be used.

The ultrafine particles of the element semiconductor are preferably at least one of Se and Te. In addition, at least one semiconductor of Se and Te may contain at least one element of P, As, Sb, B, Al, Ga, In and Cu as impurities.

The ultrafine particles of the compound semiconductor or insulator are InAs, InGaAs, InGaNAs, InAlAs, InAsP, InGaAsP, InSb, InGaSb, InAlSb, InGaAsSb, SiC, Cu ₂ O, ZnO, CdO, BaO, PbO, NiO, In ₂ O ₃ , Sb ₂ O ₃ , SnO ₂ , Ag ₂ O, AgO, RuO ₂ , V ₃ Ga, Nb ₃ Sn, Nb ₃ Al, Nb ₃ Ga, Nb ₃ Ge, NbTi, NbMo ₆ S ₈ , ZnS, CdS, HgS, PbS, Sb ₂ S ₃ , Bi ₂ S ₃ , ZnSe, CdSe, HgSe, SnSe, PbSe, In ₂ Se ₃ , Sb ₂ Se ₃ , BiSe ₃ , ZnTe, CdTe, HgTe, SnTe, PbTe, In ₂ Te ₃ , Bi ₂ Te ₃ , BN, GaN, InN, TiN, BP, AlP, GaP, InP, Zn ₃ P ₂ , Cd ₃ P ₂ , ZnP ₂ , CdP ₂ , AlAs, GaAs, Zn ₃ As ₂ , Cd ₃ As ₂ , ZnAs ₂ , CdAs ₂ , AlSb, GaSb, ZnSb, CdSb, Si ₃ N ₄ It is preferable that it is at least 1 type of compound.

Among these substance groups, at least one of Sn, Sb, Ga, Al, and In is contained in at least one compound of In ₂ O ₃ , Sb ₂ O ₃ , SnO ₂ , ZnO, and GaAs as an impurity. You can do it.

On the other hand, as a material of a mother insulator, although it can select from either a semiconductor and an insulator, it is preferable that it is a material as small as possible of the electron affinity, specifically 1.0 eV or less for the purpose of improving charge retention characteristic. Moreover, it is more preferable to select a high melting point material for the purpose of making it stable also in the heat processing in a semiconductor process, and it is preferable that it is 1400 degreeC or more specifically.

At the same time, the material is more preferably an amorphous material. This is because when the electron trapped in the ultrafine particles leaks into the parent insulator by tunnel conduction, the more likely that the parent insulator is amorphous than the crystalline, the higher the probability that the tunnel electrons will scatter to the parent insulator constituent atoms. As a result, the effective leak amount due to the tunnel conduction of electrons is expected to decrease. In order to make the mother insulator amorphous, it is very preferable to use a physical vapor deposition method such as sputtering as a film formation method of the ultrafine particle dispersion film. This is because physical deposition methods, including sputtering, are easy to obtain amorphous in that a film can be formed even at a relatively low temperature.

Examples of the material of the matrix insulator in the charge holding layer include oxides such as silica, alumina, tinania, mullite, cordierite, spinel, zeolite, forsterite and magnesia, carbides such as boron carbide (B ₄ C), And at least one compound selected from nitrides such as silicon nitride, boron nitride and aluminum nitride, and fluorides such as magnesium fluoride and aluminum fluoride.

In order to improve the charge holding force of the charge holding layer, it is also effective to arrange the ultrafine particles dispersed in the charge holding layer in two or more stages, that is, in a three-dimensional multi-layered structure. More specifically with respect to the multi-layered structure, the ultrafine particles are arranged on a plane parallel to the surface of the semiconductor substrate, and this refers to a structure in which the same planar arrangement is repeated again with one layer and a thin insulating layer interposed therebetween. The reason why the charge retention characteristics are improved due to the multilayer structure of the ultrafine particles is explained from the following facts. Here, the state in which two superfine particle layers are laminated | stacked as an arrangement structure is defined, and it defines as 1st and 2nd from the side near a semiconductor substrate. When the second electrons try to escape to the semiconductor substrate while the charge is accumulated in both the first and second times, the electrostatic potential formed by the first electrons existing in the leak path is formed. As a result, leakage of the second electron to the substrate side is inhibited, and as a result, the charge retention characteristic is improved than in the case of the single layer arrangement.

The effect of inhibiting the movement of charged particles having the same charge code by virtue of the electrostatic potential formed by the charged particles is called a chromium blockcade effect. When this effect is expressed using an equation, ΔE _c = e ² / (2C). Where ΔE _c Is the increase of the electrostatic potential, that is, the height of the energy barrier due to the chromium blockcade, e is the charge amount of the electron, and C is the tunnel junction capacitance to be the object of charge transfer.

In order to express the chloroblockide effect at room temperature, the increase of the electrostatic potential energy (ΔE _c ) Is greater than the thermal energy of the room temperature, kT _r is a requirement. Where k is Boltzmann's constant and T _r is room temperature. In addition, in addition to this, the condition derived from the uncertainty principle, that is, the resistance between junctions (R) is R to h / e ² It is necessary that it is about 26 to 26 degrees or more. Where h is the Frank constant.

In order to satisfy these requirements and to express a sufficient chromium blockade effect, it is necessary to have a small tunnel junction capacity, which is better as the size of the ultrafine particles is smaller.

In addition, the small size of the ultrafine particles can further expect the following effects. Since the ultrafine particles have a very small dimension of 5 nm or less, it is conceivable that the energy levels have a discrete distribution. Attention is now directed to two ultra-fine particles adjoining in the vertical direction in each of the first and second layers described above. The state of distribution of energy levels in the uncharged state of two ultrafine particles shall be mutually the same. Here, when charge is injected only into the ultrafine particles on the second layer, the energy levels of the charged ultrafine particles shift to the high energy side with respect to the energy levels of the uncharged ultrafine particles on the first layer. As a result, the heights of the distributions of the energy levels of the two ultra-fine particles of interest are relatively different, and the level at which the energy coincides with the energy level at which the electrons injected into the second-layer ultra-fine particles are trapped does not exist in the ultra-fine particles of the first layer. There is a possibility.

When there is no coinciding energy level, tunnel conduction between these ultrafine particles becomes impossible, so that charges in the ultrafine particles of the second layer are prevented from leaking to the semiconductor substrate side via the ultrafine particles of the first layer. This phenomenon cannot occur with a bulk material whose energy level distribution is continuous. It is expressed when the size of the ultrafine particles is sufficiently small and the energy level distribution is in a quantized and discrete state, whereby it becomes possible to suppress the movement of charge due to the tunnel phenomenon.

The above is explanation of the physical reason that the charge retention characteristic by the multilayer structure of ultrafine particles is improved. In order to effectively obtain the above-described chrome blecate effect or quantization effect, the size of each ultrafine particle is preferably small, preferably 5 nm or less, and more preferably 3 nm or less. The keulrom to locate the assembly effect in one aspect is spatially, it is preferable that the area density of the super fine particles is that 10 to ⁺¹² 10 ⁺¹⁴ / ㎠.

In addition, in order to reduce the tunnel junction capacity and increase the inter-junction resistance, the outer interval distance of the ultrafine particles, in this case, the distance between the first layer and the second layer is preferably somewhat wider, and preferably 1 nm or more. However, if the interval is too large, the interval between the semiconductor substrate and the control gate electrode is widened, and in the case of a device with a small channel length, the short channel effect is caused. Therefore, it is preferable to set 5 nm as the upper limit of the outer interval distance.

The method for forming the charge holding layer according to the present invention is formed in one process by a physical film forming method. Although it is conceivable to employ the CVD method as a method for forming the charge retaining phase, in the case of the CVD method, since the ultrafine particles and the parent insulator must be formed separately, a method of forming the dispersed state of the ultrafine particles in three dimensions in multiple layers is required. It was complicated. On the other hand, according to the forming method of the present invention, since the ultrafine particles and the mother-like insulator are formed at the same time, and the structure in which the ultrafine particles are dispersed is self-organized, it can be formed very easily and inexpensively. In this regard, in the formation of the multilayer structure of the ultrafine particles as described above, the method of forming the charge holding layer in the present invention is very suitable.

In the above comparison regarding the method for forming the charge holding layer, it is explained in more detail as follows. Compared with the physical film formation method, the CVD method has a high gas phase pressure at the time of film formation, a high frequency of collisions in the gas phase of reactive atomic species and reactive molecular species, and a high gas phase temperature and a substrate surface temperature. It is easy to form a single phase film, that is, an equilibrium film, in which phases are not separated. Therefore, chemical vapor deposition is not suitable when ultrafine particles such as the charge holding layer of the present invention and the parent insulator are separated, that is, when a film in a non-equilibrium or quasi-equilibrium state is formed. In addition, the kind of source gas applicable to the CVD method is not so large as compared with the physical vapor deposition method such as sputtering method, and in particular, there are few source gas species for forming the metal film. In addition, since the number of combinations of gas species that can be simultaneously supplied into the reactor is smaller, and therefore the material that can form a film is limited, the chemical vapor deposition method is also not suitable in this respect.

On the other hand, according to the physical film formation method, the non-equilibrium state or quasi-like state of the charge holding layer of the present invention is due to the reason that the reaction atoms involved in the film formation, the collision frequency between molecules in the gas phase are low, and the substrate temperature is low. Equilibrium films are likely to form.

As a physical vapor deposition method for forming a charge holding layer, sputtering method, thermal vapor deposition method, electron beam vapor deposition method, laser application method, molecular beam epitaxy method etc. are mentioned. Among these, the sputtering method can select a film forming material widely, the high energy of incidence of the film-forming particles on the substrate, the high atomic bonding force and the easy to obtain a dense film, and the high adhesion film to the base can be obtained. In addition to these, etc., since it is excellent in mass productivity, it is especially preferable.

In addition, the sputtering method is preferable because suitable film forming conditions are obtained in the self-organization in the present invention. For example, since a suitable substrate temperature is obtained, which is low enough in gas phase pressure and not low or high in temperature, self-organization can be obtained by causing suitable migration of film forming seed particles on the substrate surface.

In the present invention, the self-organization means that the atomic group constituting the ultrafine particles and the atomic group constituting the parent insulator are spontaneously separated and arranged by thermodynamic interaction or the like, and as a result, nano-scale ultra-fine particles of a metal or semiconductor in the mother phase insulator phase. Indicates aggregation and organization. The aspect of the atomic arrangement by self-organization is influenced by the combination and the ratio of the ultrafine particle constituent material and the parent insulator constituent material, and film forming conditions such as the applied power to the plasma, the film forming pressure, the substrate temperature, and the like.

Further, as the sputtering device, since it is low damage with respect to the tunnel insulating film of the base, it is preferable to use an inductively coupled plasma (ICP) or an electromagnetically coupled plasma (ECR plasma) or an apparatus of an opposing target method, and these In the film forming apparatus of the present invention, it is more preferable to use an apparatus having a function of giving a suitable bias voltage to the film forming substrate in terms of being able to control the incident energy of the film forming particles to the substrate.

When forming a charge holding layer by the sputtering method, it is necessary to sputter | spatter the material which forms the image of a dispersion ultrafine particle, and the material which forms the image of a mother phase insulator simultaneously. There is a method of separately preparing the material of each phase and sputtering a plurality of these targets at the same time, or a method of mixing the sputtering material in one target. The latter can also be used by sintering a mixed powder of the modal material, or by embedding a suitable number of chips so that the chip pieces of the other phase material are exposed on the surface to the single phase target of the one phase material.

Moreover, when the sputtering surface of a target is formed vertically upward in the film formation chamber of a film forming apparatus, as much as the number of chip | tip pieces of the material of the other phase was carried out on the single phase target of the material of one phase, or more. As long as the mixed powder of an aspect is spread | filled with a glass chalet etc., it can also be used as a target. However, the powder target is very unpreferable in producing a semiconductor device for the reason that powder may scatter in a film formation environment, and may adversely affect another semiconductor manufacturing process.

In the process of forming the charge holding layer by the sputtering method, by controlling the target composition and film formation conditions, the average particle diameter and density of the dispersed phase growing in the matrix phase are changed. In particular, it is confirmed that it is changed by the volume fraction of the dispersed phase and the matrix phase, and the film forming conditions (Ar gas pressure and substrate temperature during sputtering). As an example of the results, in the case of forming a film in which Co metal ultrafine particles are dispersed in Si0 ₂ using a Co-Si0 ₂ target, the film is formed at an Ar gas pressure of 0.5 Pa with a volume ratio of Co and SiO ₂ of 50:50. In one case, while the particle size of the Co particles was about 2 nm, when the film was formed with a gas pressure of 8 Pa, Co particles having a particle diameter of about 5 nm were obtained.

When the volume ratio of Co and SiO ₂ of the Co-SiO ₂ target is 23:77, the density ratio is 1 × 10 ⁺¹³ / cm 2 and the outer space distance of the ultrafine particles is 0.9 nm. The density became 7x10 ^{+ 12} / cm <2> and the outer space | interval was 1.8 nm. In this way, by adjusting the composition ratio of the target, it is possible to control the density of the ultrafine particles and the outer gap distance.

The gate insulating film 4 satisfies the following conditions in order to perform data writing and erasing operation at high speed, or to improve the controllability of the electric field distribution near the surface of the p-type semiconductor substrate 1 by the control gate voltage. Good to do. That is, the film thickness and the material are determined so that the capacitive coupling between the control gate electrode 5 and the p-type semiconductor substrate 1 and the capacitive coupling between the control gate electrode 5 and the floating gate, that is, the metal ultrafine particles 3a2, are increased. It is preferable to select a material having a low physical thickness and a high dielectric constant. Specifically, the thickness is 10 nm or less, in addition to SiO _{2 as the} material, the SiO _x N _y- based material or SiO ₂ and SiO _x N _y (0 ≦ x <2, 0 < _y ≦ 4/3; It is more preferable to use a laminated film of y) and more preferably satisfy 2x + 3y = 4.

The nonvolatile semiconductor memory device of the present invention uses a thin film having a work function or a material having an electron affinity of 4.2 eV or more as an ultrafine particle having a particle diameter of 5 nm or less and a thin film in which the ultrafine particles are dispersed in a high density in an amorphous insulator having an electron affinity of 1.0 eV or less. The charge holding layer can have a large amount of charges independently dispersed and retained, and has a high ability to hold electrons in an environment at room temperature and high temperature. This high charge holding capability makes it possible to reduce the thickness of the tunnel insulating film and the gate insulating film inserted between the charge holding layer and the control gate electrode. This is very advantageous in increasing the operation speed of writing and erasing, reducing the driving voltage, and miniaturizing and integrating elements.

Further, a thin film in which a material having a work function of 0.5 eV or less in a semiconductor substrate or a control gate electrode is made of ultra fine particles having a particle diameter of 5 nm or less, and the ultra fine particles are dispersed at high density in an amorphous insulator having an electron affinity of 1.0 eV or less. The charge holding layer of the nonvolatile semiconductor memory device according to the present invention can disperse and hold a large amount of charges independently, and can suppress a decrease in the effective value of the energy barrier. The ability to retain the electrons is very high. This high charge holding capability makes it possible to reduce the thickness of the tunnel insulating film and the insulating film inserted between the charge holding layer and the control gate electrode. This is very advantageous in increasing the operation speed of writing and erasing, reducing the driving voltage, and miniaturizing and integrating elements.

In addition, by dispersing the ultrafine particles so that the outer interval distance of the adjacent ultrafine particles in the charge holding layer is 1 nm or more and 5 nm or less, the movement between the adjacent ultrafine particles of the retained charge can be suppressed. This is very advantageous in terms of the characteristics of the device, particularly in increasing the rewrite resistance and stably performing the operation. In addition, the high charge retention characteristics described above also suppress movement of charges between adjacent ultrafine particles in the charge retention layer, and thus are effective for improving rewriting characteristics and stabilizing multi-valued operations.

In addition, by using the sputtering method when forming the charge holding layer, a material having various compositions can be selected on a dispersed phase and a matrix, and since it can be easily inserted into a conventional semiconductor manufacturing process as a film forming process, The nonvolatile semiconductor memory device having good reproducibility and high performance can be supplied without greatly changing the conventional process.

An Example is described below.

[Example 1]

The nonvolatile semiconductor memory device of this example will be described with reference to FIG. 2. The tunnel insulating film 2 was formed on the p-type semiconductor substrate 1. The tunnel insulating film 2 is thermally oxidized at 800 ° C. and has a thickness of 5 nm.

Thereafter, the charge holding layer 3 made of the mother-like insulator 3b containing the ultrafine metal particles 3a2 was formed with a thickness of 5 nm by the following method by the capacitively coupled magnetron sputtering method. Co having a work function of 5.0 eV as the ultrafine metal particles and amorphous SiO ₂ having an electron affinity of 1.0 eV were selected as the mother phase insulator. At the time of sputtering, a target having a 5 mm Co chip on a 3 inch diameter (7.62 cm) SiO ₂ target was used. The amount of Co chip was adjusted to occupy 20% of the vertical projection surface area of the target.

After exhausting the film formation chamber of a sputtering apparatus to 5x10 <^-4> Pa, Ar gas was introduce | transduced and gas flow volume was adjusted so that the gas pressure of the film formation chamber might be set to 0.5 Pa. The plasma was generated by supplying a high frequency (13.56 MHz) power of 200 W. The Co-SiO ₂ composite film thus formed was observed with a TEM (transmission electron microscope). As a result, ultrafine particles of Co crystals having an average particle diameter of about 2 nm were dispersed in an amorphous SiO _{2 with} a surface density of approximately 8 × 10 ¹² / cm 2. It was confirmed that there existed, and the outer space | interval distance was estimated to be 1.6 nm.

After the SiO ₂ film was formed as the gate insulating film 4 on the Co—SiO ₂ composite film, a laminated film was formed by sputtering tungsten nitride (W ₂ N) and tungsten as the control gate electrode 5. Thereafter, a Si0 ₂ film used as a hard mask was formed into a film. After patterning the positive photoresist as a mask for gate etching, etching the Si0 ₂ hard mask, further, the control gate electrode 5, tungsten and tungsten nitride, the gate insulating film 4, and the charge holding layer 3 Was dry etched. Thereafter, the source region 6 and the drain region 7 were formed by ion implantation and annealing of As. After the protective film was formed, a contact hole was formed, and an Al electrode was formed so as to be in contact with the source region 6, the drain region 7, and the control gate electrode 5.

The memory cell having the Co-SiO ₂ based charge holding layer thus produced has a very long charge holding time compared with each memory cell having Si ultrafine particles prepared using the same method, and the holding time by extrapolation of the measurement result. Appeared to be over twenty years. It has also been confirmed that two bits of information can be stored per memory element.

[Example 2]

The nonvolatile semiconductor memory device of this example will be described with reference to FIG. 3. As the p-type semiconductor substrate 1, an SOI (Silicon On Insulator) substrate having a p-type SOI layer 1a was used. Device separation was performed by mesa processing, and boron (B) implantation was performed for threshold adjustment. The work function of the p-type SOI layer 1a at this time was estimated to be 4.95 eV. Thereafter, the tunnel insulating film 2 was formed on the surface of the p-type SOI layer 1a. The tunnel insulating film 2 is thermally oxidized at 800 ° C. at a temperature of 3 nm.

Thereafter, the charge holding layer 3 made of the mother-like insulator 3b containing the ultrafine metal particles 3a2 was formed with a thickness of 5 nm by the following method by the capacitively coupled magnetron sputtering method. Ru having a work function of 4.7 eV as the material of the metal ultrafine particles, and AlN having a negative work function as the parent insulator were selected. In this case, the work function difference between the p-type SOI substrate 1a and the Ru ultrafine particles 3a2 is 0.25 eV. In sputtering, a sintered target obtained by sintering a mixture of high purity Ru and high purity AlN at a ratio of 10:90 Vol% was used.

After exhausting the film formation chamber of a sputtering apparatus to 5 * 10 <^-4> Pa, gas was introduce | transduced and gas flow volume was adjusted so that the gas pressure of the film formation chamber might be set to 0.5Pa. Plasma was generated by supplying a high frequency (13.56 MHz) electric power of 200 W, and a 3 nm of Ru-AlN type charge holding layer was deposited. As a result of evaluating the film by TEM, it was confirmed that Ru ultrafine particles having a density of 8 × 10 ⁺¹² / cm 2 at a size of 2 nm were dispersed in the amorphous AlN base material insulator.

After the SiO ₂ film was formed as the gate insulating film 4 on the Ru-AlN composite film, polycrystalline Si was formed as a control gate electrode 5 by low pressure CVD. Then, the positive photoresist was patterned as a mask for gate etching, and the polycrystal (Si), the gate insulating film 4, and the charge holding layer 3 which are control gate electrodes 5 were processed by dry etching.

After implanting As ions with lower energy to form a shallow junction regions (6a, 7a), Si0 ₂ film was formed on a film by low pressure CVD. The sidewall 8 was formed by etching this Si0 ₂ film anisotropically. Thereafter, As ions were implanted slightly to form the contact regions 6b and 7b, and then the formation of the source region 6 and the drain region 7 was completed by RTA (Rapid Thermal Anneal) treatment. After the protective film was formed, a contact hole was formed, and an Al electrode was formed so as to contact the source region 6, the drain region 7, and the control gate electrode 5.

As a result of estimating the height of the potential barrier for the electrons injected into the Ru floating gate in the memory cell having the Ru-SiO ₂ based charge holding layer thus manufactured, the work function of Ru and the oxide film were approximately 3.7 eV. The difference in electron affinity was nearly identical. This indicates that electrons were not previously injected into the floating gate and there was no decrease in the effective potential barrier height. In addition, the height of this potential barrier was estimated from the tunnel leak rate of the electron injected into the floating gate. The charge holding time was very long compared with each memory cell having Si ultrafine particles manufactured using the same method, and the charge holding time in an environment of 250 ° C. was found to be over 20 years by extrapolation of the measurement data. In addition, it has been confirmed that two bits of information can be stored per memory element.

The nonvolatile semiconductor memory device according to the present invention dramatically improves the charge retention characteristics in an environment at room temperature and high temperature as compared with a conventional memory device of the same type, for example, a flash memory or an Si ultrafine memory. As a result, it is possible to reduce the thickness of the gate insulating film adjacent to the tunnel insulating film and the charge holding layer, thereby improving the data writing and erasing speed and operating at a low voltage. Moreover, also in correspondence with the miniaturization of an element, correspondence with the element dimension which is difficult to implement | achieve in the said conventional memory element is attained.

In addition, the above-described effects of the nonvolatile semiconductor memory device according to the present invention enable applications that are difficult to use in conventional nonvolatile semiconductor memory devices and applications to the technical field, and are particularly applicable to a wide range of applications in portable terminal devices. In addition, it is thought that nonvolatile volatilization of the PC-mounted memory can be made possible by the replacement of DRAM.

Also, Japanese Patent Application No. 2004-121837, filed April 16, 2004, Japanese Patent Application 2004-129840, filed April 26, 2004, and Japanese Patent Application 2005, filed February 27, 2005 The entire contents of -30859 and Japanese Patent Application No. 2005-30860, the claims, the drawings, and the abstract are incorporated herein by reference and are taken as the disclosure of the present invention.

Claims (21)

A source region and a drain region formed on the surface of the semiconductor substrate; A channel formation region formed to connect the source region and the drain region or between the source region and the drain region; A tunnel insulating layer formed in contact with the channel formation region; A charge holding layer formed adjacent to the tunnel insulating film; A gate insulating film formed adjacent to the charge holding layer; And A control gate formed adjacent to the gate insulating film, The charge holding layer contains one ultrafine particle of a good conductor consisting of at least one single element material or compound having a particle diameter of 5 nm or less that functions as a floating gate per nonvolatile semiconductor memory element, or a square centimeter of the charge holding layer. It consists of a mother-like insulator which contains a plurality of dispersed independently at a density of 10 ⁺¹² to 10 ⁺¹⁴ per sugar, The mother insulator is amorphous and its electron affinity is 1.0 eV or less, and The work function of the ultrafine particles of said good conductor is 4.2 eV or more, The nonvolatile semiconductor memory element characterized by the above-mentioned. The method of claim 1, And a difference between the work function of the ultrafine particles and the work function of the semiconductor substrate is 0.5 eV or less. The method according to claim 1 or 2, A nonvolatile semiconductor memory device, wherein a difference between the work function of the ultrafine particles and the work function of the control gate is 0.5 eV or less. The method according to any one of claims 1, 2 or 3, A nonvolatile semiconductor memory device according to claim 1, wherein the ultrafine particles are adjacent to each other with a distance of 1 to 5 nm. The method according to any one of claims 1 to 4, A nonvolatile semiconductor memory device having a melting point of at least 1,400 ° C. The method according to any one of claims 1 to 5, The absolute value of the difference of the ionization energy in the said semiconductor substrate of the atom which comprises the said ultrafine particle, and the energy of the center level of the gold band of the said semiconductor substrate is 0.1 eV or more, The nonvolatile semiconductor memory element. The method according to any one of claims 1 to 6, A nonvolatile semiconductor memory device according to claim 1, wherein the ultrafine particles are a single group or a compound composed of at least one of an element group of W, Mo, Ti, Pt, Pd, Ni, Ta, Cr, Os, Nb, Ru, and Rh. The method according to any one of claims 1 to 7, A nonvolatile semiconductor memory device, wherein the mother insulator constituting the charge holding layer is formed of at least one compound selected from the group consisting of oxides, carbides, nitrides, borides, silicides, and fluorides. The method according to any one of claims 1 to 8, A nonvolatile semiconductor memory device in which the ultrafine particles constituting the charge holding layer are dispersed two-dimensionally or three-dimensionally in the mother insulator. A manufacturing method of a nonvolatile semiconductor memory device having a charge holding layer in which ultrafine particles are dispersed two-dimensionally or three-dimensionally in a mother-like insulator according to claim 9, The charge holding layer is a method for manufacturing a nonvolatile semiconductor memory device, characterized in that each material constituting the ultrafine particles and the parent insulator is formed by self-organization by physical vapor deposition. The method of claim 10, The physical vapor deposition method is a sputtering method. A source region and a drain region formed on the surface of the semiconductor substrate; A channel formation region formed to connect the source region and the drain region or between the source region and the drain region; A tunnel insulating layer formed in contact with the channel formation region; A charge holding layer formed adjacent to the tunnel insulating film; A gate insulating film formed adjacent to the charge holding layer; And A control gate formed adjacent to the gate insulating film, The charge holding layer contains one or more ultrafine particles of a semiconductor or insulator composed of one or more single element materials or compounds having a particle diameter of 5 nm or less that functions as a floating gate per nonvolatile semiconductor memory element, or It consists of a mother-like insulator, which contains a plurality of dispersions independently at a density of 10 ⁺¹² to 10 ⁺¹⁴ per square centimeter, The mother insulator is amorphous and its electron affinity is 1.0 eV or less, and A nonvolatile semiconductor memory device characterized in that the electron affinity of the ultrafine particles is 4.2 eV or more. The method of claim 12, And a difference between the work function of the ultrafine particles and the work function of the semiconductor substrate is 0.5 eV or less. The method according to claim 12 or 13, A nonvolatile semiconductor memory device, wherein a difference between the work function of the ultrafine particles and the work function of the control gate is 0.5 eV or less. The method according to any one of claims 12, 13 or 14, A nonvolatile semiconductor memory device according to claim 1, wherein the ultrafine particles are adjacent to each other with a distance of 1 to 5 nm. The method according to any one of claims 12 to 15, A nonvolatile semiconductor memory device having a melting point of at least 1,400 ° C. The method according to any one of claims 12 to 16, An absolute value of the difference between the ionization energy in the semiconductor substrate of the atoms constituting the ultrafine particles and the energy of the center level of the gold band of the semiconductor substrate is 0.1 eV or more. The method according to any one of claims 12 to 17, A nonvolatile semiconductor memory device, comprising: at least one compound selected from the group consisting of oxides, carbides, nitrides, borides, silicides, and fluorides. The method according to any one of claims 12 to 18, A nonvolatile semiconductor memory device in which the ultrafine particles constituting the charge holding layer are dispersed two-dimensionally or three-dimensionally in the mother insulator. A method of manufacturing a nonvolatile semiconductor memory device having a charge holding layer in which ultrafine particles are dispersed two-dimensionally or three-dimensionally in a mother-like insulator according to claim 19, The charge holding layer is a method of manufacturing a nonvolatile semiconductor memory device, characterized in that each material constituting the ultrafine particles and the parent insulator is formed by self-organization by physical vapor deposition. The method of claim 20, And the physical vapor deposition method is a sputtering method.

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