CN102208442B - Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure - Google Patents
Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 29
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000002159 nanocrystal Substances 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 7
- 230000001020 rhythmical effect Effects 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 23
- 238000000231 atomic layer deposition Methods 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 18
- 238000002360 preparation method Methods 0.000 claims description 17
- 229910003855 HfAlO Inorganic materials 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims description 6
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000002243 precursor Substances 0.000 claims description 4
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- DAZXVJBJRMWXJP-UHFFFAOYSA-N n,n-dimethylethylamine Chemical compound CCN(C)C DAZXVJBJRMWXJP-UHFFFAOYSA-N 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical group C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 3
- 230000006870 function Effects 0.000 abstract description 8
- 239000003990 capacitor Substances 0.000 abstract description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- 238000003949 trap density measurement Methods 0.000 abstract description 2
- 229910019897 RuOx Inorganic materials 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 2
- 230000005641 tunneling Effects 0.000 abstract 1
- 238000003860 storage Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004321 preservation Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
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- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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Abstract
The invention relates to a gate stack structure suitable for a semiconductor flash memory device and a manufacturing method of the gate stack structure. In the gate stack structure, a P-type monocrystalline silicon wafer with crystallographic orientation of 100 is used as a substrate; and an Al2O3 film used as a charge tunneling layer, ruthenium-based RuOx nano-crystals used as a first charge trapping layer, a high dielectric constant HfxAlyOz film used as a second charge trapping layer, an Al2O3 film used as a charge barrier layer and an upper electrode layer are arranged on the substrate from bottom to top sequentially. In the invention, the ruthenium-based RuOx nano-crystals have high thermal stability and are difficult to diffuse at high temperature; the high dielectric constant HfxAlyOz film has higher charge trap density; and an upper electrode is made of metal palladium and has a higher work function. Therefore, the gate stack structure disclosed by the invention has wide application prospect in a nano-crystal memory capacitor.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of capacitance structure and preparation method of flash memory, relate in particular to and a kind ofly consist of wherein rhythmic structure of the fence and the preparation method of novel heterogeneous electric charge capture layer based on metallic nano crystal and high dielectric constant.
Background technology
Development along with semiconductor process techniques, the non-volatile flash memory integration density is more and more higher, operating voltage is more and more lower, this just orders about device feature size and continues to reduce, a series of problem has appearred in traditional multi-crystal silicon floating bar structure after 65 nm technology nodes, greatly affected the performance of device stores, slow such as erasable speed, operating voltage is high.
Non-volatility memorizer of new generation based on discontinuous electric charge capture mechanism (such as nanocrystalline, SONOS memory etc.) attracts wide attention recently, they adopt the charge trap that separates to replace continuous multi-crystal silicon floating bar stored charge, so that the local defect that exists in the tunnel layer can not cause charge loss a large amount of in the electric charge capture layer, thereby effectively improved the data hold capacity of memory, and can obtain lower operating voltage, realize faster erasable speed etc.
Compare with semiconductor nano, metallic nano crystal has the higher density of states near Fermi level, the range of choice of work function is wider, with substrate channel stronger coupling etc. is arranged, so it can realize that the charge storage of lower operating voltage, higher density and the electric charge of long period keep.Studies show that the metallic nano crystal by selection has larger work function can form darker potential well, thereby trap-charge also can provide better data preservation characteristics effectively.
On the other hand, along with the development of SONOS memory, adopt the silicon nitride electric charge capture layer among high dielectric constant material (High-k) the replacement SONOS, can correspondingly increase the electric field strength that drops on the tunnel layer, thereby improve programming and erasing speed.But the shortcoming of this structure memory is that its operating voltage is higher, and service speed is slower.
Summary of the invention
The purpose of this invention is to provide the rhythmic structure of the fence that is suitable for semiconductor flash memory device that a kind of stored charge density is high, low, the erasable speed of operating voltage is fast and charge-retention property is good.A further object of the present invention provides the preparation method of above-mentioned rhythmic structure of the fence.
In order to achieve the above object, technical scheme of the present invention provides a kind of rhythmic structure of the fence and preparation method who is suitable for semiconductor flash memory device.
Wherein said rhythmic structure of the fence includes the heterogeneous electric charge capture layer based on metallic nano crystal and high dielectric constant film; In the described rhythmic structure of the fence, be disposed with from the bottom to top:
The crystal orientation is 100 p type single crystal silicon sheet, as substrate;
The Al of atomic layer deposition
2O
3Film, as the electric charge tunnel layer, thickness is 5～15 nanometers;
Described heterogeneous electric charge capture layer, it further includes:
Described metallic nano crystal is as the first electric charge capture layer, and this is nanocrystalline to be the compound of ruthenium and ruthenium-oxide, is designated as ruthenium base RuO
xNanocrystalline;
The described high dielectric constant film of atomic layer deposition is as the second electric charge capture layer, and thickness is 5 ~ 10 nanometers; Described high dielectric constant is Hf
xAl
yO
z, x wherein〉0, z〉0 and y=0 or y 0;
The Al of atomic layer deposition
2O
3Film, as electric charge barrier layer, thickness is 15～40 nanometers;
Upper electrode layer.
Described high dielectric constant film is the HfAlO film, and the ratio that wherein comprises the deposit period is the HfO of 1:1
2And Al
2O
3Perhaps, described high dielectric constant film is HfO
2Film.
Described upper electrode layer comprises the gate electrode that forms with Metal Palladium.
The preparation method of above-mentioned rhythmic structure of the fence specifically comprises following steps:
Step 1, to adopt the crystal orientation be that 100 p type single crystal silicon sheet is as substrate;
The Al of method growth 5～15 nanometer thickness of step 2, employing atomic layer deposition
2O
3Film is as the electric charge tunnel layer;
The method of step 3.1, the deposit of employing magnetron sputtering is at Al
2O
3Deposition thickness is the metal Ru layer of 2～4 nanometers on the tunnel layer, then carries out quick thermal annealing process in nitrogen atmosphere, forms ruthenium base RuO
xNanocrystalline the first electric charge capture layer as heterogeneous electric charge capture layer; Described ruthenium base RuO
xNanocrystalline is the compound of ruthenium and ruthenium-oxide;
The high-k Hf of method growth 5 ~ 10 nanometer thickness of step 3.2, employing atomic layer deposition
xAl
yO
zFilm is as the second electric charge capture layer of heterogeneous electric charge capture layer: described high-k Hf
xAl
yO
zX in the film〉0, z〉0, while y=0 or y〉0; Wherein the composition of Hf and Al is by atomic layer deposition HfO
2And Al
2O
3Period determine;
The Al of method growth 15～40 nanometer thickness of step 4, employing atomic layer deposition
2O
3Then film carries out quick thermal annealing process as electric charge barrier layer;
Step 5, use photoetching process, adopt stripping means to form the gate electrode of 50～200 nanometer thickness as upper electrode layer.
High-k Hf described in the described step 3.2
xAl
yO
zFilm is the HfAlO film, and the ratio that wherein comprises the deposit period is the HfO of 1:1
2And Al
2O
3Perhaps, described high-k Hf
xAl
yO
zFilm is HfO
2Film.
Sublayer, described step 3.2 Central Plains deposit growth HfO
2Condition be: underlayer temperature is at 250～350 ℃, and the reaction precursor is four (ethyl dimethylamine base) hafnium and water vapour.
Described step 2, step 3.2 or the sublayer deposit of step 4 Central Plains generate described Al
2O
3The condition of film is: underlayer temperature is at 250～350 ℃, and the reaction precursor is trimethyl aluminium and water vapour.
Form ruthenium base RuO in the described step 3.1
xAnnealing temperature when nanocrystalline is 700～900 ℃, and annealing time is 10～30 seconds; Form electric charge barrier layer Al in the step 4
2O
3Annealing temperature during film is 500～800 ℃, and annealing time is 10～30 seconds.
The material that forms described gate electrode in the described step 5 is Metal Palladium.
Described preparation method also comprises:
Rhythmic structure of the fence and the preparation method who is suitable for semiconductor flash memory device of the present invention has the following advantages:
1, adopt the magnetron sputtering deposit to form super thin metal ruthenium film, by regulating deposit power, time, underlayer temperature etc., can under condition of high vacuum degree, control thickness and the deposition rate of film more accurately, forming ultra-thin and uniform metal film, this so that after the annealing easier formation diameter little, be evenly distributed and nano-crystalline granule that density is high.
2, the first electric charge capture layer adopts ruthenium base RuO
xNanocrystalline as the charge storage center, because their work function higher (4.7～5.2 eV) so the larger potential well degree of depth can be provided, is conducive to improve the storage capacity of electric charge.The formation temperature of this metallic nano crystal is compatible mutually with the manufacture craft temperature of memory among the present invention, above the activation annealing temperature behind source, the leakage Implantation in the element manufacturing.
3, the second electric charge capture layer adopts high dielectric constant Hf
xAl
yO
zAs storage center, because Hf
xAl
yO
zDielectric constant high (10～25), can effectively increase the electric field strength that drops on the tunnel layer, thereby improve programming and the erasing speed of memory, and reduce operating voltage.Simultaneously, Hf
xAl
yO
zMaterial can provide abundant charge trap, is used for stored charge.
4, by high-k Hf
xAl
yO
zWith highdensity ruthenium base RuO
xThe heterogeneous electric charge capture layer of nanocrystalline composition can be captured the charge injection from substrate jointly, has greatly improved the storage density of electric charge.In addition, high density ruthenium base RuO
xThe nanocrystalline Hf that is embedded into
xAl
yO
zIn the film, effectively suppressed Hf
xAl
yO
zCrystallization occurs in medium behind high annealing, therefore reduced the charge leakage along grain boundary, has improved the charge-retention property of memory.
5, adopt the method for atomic layer deposition to prepare Hf
xAl
yO
zFilm not only can accurately be controlled composition and the thickness of film, can also effectively fill spacing in the slit of nanometer scale, thus so that RuO
xNanocrystalline can be by Hf
xAl
yO
zKeep apart fully.
6, adopt Metal Palladium as electrode, not only can form with the alumina medium on barrier layer and be beneficial to erasable barrier, and palladium is difficult for oxidizedly, have good chemical stability and thermal stability.Utilize the electron beam evaporation equipment palladium membranes of growing under high vacuum, palladium film and the alumina medium of growth can form good contact interface in this respect, thereby have improved the performance of capacitor storage.
Therefore, rhythmic structure of the fence proposed by the invention will have good application prospect at flash memory of future generation.
Description of drawings
Fig. 1 is based on ruthenium base RuO among the present invention
xNanocrystalline and high-k Hf
xAl
yO
zThe heterogeneous electric charge capture layer of film consists of the sectional structure chart of rhythmic structure of the fence holding capacitor;
The flat band voltage variation diagram that Fig. 2 is rhythmic structure of the fence holding capacitor of the present invention behind 0.1 millisecond of program/erase under the different voltages;
The flat band voltage variation diagram that Fig. 3 is rhythmic structure of the fence holding capacitor of the present invention behind+/-9 V program/erase different times;
Fig. 4 is that rhythmic structure of the fence holding capacitor of the present invention is programmed at+9 V ,-9 V wipe the charge-retention property after 1 millisecond.
Embodiment
Referring to shown in Figure 1, the rhythmic structure of the fence that is suitable for semiconductor flash memory device of the present invention, particularly include the heterogeneous electric charge capture layer based on metallic nano crystal and high dielectric constant film, in this described flash electric capacity that consists of, be disposed with from the bottom to top:
1) crystal orientation is that 100 p type single crystal silicon sheet is as substrate;
2) Al of atomic layer deposition
2O
3Film, as the electric charge tunnel layer, thickness is 5～15 nanometers;
3) described heterogeneous electric charge capture layer, it further includes:
Metallic nano crystal is as the first electric charge capture layer, and this nanocrystalline compound for ruthenium and ruthenium-oxide (is designated as ruthenium base RuO
xNanocrystalline);
The high dielectric constant film of atomic layer deposition is as the second electric charge capture layer, and thickness is 3 ~ 20 nanometers (preferred thickness range is in 5～10 nanometers); Described high dielectric constant is Hf
xAl
yO
z(x〉0, z〉0, y=0 or y〉0), its dielectric constant is between 10～25;
4) Al of atomic layer deposition
2O
3Film serves as electric charge barrier layer, and thickness is 15～40 nanometers;
5) upper electrode layer comprises the gate electrode that forms with Metal Palladium (Pd).
Comprise the storage capacitance that heterogeneous electric charge capture layer consists of in the above-mentioned rhythmic structure of the fence, its preparation method is as follows:
Step 1, adopt the crystal orientation be 100 p type single crystal silicon sheet as substrate, the resistivity of silicon chip is 8～12 ohmcms.At first silicon chip is carried out standard cleaning, and utilize diluted hydrofluoric acid to remove residual natural oxidizing layer.
Ruthenium base RuO in step 3.1, the heterogeneous electric charge capture layer
xNanocrystalline formation: adopt the method for magnetron sputtering deposit, at Al
2O
3Deposit super thin metal ruthenium layer on the tunnel layer, the thickness of ruthenium layer is 2～4 nanometers, then carries out quick rapid thermal annealing in nitrogen atmosphere, can form ruthenium base RuO
xNanocrystalline as the first electric charge capture layer.Annealing temperature is 700～900 ℃, and annealing time is 10～30 seconds.
High dielectric constant Hf in step 3.2, the heterogeneous electric charge capture layer
xAl
yO
zThe formation of film: the method growth Hf that adopts atomic layer deposition
xAl
yO
zFilm is as the second electric charge capture layer:
Described Hf
xAl
yO
zA kind of composition of film comprises HfO
2And Al
2O
3, the ratio of both deposit periods is 1:1, is designated as HfAlO.Described Hf
xAl
yO
zThe another kind of film does not contain Al in forming
2O
3, be pure HfO
2
In above-mentioned two kinds of compositions, underlayer temperature is controlled in 250～350 ℃ of scopes, HfO
2Reaction source be four (ethyl dimethylamine base) hafnium (TEMAH) and water vapours.Al
2O
3Preparation condition as described in the step (2).
HfAlO or HfO
2The thickness of film is 3 ~ 20 nanometers (preferred thickness range is in 5～10 nanometers).According to described Hf
xAl
yO
zThe thickness of film is different, if its thickness is hour, and this Hf
xAl
yO
zFilm can be filled out described ruthenium base RuO
xBetween nanocrystalline, but can not fill up this gap between nanocrystalline; When if its thickness is larger, described Hf
xAl
yO
zFilm then can fill up described ruthenium base RuO
xGap between nanocrystalline only shows latter event among Fig. 1.
Step 4, electric charge barrier layer Al
2O
3The formation of film: the Al that adopts method deposit 15～40 nanometer thickness described in the step (2)
2O
3Film.Then, the gained sample is carried out quick thermal annealing process in nitrogen, the rapid thermal annealing temperature is 500～800 ℃, and the time is 10～30 seconds.Purpose is to obtain high-quality Al
2O
3The barrier layer suppresses the leakage of electric charge.
The formation of step 5, upper electrode layer: adopt and peel off (lift-off) method formation gate electrode, namely at first form figure by photoetching, then utilize electron beam evaporation equipment growth palladium metal film, thickness is 50～200 nanometers.At last, utilize acetone to clean remaining photoresist.
Fig. 2 is for comprising the storage capacitance that heterogeneous electric charge capture layer consists of in the rhythmic structure of the fence described in this example, in programming under the different voltages with wipe flat band voltage variation diagram after 0.1 millisecond.As seen from the figure, along with the increase of forward bias, the gained flat band voltage is all to the positive direction drift, and this is because electronic injection causes capturing of negative electrical charge to be caused.Along with the increase of negative bias, the flat band voltage of gained is all to the negative direction drift, and this is to inject owing to captive electric charge generation release in the electric charge capture layer or from the hole of substrate to cause.In addition, can observe under same operation voltage RuO
x/ HfO
2Heterogeneous electric charge capture layer compares RuO
xThe heterogeneous electric charge capture layer of/HfAlO can provide larger memory window, and for example, under the operating voltage of 6 V, the former memory window is 2.6 V, and latter is 1.4 V.
Fig. 3 for storage capacitance described in this example+9V programming/-flat band voltage variation diagram after 9V wipes different time.As seen from the figure, the flat band voltage of two electric capacity under the program/erase state all increases along with the increase in burst length, and finally tends to saturated.For 0.1 millisecond program/erase, based on RuO
xThe resulting memory window of the device of/HfAlO electric charge capture layer is near 2V, based on RuO
x/ HfO
2The resulting memory window of the device of electric charge capture layer reaches 3.5V.The two has all shown fast programming and the function of wiping under the low pressure.
Fig. 4 for storage capacitance described in this example at+9 V, 1 millisecond of programming and-9 V, 1 millisecond of retention performance after wiping.Medium in heterogeneous electric charge capture layer is HfO
2The time, the memory window that is extrapolated to this holding capacitor after 10 years is about 3.4 V, has demonstrated good retention performance; When the medium in the heterogeneous electric charge capture layer was HfAlO, its corresponding memory window was about 1.6 V.
The above results shows, based on RuO
xAnd Hf
xAl
yO
zThe storage capacitance of heterogeneous electric charge capture layer all shown under the low pressure fast erasable function, and good electric charge preservation characteristics.
In sum, the present invention fully combines the advantage of metallic nano crystal and high dielectric constant, and consisted of the heterogeneous electric charge capture layer in the rhythmic structure of the fence with this: in this novel heterogeneous electric charge capture layer owing to introduced high dielectric constant, so can increase the electric field strength that drops on the electric charge tunnel layer, reach the potential barrier that reduces charge injection, thereby improve programming and the erasing speed of memory, realize that simultaneously device operates under lower voltage.Simultaneously, the metallic nano crystal that has larger work function can form darker potential well, thereby preferably data preservation characteristics is arranged behind trap-charge.
Metallic nano crystal described in the present invention is that the compound of ruthenium and ruthenium-oxide (is designated as ruthenium base RuO
xNanocrystalline), it has good thermal stability, has both made oxidizedly, also is a kind of good conductor.In addition, it at high temperature is not easy diffusion, is easy to dry etching.
High dielectric constant described in the present invention is Hf
xAl
yO
z(y=0 or〉0), its dielectric constant has higher charge trap density between 10～25, and this is just so that Hf
xAl
yO
zMaterial can be used as desirable electric charge capture layer and replaces silicon nitride.
Top electrode among the present invention adopts Metal Palladium (Pd) material, and it has larger work function (5.22 eV), can be formed with the electric charge barrier layer medium to be beneficial to the erasable barrier height of electric charge, and palladium has good chemical stability and thermal stability.
Therefore, rhythmic structure of the fence proposed by the invention will have good application prospect at flash memory of future generation.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a rhythmic structure of the fence that is suitable for semiconductor flash memory device is characterized in that, includes the heterogeneous electric charge capture layer based on metallic nano crystal and high dielectric constant film; In the described rhythmic structure of the fence, be disposed with from the bottom to top:
The crystal orientation is 100 p type single crystal silicon sheet, as substrate;
The Al of atomic layer deposition
2O
3Film, as the electric charge tunnel layer, thickness is 5～15 nanometers;
Described heterogeneous electric charge capture layer, it further includes:
Described metallic nano crystal is as the first electric charge capture layer, and this is nanocrystalline to be the compound of ruthenium and ruthenium-oxide, is designated as ruthenium base RuO
xNanocrystalline;
The described high dielectric constant film of atomic layer deposition is as the second electric charge capture layer, and thickness is 5 ~ 10 nanometers; Described high dielectric constant is Hf
xAl
yO
z, x wherein〉0, z〉0 and y=0 or y 0;
The Al of atomic layer deposition
2O
3Film, as electric charge barrier layer, thickness is 15～40 nanometers;
Upper electrode layer.
2. rhythmic structure of the fence as claimed in claim 1 is characterized in that described high dielectric constant film is the HfAlO film, and the ratio that wherein comprises the deposit period is the HfO of 1:1
2And Al
2O
3Perhaps, described high dielectric constant film is HfO
2Film.
3. rhythmic structure of the fence as claimed in claim 1 is characterized in that, described upper electrode layer comprises the gate electrode that forms with Metal Palladium.
4. a preparation method who is suitable for the rhythmic structure of the fence of semiconductor flash memory device is characterized in that, comprises following steps:
Step 1, to adopt the crystal orientation be that 100 p type single crystal silicon sheet is as substrate;
The Al of method growth 5～15 nanometer thickness of step 2, employing atomic layer deposition
2O
3Film is as the electric charge tunnel layer;
The method of step 3.1, the deposit of employing magnetron sputtering is at Al
2O
3Deposition thickness is the metal Ru layer of 2～4 nanometers on the tunnel layer, then carries out quick thermal annealing process in nitrogen atmosphere, forms ruthenium base RuO
xNanocrystalline the first electric charge capture layer as heterogeneous electric charge capture layer; Described ruthenium base RuO
xNanocrystalline is the compound of ruthenium and ruthenium-oxide;
The high-k Hf of method growth 5 ~ 10 nanometer thickness of step 3.2, employing atomic layer deposition
xAl
yO
zFilm is as the second electric charge capture layer of heterogeneous electric charge capture layer: described high-k Hf
xAl
yO
zX in the film〉0, z〉0, while y=0 or y〉0; Wherein the composition of Hf and Al is by atomic layer deposition HfO
2And Al
2O
3Period determine;
The Al of method growth 15～40 nanometer thickness of step 4, employing atomic layer deposition
2O
3Then film carries out quick thermal annealing process as electric charge barrier layer;
Step 5, use photoetching process, adopt stripping means to form the gate electrode of 50～200 nanometer thickness as upper electrode layer.
5. preparation method as claimed in claim 4 is characterized in that high-k Hf described in the described step 3.2
xAl
yO
zFilm is the HfAlO film, and the ratio that wherein comprises the deposit period is the HfO of 1:1
2And Al
2O
3Perhaps, described high-k Hf
xAl
yO
zFilm is HfO
2Film.
6. preparation method as claimed in claim 5 is characterized in that, sublayer, described step 3.2 Central Plains deposit growth HfO
2Condition be: underlayer temperature is at 250～350 ℃, and the reaction precursor is four (ethyl dimethylamine base) hafnium and water vapour.
7. such as preparation method as described in claim 4 or 5 or 6, it is characterized in that described step 2, step 3.2 or the sublayer deposit of step 4 Central Plains generate described Al
2O
3The condition of film is: underlayer temperature is at 250～350 ℃, and the reaction precursor is trimethyl aluminium and water vapour.
8. preparation method as claimed in claim 4 is characterized in that, forms ruthenium base RuO in the described step 3.1
xAnnealing temperature when nanocrystalline is 700～900 ℃, and annealing time is 10～30 seconds; Form electric charge barrier layer Al in the step 4
2O
3Annealing temperature during film is 500～800 ℃, and annealing time is 10～30 seconds.
9. preparation method as claimed in claim 4 is characterized in that, the material that forms described gate electrode in the described step 5 is Metal Palladium.
10. preparation method as claimed in claim 4 is characterized in that, also comprises:
Step 6, remove the natural oxidizing layer of substrate back with hydrofluoric acid first, then deposit layer of metal aluminium lamination is as bottom electrode, to form good ohmic contact.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101304848A CN102208442B (en) | 2010-06-03 | 2011-05-19 | Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure |
| PCT/CN2011/000891 WO2011150670A1 (en) | 2010-06-03 | 2011-05-24 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
| US13/518,306 US20130062684A1 (en) | 2010-06-03 | 2011-05-24 | Gate stack structure and fabricating method used for semiconductor flash memory device |
| EP11789049.1A EP2442364A4 (en) | 2010-06-03 | 2011-05-24 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010191659.1 | 2010-06-03 | ||
| CN2010101916591A CN101887910A (en) | 2010-06-03 | 2010-06-03 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
| CN2011101304848A CN102208442B (en) | 2010-06-03 | 2011-05-19 | Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure |
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| CN102208442A CN102208442A (en) | 2011-10-05 |
| CN102208442B true CN102208442B (en) | 2013-04-17 |
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|---|---|---|---|
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| CN2011101304848A Expired - Fee Related CN102208442B (en) | 2010-06-03 | 2011-05-19 | Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure |
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|---|---|
| US (1) | US20130062684A1 (en) |
| EP (1) | EP2442364A4 (en) |
| CN (2) | CN101887910A (en) |
| WO (1) | WO2011150670A1 (en) |
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| CN101887910A (en) * | 2010-06-03 | 2010-11-17 | 复旦大学 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
| CN102646579B (en) * | 2011-02-17 | 2015-01-07 | 中芯国际集成电路制造(上海)有限公司 | Silicon oxide nitride oxide semiconductor (SONOS) structure and manufacturing method |
| CN102938404A (en) * | 2011-08-16 | 2013-02-20 | 北京天中磊智能科技有限公司 | Electrically erasable programmable read only memory (EEPROM) storage chip especial for intelligent ammeter |
| CN102623459B (en) * | 2012-04-10 | 2015-01-07 | 复旦大学 | Thin-film transistor memory and preparation method thereof |
| US9336919B2 (en) | 2012-08-17 | 2016-05-10 | The Trustees Of The University Of Pennsylvania | Methods for preparing colloidal nanocrystal-based thin films |
| WO2014113655A2 (en) * | 2013-01-18 | 2014-07-24 | The Trustees Of The University Of Pennsylvania | Nanocrystal thin film device fabrication methods and apparatus |
| US10720504B2 (en) | 2015-09-11 | 2020-07-21 | Intel Corporation | Transistor with dynamic threshold voltage for low-leakage standby and high speed active mode |
| KR102331474B1 (en) | 2017-06-19 | 2021-11-29 | 삼성전자주식회사 | Semiconductor devices |
| JP2019062170A (en) | 2017-09-28 | 2019-04-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method for manufacturing the same |
| CN108649031A (en) * | 2018-04-09 | 2018-10-12 | 复旦大学 | Ultrafast quasi- nonvolatile storage of two dimension based on self-rectifying elastomeric material and preparation method thereof |
| CN108588677B (en) * | 2018-04-18 | 2020-09-08 | 北京航空航天大学 | High-dielectric-constant nano laminated dielectric film and preparation method thereof |
| TWI815891B (en) * | 2018-06-21 | 2023-09-21 | 美商應用材料股份有限公司 | Thin films and methods of depositing thin films |
| CN109116691B (en) * | 2018-09-25 | 2022-08-16 | 湖南哲龙科技有限公司 | Formula for weakening influence of substrate surface on characteristics of organic photosensitive drum |
| CN112080732B (en) * | 2020-07-29 | 2021-12-28 | 西安交通大学 | Silicon integrated BT-BMZ film, capacitor and manufacturing method thereof |
| CN112908999A (en) * | 2021-03-25 | 2021-06-04 | 复旦大学 | Manufacturing process of semi-floating gate memory and semi-floating gate memory |
| US20230069105A1 (en) * | 2021-08-30 | 2023-03-02 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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| US7012297B2 (en) * | 2001-08-30 | 2006-03-14 | Micron Technology, Inc. | Scalable flash/NV structures and devices with extended endurance |
| KR100672998B1 (en) * | 2005-02-14 | 2007-01-24 | 삼성전자주식회사 | Non-volatile memory device, operation thereof and method for forming thereof |
| US7629641B2 (en) * | 2005-08-31 | 2009-12-08 | Micron Technology, Inc. | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection |
| US7847341B2 (en) * | 2006-12-20 | 2010-12-07 | Nanosys, Inc. | Electron blocking layers for electronic devices |
| KR100900569B1 (en) * | 2007-03-29 | 2009-06-02 | 국민대학교산학협력단 | Method of forming floating gate and method of fabricating non-volatile memory device using the same |
| CN101692463B (en) * | 2009-09-24 | 2011-12-14 | 复旦大学 | Capacitor structure of mixed nano-crystal memory and preparation method thereof |
| CN101887910A (en) * | 2010-06-03 | 2010-11-17 | 复旦大学 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
-
2010
- 2010-06-03 CN CN2010101916591A patent/CN101887910A/en active Pending
-
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- 2011-05-19 CN CN2011101304848A patent/CN102208442B/en not_active Expired - Fee Related
- 2011-05-24 WO PCT/CN2011/000891 patent/WO2011150670A1/en active Application Filing
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Also Published As
| Publication number | Publication date |
|---|---|
| US20130062684A1 (en) | 2013-03-14 |
| EP2442364A1 (en) | 2012-04-18 |
| CN101887910A (en) | 2010-11-17 |
| CN102208442A (en) | 2011-10-05 |
| WO2011150670A1 (en) | 2011-12-08 |
| EP2442364A4 (en) | 2014-08-27 |
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