CN101692463B - Capacitor structure of mixed nano-crystal memory and preparation method thereof - Google Patents
Capacitor structure of mixed nano-crystal memory and preparation method thereof Download PDFInfo
- Publication number
- CN101692463B CN101692463B CN2009101963000A CN200910196300A CN101692463B CN 101692463 B CN101692463 B CN 101692463B CN 2009101963000 A CN2009101963000 A CN 2009101963000A CN 200910196300 A CN200910196300 A CN 200910196300A CN 101692463 B CN101692463 B CN 101692463B
- Authority
- CN
- China
- Prior art keywords
- layer
- ruthenium
- crystal
- nano
- mixed nano
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention belongs to the technical field of manufacturing semiconductor integrated circuits, and particularly relates to a capacitor of a nano-crystal memory and a preparation method thereof. The capacitor uses P-type monocrystalline silicon as a substrate, and an Al2O3 tunneling layer, a ruthenium and ruthenium oxide mixed nano-crystal, an Al2O3 blocking layer and a palladium electrode layer are arranged on the substrate in turn, wherein the Al2O3 layer is prepared by adopting an atomic layer deposition method; the mixed nano-crystal is formed by depositing a ruthenium layer through magnetron sputtering first and then performing rapid thermal annealing in a mixed gas atmosphere of nitrogen gas and a trace amount of oxygen gas; and the palladium electrode layer is formed by adopting a lift-off method. The capacitor structure of the memory has the excellent characteristics of good programming and erasing properties, long charge retention time and the like, and has a good application prospect on a flash memory.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing technology field, be specifically related to a kind of capacitance structure and preparation method of flash memory, especially a kind of mixed nano-crystal storage capacitor construction and preparation method.
Background technology
Continuous development along with semiconductor process techniques, Nonvolatile flash memory integration density is more and more higher, memory cell size reduces thereupon, a series of problem has appearred in traditional multi-crystal silicon floating bar structure after the 65nm technology node, greatly influenced the performance of device stores, slow such as erasable speed, operating voltage high [1].Non-volatility memorizer of new generation based on discontinuous electric charge capture mechanism (as nano-crystal memory etc.) has caused extensive concern recently, it is compared with traditional multi-crystal silicon floating bar structure memory and has numerous advantages, as better data retention characteristics, lower operating voltage and erasable speed etc. [2-4] faster.At present, be used for the nanocrystalline semiconductor and the metal two big classes of mainly containing of flash memory, also have little metal oxide-based nanocrystalline.With respect to the semiconductor nano memory, metallic nano crystal memory has numerous advantages: have the higher density of states near Fermi level, the range of choice of work function is wider, with the raceway groove of substrate stronger coupling [4] is arranged.Studies show that the metal that has big work function can form darker potential well, thus trap-charge and better data preservation characteristics is provided preferably.
Metal Ru (Ru) has bigger work function (4.7eV), good electrical conductivity, and thermal stability is preferably arranged between the high dielectric constant, and its metal oxide also has good charge storage characteristic, so metal Ru has application promise in clinical practice in metallic nano crystal memory.By research, utilize a kind of effective method prepare size consistent, be evenly distributed, density the is high nanocrystalline key issue that will solve before the nano-crystal memory practical application.In addition, the selection of electrode also can greatly influence the performance of device when capacitor storage prepared, there are problems such as resistivity is big, work function is low in traditional polysilicon electrode material, in the application of nano-crystal storage capacitor device, significant limitation is arranged, and the Metal Palladium electrode has bigger work function (5.22eV), can be formed with capacitor dielectric and be beneficial to the erasable barrier height of electric charge, and palladium has good chemical stability and thermal stability, so it has very big application prospect in the preparation of nano-crystal storage capacitor device.
List of references
[1]J.D.Blauwe，IEEE?Trans.Nanotechnology?1，1(2002).
[2]J.J.Lee，and?D.L.Kwong，IEEE?Trans.Electron?Devices?52，507(2005).
[3]H.L.Hanafi，S.Tiwari，and?I.Khan，IEEE?Trans.Electron?Devices?43，1553(1996).
[4]Z.Liu，C.Lee，V.Narayanan，G.Pei，and?E.C.Kan，IEEE?Trans.Electron?Devices?49，1606(2002).
[5]B.Govoreanu，P.Blomme，M.Rosmeulen，and?J.V.Houdt，IEEE?Electron?Device?Lett.24，99(2003).
Summary of the invention
The purpose of this invention is to provide a kind of stored charge density height, data retention characteristics is good, operating voltage is low and erasable fireballing novel ruthenium, ruthenium-oxide mixed nano-crystal memory capacitance structure.
A further object of the present invention provides the preparation method of the said goods.
The capacitance structure of the brilliant memory of the novel nano that the present invention proposes is a substrate layer with the p type single crystal silicon sheet, uses the Al of the method growth of atomic layer deposition
2O
3Nano thin-film is as the electric charge tunnel layer, and thickness is the 5-10 nanometer.After forming tunnel layer, the then ruthenium film of magnetron sputtering one deck 1-4 nanometer thickness, and in the mixed atmosphere of forming by nitrogen and trace oxygen, in 600-900 ℃ of following rapid thermal annealing with formation ruthenium, ruthenium-oxide mixed nano-crystal.Subsequently, the Al of atomic layer deposition 15-40 nanometer thickness
2O
3Film is as the barrier layer, and through rapid thermal treatment in high temperature, the blanket of nitrogen.Through the photoetching process of standard, utilize the lift-off method to form gate electrode, gate electrode is the palladium metal layer of 50-200 nanometer.
The cross-sectional view of the novel mixed nano-crystal storage capacitance of the present invention as shown in Figure 1.
Al among the present invention
2O
3The thickness of film is to realize by the reaction cycle number of times of control atomic layer deposition, and the thickness of ruthenium film and uniformity are to realize by power, time and the substrate rotating speed of control magnetron sputtering.The density of ruthenium, ruthenium-oxide mixed nano-crystal and size are determined by the original depth of ruthenium and the temperature and time of after annealing.The electrode palladium is to utilize electron beam evaporation to form under high vacuum, contacts well the electrode quality height with dielectric surface.
On above-mentioned preparation method basis, the measurement of device performance is for convenience cleaned, is removed the natural oxidizing layer of substrate back with hydrofluoric acid the p type single crystal silicon sheet in (100) crystal orientation, and the aluminium lamination of deposit layer of metal then is to form good Ohmic contact.
The preparation method of Ru nanocrystalline memory capacitor proposed by the invention is as follows:
1, adopts the p type single crystal silicon sheet as substrate, at first silicon chip is carried out standard cleaning, and utilize diluted hydrofluoric acid to remove residual natural oxidizing layer.
2, form tunnel layer: at first in the atomic layer deposition system, with trimethyl aluminium gas silicon chip surface is modified processing, the time is 30-60 minute, and temperature is 250-350 ℃, and purpose is to stop follow-up Al
2O
3The formation of growth for Thin Film process median surface layer; Then, adopt the method growth Al of atomic layer deposition
2O
3Film, underlayer temperature is controlled in the 250-350 ℃ of scope during deposition.Wherein, Al
2O
3Reaction source select trimethyl aluminium and water vapour, Al for use
2O
3The tunnel layer THICKNESS CONTROL is being in the 5-10 nanometer range.
3, form mixed nano-crystal: adopt the method deposit super thin metal ruthenium layer of magnetron sputtering deposition, the thickness of ruthenium layer is the 1-4 nanometer, carries out rapid thermal annealing then in the mixed atmosphere of nitrogen and trace oxygen composition, can form ruthenium, ruthenium-oxide mixed nano-crystal.Annealing temperature is 600-900 ℃, and the time is 10-30 second.
4, form high-quality barrier layer: the method that adopts atomic layer deposition is at mixed nano-crystal/Al
2O
3The long one deck Al of surface regeneration
2O
3Film, underlayer temperature is controlled in the 250-350 ℃ of scope during deposition.Wherein, Al
2O
3Reaction source select trimethyl aluminium and water vapour, Al for use
2O
3The thickness on barrier layer is the 15-40 nanometer.Then above-mentioned sample is carried out rapid thermal treatment in nitrogen, heat treatment temperature is 600-800 ℃, and the time is 10-30 second, and purpose is further to obtain fine and close flawless Al
2O
3The barrier layer suppresses the leakage of electric charge.
5, form gate electrode: adopt the lift-off method to form gate electrode, promptly at first form figure by photoetching, then utilize electron beam evaporation equipment growth palladium metal film, thickness is the 50-200 nanometer, at last, utilize acetone to clean remaining photoresist, thereby finish the manufacture craft of mixed nano-crystal memory electric capacity.
6, the measurement of device performance for convenience, with the natural oxidizing layer of hydrofluoric acid removal substrate back, the aluminium lamination of deposit layer of metal then is as next electrode, to form good Ohmic contact earlier.
The present invention has the following advantages:
1, adopt the magnetron sputtering deposit to form super thin metal ruthenium film, by regulating deposit power, time, underlayer temperature etc., can under condition of high vacuum degree, control the thickness and the deposition rate of film more accurately, forming ultra-thin and the even metal film, this makes, and easier formation diameter after the annealing is little, be evenly distributed and nano-crystalline granule that density is high.
2, adopt ruthenium, ruthenium-oxide mixed nano-crystal as the charge storage center since their work function higher (4.7～5.2eV), so the bigger potential well degree of depth can be provided, help improving the storage capacity of electric charge.New interface has been introduced in the nano particle inside that co-exists in of ruthenium and ruthenium-oxide, thereby has produced new interface trap at the interface at ruthenium/ruthenium-oxide, helps improving the storage density of electric charge.The formation temperature of mixed nano-crystal is compatible mutually with the manufacture craft temperature of memory among the present invention, does not surpass source in the element manufacturing, leaks the activation annealing temperature after ion injects.
3, adopt the method for atomic layer deposition to prepare Al
2O
3Dielectric film not only can accurately be controlled the thickness of film, can also be lower than 350 ℃ of following growth qualities film preferably, helps suppressing the chemical reaction between substrate silicon and the dielectric film.In addition, adopt the atomic layer deposition film technique can effectively fill the slit of spacing, thereby make and kept apart fully between nanocrystalline in nanometer scale.
4, adopt Metal Palladium as gate electrode, not only can form and be beneficial to erasable barrier, and palladium is difficult for oxidizedly, have good chemical stability and thermal stability with the alumina medium on barrier layer.Utilize the electron beam evaporation equipment palladium membranes of under high vacuum, growing, make it and alumina medium can form good contact interface, thereby improved the performance of capacitor storage.
Description of drawings
Fig. 1 contains the memory capacitor cross-sectional view of ruthenium, ruthenium-oxide mixed nano-crystal.
Fig. 2 (a) contains electric capacity-voltage (C-V) curve that the memory capacitor of ruthenium, ruthenium-oxide mixed nano-crystal obtains under the different scanning voltage when 1MHz; (b) the no nanocrystalline electric capacity-voltage curve of alumina medium electric capacity under different scanning voltage.
Fig. 3 contains ruthenium, the nanocrystalline memory capacitor resulting electric capacity-voltage hysteresis window under the different scanning voltage range of ruthenium-oxide.
Fig. 4 contains the programming and the erasing characteristic of ruthenium, ruthenium-oxide mixed nano-crystal storage capacitance: (a) in+8V programming; (b) wipe at-8V.
Fig. 5 contain the nanocrystalline electric capacity of ruthenium, ruthenium-oxide the 8V programming ,-retention performance after 8V wipes.
Number in the figure: 1 is substrate, and 2 is the electric charge tunnel layer, and 3 is ruthenium, ruthenium-oxide mixed nano-crystal, and 4 is the barrier layer, 5 pseudo-gate electrodes.
Embodiment
Below for adopting storage capacitor structures provided by the invention and preparation method, the example of preparation ruthenium, ruthenium-oxide mixed nano-crystal memory electric capacity.
The p type single crystal silicon sheet that adopts (100) crystal orientation is as substrate, and the resistivity of silicon chip is the 8-12 ohmcm.Silicon chip is put into the atomic layer deposition system through after the standard cleaning with it, with trimethyl aluminium gas silicon chip surface is modified processing then, and the time is 60 minutes, and temperature is 300 ℃.Then use the method growth Al of atomic layer deposition
2O
3Nano thin-film is as tunnel layer, Al
2O
3Thickness is 9 nanometers.Then, the ruthenium metal film of magnetron sputtering 2 nanometer thickness on tunnel layer, 800 ℃ of following rapid thermal annealings 30 seconds in the mixed atmosphere of nitrogen and trace oxygen then are to form ruthenium, ruthenium-oxide mixed nano-crystal.And then at mixed nano-crystal/Al
2O
3On the Al of atomic layer deposition 18 nanometer thickness again
2O
3Film serves as the barrier layer, and 800 ℃ of following ANs 30 seconds.At last, at Al
2O
3Form electrode pattern by the standard photoetching on the barrier layer, the electron beam evaporation growth thickness is the palladium film of 50 nanometers under high vacuum, and the back is removed the residue photoresist with acetone and formed gate electrode.The measurement of device performance for convenience, with the natural oxidizing layer of hydrofluoric acid removal substrate back, the aluminium lamination of deposit layer of metal then is as bottom electrode, to form good Ohmic contact earlier.For the ease of comparing, this example has also been made the single Al of no nanometer crystal layer
2O
3The electric capacity of medium, wherein Al
2O
3Thickness be 27 nanometers, electrode preparation is same as described above.In the present embodiment 1, deposit Al
2O
3Reaction source be trimethyl aluminium and water vapour, underlayer temperature is 300 ℃.
Electric capacity-voltage (C-V) curve that Fig. 2 (a) is obtained when different voltage scan range and scanning direction under 1MHz for the storage capacitance in this example.The result shows that along with the increase of scanning voltage scope, C-V hysteresis window also constantly increases, and reflects effective storage characteristics.+ 8V～-8V scanning voltage scope in gained C-V hysteresis window be 7.8V.On the contrary, if adopt single Al
2O
3Dielectric layer does not promptly contain nanocrystallinely, does not then observe C-V hysteresis window basically, shown in Fig. 2 (b).This shows ruthenium and ruthenium-oxide mixed nano-crystal stored charge very effectively.Along with maximum scan voltage increase further to+/-11V, the C-V hysteresis window of above-mentioned mixed nano-crystal storage capacitance increases to 11.2V, shows as Fig. 3.This shows that this mixed nano-crystal has very high electric charge capture center, can store a large amount of electric charges.
Fig. 4 is the C-V curve of made storage capacitance under programming and erase status in this example, as can be seen, programmes under the condition of 8V and 100 microseconds, and the skew of gained flat band voltage is+2V; Under the condition of-8V and 100 microseconds, wipe, gained flat band voltage skew-2.2V, so memory window reaches 4.2V.Further, if shorten programming and erasing time to 10 microseconds, its memory window also can reach 2.5V.This has shown that memory capacitor structure of the present invention can be programmed effectively, also can be wiped effectively, and has very fast erasable speed.
Fig. 5 for made storage capacitance in this example+8V, 1 millisecond of programming and-charge-retention property after 8V, 1 millisecond wipe, the result shows and is extrapolated to 10 years that the memory window of this structure demonstrates the excellent electric charge retention performance still up to 5.5V.
In a word, good characteristics such as the memory capacitor structure that this invention proposed has programming and erasing characteristic is good, charge retention time length have good application prospects on flash memory.
Claims (4)
1. the electric capacity of a mixed nano-crystal memory is substrate layer with the p type single crystal silicon sheet, it is characterized in that on it being in regular turn:
1) Al that grows by the atomic layer deposition method
2O
3Nano thin-film, as the electric charge tunnel layer, film thickness is 5～10 nanometers;
2) be ruthenium and the ruthenium-oxide mixed nano-crystal layer that the ruthenium layer of 1-4 nanometer forms by original depth;
3) Al that grows by the atomic layer deposition method
2O
3Film, film thickness are 15～40 nanometers, carry out high-temperature heat treatment after, as the barrier layer;
4) gate electrode layer that is formed by the lift-off method, gate electrode layer thickness are 50～200 nanometers, and material is a Metal Palladium.
2. the electric capacity of mixed nano-crystal memory according to claim 1, it is characterized in that: described ruthenium and ruthenium-oxide mixed nano-crystal layer are the ruthenium layers by magnetron sputtering one deck 1-4 nanometer thickness, and under 600-900 ℃ the temperature in the mixed atmosphere of nitrogen and trace oxygen rapid thermal annealing 10-30 form after second.
3. the electric capacity of mixed nano-crystal memory according to claim 1 is characterized in that: described Al
2O
3Film barrier layer is to adopt atomic layer deposition method deposition, carries out rapid thermal annealing 10-30 after the deposit in the nitrogen and form after second under 600-800 ℃ temperature.
4. the preparation method of the electric capacity of mixed nano-crystal memory according to claim 1 is characterized in that concrete steps are as follows:
1) adopts the p type single crystal silicon sheet as substrate, at first, silicon chip is cleaned, remove residual natural oxidizing layer with diluted hydrofluoric acid;
2) form the electric charge tunnel layer: the method growth Al that adopts atomic layer deposition
2O
3Film is controlled underlayer temperature in 250-350 ℃ of scope, Al during precipitation
2O
3Reaction source select trimethyl aluminium and water vapour, Al for use
2O
3Thickness is the 5-10 nanometer;
3) form the mixed nano-crystal layer: adopt the method deposit super thin metal ruthenium layer of magnetron sputtering, the thickness of ruthenium layer is the 1-4 nanometer, carries out rapid thermal annealing then in nitrogen and trace oxygen, form ruthenium, ruthenium-oxide mixed nano-crystal, wherein, annealing temperature is 600-900 ℃, and the time is 10-30 second;
4) form the barrier layer: the method that adopts atomic layer deposition is at mixed nano-crystal/Al
2O
3The long Al of surface regeneration
2O
3Film, as the barrier layer, thickness is the 15-40 nanometer; The control underlayer temperature is controlled at 250-350 ℃, Al during precipitation
2O
3Reaction source select trimethyl aluminium and water vapour for use;
5) form gate electrode: adopt " lift-off " method to form electrode, promptly at first on photoresist, form gate patterns by photoetching, then adopting the electron beam evaporation growth thickness is the palladium layer of 50-200 nanometer, last, cleans remaining photoresist to form gate electrode through acetone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101963000A CN101692463B (en) | 2009-09-24 | 2009-09-24 | Capacitor structure of mixed nano-crystal memory and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101963000A CN101692463B (en) | 2009-09-24 | 2009-09-24 | Capacitor structure of mixed nano-crystal memory and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101692463A CN101692463A (en) | 2010-04-07 |
| CN101692463B true CN101692463B (en) | 2011-12-14 |
Family
ID=42081133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101963000A Expired - Fee Related CN101692463B (en) | 2009-09-24 | 2009-09-24 | Capacitor structure of mixed nano-crystal memory and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101692463B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887910A (en) * | 2010-06-03 | 2010-11-17 | 复旦大学 | Gate stack structure for semiconductor flash memory device and preparation method thereof |
| CN101916825B (en) * | 2010-08-02 | 2012-08-01 | 复旦大学 | Polymer matrix nano-crystalline memory capacitor and manufacturing method thereof |
| CN107768380B (en) * | 2017-09-01 | 2020-01-14 | 河北大学 | Embedded charge trapping memory and preparation method thereof |
| CN109037220A (en) * | 2018-06-25 | 2018-12-18 | 浙江师范大学 | A kind of method of low temperature preparation tin nano-crystal memory |
| CN109728096B (en) * | 2018-12-20 | 2020-08-04 | 西安电子科技大学 | Ferroelectric field effect transistor based on aluminum oxide material embedded nanocrystalline and preparation method thereof |
| CN110957377B (en) * | 2019-12-16 | 2021-05-28 | 南京大学 | Memory container based on MOS (metal oxide semiconductor) transistor and preparation method thereof |
| KR102370705B1 (en) * | 2020-06-30 | 2022-03-04 | 고려대학교 산학협력단 | Ruthenium-based nanowire and manufacturing method thereof |
| CN112908999A (en) * | 2021-03-25 | 2021-06-04 | 复旦大学 | Manufacturing process of semi-floating gate memory and semi-floating gate memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101060077A (en) * | 2007-05-17 | 2007-10-24 | 复旦大学 | Manufacture method of HD Ru nanocrystalline atomic layer deposition for flash memory |
| CN101060078A (en) * | 2007-05-17 | 2007-10-24 | 复旦大学 | Manufacture method of HD Ru nanocrystalline sputtering deposition for flash memory |
| CN101388397A (en) * | 2008-10-23 | 2009-03-18 | 复旦大学 | Low-voltage erasable nano-crystal storage capacitor construction and preparation thereof |
-
2009
- 2009-09-24 CN CN2009101963000A patent/CN101692463B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101060077A (en) * | 2007-05-17 | 2007-10-24 | 复旦大学 | Manufacture method of HD Ru nanocrystalline atomic layer deposition for flash memory |
| CN101060078A (en) * | 2007-05-17 | 2007-10-24 | 复旦大学 | Manufacture method of HD Ru nanocrystalline sputtering deposition for flash memory |
| CN101388397A (en) * | 2008-10-23 | 2009-03-18 | 复旦大学 | Low-voltage erasable nano-crystal storage capacitor construction and preparation thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101692463A (en) | 2010-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101692463B (en) | Capacitor structure of mixed nano-crystal memory and preparation method thereof | |
| CN102208442B (en) | Gate stack structure suitable for semiconductor flash memory device and manufacturing method of gate stack structure | |
| Kossar et al. | Ferroelectric polarization induced memristive behavior in bismuth ferrite (BiFeO3) based memory devices | |
| CN102231365B (en) | Preparation method of non-volatile charge storage device, non-volatile charge storage device and application of device | |
| CN105206615A (en) | High-dielectric-coefficient composite oxide charge storage medium thin film and application | |
| Lu et al. | Nanocrystalline silicon embedded zirconium-doped hafnium oxide high-k memory device | |
| CN100590101C (en) | Hafnium oxide doping cerium oxide grid dielectric material and preparation method thereof | |
| CN101388397A (en) | Low-voltage erasable nano-crystal storage capacitor construction and preparation thereof | |
| CN104882490B (en) | A kind of preparation method of the floating-gate memory based on metal hetero quntum point | |
| CN110459611B (en) | Ferroelectric field effect transistor and preparation method thereof | |
| WO2012142804A1 (en) | Non-volatile charge capture storage device, method for preparing same and application thereof | |
| CN100477095C (en) | Manufacture method of sputtering deposition of high-density Ru nanocrystalline for flash memory | |
| Choi et al. | Bi modification for low-temperature processing of YMnO3 thin films | |
| CN113363384B (en) | HfO 2 Ferroelectric tunnel junction device and method for manufacturing the same | |
| CN101864556A (en) | High dielectric coefficient titanium-aluminum oxide film and preparation method and application thereof | |
| Lin et al. | Embedding of Nanocrystalline Ruthenium in ZrHfO High-k Film for Nonvolatile Memories | |
| CN112820826B (en) | MXene/MoSe2/PMMA/MXene structure-based nonvolatile memory device | |
| Kang et al. | Effect of nitrogen plasma treatment on electrical characteristics for Pd nanocrystals in nonvolatile memory | |
| Wang et al. | Characteristics of Ag/Bi 3.25 La 0.75 Ti 3 O 12/p-Si heterostructure prepared by sol-gel processing | |
| CN110047842A (en) | A kind of silicon substrate charge trapping memory part and preparation method | |
| CN116634774A (en) | Based on Al 2 O 3 /Hf x Zr 1-x O 2 /Al 2 O 3 Structured charge storage device and method of making same | |
| CN100583400C (en) | Preparation method of non-volatile memory | |
| Lee et al. | Fabrication and memory effect of Zr nanocrystals embedded in ZrO2 dielectric layer | |
| CN116406225A (en) | Ferroelectric tunneling junction memory with high-uniformity floating gate structure and preparation method thereof | |
| Seo et al. | Trade-off relationship of size and density of platinum nanocrystal in nonvolatile memory characteristics |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111214 Termination date: 20140924 |
|
| EXPY | Termination of patent right or utility model |