WO2012142804A1

WO2012142804A1 - Non-volatile charge capture storage device, method for preparing same and application thereof

Info

Publication number: WO2012142804A1
Application number: PCT/CN2011/078223
Authority: WO
Inventors: 汤振杰; 夏奕东; 殷江; 刘治国
Original assignee: 南京大学
Priority date: 2011-04-22
Filing date: 2011-08-10
Publication date: 2012-10-26
Also published as: CN102208346A; CN102208346B

Abstract

A non-volatile charge capture storage device, a method for preparing the same and an application thereof. The preparation method is simple to operate and easy to control, and the nano-microcrystal acting as a storage medium in the obtained storage device is evenly distributed. The preparation method includes the steps of: a) forming a tunneling layer on the substrate surface; b) forming a (ZrO₂)_x(M)_1-x thin film with homogeneous composition acting as a storage layer on the tunneling layer, wherein l > x > 0.5, M is SiO₂ or Al₂O₃; c) forming a barrier layer on the storage layer; d) and annealing the above prepared sample so as to precipitate the nano-microcrystal ZrO₂ from the storage layer to act as the storage medium. By way of high temperature annealing processing, the nano-microcrystal ZrO₂ is precipitated from the parent phase of the storage layer, thereby realizing the effect of nano-microcrystal storage. The nano-microcrystal acting as the storage medium obtained in the method is evenly distributed in the non-crystal parent phase.

Description

TECHNICAL FIELD The present invention relates to a nonvolatile charge trap type memory device, a method of fabricating the same, and an application thereof. BACKGROUND OF THE INVENTION For decades, the development of integrated circuits has largely followed Moore's Law, which was predicted by Dr. Gordon E. Moore, one of the founders of Intel Corporation, in 1964: the number of components integrated on a single chip of an integrated circuit, that is, the integration of integrated circuits. Every 12 to

Doubled in 18 months, the feature size is reduced by a factor of two. As floating features of devices become smaller and smaller, conventional floating gate type nonvolatile semiconductor memory devices face serious leakage problems. The size of the tunneling layer in the floating gate type memory device is continuously reduced, so that a defect causes a total loss of the charge stored in the polysilicon floating gate. In order to solve this problem, polycrystalline silicon-oxide-nitride-oxide-silicon (SONOS) type semiconductor memory devices have been extensively studied. In such devices, electrons are trapped by discrete traps in the Si ₃ N ₄ storage layer for storage. Since these traps are separated from each other, defects in the tunneling layer cannot leak all of the stored electrons, and the holding performance of the device is improved, thereby overcoming the drawbacks of the conventional floating gate type memory device. In recent years, the use of nanocrystallites as charge storage media has become a research hotspot. However, many researchers spend most of their energy in the preparation of metal nanocrystallites and semiconductor nanocrystallite memory devices, with less research on other forms of nanocrystallites.

In recent years, high dielectric constant materials have been widely studied as CMOS process gate dielectric layers, and pseudo-diode oxides are also a hot research topic. The dielectric properties are improved by mixing two high dielectric constant materials. Based on this idea, it is possible to mix one of the two high dielectric constant materials with different crystallization temperatures to benefit the difference in crystallization temperature. One of the materials is crystallized by high temperature annealing, and the other material remains non-ferrous. In the crystalline state, the crystallized nanocrystallites are surrounded by an amorphous matrix phase. By combining this process characteristic with the traditional SONOS-type semiconductor charge storage process, a nano-crystal-based charge trapping memory device with high dielectric constant material is realized. On the other hand, compared to Si0 ₂ , A1 ₂ 0 ₃ has a high dielectric constant (9) and a wide forbidden band width (8.8 eV), so A1 ₂ 0 _{3 is} used as a tunneling layer and a barrier layer instead of the conventional device. Si0 ₂ can reduce leakage current and improve device storage performance. Zr0 ₂ has proven to have the potential to replace sio ₂ as a gate dielectric material as a high dielectric constant material. At the same time, the crystallization temperature is relatively lower than the crystallization temperatures above sio ₂ and AI ₂ O ₃ loocrc.

As the main preparation method in the film growth process, pulsed laser deposition (PLD) and atomic layer chemical vapor deposition (ALD) not only play a key role in the growth of the film, but also play a decisive role in the performance of the device. The pulsed laser deposition method is a new type of thin film preparation technology developed in the late 1980s. The basic principle is to use a UV pulsed laser that is focused and has a high energy flow density to illuminate the target, generate a laser plasma, and finally on the substrate. The film is deposited on the film. The biggest advantage is that the chemical composition of the membrane is close to the chemical composition of the target, so that it is easy to obtain a membrane with tightly controlled composition. It is particularly suitable for the preparation of high melting point, multi-component oxide films and heterostructures. Atomic layer chemical vapor deposition (ALD) is a challenging preparation technique in the field of high-fc material preparation. The principle is to realize the layer by layer growth by the self-saturation of the gas phase source adsorbing or reacting on the surface of the substrate, and the thickness of the formed film does not depend on the substrate temperature, vapor pressure, source flow and other growth parameters in the working window. , only related to the number of cycles. Due to its unique self-limiting growth process, Atomic Layer Deposition Film has the advantages of precise thickness control, excellent three-dimensional conformability and large-area film formation uniformity, and has unique advantages in the preparation of ultra-thin films and nanostructures. SUMMARY OF THE INVENTION The present invention provides a method for fabricating a nonvolatile charge trap type memory device which is simple in operation and easy to control, and has a uniform distribution of nanocrystallites as a storage medium.

The present invention also provides a nonvolatile charge trap type memory device obtained by the above production method.

The present invention also provides the use of the above-described preparation method for a nonvolatile charge trap type memory device in an information storage and nonvolatile semiconductor memory device.

The method for preparing the nonvolatile charge trap type memory device includes the following steps:

a) forming a tunneling layer on the surface of the substrate;

b) forming a uniform composition (ZrCK Mh— _x film as a memory layer on the tunneling layer, wherein l>x>0.5, the M is Si0 ₂ or A1 ₂ 0 ₃ , preferably 0.6×0.9, further preferably 0.7×0.9 .

c) forming a barrier layer on the storage layer;

d) The sample prepared above is annealed at a temperature lower than the melting point of M, and Zr0 ₂ nanocrystallites are precipitated from the storage layer and surrounded by an amorphous mother phase, and the ZrO ₂ nanocrystallite is used as a storage medium.

The invention is based on the difference in crystallization temperature of the two substances in the mixture, and the supersaturated component in the mixture is crystallized by means of high temperature annealing treatment, that is, Zr0 ₂ nanocrystallites are precipitated from the mother layer of the storage layer, and are amorphous mother phase. Surrounded by, thereby achieving the effect of nanocrystal storage. The nanocrystallites obtained as a storage medium by this method are uniformly distributed in the amorphous mother phase. Obviously, this would result in a composition of the final amorphous mother phase that is different from the memory layer film originally formed on the tunneling layer, but the overall composition of the memory layer does not change. As a common sense, in order to avoid adverse effects on the device structure, the annealing time should be limited. Preferably, the annealing time in step d) is 10~60s. The annealing atmosphere is prior art, either an oxygen atmosphere or a nitrogen atmosphere. Those skilled in the art can select suitable annealing conditions according to the specific conditions.

The method of forming a ZrCK Mh- _x film on the tunneling layer is preferably: (ZrC^MMh- _x is used as a target, and is deposited by a pulsed laser deposition method on the tunneling layer (ZrCK M^ _x film. Pulsed laser deposition conditions) Preferably, the energy is 150-400 mJ, and the frequency is l~10 Hz. (The preparation method of the ZrC^Mh- _x target adopts the prior art, for example, the Zr0 ₂ and the SiO ₂ (or Zr0 ₂ and A1 ₂ 0 ₃ ) powders are uniformly mixed. Then, it is pressed into a wafer under a pressure of 10 to 15 MPa, and finally fired at 125 CTC for 6 hours to prepare (ZrC^MMh- _x ceramic target. As a prior art, usually for Zr0 ₂ and Si0 ₂ (or Zr0) ₂ and A1 ₂ 0 ₃ ) powder Mix well, wet grinding in a ball mill, then dry the powder before pressing the wafer.

Preferably, the tunneling layer and the barrier layer are both A1 ₂ 0 ₃ , and further preferably, the tunneling layer, the storage layer and the barrier layer have thicknesses of 2 to 4 nm, 5 nm, and 7 to 12 nm, respectively. The substrate is preferably Si.

Of course, the present invention should also deposit a known material such as platinum, aluminum, TaN or Hf as an upper electrode on the barrier layer. The nonvolatile charge trap type memory device obtained by the above preparation method comprises a tunneling layer, a memory layer and a barrier layer which are sequentially connected, and the Zr0 ₂ nanocrystallite obtained by annealing treatment is used (ZrCK SiO^ _-x is a storage layer) The role of the storage medium. The structure is shown in Figure 1.

The application of the above non-volatile charge trap type memory device in the information storage and non-volatile semiconductor memory device is as shown in FIG. 2:

a) When the platinum electrode is applied with a positive voltage relative to the Si substrate, the electric field is directed from the upper electrode to the substrate. As the applied voltage increases, the electric field strength increases. The surface of the Si substrate reaches an inversion, forms a surface electron channel, and tunnels through the A1 ₂ 0 ₃ tunneling layer under the electric field to enter the (ZrC^Mh- _x memory layer, and then the electrons on the surface of the Zr0 ₂ nanocrystallite The trap state captures the effect of storage, which is the writing process of the nonvolatile charge trap type memory device.

c) When the power is turned off, the electrons are stored in the Zr0 ₂ nm crystallite without leaking, thus functioning as a charge storage.

d) When the platinum electrode is applied with a negative voltage relative to the Si substrate, the electric field is directed from the substrate to the upper electrode. The electrons stored in the Zr0 ₂ nanocrystallites return to the substrate through the tunneling layer under the action of the electric field force, thereby realizing the erasing operation of the device.

The invention has the following beneficial effects:

a) The device structure can achieve a large amount of stored information. Figure 3 shows that when the scan voltage is ±1V, the memory window is 0.3V. When the scan voltage is ±5V and ±14V, there are already obvious hysteresis windows, which are 4.0V and 7.5V, respectively.

b) Figure 4 shows that the device after annealing has a large memory window compared to before annealing, indicating that Zr0 ₂ nanocrystallites play a crucial role in the memory performance of the device. Zr0 ₂ nanocrystallites increase the density of trap states in the film, allowing the device to have a high charge storage.

c) As can be seen from Figure 5, as the test temperature increases, the amount of charge loss of the device increases; and the charge loss of the device after 10 ⁵ erase writes is large. However, at 15 CTC (test time is 4x10 ⁴ ), the charge loss of the Zr0 ₂ nm microcrystalline based nonvolatile charge trap type memory device after 10 ⁵ erase writes is only 12%.

d) Figure 6 is: Anti-fatigue properties of Zr0 ₂ nm microcrystalline based nonvolatile charge trap type memory devices at different temperatures. As can be seen from the figure, as the temperature increases, the fatigue resistance of the device decreases slightly. At 15 CTC, the memory window is only reduced by 0.15V. It is shown that Zr0 ₂ nanocrystallites can be used as a storage medium to significantly improve the fatigue resistance of the device. DRAWINGS Figure 1: High resolution projection electron micrograph of a Zr0 ₂ nanocrystallite nonvolatile charge trap type memory device. Figure 2: Schematic diagram of the structure and principle of a Zr0 ₂ nanocrystalline microcrystalline nonvolatile charge trap type memory device. Wherein, A1 ₂ 0 ₃ adjacent to the Si sinking bottom serves as a tunneling layer, and A1 ₂ 0 ₃ of the platinum electrode is used as a barrier layer, and (Zr0 ₂ ) _x (Si0 ₂ )!. _{x is} used as a storage layer, and Zr0 ₂ obtained by annealing treatment is obtained. Nanocrystallites act as a storage medium.

Figure 3: Capacitance-voltage characteristics of Zr0 ₂ nm microcrystalline based nonvolatile charge trap type memory devices at different scan voltages at high frequencies (1 MHz). The X axis represents the voltage applied to the platinum electrode (in volts) and the y axis represents the normalized storage capacitor.

Figure 4: Device memory window before and after annealing as the scan voltage of the platinum electrode changes. The X-axis represents the scan voltage (in volts) applied to the platinum electrode and the y-axis represents the memory window (in volts).

Figure 5: Maintainability of Zr0 ₂ nm microcrystalline based non-volatile charge trapping memory devices at different test temperatures. The X axis represents the hold time (in seconds) and the y axis represents the amount of charge loss. In the figure, the hollow curve is a device that has not undergone 10 ⁵ write/erase operations; the solid curve is a device subjected to 10 ⁵ write/erase operations. Figure 6: Fatigue resistance of ZrO A-meter microcrystalline based nonvolatile charge trap type memory devices. The X axis represents the number of write/erase times, and the y axis represents the flat band voltage (in volts). In the figure, the hollow curve is an erase operation; the solid curve is a write operation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 : Based on a Si substrate, a preparation process of a Zr0 ₂ nanocrystal-based nonvolatile charge trap type memory device is as follows:

(a) The Si substrate was placed in an appropriate amount of acetone, ultrasonically cleaned, and ultrasonically cleaned with deionized water to rinse off impurities remaining on the surface of the substrate. The substrate is then immersed in hydrofluoric acid to remove surface oxides, ultrasonically cleaned with deionized water, blown dry with high purity nitrogen, and placed in an atomic layer chemical vapor deposition chamber for deposition of the film.

(b) A1(CH ₃ ) _{3 is} used as the metal source during the deposition process, and ozone is the oxygen source. A1(CH ₃ ) ₃ enters the cavity with nitrogen, reacts with the surface of the silicon substrate at the hydroxyl end and saturates, and then the oxygen source is brought into the cavity by nitrogen to form a surface reaction with the metal source to form A1 ₂ 0 ₃ to form a tunneling layer. By controlling the atomic layer deposition cycle coefficient, A1 ₂ 0 _{3 with} a thickness of 3 nm is deposited as a tunneling layer.

(c) When the tunneling layer is deposited, the sample is placed in a pulsed laser deposition chamber, and the prepared (ZrC^WSiO^ _-x target is deposited on the surface of the sample (ZrC^SiO^ _-x film for storage). The layer has a thickness of 5 nm, wherein x = 0.8. The (Zr0 ₂ ) _x (Si0 ₂ ) i_ _x target is prepared by mixing Zr0 ₂ and SiO ₂ powders in a molar ratio; and then in a planetary ball mill. After wet grinding for 12 hours, the powder is dried, and then pressed into a wafer having a thickness of 5 mm and a diameter of 20 mm under a pressure of 10 to 15 MPa, and finally fired at 125 CTC for 6 hours to prepare (ZrC^MSiO^ _-x ceramic). Target.

(d ZrCK SiO ^ - _x end the storage layer deposition, depositing a 7 nm thick dielectric layer of A1 ₂ 0 ₃ on its surface, as a barrier layer, is formed during step (b). (e) After the above preparation process, the device was placed in a rapid annealing furnace and annealed at 800 ° C for 30 seconds in an oxygen atmosphere.

(f) Platinum (Pt) was used as the upper electrode and deposited on the annealed device by magnetron sputtering. A layer of conductive silver paste is applied as a lower electrode on the side of the Si sinker. The storage window and retention performance of the Zr0 ₂ nanocrystallite nonvolatile charge trap type memory device were measured using a Keithley 4200 semiconductor parameter analyzer. In the case of high-frequency scanning, the upper electrode is connected to a positive voltage, and the lower electrode is connected to a negative voltage. During the scanning process, electrons enter the storage layer under the action of an electric field and are captured by the Zr0 ₂ nanocrystallite, which is equivalent to a writing operation; The voltage and the lower electrode are connected to a positive voltage. During the scanning process, the electrons trapped by the Zr0 ₂ nanocrystallite return to the substrate under the action of the electric field force, which is equivalent to the erasing operation.

The test method for maintaining performance is as follows: A voltage pulse of 10 V, lms is applied to the upper electrode, and electrons enter the storage layer under the action of an electric field and are captured by the Zr0 ₂ nanocrystallite. The amount of charge loss after different times was tested to obtain the amount of charge loss at different retention times.

The test method for the fatigue resistance of the device is as follows: First, a voltage pulse of 10 V, lms is applied to the upper electrode, and electrons enter the storage layer under the action of an electric field and are captured by the Zr0 ₂ nanocrystallite. A voltage pulse of -10 V, lms is then applied to the upper electrode, and the electrons return to the substrate under the action of an electric field. This is repeated 10 ⁵ times.

The test results are shown in Figure 3-6.

Claims

Claim

A method of fabricating a nonvolatile charge trap type memory device, comprising the steps of: a) forming a tunneling layer on a surface of a substrate;

b) forming a uniform composition (ZrCK Mh- _x film as a storage layer, wherein l>x>0.5, the M is Si0 ₂ or A1 ₂ 0 _3;

c) forming a barrier layer on the storage layer;

2. The method of preparing a nonvolatile charge trap type memory device according to claim 1, which is characterized by 0.6 x 0.9.

3. A method of fabricating a nonvolatile charge trap type memory device according to claim 2, wherein x = 0.8.

The method of producing a nonvolatile charge trap type memory device according to any one of claims 1 to 3, wherein the M is Si0 ₂ .

The method of fabricating a nonvolatile charge trap type memory device according to any one of claims 1 to 3, wherein the annealing time in the step d) is 10 to 60 s.

The method of manufacturing a nonvolatile charge trap type memory device according to any one of claims 1 to 3, wherein the tunneling layer and the barrier layer are both A1 ₂ 0 ₃ .

7. The method of fabricating a nonvolatile charge trap type memory device according to claim 6, wherein the tunneling layer, the memory layer, and the barrier layer have thicknesses of 2 to 4 nm, 5 to 8 nm, and 7 to 5, respectively. 12nm.

The method of fabricating a nonvolatile charge trap type memory device according to any one of claims 1 to 3, wherein the method of forming a ZrCK Mh- _x film on the tunneling layer is: (ZrCK) Mh- _x is a target and is deposited on the tunneling layer by pulsed laser deposition (ZrCK Mh- _x film).

9. The nonvolatile charge trap type memory device obtained by the preparation method according to any one of claims 1-8.

The use of the nonvolatile charge trap type memory device obtained by the preparation method according to any one of claims 1 to 8 in information storage and non-volatile semiconductor memory devices.