CN112908999A - Manufacturing process of semi-floating gate memory and semi-floating gate memory - Google Patents
Manufacturing process of semi-floating gate memory and semi-floating gate memory Download PDFInfo
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
The invention provides a manufacturing process of a semi-floating gate memory, which comprises the following steps: providing a substrate; generating a tunneling layer and a first semiconductor on the upper surface of a substrate, wherein the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor is parallel to the tunneling layer and forms a diode structure with the substrate; and metal nanocrystals are arranged on the first semiconductor at intervals. According to the invention, the first semiconductor and the substrate form a diode structure, when the diode structure is conducted, the functions of fast data writing and storage are realized, and due to the performance of the diode structure and the tunneling layer, charges in the metal nano-crystal are not easy to flow back to the substrate, so that the storage time is prolonged. Most importantly, the metal nanocrystals are arranged at intervals so that charges at other positions can still be fixed in the metal nanocrystals when leakage occurs, the charge retention capability is effectively enhanced, and the refreshing time of the memory is prolonged. In addition, the invention also provides a semi-floating gate memory.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a manufacturing process of a semi-floating gate memory and the semi-floating gate memory.
Background
Today's mainstream storage technologies fall into two categories: volatile memory technology and non-volatile memory technology.
The volatile Memory technology is mainly Static Random-Access Memory (SRAM) and dynamic Random Access Memory (dram). The volatile memory has a nanometer writing speed, but the data retention capacity is only in millisecond level, so that the volatile memory can be only used in limited storage fields such as cache and the like.
For non-volatile memory technologies, such as flash memory technology, the data retention capacity can reach 10 years, however, the relatively slow write operation greatly limits the application of the technology in the cache field. Therefore, in this context, a semi-floating gate memory based on two-dimensional semiconductor material has been developed, which uses van der waals heterojunction as an electronic switch for charge storage, greatly improving the charge writing speed and data refresh time. However, in the semi-floating gate memory, the main constituent materials are two-dimensional semiconductors, and the semi-floating gate memory is formed by mechanical stripping, which is a low-throughput method, that is, it is difficult to prepare a large-area semi-floating gate memory, and the mechanical stripping process is not compatible with integrated circuit processes.
Chinese patent publication No. CN 104465381B discloses a manufacturing process of a planar-channel semi-floating gate device, which is to prepare a planar-channel semi-floating gate device by using a gate-last process, after forming a source contact region and a drain contact region, first etch away a polysilicon control gate sacrificial material, then make the metal control gate material occupy the position of the original polysilicon control gate sacrificial material to form a metal control gate, which can prevent the metal control gate from being damaged in the high-temperature annealing process of the source contact region and the drain contact region, thereby improving the performance of the planar-channel semi-floating gate device. However, there is no mention of a semi-floating gate memory capable of increasing data writing speed and data retention time.
Therefore, it is necessary to provide a semi-floating gate memory and a manufacturing process thereof, which solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a manufacturing process of a semi-floating gate memory and the semi-floating gate memory, which can increase the data writing speed, increase the data storage time, enhance the charge storage capacity and increase the refreshing time of the memory.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a manufacturing process of a semi-floating gate memory comprises the following steps:
s01: providing a substrate;
s02: generating a tunneling layer and a first semiconductor on the upper surface of the substrate, wherein the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor is parallel to the tunneling layer and forms a diode structure with the substrate;
s03: and metal nanocrystals are arranged on the first semiconductor at intervals.
The manufacturing process of the semi-floating gate memory provided by the invention has the beneficial effects that: the first semiconductor and the substrate form the diode structure, when the diode structure is conducted, most of charges can flow into the metal nanocrystalline through the diode structure quickly, so that the quick data writing and storing functions are realized, and due to the performance of the diode structure and the tunneling layer, the charges in the metal nanocrystalline are not easy to flow back to the substrate, so that the storing time is prolonged. Most importantly, the metal nanocrystals are arranged at intervals, so that charges at other positions can still be fixed in the metal nanocrystals when leakage occurs, the charge retention capability is effectively enhanced, the refreshing time of the memory is increased, and in addition, the manufacturing process of the semi-floating gate memory is simple, large-area production can be realized, and the manufacturing process is compatible with the existing integrated circuit manufacturing process.
Preferably, the method further comprises a step S04, wherein the step S04 comprises: sequentially arranging a barrier layer and a grid electrode on the metal nanocrystalline, wherein the barrier layer covers the metal nanocrystalline and fills gaps formed between the adjacent metal nanocrystalline; the tunneling layer, the first semiconductor, the metal nanocrystalline, the blocking layer and the grid are sequentially stacked on the upper surface of the substrate to form a stacked structure, and the stacked structure is combined with the substrate to form a convex structure. The beneficial effects are that: the barrier layer separates the metal nanocrystals, so that charges at other positions can still be fixed in the metal nanocrystals when leakage occurs at a certain position, the charge retention capability is effectively enhanced, the refreshing time of the memory is increased, and the compatibility of the manufacturing process and the manufacturing process of the integrated circuit is realized.
Preferably, the step S04 further includes: and side walls are respectively arranged on two sides of the laminated structure, the side walls are respectively connected with two sides of the laminated structure, and one end of each side wall is arranged on the substrate.
Preferably, the sidewall, the gate and the substrate are combined to form a cavity, and the blocking layer, the semi-floating gate, the tunneling layer and the first semiconductor are all located in the cavity. The beneficial effects are that: the internal structure can be effectively protected by forming the cavity, and the performance of the whole structure is improved.
Preferably, ions are implanted into the two side edges of the substrate and the lower ends of the side walls to form a source region and a drain region, and the source region and the drain region are respectively abutted to the side walls on the two sides. The beneficial effects are that: the source region and the drain region are formed by implanting ions at two side edges of the substrate and at the lower end of the side wall, so that the space occupied by the source region and the drain region is reduced, and the structure is more compact.
A semi-floating gate memory, comprising:
a substrate;
the tunneling layer is arranged on the upper surface of the substrate;
the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor and the substrate form a diode structure;
and the metal nanocrystals are arranged at intervals on the first semiconductor.
The semi-floating gate memory provided by the invention has the beneficial effects that: the first semiconductor and the substrate form a diode structure, so that when the diode structure is conducted, the charge can rapidly flow into the metal nanocrystalline to be stored, and due to the performance of the diode structure and the tunneling layer, the charge in the metal nanocrystalline is not easy to flow back to the substrate, so that the storage time is prolonged.
Preferably, the device further comprises a barrier layer, a gate and a side wall;
the barrier layer covers the metal nanocrystals and fills gaps formed by the adjacent metal nanocrystals, the gate covers the barrier layer, the gate, the barrier layer, the metal nanocrystals, the first semiconductor and the tunneling layer are sequentially stacked on the substrate to form a stacked structure, and the stacked structure is combined with the substrate to form a convex structure;
the side walls are arranged on two sides of the laminated structure and are respectively connected with two sides of the laminated structure, and one end of each side wall is arranged on the substrate. The beneficial effects are that: simple structure, easy shrink makes the further improvement of integrated density.
Preferably, the side wall, the gate and the substrate are combined to form a cavity, and the blocking layer, the metal nanocrystal, the tunneling layer and the first semiconductor are all located in the cavity. The beneficial effects are that: the internal structure can be effectively protected by forming the cavity, and the performance of the whole structure is improved.
Preferably, the semiconductor device further comprises a source region and a drain region, wherein the source region and the drain region are both arranged on the substrate, and the source region and the drain region are respectively abutted against the side walls on two sides. The beneficial effects are that: the source region and the drain region are arranged on the substrate and are abutted to the side walls, so that the space occupied by the source region and the drain region is reduced, and the structure is simpler and more compact.
Preferably, the material of the substrate comprises a first conductive material, the material of the first semiconductor comprises a second conductive material, and the first conductive material and the second conductive material have opposite conductivity types. The beneficial effects are that: the substrate and the first semiconductor form a diode structure, so that charges flow into the semi-floating gate through the diode structure, and the semi-floating gate memory which can be stored quickly and has long data storage time is obtained through the mode of arrangement in sequence.
Drawings
FIG. 1 is a flow chart of the manufacturing process of the semi-floating gate memory of the present invention;
FIG. 2 is a schematic structural diagram of a semi-floating gate memory device according to the present invention, wherein a tunneling layer is disposed on a substrate and a portion of the substrate is exposed;
FIG. 3 is a schematic structural diagram of a semi-floating gate memory formed after a semiconductor material is disposed in a manufacturing process of the semi-floating gate memory according to the present invention;
FIG. 4 is a schematic structural diagram of a semi-floating gate memory according to the present invention after a metal nanocrystal array is disposed in the manufacturing process;
FIG. 5 is a schematic structural diagram of a semi-floating gate memory formed after a barrier layer and a gate are prepared in the manufacturing process of the semi-floating gate memory according to the present invention;
FIG. 6 is a schematic diagram of a stacked structure formed in the manufacturing process of the semi-floating gate memory according to the present invention;
FIG. 7 is a schematic structural diagram formed after a sidewall is arranged in the manufacturing process of the semi-floating gate memory according to the present invention;
FIG. 8 is a schematic structural diagram of an embodiment of a semi-floating gate memory according to the present invention.
The reference numbers illustrate:
a substrate 100, a source region 101, a drain region 102;
a tunneling layer 200;
a semiconductor material 300, an abutting terminal 301, a covering terminal 302;
a nanocrystal 400; a barrier layer 500; a gate electrode 600; a sidewall 700.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In order to solve the problems in the prior art, an embodiment of the present invention provides a manufacturing process of a semi-floating gate memory, which is shown in fig. 1 and includes the following steps:
s01: providing a substrate;
s02: generating a tunneling layer and a first semiconductor on the upper surface of the substrate, wherein the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor is parallel to the tunneling layer and forms a diode structure with the substrate;
s03: and metal nanocrystals are arranged on the first semiconductor at intervals.
It should be noted that, in this embodiment, the substrate 100 is a p-type silicon substrate 100, and in practical applications, the substrate 100 may be made of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, or InGaSb materials. Referring to fig. 2, an insulating medium is grown on the substrate 100 as the tunneling layer 200 by an atomic deposition process to effectively block the flow of charges, and then a photoresist is used as a mask to remove a portion of the tunneling layer 200 by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, inductively coupled plasma etching, or wet etching using an etchant solution until a portion of the upper surface of the substrate 100 is exposed.
Referring to fig. 3, a layer of lightly doped semiconductor material 300 is further grown on the tunneling layer 200 and the exposed upper surface of the substrate 100 by using a chemical vapor deposition process to form the first semiconductor having the capping end 302 and the abutting end 301, in this embodiment, the lightly doped semiconductor material 300 is n-type polysilicon. So that the first semiconductor and the substrate 100 constitute a diode structure.
In this embodiment, the first semiconductor may be made of Si, Ge, SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, or InGaSb materials, as long as the conductivity type of the substrate 100 is opposite to that of the first semiconductor, and the sequentially performed preparation process may be any one of physical vapor deposition, chemical vapor deposition, or pulsed laser deposition.
Further, referring to fig. 4, a layer of gold thin film is grown on the first semiconductor by using a physical vapor deposition process, and then the gold thin film is placed in a rapid thermal annealing furnace to anneal the gold thin film, so that the gold thin film is agglomerated into gold nanocrystals 400 which are mutually dispersed, and the metal nanocrystals 400 and the first semiconductor are used as a semi-floating gate material of a memory together.
Further, in the step S04: the barrier layer 500 and the gate 600 are sequentially arranged on the metal nanocrystal 400, the gate 600, the barrier layer 500, the metal nanocrystal 400, the first semiconductor and the tunneling layer 200 are sequentially stacked on the upper surface of the substrate 100 to form a stacked structure, and the stacked structure is combined with the substrate 100 to form a convex structure.
Specifically, the barrier layer 5 is deposited on the surfaces of the first semiconductor and the metal nanocrystalline 400 by adopting an atomic layer deposition method00, the metal nanocrystal 400 is wrapped up, in this embodiment, the metal nanocrystal 400 is made of a gold nanocrystal material, and the barrier layer 500 is made of Al2O3The material is made, in practical application, the material of the metal nanocrystalline 400 may be at least one selected from Au, Pt, Pd, Ni, and the barrier layer 500 may also be SiO2、ZrO2、HfZrO、HfO2HfAlO, HfSiO, and any combination thereof. Then, the gate 600 is formed on the surface of the barrier layer 500 by using a pvd method, in this embodiment, the gate 600 is made of a TiN material, in practical applications, the gate 600 may be made of one of TiN, TaN, Ru, Co and any combination thereof, or the gate 600 may be made of heavily doped polysilicon.
Referring to fig. 5, a photoresist is spin-coated on the gate electrode 600 and is patterned into a shape for defining the stacked structure through a photolithography process of exposure and development, and then, referring to fig. 6, by dry etching: such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching using an etchant solution, the tunneling layer 200, the first semiconductor, the metal nanocrystals 400, the blocking layer 500, and the gate electrode 600 are removed from both left and right side portions, thereby forming the stacked structure.
Referring to fig. 7, the photoresist is removed by dissolving or ashing in a solvent, then a sidewall 700 material is grown on the surface of the substrate 100 and the stacked structure by using a chemical vapor deposition method, and then a portion of the sidewall 700 material is removed by using a photolithography and dry etching method, so that the sidewalls 700 are formed on both sides of the stacked structure. Referring to fig. 8, finally, ions are implanted into the two sides of the substrate 100 and the lower ends of the side walls 700 by using an ion implantation process, so that a source region and a drain region are formed at the two sides of the stacked structure as a source and a drain.
In this embodiment, Si is used3N4The sidewall 700 is formed by material preparation, but the invention is not limited thereto, and SiO may also be selected2Or SiON. It is worth to say thatWhen a negative electrode is applied to the gate 600, the diode structure formed by the substrate 100 and the first semiconductor is turned on, a large amount of positive charges rapidly flow into the first semiconductor from the substrate 100, and then a part of the positive charges flowing into the first semiconductor is captured by the metal nanocrystals 400, in this embodiment, the metal nanocrystals 400 are made of gold nanocrystals, and since the work function of the gold nanocrystals 400 is greater than that of the first semiconductor, the positive charges are equivalent to being bound in the gold nanocrystals, thereby completing the rapid storage of data. In practical applications, the metal nanocrystal 400 material may be at least one selected from Au, Pt, Pd, and Ni.
In another embodiment of the present disclosure, a semi-floating gate memory, as shown in fig. 8, includes: the tunneling layer comprises a substrate 100, a tunneling layer 200 and a first semiconductor, wherein the tunneling layer 200 is arranged on the upper surface of the substrate 100, the first semiconductor is provided with a covering end 302 and an abutting end 301 which are arranged up and down, the abutting end 301 is arranged on the upper surface of the substrate 100, and one side of the abutting end 301 abuts against the side edge of the tunneling layer 200. It is understood that the tunneling layer 200 is in contact with the side of the abutting end 301, covering the substrate 100. The cover terminal 302 covers the tunneling layer 200, the first semiconductor and the substrate 100 form a diode structure, and the metal nanocrystals 400 are arranged at intervals in an array form, cover the first semiconductor, and together serve as a semi-floating gate material of the memory.
It should be noted that, by arranging the metal nanocrystals 400 at intervals in an array, when the metal nanocrystals 400 at a certain position leak, the charges at other positions can still be fixed in the metal nanocrystals 400 at the non-leaking position, so as to effectively enhance the charge retention capability and increase the refresh time of the memory.
In addition, the first semiconductor and the substrate 100 form a diode structure, so that when the diode structure is turned on, the charges can rapidly flow into the metal nanocrystal 400 for storage, and due to the performance of the diode structure and the tunneling layer 200, the charges in the metal nanocrystal 400 are not easy to flow back to the substrate 100, thereby increasing the storage time. The substrate comprises a material comprising a first conductive material and the first semiconductor comprises a second conductive material, the first conductive material and the second conductive material being of opposite conductivity types to form, in combination, the diode structure.
Preferably, as shown in fig. 8, the semiconductor device further includes a blocking layer 500, a gate 600 and a sidewall 700, where the blocking layer 500 covers the metal nanocrystal 400, the gate 600 covers the blocking layer 500, and the gate 600, the blocking layer 500, the metal nanocrystal 400, the first semiconductor and the tunneling layer 200 are sequentially stacked on the upper surface of the substrate 100 to form a stacked structure. The laminated structure and the substrate 100 are combined to form a convex structure, the side walls 700 are arranged on two sides of the laminated structure and are respectively connected with two sides of the laminated structure, and one end of each side wall 700 is arranged on the substrate 100. The convex structure is simple in structure and easy to shrink, and the integration density is further improved.
Further preferably, as shown in fig. 8, the sidewall 700, the gate 600 and the substrate 100 are combined to form a chamber, and the blocking layer 500, the metal nanocrystal 400, the tunneling layer 200 and the first semiconductor are all disposed in the chamber. The internal structure can be effectively protected by forming the cavity, and the reliability and the safety of the whole structure are improved.
Preferably, as shown in fig. 8, the semiconductor device further includes a source region 101 and a drain region 102, where the source region 101 and the drain region 102 are both disposed on the substrate 100, the source region 101 abuts against the sidewall 700 on one side, and the drain region 102 abuts against the sidewall 700 on the other side, that is, the source region 101 is a source region portion disposed on the substrate 100, and the drain region 102 is a drain region portion disposed on the substrate 100.
The source region 101 and the drain region 102 are arranged on the upper surface of the substrate 100 and abut against the side wall 700, that is, the source region 101 and the drain region 102 are arranged at the lower end of the side wall 700, so that the space occupied by the source region 101 and the drain region 102 is reduced, and the structure is more compact and simpler.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (10)
1. A manufacturing process of a semi-floating gate memory is characterized by comprising the following steps:
s01: providing a substrate;
s02: generating a tunneling layer and a first semiconductor on the upper surface of the substrate, wherein the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor is parallel to the tunneling layer and forms a diode structure with the substrate;
s03: and metal nanocrystals are arranged on the first semiconductor at intervals.
2. The manufacturing process of the semi-floating gate memory of claim 1, wherein:
further comprising a step S04, the step S04 comprising: sequentially arranging a barrier layer and a grid electrode on the metal nanocrystalline, wherein the barrier layer covers the metal nanocrystalline and fills gaps formed between the adjacent metal nanocrystalline;
the tunneling layer, the first semiconductor, the metal nanocrystalline, the blocking layer and the grid are sequentially stacked on the upper surface of the substrate to form a stacked structure, and the stacked structure is combined with the substrate to form a convex structure.
3. The manufacturing process of the semi-floating gate memory of claim 2, wherein:
the step S04 further includes: and side walls are respectively arranged on two sides of the laminated structure, the side walls are respectively connected with two sides of the laminated structure, and one end of each side wall is arranged on the substrate.
4. The manufacturing process of the semi-floating gate memory of claim 3, wherein:
the side wall, the grid and the substrate are combined to form a cavity, and the blocking layer, the semi-floating gate, the tunneling layer and the first semiconductor are all located in the cavity.
5. The manufacturing process of the semi-floating gate memory of claim 4, wherein:
the step S04 further includes: and implanting ions into the two sides of the substrate and the lower ends of the side walls to form a source region and a drain region, wherein the source region and the drain region are respectively abutted against the side walls on the two sides.
6. A semi-floating gate memory prepared by the semi-floating gate memory manufacturing process of any one of claims 1-5, the semi-floating gate memory comprising:
a substrate;
the tunneling layer is arranged on the upper surface of the substrate;
the first semiconductor comprises a covering end and an abutting end, the abutting end is arranged on the substrate, one side of the abutting end abuts against the tunneling layer, the covering end covers the tunneling layer, and the first semiconductor and the substrate form a diode structure;
and the metal nanocrystals are arranged at intervals on the first semiconductor.
7. The semi-floating gate memory of claim 6, further comprising:
the barrier layer, the grid and the side wall;
the barrier layer covers the metal nanocrystals and fills gaps formed by the adjacent metal nanocrystals, the gate covers the barrier layer, the gate, the barrier layer, the metal nanocrystals, the first semiconductor and the tunneling layer are sequentially stacked on the substrate to form a stacked structure, and the stacked structure is combined with the substrate to form a convex structure;
the side walls are arranged on two sides of the laminated structure and are respectively connected with two sides of the laminated structure, and one end of each side wall is arranged on the substrate.
8. The semi-floating gate memory of claim 7, wherein:
the side wall, the grid and the substrate are combined to form a cavity, and the blocking layer, the metal nanocrystalline, the tunneling layer and the first semiconductor are all located in the cavity.
9. The semi-floating gate memory of claim 8, further comprising:
the source region and the drain region are arranged on the substrate and are respectively abutted against the side walls on two sides.
10. The semi-floating gate memory of claim 6, wherein:
the substrate comprises a material comprising a first conductive material, the first semiconductor comprises a material comprising a second conductive material, and the first conductive material and the second conductive material are of opposite conductivity types.
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