KR20040079884A - Perovskite structure fatigue-free ferroelectric transistor with gallium nitride substrate and method for fabricating the same - Google Patents
Perovskite structure fatigue-free ferroelectric transistor with gallium nitride substrate and method for fabricating the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims description 52
- 229910002601 GaN Inorganic materials 0.000 title claims description 39
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000003980 solgel method Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
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- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 19
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- 238000000137 annealing Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 238000002425 crystallisation Methods 0.000 claims description 5
- 230000008025 crystallization Effects 0.000 claims description 5
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
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- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000005621 ferroelectricity Effects 0.000 abstract description 7
- 230000001066 destructive effect Effects 0.000 abstract description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052733 gallium Inorganic materials 0.000 abstract description 3
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 abstract 2
- 229910002340 LaNiO3 Inorganic materials 0.000 abstract 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 abstract 1
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- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 3
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- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
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- OGHBATFHNDZKSO-UHFFFAOYSA-N propan-2-olate Chemical compound CC(C)[O-] OGHBATFHNDZKSO-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 229910052727 yttrium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
Abstract
Description
본 발명은 비휘발성 강유전체 트랜지스터 및 그 제조방법에 관한 것으로, 특히 페로브스카이트구조 타입(Perovskite structure-type)의 [(Pbx,La1-x)(Zry,Ti1-y)O3] (이하 PLZT) 계의 강유전체 박막을 졸-겔 법(Sol-Gel method)에 의한 질화물GaN 박막 위에 형성하고, 상하부 전극으로 강유전체 피로 현상을 제어하기 위해 페로브스카이트형의 전도성 산화물 LaNiO3(이하 LNO)을 Sol-Gel 법으로 형성하고, 완충층으로 Ga2O3박막을 형성하여 GaN 기판 표면의 안정성을 높인 비파괴 읽기(NDRO)가 가능한 갈륨나이트라이드를 기판으로한 페로브스카이트 구조의 강유전체 박막트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric transistor and a method of manufacturing the same, and more particularly, to [(Pb x , La 1-x ) (Zr y , Ti 1- y) O 3 of a perovskite structure-type. A ferroelectric thin film of the following PLZT is formed on a nitride GaN thin film by the Sol-Gel method, and a perovskite-type conductive oxide LaNiO 3 (hereinafter referred to as the upper and lower electrodes to control the ferroelectric fatigue phenomenon). LnO) was formed by Sol-Gel method, and a Ga 2 O 3 thin film was used as a buffer layer to increase the stability of GaN substrate surface. A transistor and a method of manufacturing the same.
최근 수년간 소재 개발 및 박막 증착기술의 발달에 힘입어, 비휘발성 메모리 소자로서, 강유전체 산화물 박막(ferroelectric thin film)을 게이트 유전막(gate dielectric layer)로 직접사용한 비휘발성 강유전체 메모리 트랜지스터(non-volatile ferroelectric memory transistor)에 대한 많은 연구가 진행되고 있다.Thanks to the development of materials and thin film deposition technology in recent years, non-volatile ferroelectric memory transistors using ferroelectric thin films directly as gate dielectric layers as non-volatile memory devices. Much research is being conducted on transistors.
이러한 비휘발성 강유전체 메모리 소자는 강유전체 박막의 자발분극(spontaneous polarization)의 방향에 따른 전계효과 트랜지스터의 소오스/드레인간의 저항 변화를 이용하는 것으로서, 비파괴 읽기(NDRO; Non-Destructive Read-Out)가 가능하고, 구조가 간단하여 공정요건에서 다른 소자 구조보다 유리한 점이 있으며, 하나의 메모리 셀 당 소요 면적이 작은 장점이 있다.The nonvolatile ferroelectric memory device utilizes a source / drain resistance change of a field effect transistor according to the direction of spontaneous polarization of the ferroelectric thin film, and enables non-destructive read-out (NDRO). The simple structure has advantages over other device structures in process requirements, and has a small area required per memory cell.
그러나 이러한 장점에도 불구하고, 전계효과 트랜지스터의 소오스/드레인 형성을 위해서는 기판 상에 불순물(impurity) 활성화(activation)가 필요한데, 현재 실리콘을 기판으로 사용한 공정에서는 약 850℃ 이상의 고온 공정이 요구되어 고온에서 휘발하는 원소를 갖고 있는 강유전체 박막을 게이트 유전막으로 채택하기가 어렵다.However, despite these advantages, impurity activation is required on the substrate for the source / drain formation of the field effect transistor. Currently, a process using silicon as a substrate requires a high temperature process of about 850 ° C. or higher. It is difficult to adopt a ferroelectric thin film having a volatilizing element as a gate dielectric film.
따라서 강유전체 메모리 소자로 활용 가능한 강유전 박막의 조건은 다음과 같다. 고온공정에서도 강유전특성이 유지되어야 하고, 게이트 절연층의 유전율이 낮아야 하고, 소자의 온도변화에 따른 안정한 동작특성을 얻을 수 있도록 구조 상전이 온도가 높아야한다.Therefore, ferroelectric thin films that can be used as ferroelectric memory devices have the following conditions. Ferroelectric properties should be maintained even at high temperature, the dielectric constant of the gate insulating layer should be low, and the structure phase transition temperature should be high to obtain stable operating characteristics according to the temperature change of the device.
그리고 강유전체 박막으로 알려진 대부분은 PbTiO3, Pb(ZrxTi1-x)O3(이하 “PZT”) 등의 페로브스카이트(perovskite) 형태와 SrBi2Ta2O9(이하 "SBT"), KNbO3의 층상형(layered structure) 산화물로서, 이것들을 바로 게이트 유전막으로 이용하면 Pb-계의 경우 Pb의 확산에 의한 실리콘 기판과의 계면반응과 피로현상 발생, 그리고 Bi-계의 경우는 고온 열처리 및 낮은 분극값 등의 특성으로 우수한 특성의 강유전성을 얻기가 어렵다.In addition, most known ferroelectric thin films are formed of perovskite such as PbTiO 3 , Pb (Zr x Ti 1-x ) O 3 (hereinafter referred to as “PZT”), and SrBi 2 Ta 2 O 9 (hereinafter referred to as “SBT”). , A layered structure oxide of KNbO 3 , which can be used as a gate dielectric layer to cause interfacial reactions and fatigue phenomena with silicon substrates due to Pb diffusion in the case of Pb-based, and high temperature in the case of Bi-based It is difficult to obtain ferroelectric properties of excellent properties due to properties such as heat treatment and low polarization values.
통상 FRAM의 셀(cell) 구조는 자료가 MFM 커패시터에 기억되는 한 개의 트랜지스터와 한 개의 커패시터형이다.Typically, the cell structure of a FRAM is one transistor and one capacitor type whose data is stored in an MFM capacitor.
FRAM의 최대한의 잇점을 사용하기 위해서, 프래쉬(flash) 메모리로서 같은 작은 1T 셀 구조를 가진 한 개의 트랜지스터를 포함한 강유전체 Fe-MOSFET 형 메모리가 바람직한 것으로 알려져 있다. 강유전 효과로 유도된 전압은 1T-1C 셀보다 더 높은 감도를 줄 수 있는 1T MOSFET에서의 트랜지스터에 의해 증폭될 수 있으나, 불행하게도 1T Fe-MOSFET 메모리 동작 중, 대부분의 강유전 물질과 Si 사이에 소자 특성을 나쁘게 할 수 있는, 심각한 계면 확산반응에 의해 문제를 일으킨다. 실리콘 기판과 박막 사이에 중간층(buffer layer)을 끼워 상호 간에 반응과 내부확산(inter-diffusion)을 막는 구조들이 등장하였고, 현재에는 이러한 MFIS(metal-ferroelectrics-insulator-silicon) 구조와, 강유전체 박막 상 또는 하에 접하도록 산화물금속 전극을 형성한 구조의 MFMIS(metal ferroelectrics-metal-insulator silicon) 구조가 응용 가능성이 높다고 알려져 있다.In order to take full advantage of FRAM, ferroelectric Fe-MOSFET type memories containing one transistor having the same small 1T cell structure as a flash memory are known to be preferred. The voltage induced by the ferroelectric effect can be amplified by a transistor in a 1T MOSFET that can give higher sensitivity than a 1T-1C cell, but unfortunately during the 1T Fe-MOSFET memory operation, the device between most ferroelectric materials and Si Problems are caused by severe interfacial diffusion reactions, which can degrade properties. Structures have been introduced to prevent a reaction and inter-diffusion between a silicon substrate and a thin film by interposing a buffer layer. Currently, these metal-ferroelectrics-insulator-silicon (MFIS) structures and ferroelectric thin film phases have been introduced. Alternatively, it is known that a metal ferroelectrics-metal-insulator silicon (MFMIS) structure having an oxide metal electrode formed in contact with the bottom is highly applicable.
관련연구로서 MOSFET와 강유전체/Si 사이의 계면반응 장벽에 대한 두 게이트 유전체(gate dielectric)로서 Al2O3와 Ga2O3를 사용하여 1T Fe-MOSFET 메모리 개발에 관한 연구와 BLT(BixLa1-xTi3O12,이하 BLT라 함)계 강유전체가 백금(Pt) 전극 위에 비피로 거동을 가진 탁월한 특성을 가진 강유전 물질이기 때문에 Si 상에 BLT/Al2O3구조에 대한 게이트 유전체(gate dielectric) 연구가 진행되고 있다.As a related research, a study on the development of 1T Fe-MOSFET memory using Al 2 O 3 and Ga 2 O 3 as two gate dielectrics for the interfacial barrier between MOSFET and ferroelectric / Si and BLT (Bi x La) 1-x Ti 3 O 12 ( hereinafter referred to as BLT) -based ferroelectric is a ferroelectric material with excellent properties with specific fatigue behavior over platinum (Pt) electrodes, so that the gate dielectric for BLT / Al 2 O 3 structures on Si gate dielectric) Research is ongoing.
특히 Ga2O3의 경우는 낮은 유전율과 누설전류특성이 우수하여 이 분야에 활발하게 연구가 진행되고 있다.In particular, Ga 2 O 3 has been actively researched in this field because of its low dielectric constant and excellent leakage current characteristics.
최근에는 실리콘을 기판으로한 MFM 구조의 PZT 강유전체와 금속 산화물 전극을 활용하여 1T-1C 구조의 FRAM 소자를 제조하고 있으나, 64M FRAM 급 이상의 고집적소자화를 위해서는 수십 nm 두께의 초박막화가 요구되고 있으며, 이의 효과적인 구현을 위해서는 고온공정의 안정성과 초고속 광소자용 기판에 대해 선행과제로 연구할 필요성이 대두되고 있다.Recently, a 1T-1C structure FRAM device is fabricated using a silicon-based MFM-structured PZT ferroelectric and a metal oxide electrode, but ultra-thin film of several tens of nm thickness is required for high integration devices of 64M FRAM level or higher. In order to effectively implement, there is a need to study the stability of the high-temperature process and research into the substrate for the ultra-fast optical device as a prior task.
따라서, 본 발명은 상기한 종래기술들의 문제점을 해결하기 위해 안출된 것으로, PLZT 박막의 물성적인 측면에서 화학량론적인 제어와 대면적 증착, 저온 공정 등이 가능한 졸-겔(Sol-gel)법 등으로 강유전체인 PLZT 그리고 산화물 전극으로 LNO, 중간층으로 Ga2O3박막을 GaN 단결정 기판 위에 성장시켜 강유전성(ferroelectricity)이 향상된 비파괴 독출형(Non-destructive readout-type)의 트랜지스터를 형성시키는 갈륨나이트라이드를 기판으로한 페로브스카이트 구조의 강유전체 박막트랜지스터 및 그 제조방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention has been made to solve the above problems of the prior art, sol-gel (Sol-gel) method, such as stoichiometric control, large-area deposition, low-temperature process, etc. in terms of physical properties of PLZT thin film PLZT (ferroelectric), LNO as an oxide electrode, and Ga 2 O 3 thin film as an interlayer are grown on a GaN single crystal substrate to form a non-destructive readout-type transistor with improved ferroelectricity. An object of the present invention is to provide a ferroelectric thin film transistor having a perovskite structure as a substrate and a method of manufacturing the same.
도1 - 본 발명의 바람직한 실시 예에 따라 [(Pbc,La1-x)(Zry,Ti1-y)O3] (이하 PLZT) 강유전체 박막과 LaNiO3(이하 LNO)을 졸-겔(Sol-Gel) 법으로 형성하여 XRD (X-ray diffraction)로 측정한 결정성 분석도. 1- Sol-gel of [(Pb c , La 1-x ) (Zr y , Ti 1-y ) O 3 ] (hereinafter referred to as PLZT) ferroelectric thin film and LaNiO 3 (hereinafter referred to as LNO) according to an embodiment of the present invention. Crystallinity diagram formed by (Sol-Gel) method and measured by XRD (X-ray diffraction).
도2a - 전도성 산화물 박막 LNO를 PLZT 박막의 상부 및 기저전극으로 이용한 단면구조 형태의 SEM 사진을 나타낸 도.FIG. 2A is a SEM photograph of a cross-sectional structure in which a conductive oxide thin film LNO is used as a top and base electrode of a PLZT thin film. FIG.
도2b - PLZT와 PZT에 대한 상부전극인 LNO의 표면 형태의 SEM 사진을 나타낸 도,FIG. 2b is a SEM photograph of the surface shape of the upper electrode LNO for PLZT and PZT. FIG.
도3a, 도3b - Ga2O3의 증착 싸이클(cycle)의 변화에 따른 PLZT/Ga2O3/GaN/Al2O3박막구조의 XRD 구조분석 및 표면 형상 SEM 사진을 나타낸 도.Figure 3a, Figure 3b - diagram showing the structure XRD analysis and SEM images of the surface shape PLZT / Ga 2 O 3 / GaN / Al 2 O 3 thin film structure in accordance with the change of the deposition cycle (cycle) of the Ga 2 O 3.
도4 - Ga2O3의 증착 싸이클(cycle)의 변화에 따른 Ga2O3/GaN 구조의 AES 깊이조성분석 결과를 나타낸 도.Figure 4 - Ga 2 O 3 Ga 2 O showing an AES depth of 3 / GaN structure, the composition analysis according to the change of the deposition cycle (cycle) of FIG.
도5 - PLZT 강유전체 박막과 LNO 박막의 이종접합에 대한 GDS 깊이조성 분석 결과를 나타낸 도.5-GDS depth composition analysis results for the heterojunction of the PLZT ferroelectric thin film and LNO thin film.
도6 - MFMIS 구조의 전계효과 트랜지스터를 나타내는 요부단면도.Fig. 6-A cross-sectional view showing main parts of a field effect transistor of an MFMIS structure.
도7 - 전도성 산화물 박막을 상하부 기저전극으로 사용했을 때의 초기상태 및 피로 후의 강유전 박막의 이력곡선을 나타낸 도.Fig. 7 shows the hysteresis curve of the ferroelectric thin film after the initial state and the fatigue when the conductive oxide thin film is used as the upper and lower base electrodes.
도8 - 상하부 전극층의 형성여부에 따른 PLZT 강유전체 박막의 피로특성을 나타낸 도.8 shows fatigue characteristics of PLZT ferroelectric thin films depending on whether upper and lower electrode layers are formed.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 실리콘기판 2 : GaN 박막1: silicon substrate 2: GaN thin film
3, 4 : 소오스/드레인 확산층 5 : 활성영역3, 4: source / drain diffusion layer 5: active region
6 : 격리영역 7 : 중간층6: isolation region 7: intermediate layer
8 : PLZT 박막층 9 : 고립층8: PLZT thin film layer 9: isolated layer
10 : 보호층 11 : 상하부 전극층10: protective layer 11: upper and lower electrode layers
상기한 목적을 달성하기 위한 본 발명은, 갈륨나이트라이드(GaN) 박막 상면에 Ga2O3박막을 증착시켜 중간층을 형성시키는 중간층 형성단계와; 상기 중간층 상면에 페로브스카이트 구조를 가지는 납(Pb)-란타늄(La)-지르코늄(Zr)-티타늄(Ti) 산화물(PbxLa1-xZryTi1-yO3, PLZT)계 강유전체 박막층을 형성시키는 PLZT 박막층 형성단계와; 상기 PLZT 박막층 상면에 전도성 산화물 LaNiO3(LNO)박막을 형성시키는 상부전극층 형성단계; 그리고, 증착된 박막을 식각공정을 통해 소자 구조를 형성시키는 소자 형성단계;를 포함하여 구성되는 갈륨나이트라이드를 기판으로한 페로브스카이트 구조의 강유전체 박막트랜지스터 제조방법을 기술적 요지로 한다.The present invention for achieving the above object, the intermediate layer forming step of forming an intermediate layer by depositing a Ga 2 O 3 thin film on the upper surface of the gallium nitride (GaN) thin film; Lead (Pb) -lanthanum (La) -zirconium (Zr) -titanium (Ti) oxide (Pb x La 1-x Zr y Ti 1- yO 3 , PLZT) ferroelectric having a perovskite structure on the upper surface of the intermediate layer A PLZT thin film layer forming step of forming a thin film layer; Forming an upper electrode layer on the PLZT thin film layer to form a conductive oxide LaNiO 3 (LNO) thin film; In addition, a method of fabricating a ferroelectric thin film transistor having a perovskite structure based on gallium nitride as a substrate, the device forming step of forming a device structure through an etch process of the deposited thin film as a technical gist.
그리고, 본원발명은, 사파이어(Al2O3)기판 상면에 금속유기화학 증착법에 의해 형성된 GaN 박막층과; 상기 GaN 박막층 상면에 Ga2O3박막을 증착시킴에 의해 형성된 중간층과; 상기 중간층 상면에 페로브스카이트 구조를 가지는 납(Pb)-란타늄(La)-지르코늄(Zr)-티타늄(Ti) 산화물(PbxLa1-xZryTi1-yO3, PLZT)계 강유전체층을 박막형태로 형성된 PLZT 박막층; 그리고, 상기 PLZT 박막층 상면에 전도성 산화물 LaNiO3(LNO)박막을 증착시킴에 의해 형성된 상부전극층;을 포함하여 구성되는 갈륨나이트라이드를 기판으로한 페로브스카이트 구조의 강유전체 박막트랜지스터를 또한 기술적 요지로 한다.In addition, the present invention, GaN thin film layer formed by a metal organic chemical vapor deposition method on the sapphire (Al 2 O 3 ) substrate upper surface; An intermediate layer formed by depositing a Ga 2 O 3 thin film on an upper surface of the GaN thin film layer; Lead (Pb) -lanthanum (La) -zirconium (Zr) -titanium (Ti) oxide (Pb x La 1-x Zr y Ti 1- yO 3 , PLZT) ferroelectric having a perovskite structure on the upper surface of the intermediate layer PLZT thin film layer formed in a thin film form; In addition, the upper electrode layer formed by depositing a conductive oxide LaNiO 3 (LNO) thin film on the upper surface of the PLZT thin film layer; and a ferroelectric thin film transistor having a perovskite structure based on gallium nitride as a substrate. do.
여기서, 상기 중간층과 PLZT 박막층 사이에는 전도성 산화물 LaNiO3(LNO) 박막을 증착시킴에 의해 형성된 하부전극층이 더 포함되고, 상기 갈륨나이트라이드(GaN) 박막은, 사파이어(Al2O3)기판 상면에 금속유기화학 증착법에 의해 형성되고, 상기 중간층은, 플라즈마 원자층 증착(Plasma Enhanced Atomic Layer Deposition, PEALD)법 또는 졸겔법을 이용하여 형성되는 것이 바람직하다.Here, a lower electrode layer formed by depositing a conductive oxide LaNiO 3 (LNO) thin film is further included between the intermediate layer and the PLZT thin film layer, and the gallium nitride (GaN) thin film is formed on an upper surface of a sapphire (Al 2 O 3 ) substrate. It is preferably formed by a metal organic chemical vapor deposition method, the intermediate layer is preferably formed using a plasma enhanced atomic layer deposition (PEALD) method or a sol-gel method.
그리고, 상기 PLZT 박막층은 Pb-아세테이트(acetate), La-2 메톡시에톡사이드(methoxyethoxide), Zr-아이소프록사이드(isopropoxide), Ti-아이소프록사이드(isopropoxide)를 소스로 사용하여 2-메톡시에탄올(2-methoxyethanol; CH3OCH2CH2OH)에 녹여 선구 용액(precursor solution)을 제조하는 제1단계와; 상기 선구물질을 스핑코팅시키는 제2단계와; 상기 스핀 코팅된 선구물질을 건조시키는 제3단계; 그리고, 최종 결정화를 위한 어닐링을 실시하는 제4단계;를 거쳐 형성되는 것이 바람직하다.In addition, the PLZT thin film layer was prepared by using Pb-acetate, La-2 methoxyethoxide, Zr-isopropoxide, and Ti-isopropoxide as a source. A first step of preparing a precursor solution by dissolving in 2-methoxyethanol (CH 3 OCH 2 CH 2 OH); A second step of spun coating the precursor; A third step of drying the spin coated precursor; And, the fourth step of performing annealing for the final crystallization; is preferably formed through.
이에 따라, PLZT 박막의 물성적인 측면에서 화학량론적인 제어와 대면적 증착, 저온 공정 등이 가능한 졸-겔(Sol-gel) 법으로 강유전체인 PLZT 그리고 산화물전극으로 LNO, 중간층으로 Ga2O3박막을 GaN 단결정 기판 위에 성장시켜 강유전성(ferroelectricity)이 향상된 비파괴 독출형(Non-destructive readout-type)의 트랜지스터를 형성시켜 전기-광학 소자 응용은 물론 2T-2C, 1T-1C, MFIS, MFMIS 형의 단일트랜지스터 강유전체 메모리 소자(single transistor ferroelectric memory device)에 응용가능하다는 이점이 있다.Accordingly, the stoichiometric control and large-area deposition, the low temperature process such as the available sol properties aspects of PLZT thin-gel (Sol-gel) method as a ferroelectric PLZT and the oxide electrode as Ga 2 O 3 thin film as LNO, intermediate Is grown on a GaN single crystal substrate to form non-destructive readout-type transistors with improved ferroelectricity, so that not only electro-optic devices but also 2T-2C, 1T-1C, MFIS and MFMIS types There is an advantage in that it is applicable to a single transistor ferroelectric memory device.
본 발명의 설명에 앞서 본 발명의 배경에 대해 간단하게 설명하기로 한다.Prior to the description of the present invention, the background of the present invention will be briefly described.
통상, 비휘발성 메모리소자로서의 강유전체는 소재의 고온안정성, 기판과 박막의 제한적인 계면확산반응, 다양한 공정의 용이성, 단순화 식각(lithography) 조건의 확보 등이 요구된다. 특히, MFIS 구조의 경우는 중간층을 활용한 것으로 낮은 유전율의 소재가 필수적이다. 또한, 광-전자 소자응용을 위한 강유전체는 투명한 박막의 형성이 요구되며, 이와 더불어, 투명한 반도체 기판이 확보되거나 절연기판 위에 투명 전극 및 반도체의 형성이 요청된다.BACKGROUND ART In general, ferroelectrics as nonvolatile memory devices require high temperature stability of materials, limited interfacial diffusion reaction between substrates and thin films, ease of various processes, and secured simple etching conditions. In particular, in the case of the MFIS structure, an intermediate layer is used, and a low dielectric constant material is essential. In addition, the ferroelectric for photo-electronic device application is required to form a transparent thin film, and in addition, a transparent semiconductor substrate is secured or the formation of a transparent electrode and a semiconductor on the insulating substrate is required.
반도체 메모리소자의 강유전체 재료로 사용되고 있는 층상구조(layered structure)의 Bi-계 산화물은 읽기(read), 쓰기(write) 횟수에 있어서는 우수하나, 낮은 박막의 치밀도(density)와 높은 누설전류(leakage current) 특성이 문제점으로 지적되고 있다. 단일 트랜지스터형 강유전체 소자응용에 있어 박막의 비-피로(fatigue-free) 특성은 Bi-계 층상구조 물질 이외에는 알려지지 않고 있다. 이와 병행하여 Pb-계를 이용한 FRAM의 연구가 진행되어오고 있으며, 현재는 층간물질과 전도성 산화물 박막을 이용하여 무-피로 특성과 기타 강유전체의 소자화에 대한 문제점을 극복하고 있으나, 초박막화로 인한 박막특성 구현의 한계에 직면하고 있다.Layered structure Bi-based oxides, which are used as ferroelectric materials for semiconductor memory devices, are excellent in the number of reads and writes, but have low densities and high leakage currents. The current characteristic is pointed out as a problem. The fatigue-free properties of thin films in single transistor type ferroelectric device applications are not known other than Bi-based layered materials. In parallel with this, research on FRAM using Pb-based materials has been conducted. Currently, the problems of fatigue-free and other ferroelectric elements are overcome by using interlayer materials and conductive oxide thin films. There are limitations to the implementation.
또한, 물리적인 방법(physical method) [RF 스퍼터링 법(RF sputtering), 레이저 증발법(laser ablation) 등]으로 트랜지스터 구조를 형성하는 경우 장시간의 고온 열처리 과정이 필요하며, 재료물질로 비스무스(Bi)와 납(Pb)을 함유하는 화합물은 고온 열처리시 Bi와 Pb의 휘발이 예상되어 불안정한 반면, 화학적인 방법을 활용하면 낮은 제조단가, 대구경 박막 소재의 제조, 화학량론적인 제어로 안정성 확보 등의 여러 가지 잇점이 있다.In addition, when forming a transistor structure by a physical method (RF sputtering, laser ablation, etc.), a long time high temperature heat treatment process is required, and bismuth (Bi) as a material material Compounds containing and lead (Pb) are unstable due to the volatilization of Bi and Pb during high temperature heat treatment.However, chemical methods can be used to lower the production cost, manufacture large diameter thin film materials, and secure stability through stoichiometric control. There are advantages.
재료적인 측면에서 Bi-계, Pb-계 강유전체 소재는 물성적인 잇점이 있지만, 소자응용을 위한 MFS 구조의 경우에는 위에서 기술한 많은 단점이 있다. 이를 극복하기 위한 다양한 시도가 행해지고 있으며, 하부와 상부전극으로 실리콘과 산화물 금속을 사용한 경우, SBN, BTN 물질은 읽기, 쓰기 횟수 및 절연성이 증가하며, 고온 열처리에도 안정하다. 이러한 장점에도 불구하고 강유전성의 확보에 여전히 신뢰도가 떨어지는 어려움이 있고, 상대적으로 SBT, PZT 계에 비해 연구가 집중적으로 이루어지지 않아 물성연구가 계속적으로 진행되어야 할 것으로 예상된다.In terms of materials, Bi-based and Pb-based ferroelectric materials have physical advantages, but MFS structures for device applications have many disadvantages described above. Various attempts have been made to overcome this problem. In the case of using silicon and oxide metals as the lower and upper electrodes, SBN and BTN materials have increased reads, write times, and insulation properties, and are stable to high temperature heat treatment. Despite these advantages, there is still a lack of reliability in securing ferroelectricity, and it is expected that the study of physical properties should be continued as research is not intensive compared to SBT and PZT systems.
한편, 본 연구에서 강유전체 물질로서 고려되고 있는 PLZT 박막은 전기광학 특성이 우수하여 전기-광학(electro-optic) 소자 응용 목적으로 많이 연구되고 있으며, 주로 단결정(single crystal) 위에 물리적인 방법(physical method) [RF 스퍼터링 법(RF sputtering), 레이저 증발법(laser ablation) 등]으로 제조하고 있다. 화학적인 방법(chemical method)으로는 졸-겔 법이 주로 사용되어 왔다.On the other hand, the PLZT thin film, which is considered as a ferroelectric material in this study, has excellent electro-optic properties and has been studied for the purpose of electro-optic device application. It is mainly a physical method on a single crystal. ) (RF sputtering, laser ablation, etc.). The sol-gel method has been mainly used as a chemical method.
반도체 GaN은 SiC 소재와 더불어 고출력, 고온 응용을 위한 전자소자 응용에활용 가능하여 연구가 폭넓게 진행되고 있으며, 특히 4.2eV의 와이드밴드갭(wide band-gap)을 가지고 있어 전기-광학소자 응용에 주목을 받고 있을 뿐만 아니라 LED(light emitting diode)와 LD(laser diode) 소자 응용에 성공하였다.In addition to SiC materials, semiconductor GaN can be utilized for electronic device applications for high power and high temperature applications, and research is being widely conducted. Especially, it has a wide band-gap of 4.2 eV. As well as receiving a successful light emitting diode (LED) and laser diode (LD) device application.
현재 MIS 또는 MOSFET 구조의 소자는 기존의 산화물 SiO2, Si3N4, Al2O3등이 사용되고 있다. 그러나 대부분의 다른 전자소자와 비교할 때, n-type의 다량 도핑이 어려워 GaN MIS 구조에 큰 전압이 인가되므로 실제적인 GaN MOSFET에 대한 연구가 적은 분야이다. 이는 비록 중간층이 매우 얇다고 하더라도 10V 이하의 전압에서 강유전체를 필드(field) 효과로 분극 반전시키기가 매우 어렵다.Currently, MIS or MOSFET structure devices include conventional oxides SiO 2 , Si 3 N 4 , and Al 2 O 3 . However, compared with most other electronic devices, since a large amount of voltage is applied to the GaN MIS structure due to the difficulty in doping a large amount of n-type, there is little research on the actual GaN MOSFET. This makes it very difficult to polarize the ferroelectric with field effect at voltages below 10V, even if the intermediate layer is very thin.
통상 강유전 박막이 증착될 때 강유전체/실리콘 계면에서의 상호 내부확산에 기인하여 이차상을 형성할 수 있다. 그러나 GaN은 약 900℃에서도 질량손실이 없어 박막 증착시 재료적인 측면에서 상당히 안정한 물질이다.Usually, when a ferroelectric thin film is deposited, a secondary phase may be formed due to mutual internal diffusion at the ferroelectric / silicon interface. However, GaN is a material that is quite stable in terms of material during thin film deposition because there is no mass loss even at about 900 ℃.
따라서 GaN을 활용한 산화물 소재의 증착은 증착 방법과 증착조건 등을 효과적으로 활용할 시 MFIS 또는 MFMIS 소자를 구현하기에 적절한 물질로 판단된다.Therefore, the deposition of oxide material using GaN is considered to be a suitable material for implementing MFIS or MFMIS devices when the deposition method and deposition conditions are effectively utilized.
이러한 여러 가지 특성으로 볼 때, GaN을 사용한 MFSFET는 비휘발성, 고속소자, 집적회로에서의 그들의 응용이 가능하고, 강유전성에 의해 제공되는 큰 분극과 강유전 게이트(gate)의 고유전 상수 때문에 차세대 전기광학, 전자소자 제조를 위해 GaN 기판 위에 페로브스카이트 구조의 강유전성 PLZT 박막을 증착하여 FET-타입(type)의 구조를 형성시키는 본 발명에 이르게 된 것이다.These characteristics make GaN-based MFSFETs possible for their application in nonvolatile, high-speed devices, integrated circuits, and because of the large polarization provided by ferroelectricity and the high dielectric constants of ferroelectric gates, In the present invention, a ferroelectric PLZT thin film having a perovskite structure is deposited on a GaN substrate to form an FET-type structure.
이하 첨부된 도면을 참조로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 갈륨나이트라이드(GaN)를 기판으로한 페로브스카이트 구조의 강유전체 박막트랜지스터 제조방법은 크게 중간층형성단계와, 하부전극층 형성단계와, PLZT 박막층 형성단계 그리고 상부전극층 형성단계로 구성된다.The method of manufacturing a ferroelectric thin film transistor having a perovskite structure based on gallium nitride (GaN) according to the present invention is composed of an intermediate layer forming step, a lower electrode layer forming step, a PLZT thin film layer forming step, and an upper electrode layer forming step. .
먼저 중간층 형성단계를 설명한다.First, the intermediate layer forming step will be described.
상기 중간층 형성단계를 위해서는 GaN 박막이 형성되어야 하는 바, 사파이어(Al2O3(0001)) 기판 위에 GaN를 금속유기 화학증착법(Metal Organic Chemical Vapor Deposition, 이하 MOCVD법이라 함)로 증착시키며 1000 ℃에서 3um의 두께로 증착하였다.In order to form the intermediate layer, a GaN thin film should be formed. The GaN is deposited on a sapphire (Al 2 O 3 (0001)) substrate by a metal organic chemical vapor deposition method (hereinafter referred to as a MOCVD method) and 1000 ° C. At a thickness of 3 μm.
그리고 전기전도도를 증가하기 위해 Al을 첨가하여 2D 전자기체 형태의 박막을 형성하였으며 GaN 박막은 n-형으로 1~5x1018개의 carrier 농도로 준비 되었다.In order to increase the electrical conductivity, Al was added to form a thin film of 2D electromagnetic form, and the GaN thin film was prepared with n-type 1 ~ 5x10 18 carrier concentration.
상기 전자기체의 형성은 GaN 박막의 특성을 향상시키기 위함이다.The formation of the electromagnetic body is to improve the characteristics of the GaN thin film.
GaN 박막이 형성되면 GaN 박막 상면에 중간층을 형성시키는 중간층 형성단계가 진행되는 바, 중간층재료인 Ga2O3는 PEALD(Plasma enhanced atomic layer deposition)법으로 아르곤과 산소의 분압비를 변화시켜 200℃이하의 낮은 기판 온도에서 사이클(cycle, 여기서 1싸이클은 Ga, O 원자의 1원자 층을 의미함.) 횟수를 바꾸면서 박막을 형성하고, 고온에서 급속 열처리함에 의해 중간층을 형성하였다.When the GaN thin film is formed, an intermediate layer forming step of forming an intermediate layer on the upper surface of the GaN thin film is performed. Ga 2 O 3 , which is an intermediate layer material, is changed to a partial pressure ratio of argon and oxygen by a plasma enhanced atomic layer deposition (PEALD) method to 200 ° C. Thin films were formed by varying the number of cycles (where one cycle means one atomic layer of Ga, O atoms) at the following low substrate temperatures, and an intermediate layer was formed by rapid heat treatment at high temperatures.
여기서, 상기 중간층의 형성은 졸겔법에 의해서도 가능한 바, 중간층재료인 Ga2O3는 Ga-트리메틸아세토네이트(trimethylacetonate)를 각각 소스로 사용하여 2-메톡시에탄올(2-methoxyethanol; CH3OCH2CH2OH)에 녹여 선구 용액(precursor solution)을 만들고, 스핀 코팅(Spin-coating)으로 박막을 증착하고, 건조(drying)한 다음 열처리 하는 방법으로 중간층을 형성하여도 무방하며 본 발명의 범주에 속한다.Here, the formation of the intermediate layer is also possible by the sol-gel method, and the intermediate layer Ga 2 O 3 is made of 2-methoxyethanol (2-methoxyethanol; CH 3 OCH 2 using Ga-trimethylacetonate) as a source. CH 2 OH) to form a precursor solution (precursor solution), spin-coating to deposit a thin film (drying), and then heat-treat the method of forming an intermediate layer in the scope of the present invention. Belongs.
다음은 하부전극층 형성단계가 진행되는 바, 상기 하부전극층은 본 발명에 있어서 선택층으로 형성하지 않아도 무방하다.Next, as the lower electrode layer forming step is performed, the lower electrode layer may be formed as a selective layer in the present invention.
상기 하부전극층 형성은 전도성 산화물 LaNiO3(이하 LNO)박막을 형성시키는 것으로 La-2 메톡시에톡사이드(methoxyethoxide), Ni-아세테이트(acetate)를, 소스로 사용하여 2-메톡시에탄올(2-methoxyethanol; CH3OCH2CH2OH)에 녹여 선구 용액(precursor solution)을 만든다.The lower electrode layer is formed to form a conductive oxide LaNiO 3 (hereinafter referred to as LNO) thin film, 2-methoxyethanol (2-) using La-2 methoxyethoxide and Ni-acetate as a source. methoxyethanol; CH 3 OCH 2 CH 2 OH) to form a precursor solution.
이어서, 약 3000rpm의 스핀 코팅(Spin-coating)으로 박막을 증착하고, 건조(drying)를 두 번에 걸쳐 수행한다. 첫번째 건조는 약 150 ℃의 비교적 저온에서 약 5분 동안 수행하고, 두 번째 건조는 약 450 ℃에서 약 5분 동안 행한다.Subsequently, the thin film is deposited by spin-coating at about 3000 rpm, and drying is performed twice. The first drying is carried out at a relatively low temperature of about 150 ° C. for about 5 minutes and the second drying is carried out at about 450 ° C. for about 5 minutes.
스핀 코팅에서 두 번째 건조를 반복 실시하여 원하는 LNO 박막의 두께를 얻는 것이 바람직하다.It is preferable to repeat the second drying in spin coating to obtain the desired thickness of the LNO thin film.
그리고, 최종 결정화를 위한 어닐링(Annealing)를 실시하는 바, 약 500-700℃ 온도의 산소 및 공기 분위기에서 30분 내지 1시간 동안 실시하면 하부전극층이 형성된다.Then, annealing (annealing) for the final crystallization, the lower electrode layer is formed by performing for 30 minutes to 1 hour in an oxygen and air atmosphere of about 500-700 ℃ temperature.
다음은 PLZT 박막층 형성단계가 진행되는 바, PLZT 박막층 형성은 Pb-아세테이트(acetate), La-2 메톡시에톡사이드(methoxyethoxide), Zr-아이소프로폭사이드(isopropoxide), Ti-아이소프로폭사이드(isopropoxide)를 소스로 사용하여 2-메톡시에탄올(2-methoxyethanol; CH3OCH2CH2OH)에 녹여 선구 용액(precursor solution)을 만든다.Next, the PLZT thin film layer forming step is performed. The PLZT thin film layer is formed of Pb-acetate, La-2 methoxyethoxide, Zr-isopropoxide, and Ti-isopropoxide. (isopropoxide) is used as a source to dissolve in 2-methoxyethanol (CH 3 OCH 2 CH 2 OH) to make a precursor solution (precursor solution).
이어서, 약 3000 rpm의 스핀 코팅(Spin-coating)으로 박막을 증착하고, 건조(drying)를 두 번에 걸쳐 수행한다. 첫번째 건조는 약 150 ℃의 비교적 저온에서 약 5분 동안 수행하고, 두 번째 건조는 약 450 ℃에서 약 5분 동안 행한다. 스핀 코팅에서 두 번째 건조를 반복 실시하여 원하는 PLZT 박막의 두께를 얻는다.Subsequently, the thin film is deposited by spin-coating at about 3000 rpm, and drying is performed twice. The first drying is carried out at a relatively low temperature of about 150 ° C. for about 5 minutes and the second drying is carried out at about 450 ° C. for about 5 minutes. The second drying is repeated in spin coating to obtain the desired thickness of the PLZT thin film.
최종 결정화를 위한 어닐링(Annealing)를 실시하는 바, 약 500-700℃온도의 산소 및 공기 분위기에서 30분 내지 1시간 동안 실시 하면 PLZT 박막층이 형성된다.Annealing (annealing) for the final crystallization, the PLZT thin film layer is formed for 30 minutes to 1 hour in an oxygen and air atmosphere of about 500-700 ℃ temperature.
상기 PLZT 박막층의 두가지 조성비로 형성하였으며, PLZT (Pb0.91La0.09Zr0.65Ti0.35O3) 및 PZT(PbZr0.65Ti0.35O3)의 조성비를 가지는 PLZT 박막층을 형성하였으며 PLZT (Pb0.91La0.09Zr0.65Ti0.35O3)의 조성비를 가지는 박막층이 바람직한 것으로 확인되었다. .The PLZT thin film layer was formed with two composition ratios, and a PLZT thin film layer having a composition ratio of PLZT (Pb 0.91 La 0.09 Zr 0.65 Ti 0.35 O 3 ) and PZT (PbZr 0.65 Ti 0.35 O 3 ) was formed, and PLZT (Pb 0.91 La 0.09 Zr 0.65 It was confirmed that a thin film layer having a composition ratio of Ti 0.35 O 3 ) is preferable. .
상기 PLZT 박막층 형성단계가 완료되면 상부전극층 형성단계가 진행되는 바, 상기 상부전극층 형성은 전도성 산화물 LaNiO3(이하 LNO)박막을 형성시키는 것으로 La-2 메톡시에톡사이드(methoxyethoxide), Ni-아세테이트(acetate)를, 소스로 사용하여 2-메톡시에탄올(2-methoxyethanol; CH3OCH2CH2OH)에 녹여 선구 용액(precursor solution)을 만든다.When the PLZT thin film layer forming step is completed, the upper electrode layer forming step is performed. The upper electrode layer is formed by forming a conductive oxide LaNiO 3 (hereinafter referred to as LNO) thin film. La-2 methoxyethoxide and Ni-acetate. (acetate) is dissolved in 2-methoxyethanol (CH 3 OCH 2 CH 2 OH) using a source to form a precursor solution.
이어서, 약 3000rpm의 스핀 코팅(Spin-coating)으로 박막을 증착하고, 건조(drying)를 두 번에 걸쳐 수행한다. 첫번째 건조는 약 150 ℃의 비교적 저온에서 약 5분 동안 수행하고, 두 번째 건조는 약 450 ℃에서 약 5분 동안 행한다.Subsequently, the thin film is deposited by spin-coating at about 3000 rpm, and drying is performed twice. The first drying is carried out at a relatively low temperature of about 150 ° C. for about 5 minutes and the second drying is carried out at about 450 ° C. for about 5 minutes.
스핀 코팅에서 두 번째 건조를 반복 실시하여 원하는 LNO 박막의 두께를 얻는다.The second drying is repeated in spin coating to obtain the desired thickness of the LNO thin film.
그리고, 최종 결정화를 위한 어닐링(Annealing)를 실시하는 바, 약 500-700℃ 온도의 산소 및 공기 분위기에서 30분 내지 1시간 동안 실시하면 하부전극층이 형성된다.Then, annealing (annealing) for the final crystallization, the lower electrode layer is formed by performing for 30 minutes to 1 hour in an oxygen and air atmosphere of about 500-700 ℃ temperature.
상기의 과정이 완료되면 GaN 박막 상면에 페로브스카이트 구조의 게이트 유전체가 형성되는 바, 이들에 대한 물성 및 구조적 특성조사를 하였다.When the above process is completed, a gate dielectric having a perovskite structure is formed on the upper surface of the GaN thin film, and physical and structural characteristics thereof were investigated.
도1은 본 발명의 바람직한 실시 예에 따라 [(PbX,La1-X)(ZrY,Ti1-Y)O3] (이하 PLZT) 강유전체 박막과 LaNiO3(이하 LNO)을 졸-겔(Sol-Gel) 법으로 형성하여 XRD (X-ray diffraction)로 측정한 결정성 분석도이다.1 is a sol-gel of [(Pb X , La 1-X ) (Zr Y , Ti 1-Y ) O 3 ] (hereinafter referred to as PLZT) ferroelectric thin film and LaNiO 3 (hereinafter referred to as LNO) according to a preferred embodiment of the present invention. It is a crystallinity diagram formed by (Sol-Gel) method and measured by XRD (X-ray diffraction).
여기서, X=0.91, Y=0.65 인 경우를 PLZT로 표시하였으며, X=1, Y=0.65인 경우를 PZT로 표시하였으며, 상하부 전극층이 형성된 유전체 박막을 LNO/PLZT/LNO로 표시하였고, 상부전극층 만이 형성된 유전체 박막을 LNO/PLZT로 표시하였고, 하부전극층만이 형성된 유천체 박막을 PLZT/LNO로 표시하였다. 이하 도면의 표기방식은 상기의 규칙에 따라 표현하였다.Here, the case of X = 0.91 and Y = 0.65 is represented by PLZT, and the case of X = 1 and Y = 0.65 is represented by PZT. The dielectric thin film on which the upper and lower electrode layers are formed is represented by LNO / PLZT / LNO, and the upper electrode layer. Only the dielectric thin film on which the formation was made was represented by LNO / PLZT, and the inductor thin film on which only the lower electrode layer was formed was represented by PLZT / LNO. The notation in the drawings is represented according to the above rules.
도1에 도시된 바와 같이,각각의 박막층 이외의 다른 상들은 나타나지 않았다. 그리고 박막의 결정구조 조사에서 기판의 이차상은 관측되지 않았다.As shown in Fig. 1, no phases other than the respective thin film layers were shown. And no secondary phase was observed in the crystal structure investigation of the thin film.
LNO의 배향은 기판의 배향과 관련되어 (100), (200) 피크들만 검출 되었고, 강유전체 PLZT 박막은 (110) 피크 이외에 (001), (002) 피크들이 뚜렷하게 나타났으며, 이는 LNO의 우선 배향에 기인한 것으로 판단된다.The orientation of the LNO was related to the orientation of the substrate and only (100) and (200) peaks were detected, and the ferroelectric PLZT thin film showed distinct (001) and (002) peaks in addition to the (110) peak, which was the preferred orientation of the LNO. It seems to be due to.
La이 첨가되지 않은 경우(PZT)는 뚜렷한 테트라고낼러티(tetragonality)로 (100), (001)와 (002), (200) 피크들의 분리가 나타났으며, 상부전극이 증착된 경우는 다소 결정성이 떨어졌으며, 이는 LNO의 결정성과 계면 확산 현상이 원인인 것으로 생각된다.La not added (PZT) showed distinct tetragonality, resulting in the separation of the (100), (001), (002) and (200) peaks, somewhat determined when the upper electrode was deposited. The property was inferior, which is thought to be due to the crystallinity of LNO and the interfacial diffusion phenomenon.
도2a는 전도성 산화물 박막 LNO를 PLZT 박막의 상부 및 기저전극으로 이용한 단면구조 형태의 SEM 사진을 나타낸 도로써, 도2a의 그림으로부터 GaN는 약 3μm이고 LNO와 PLZT 박막은 각각 약 300nm, 400nm의 두께임이 확인 되었다.FIG. 2A is a SEM image of a cross-sectional structure using a conductive oxide thin film LNO as a top and base electrode of a PLZT thin film. FIG. 2A shows that GaN is about 3 μm, and LNO and PLZT thin films are about 300 nm and 400 nm thick, respectively. Im confirmed.
PLZT는 분말(granular)형의 LNO 박막과는 달리 칼럼날(columnar) 구조로 균일하게 증착되었다.PLZT was uniformly deposited in a columnar structure, unlike a granular LNO thin film.
이러한 두께의 박막에서 산화물 박막의 특성이 유지 됨은 최적 증착조건이 확보 되었고, 적절한 기판 선택으로 박막의 결정성을 확보하는데 어려움이 없음을 알 수 있다.The maintenance of the characteristics of the oxide thin film in the thin film of such a thickness has ensured the optimum deposition conditions, it can be seen that there is no difficulty in securing the crystallinity of the thin film by selecting the appropriate substrate.
도2b는 PLZT와 PZT에 대한 상부전극인 LNO의 표면 형태를 나타낸 것으로 그레인(grain)의 크기나 모양은 크게 구별되지 않았으며, 약 50~60nm 크기의 균일한원형의 결정립으로 되어있음을 알 수있다.Figure 2b shows the surface shape of LNO, the upper electrode for PLZT and PZT, the grain size or shape was not largely distinguished, it can be seen that it is a uniform circular grain of about 50 ~ 60nm size have.
도3a는 GaN 기판 위에 PEALD 법으로 증착한 Ga2O3박막의 싸이클(1싸이클 Ga, O 원자의 1원자 층을 의미) 의존성을 측정하기 위한 것으로, 강유전체 박막을 증착하여 700℃에서 30 분간 열처리한 후의 결정성을 측정한 XRD 회절형태이다.FIG. 3A is a graph for measuring the dependence of a cycle of Ga 2 O 3 thin film deposited on a GaN substrate by PEALD method (1 cycle Ga, meaning an atomic layer of O atoms), and depositing a ferroelectric thin film for 30 minutes at 700 ° C. It is the XRD diffraction form which measured the crystallinity afterwards.
강유전체 박막의 결정성은 낮은 싸이클 즉, 두께가 얇은 경우 PLZT (111)의 배향이 우선 성장하였으며, 반면, 두꺼운 경우 (111) 보다 (110) 즉, 다결정 형태의 결정성이 나타났다.The crystallinity of the ferroelectric thin film was a low cycle, that is, when the thickness of the PLZT (111) orientation was first grown, while the thick crystal (110), that is, the crystallinity of the polycrystalline form appeared.
도3b는 박막의 표면을 측정한 것으로 결정성은 일반적인 칼럼날(columnar) 형으로 큰 그레인(grain)의 크기로 측정 되었으며, 50 싸이클(cycle)의 경우가 균일하고 균질한 표면 형태로 싸이클(cycle)이 증가 할수록 작은 구형의 그레인(grain)이 발달하였으며, 얇은 경우의 박막이 큰 그레이(grain)과 균질한 표면형태로 나타났다.Figure 3b is a measurement of the surface of the thin film, the crystallinity of the general columnar (columnar) type was measured with a large grain (grain) size, the case of 50 cycles (cycle) in the form of a uniform and homogeneous surface As this increased, small spherical grains developed, and thin films showed large grains and homogeneous surface morphology.
도4는 중간층으로 사용한 Ga2O3박막의 두께에 따른 GaN 기판과의 계면 확산 반응 관계를 조사하기 위해 AES(Auger Electron Spectroscopy) 깊이조성 분석한 결과도이다.4 is a result of AES (Auger Electron Spectroscopy) depth composition analysis to investigate the interfacial diffusion reaction relationship with the GaN substrate according to the thickness of the Ga 2 O 3 thin film used as an intermediate layer.
준비된 시료 상태의 표면 특성을 조사한 결과 물리적으로 흡착된 탄소(C KLL: 270eV) 피크 이외에는 불순물에 의한 원소들이 나타나지 않았다.As a result of examining the surface characteristics of the prepared sample state, no elements due to impurities appeared except for the physically adsorbed carbon (C KLL: 270 eV) peak.
시료의 벌크(bulk) 특성을 확인하기 위해 2 mm2면적에 대해 3 kV, 200 nA의 Ar 이온으로 시료를 에칭하면서 약 5,000 배로 확대된 표면에 10 kV의 전자를 조사하여 스펙트럼을 얻었다.In order to confirm the bulk characteristics of the sample, the spectrum was obtained by irradiating electrons of 10 kV on a surface magnified about 5,000 times while etching the sample with 3 kV and 200 nA Ar ions for an area of 2 mm 2 .
도4에서, 각 원소 즉, 산소(O KLL: 508 eV), 질소(N KLL: 381 eV), 갈륨(Ga LMM: 1066 eV)의 피크세기를 에칭시간(분)에 따라 나타내었다.In Fig. 4, the peak intensities of each element, that is, oxygen (O KLL: 508 eV), nitrogen (N KLL: 381 eV), and gallium (Ga LMM: 1066 eV) are shown according to the etching time (minutes).
싸이클(Cycle) 수가 증가 할수록 Ga2O3박막의 두께는 증가하였으며, 박막 영역에서 균일한 분포를 나타내었다. 상대적으로 두꺼운 박막의 경우, 경계에서의 내부확산은 극히 제한되었으며, 계면 반응은 크지 않았으며, 안정한 중간층의 역할을 충분히 한 것으로 판단된다.As the number of cycles increased, the thickness of the Ga 2 O 3 thin film increased and showed a uniform distribution in the thin film area. In the case of relatively thick films, the internal diffusion at the boundary was extremely limited, the interfacial reaction was not large, and it was considered that the role of the stable intermediate layer was sufficient.
도5는 MFIS와 MFMIS 박막 구조에 대한 원소의 깊이 조성 분포를 측정한 것이다.5 is a measurement of the depth composition distribution of the elements for the MFIS and MFMIS thin film structure.
분석 영역은 약 6 mm의 지름으로 Ar 이온을 이용하여 에칭하였다. 에칭된 원소의 광 방출원을 디텍터(detector)에서 세기로 측정하게 되며, 이러한 분석을 위한 장비는 GDS(Glow Discharge Spectrometer)였다. 박막의 경계면은 내부확산에 의한 계면반응이 없는 일정한 분포를 나타내었으며, 상하부에 전도성 산화물 박막을 증착한 경우 상부의 전극을 증착한 것과 마찬가지로 원소의 확산은 크게 제한 되어있다.The analysis region was etched using Ar ions with a diameter of about 6 mm. The light emitter of the etched element was measured by intensity at the detector, and the instrument for this analysis was a GDS (Glow Discharge Spectrometer). The interface of the thin film showed a constant distribution without interfacial reaction due to internal diffusion. In the case of depositing the conductive oxide thin film on the upper and lower parts, the diffusion of elements is largely limited as the upper electrode is deposited.
도6은 앞서 상술한 바와 같은 방법으로 제조된 PLZT/Ga2O3박막을 게이트 유전체에 적용한 MFMIS(Metal-Ferroelectric-Metal-insulator-GaN) 구조의 전계효과 트랜지스터를 나타내는 단면도이다.FIG. 6 is a cross-sectional view illustrating a field effect transistor having a metal-ferroelectric-metal-insulator-GaN (MFMIS) structure in which a PLZT / Ga 2 O 3 thin film manufactured by the method described above is applied to a gate dielectric.
도6에서, 실리콘 기판(1) 위에 GaN(2) 박막이 접합된 상태 또는 GaN 박막을기판으로 사용한 상태로 PLZT 강유전체를 증착하기 전 강유전성을 증가시킬 목적으로 PEALD 또는 졸-겔 법으로 Ga2O3등의 중간(buffer)층(7)을 확보하여 MFMIS 구조의 게이트를 구비한다.In Fig. 6, Ga 2 O is bonded by a silicon or sol-gel method for the purpose of increasing ferroelectricity before depositing a PLZT ferroelectric with a GaN (2) thin film bonded on a silicon substrate 1 or using a GaN thin film as a substrate. A buffer layer 7 such as 3 is secured to provide a gate of the MFMIS structure.
상기 게이트는 하부로부터 Si 기판(1), GaN 박막(2), 절연 중간(buffer)층(7), 하부전극층(11), 졸-겔 법에 의한 PLZT 박막층(8), 상부전극층(11)이 차례로 적층되며 그 위는 금 전극으로 증착한 구조를 갖는다. 여기서 상기 실리콘 기판(1) 대신에 원래의 사파이어(Al2O3) 기판을 그대로 사용하여도 무방하다.The gate is formed of a Si substrate (1), a GaN thin film (2), an insulating buffer layer (7), a lower electrode layer (11), a PLZT thin film layer (8) by a sol-gel method, and an upper electrode layer (11). It is laminated in this order and has a structure deposited on it by a gold electrode. In place of the silicon substrate 1, the original sapphire (Al 2 O 3 ) substrate may be used as it is.
도6의 구조를 갖는 전계효과트랜지스터를 제조하기 위한 방법을 구체적으로 살펴본다.A method for manufacturing a field effect transistor having the structure of FIG. 6 will be described in detail.
GaN 기판(2)에 채널 스탑 이온주입, 필드 산화 등의 세부 공정은 그 서술을 생략한다.Detailed processes, such as channel stop ion implantation and field oxidation, are omitted in the GaN substrate 2.
박막 형성 단계로서 우선 GaN 기판(2) 상에 10~50nm 두께의 중간(buffer)층(7)을 증착한다. 이어서, 중간(buffer)층(7) 상에 전도성 산화물 전극인 하부전극층(11)과, PLZT 박막층(8) 그리고 상부전극층(11)을 졸-겔 법으로 형성하고, 금속 전극을 스퍼터링으로 증착한다.As a thin film forming step, a buffer layer 7 having a thickness of 10 to 50 nm is first deposited on the GaN substrate 2. Subsequently, the lower electrode layer 11, the PLZT thin film layer 8, and the upper electrode layer 11, which are conductive oxide electrodes, are formed on the buffer layer 7 by a sol-gel method, and metal electrodes are deposited by sputtering. .
다음으로 이 적층된 박막들을 반응성 이온 식각(RIE : reactive ion etch) 방법으로 식각(etching)한 후, 고립층(9) 및 보호층(10)을 형성하기 위하여 화학 기상 증착(CVD) 법으로 실리콘 산화막(또는 실리콘 질화막)을 증착 한다. 그리고, 소스/드레인 확산층(3, 4)을 형성한다.Next, the laminated thin films are etched by reactive ion etching (RIE), and then silicon is formed by chemical vapor deposition (CVD) to form the isolation layer 9 and the protective layer 10. An oxide film (or silicon nitride film) is deposited. Then, source / drain diffusion layers 3 and 4 are formed.
미설명 부호는 활성영역(5) 및 격리영역(6)을 나타낸다.Reference numerals denote the active area 5 and the isolation area 6.
여기서 상기에서는 MFMIS 구조에 대해 설명하였으나, MFIS 구조인 경우는 상기 예에서 하부전극층(11) 만을 형성시키지 않는 방법으로 형성할 수 있으며 본 발명의 범주에 속하는 것은 자명한 것이라 할 것이다.Herein, the MFMIS structure has been described, but the MFIS structure can be formed by a method in which only the lower electrode layer 11 is not formed in the above example, and it will be obvious that it belongs to the scope of the present invention.
상기와 같이 제작된 유전체 게이트 등에 대해 강유전이력특성 측정을 하였는 바,Ferroelectric history characteristics were measured for the dielectric gate fabricated as described above.
도7은 전도성 산화물 박막을 상하부 기저전극으로 사용한 경우와 사용하지 안흔 경우의 초기상태 및 피로 후의 강유전 박막의 이력곡선을 나타낸 도이다.Fig. 7 shows the hysteresis curves of the ferroelectric thin film after the initial state and the fatigue when the conductive oxide thin film is used as the upper and lower base electrodes and when it is not used.
전도성 산화물인 LaNiO3를 상하부 전극으로 사용하였을 때 1 kHz 진동수와 160 kV/cm의 인가전기장 하에서 박막의 초기상태와 피로(fatigue)가 나타난 후의 최종상태를 측정한 것이다.When the conductive oxide LaNiO 3 was used as the upper and lower electrodes, the initial state of the thin film and the final state after fatigue were measured at 1 kHz frequency and applied electric field of 160 kV / cm.
도7에서, 박막의 피로특성은 상하부에 전도성 산화물 구조가 있는 경우에 대해 가장 좋은 특성이 나타났다. 즉, MFMIS 구조가 박막의 피로특성이 가장 우수하게 나타났다.In FIG. 7, the fatigue property of the thin film was best when the conductive oxide structure was present in the upper and lower parts. That is, the MFMIS structure showed the best fatigue properties of the thin film.
도면에는 도시하지 않았지만 PZT 박막이 GaN 위에 증착된 경우, 이력곡선의 비대칭성은 증가 하였으며, 피로특성이 크게 개선되지 않았다. 160 kV/cm의 인가전기장에서 약 12 μC/cm2의 잔류분극(remanent polarization)과 30 kV/cm의 항전기장(coercive field)을 나타내었다. 잔류분극과 항전기장 값은 기존의 금속전극을 사용하였을 때보다 낮게 나왔으며, 중간층의 역할이 내부반응에 의한 확산현상을크게 제어한 것으로 생각된다.Although not shown in the figure, when the PZT thin film was deposited on GaN, the hysteresis curve asymmetry was increased and the fatigue properties were not significantly improved. Residual polarization of about 12 μC / cm 2 and coercive field of 30 kV / cm were shown at an applied electric field of 160 kV / cm. Residual polarization and anti-electric field values are lower than those of conventional metal electrodes, and the role of the intermediate layer is thought to greatly control the diffusion phenomenon due to internal reaction.
도8은 상하부 기저전극에 따른 PLZT 강유전체 박막의 피로특성 측정도로써, 박막의 피로 특성을 50 kHz, 5 V에서 측정한 것으로 측정자료를 규격화한 것이다. 1010싸이클(cycle) 동안 LNO/PLZT/LNO/GaN의 경우가 가장 우수한 피로저항 특성을 나타내었다.FIG. 8 is a fatigue characteristic measurement diagram of a PLZT ferroelectric thin film according to upper and lower base electrodes. The fatigue characteristics of the thin film were measured at 50 kHz and 5 V, and standardized measurement data. LNO / PLZT / LNO / GaN showed the best fatigue resistance during the 10 10 cycle.
상기의 구성에 의한 본 발명은, PLZT 박막의 물성적인 측면에서 화학량론적인 제어와 대면적 증착, 저온 공정 등이 가능한 졸-겔(Sol-gel) 법으로 강유전체인 PLZT 그리고 산화물 전극으로 LNO, 중간층으로 Ga2O3박막을 GaN 단결정 기판 위에 성장시켜 강유전성(ferroelectricity)이 향상된 비파괴 독출형(Non-destructive readout-type)의 트랜지스터를 형성시켜 전기-광학 소자 응용은 물론 2T-2C, 1T-1C, MFIS, MFMIS 형의 단일트랜지스터 강유전체 메모리 소자(single transistor ferroelectric memory device)에 응용가능하다는 효과가 있다.The present invention by the above configuration, PLZT ferroelectric by the sol-gel method capable of stoichiometric control, large-area deposition, low-temperature process, etc. in terms of physical properties of the PLZT thin film and LNO, intermediate layer as the oxide electrode By growing a Ga 2 O 3 thin film on a GaN single crystal substrate to form a non-destructive readout-type transistor with improved ferroelectricity, it is possible to apply to 2T-2C, 1T-1C, It is effective to apply to single transistor ferroelectric memory device of MFIS and MFMIS type.
그리고, 페로브스카이트 구조 강유전체의 분극특성과 졸-겔법을 이용한 박막 제조로 소자 제조시 식각공정에 의해 전체를 에칭할 수 있다는 효과가 있다.In addition, there is an effect that the whole can be etched by an etching process during device fabrication by manufacturing a thin film using the polarization characteristic of the perovskite structure ferroelectric and the sol-gel method.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100802248B1 (en) * | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Non-volatile semiconductor memory device |
| US7590024B2 (en) | 2005-12-30 | 2009-09-15 | Hynix Semiconductor Inc. | Nonvolatile semiconductor memory device |
| US9634186B2 (en) | 2014-05-29 | 2017-04-25 | Samsung Electronics Co., Ltd. | Method of manufacturing light emitting device package |
| KR20180046835A (en) | 2016-10-28 | 2018-05-09 | 광주과학기술원 | Perovskite-based solar cell of large area |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100802248B1 (en) * | 2005-12-30 | 2008-02-11 | 주식회사 하이닉스반도체 | Non-volatile semiconductor memory device |
| US7590024B2 (en) | 2005-12-30 | 2009-09-15 | Hynix Semiconductor Inc. | Nonvolatile semiconductor memory device |
| US9634186B2 (en) | 2014-05-29 | 2017-04-25 | Samsung Electronics Co., Ltd. | Method of manufacturing light emitting device package |
| KR20180046835A (en) | 2016-10-28 | 2018-05-09 | 광주과학기술원 | Perovskite-based solar cell of large area |
| KR20190033494A (en) | 2016-10-28 | 2019-03-29 | 광주과학기술원 | Perovskite-based solar cell of large area |
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