JP2008270313A - Semiconductor memory element - Google Patents

Semiconductor memory element Download PDF

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JP2008270313A
JP2008270313A JP2007107808A JP2007107808A JP2008270313A JP 2008270313 A JP2008270313 A JP 2008270313A JP 2007107808 A JP2007107808 A JP 2007107808A JP 2007107808 A JP2007107808 A JP 2007107808A JP 2008270313 A JP2008270313 A JP 2008270313A
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film
semiconductor memory
memory element
semiconductor
oxygen barrier
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Japanese (ja)
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Yukihiro Kaneko
Takehisa Kato
Hiroyuki Tanaka
剛久 加藤
浩之 田中
幸広 金子
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory element that is superior in retention characteristic and can suppress the degradation of a characteristic of a semiconductor film caused by the diffusion of oxygen from an external environment or the like. <P>SOLUTION: The semiconductor memory element is comprised of a field effect transistor with an interface between a ferrodielectric film 3 and a semiconductor film 4 as a channel, and provided with a gate electrode 2 to which a voltage is applied to control the polarization of the ferrodielectric film 3 and a source electrode 5 and a drain electrode 6 that are provided at both ends of the channel and detect current flowing in the channel according to a polarization state. The semiconductor film 4 is formed of an n-type oxide semiconductor wherein an oxygen carrier film 7 is formed to cover at least the channel region of the semiconductor film 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device that maintains a change in conductivity of a channel by polarization of a ferroelectric film.

  Non-volatile memories using ferroelectrics can be broadly divided into capacitor types and FETs (Fields having a structure in which the gate insulating film of a metal-oxide-semiconductor (MOS) field effect transistor is replaced with a ferroelectric film). There are two types: Effect Transistor) type.

  The capacitor type has a structure similar to that of a dynamic random access memory (DRAM), holds charges in a ferroelectric capacitor, and distinguishes 0 and 1 of information depending on the polarization direction of the ferroelectric. Even in a state where the voltage is cut off, the polarization charge in the ferroelectric capacitor is not lost because it is combined with the charge induced in the electrodes arranged above and below it. However, since the stored information is destroyed when information is read, the nonvolatile memory having this structure requires an information rewriting operation. Therefore, the polarization inversion is repeated for each read operation, and the fatigue deterioration of the ferroelectric film accompanying the polarization inversion becomes a problem.

  In addition, in the nonvolatile memory having this structure, since the polarization charge is read by the sense amplifier, a charge amount (typically 100 fC) that is greater than the detection limit of the sense amplifier is required. Ferroelectric materials have a specific amount of polarization charge per area, and even when the memory cell is miniaturized, the electrode area must have a certain size as long as the same material is used. Therefore, it is difficult to reduce the capacitor size as the process rule becomes finer, and it is not suitable for increasing the capacity.

  On the other hand, the FET-type non-volatile memory reads information by detecting the conduction state of the channel that changes depending on the polarization direction of the ferroelectric film, so that non-destructive information reading is possible. Further, the output voltage amplitude can be increased by the amplification action of the FET, and miniaturization according to the scaling law is possible.

  To date, FET transistors have been proposed in which a ferroelectric film serving as a gate insulating film is formed on a silicon substrate serving as a channel. This structure is called MFS (Metal Ferroelectric Semiconductor) FET. In this structure, since the ferroelectric film is formed on the silicon substrate at a high temperature, there is a problem that silicon oxide is formed at the interface between the ferroelectric and the silicon substrate, and it is difficult to obtain a good interface. Since silicon oxide formed at the interface has a low dielectric constant, it causes a loss of gate application voltage, and carrier travel is scattered by the rough interface, leading to a decrease in channel mobility. Furthermore, since the internal electric field is induced in the silicon oxide layer in the state where the voltage is cut off, the polarization holding characteristic is also deteriorated.

  In order to avoid this, an MFIS (Metal Ferroelectric Insulator Semiconductor) type FET having a structure in which an insulator film is sandwiched between a silicon substrate and a ferroelectric film has been proposed. However, the MFIS type FET also has a problem that the memory retention characteristic is deteriorated due to the internal electric field generated between the depletion layer and the insulator.

Recently, a ferroelectric memory having a structure using no Si substrate in an MFS type FET has been proposed (see, for example, Patent Document 1). This has a structure in which a gate electrode, a ferroelectric film, and a semiconductor film are stacked on a substrate, and a semiconductor material that does not easily react with the ferroelectric is used for a channel. As a material of the semiconductor film, for example, an oxide such as SnO 2 or ZnO or a nitride semiconductor such as GaN is used.
JP 2005-310881 A

  However, when an n-type oxide semiconductor is used as the semiconductor film, if oxygen is adsorbed on the surface of the semiconductor film, the adsorbed oxygen draws electrons from the semiconductor film and is adsorbed as negative charges. A depletion layer with a thickness of nm is produced. When the semiconductor film is thinned, the thickness of the depletion layer cannot be ignored, and as a result, the accumulated charge held by the ferroelectric film may be eliminated and the holding characteristics may be deteriorated. In addition, at the interface between the semiconductor film and the ferroelectric film, an increase in the interface state due to oxygen deficiency may occur, resulting in a decrease in mobility due to scattering and a deterioration in retention characteristics due to trapped charges. .

  The present invention has been made in view of such a problem, and a main object thereof is to provide a semiconductor memory element having excellent retention characteristics by suppressing deterioration of characteristics of a semiconductor film due to oxygen diffusion from the external environment. .

  In order to achieve the above object, a semiconductor memory element according to the present invention includes a channel portion of a semiconductor film made of an n-type oxide semiconductor in a field effect transistor having a channel at the interface between a ferroelectric film and a semiconductor film. The structure which covers this with an oxygen barrier film is adopted.

  That is, the semiconductor memory element according to the present invention is a semiconductor memory element including a field effect transistor having a channel at the interface between the ferroelectric film and the semiconductor film, and the field effect transistor is a polarization state of the ferroelectric film. And a source electrode and a drain electrode that are provided at both ends of the channel and detect a current flowing through the channel according to the polarization state, and the semiconductor film is formed of an n-type oxide semiconductor The oxygen barrier film is formed so as to cover at least a channel portion of the semiconductor film.

  According to the semiconductor memory element of the present invention, by covering the semiconductor film corresponding to the channel portion with the oxygen barrier film, it is possible to suppress the deterioration of the characteristics of the semiconductor film due to oxygen diffusion from the external environment. A semiconductor memory element having excellent characteristics can be realized.

  Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of simplicity. In addition, this invention is not limited to the following embodiment.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor memory element according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory element in the present embodiment is composed of a field effect transistor having a channel at the interface between the ferroelectric film 3 and the semiconductor film 4, and the polarization state of the ferroelectric film 3 is changed. A gate electrode 2 to which a voltage to be controlled is applied, and source and drain electrodes 5 and 6 that are provided at both ends of the channel and detect a current flowing through the channel according to the polarization state are provided. The semiconductor film 4 is made of an n-type oxide semiconductor, and an oxygen barrier film 7 is formed so as to cover at least a channel portion of the semiconductor film 4.

  Thus, by covering the semiconductor film 4 corresponding to the channel portion with the oxygen barrier film 7, it is possible to prevent oxygen from diffusing into the semiconductor film 4 from the external environment. Thereby, characteristic deterioration of the semiconductor film 4 due to oxygen adhesion or the like can be suppressed, and a semiconductor memory element having excellent retention characteristics can be realized.

The “oxygen barrier film” in the present invention is not limited to the one that does not allow oxygen to enter, but may be one that traps the oxygen that has entered. As the oxygen barrier film 7, for example, AlN, AlO x , TiO x , TiAlO x , SiN, SiON, ZrO x , HfO x , TaO x or the like can be used. In addition, a film made of a metal oxide can be provided with an oxygen trapping property by having a metal-rich composition.

Here, for example, zinc oxide (ZnO), tin oxide (SnO 2 ), indium tin oxide (InO—SnO, ITO), or the like can be used for the semiconductor film 4. The ferroelectric film 3 is made of, for example, Pb (Zr, Ti) O 3 (PZT), SrBi 2 Ta 2 O 9 (SBT), Bi 4−X La X Ti 3 O 12 (BLT), or the like. Can do.

  Hereinafter, a specific configuration of the semiconductor memory element in the present embodiment will be described with reference to process cross-sectional views shown in FIGS. 2 (a) to 3 (d).

First, as shown in FIG. 2 (a), on a (100) surface of a substrate 1 made of conductive niobium-doped strontium titanate (SrTiO 3 : Nb, NSTO), a pulse laser deposition (PLD) method is used. A gate electrode 2 made of strontium ruthenate (SrRuO 3 , SRO) having a thickness of about 30 nm is formed at a substrate temperature of ° C.

  Next, as shown in FIG. 2B, a PZT film (ferroelectric film) 3 having a thickness of about 450 nm is formed at a substrate temperature of 700.degree. The composition of the sintered body used for the target is Pb: Zr: Ti = 1: 0.52: 0.48. The lattice mismatch with NSTO substrate 1 in this composition is 3%. Since the lattice constant of SRO (0.393 nm) is an intermediate value between the lattice constant of NSTO (0.3905 nm) and the lattice constant of PZT (0.403 nm), by inserting the SRO film 2, the NSTO substrate 1 High-quality <100> -oriented PZT film 3 can be epitaxially grown compared to directly forming PZT film 3 thereon. When the surface of the PZT film 3 formed by this method was observed with an atomic force microscope (AFM), the mean square roughness was as extremely smooth as 3 nm or less.

  Subsequently, after forming a ZnO film (semiconductor film) 4 having a thickness of about 30 nm at a substrate temperature of 400 ° C. in the same chamber of the PLD apparatus, a ZnO film other than the element region is formed as shown in FIG. 4 is removed.

  Next, as shown in FIG. 2D, after patterning the resist film 14, a Ti film 5 having a thickness of about 30 nm and a Pt film 6 having a thickness of about 60 nm are formed by electron beam evaporation. Thereafter, the resist film 14 is removed, thereby forming source and drain electrodes 5 and 6 on the ZnO film 4 as shown in FIG.

  Next, as shown in FIG. 3A, an AlN film (oxygen barrier film) 7 having a thickness of about 100 nm is formed by a sputtering method with a DC power of 2 kW, an RF power of 15 W, and a substrate temperature of 200 ° C. To do.

  Next, as shown in FIG. 3B, after patterning a resist film 15 on the AlN film 7, the AlN film 7 is etched by an ISM (Inductively Super Magnetron) type plasma etching apparatus to obtain source and drain electrodes. Openings are formed on 5 and 6.

  Next, as shown in FIG. 3C, with the resist film 15 left (the resist film 15 may be removed and then a new resist film may be patterned), the thickness is increased by electron beam evaporation. A Ti film 8 having a thickness of about 10 nm and a Pt film 9 having a thickness of about 190 nm are formed.

  Finally, as shown in FIG. 3D, the resist film 15 is removed to form metal electrodes connected to the source and drain electrodes 5 and 6 to complete the semiconductor memory element shown in FIG. To do.

In the present embodiment, it is known that the number of carriers of ZnO used as the semiconductor film 4 increases when hydrogen is taken into the film. As the number of carriers increases, the resistance decreases, and there is a risk of deterioration of the on / off ratio due to an increase in off current and a change in threshold voltage. Therefore, the oxygen barrier film 7 is preferably a material further having hydrogen barrier properties. Examples of such a film include Al 2 O 3 , SiN, and SiON.

  The oxygen barrier film 7 having such a hydrogen barrier property is also useful when the ferroelectric film 3 is made of a metal oxide such as PZT. That is, it is known that such a ferroelectric film is deteriorated in remanent polarization and retention characteristics of the ferroelectric film by being reduced with hydrogen. Therefore, the deterioration of the ferroelectric film can be suppressed by preventing the intrusion of hydrogen entering from the external environment or the hydrogen generated in the manufacturing process.

FIG. 4 is a graph showing the polarization characteristics of a capacitor having a Pt / Ti / ZnO / PZT / SRO structure. 4A shows a case where a silicon oxide (SiO 2 ) film (thickness 200 nm) formed using silane (SiH 4 ) as a raw material by a plasma CVD method is used as an oxygen barrier film, and FIG. A laminated film of an AlN film (thickness 100 nm) formed by the method and a silicon nitride (SiN) film (thickness 100 nm) formed on the AlN film by using a silane gas and ammonia (NH 3 ) as a raw material by the plasma CVD method Polarization characteristics when used as an oxygen barrier film are shown. For comparison, the results without the oxygen barrier film are also shown.

From FIG. 4A, the polarization-voltage characteristic obtained by applying a voltage of ± 10 V between the NSTO substrate 1 and the electrode shows the difference in remanent polarization value at 0 V compared to the case without the SiO 2 film. It can be seen that the characteristics of the PZT film (ferroelectric film) are deteriorated. This is presumably because hydrogen contained in silane deteriorates the characteristics of the ferroelectric film due to decomposition of silane as a raw material when SiO 2 is formed using plasma CVD. On the other hand, in the case of the SiN / AlN laminated oxygen barrier film shown in FIG. Although the silane is used when the SiN film is laminated, the characteristics are not deteriorated, which indicates that the AlN film also functions as a hydrogen barrier film.

  By the way, in order to ensure the barrier property of the oxygen barrier film 7, it is preferable to increase the film thickness to some extent, for example, 100 nm or more. However, for example, when the AlN film 7 having good crystallinity is formed by increasing the RF power, if the film thickness is greater than 100 nm, the film may be peeled off due to the influence of compressive residual stress. Further, when the RF power is reduced, active nitrogen is reduced, so that the nitrogen content in the AlN film 7 is lowered, the crystallinity is lowered, and as a result, the leakage current may be increased. Therefore, when forming the AlN film 7 having a thickness of 100 nm or more, the RF power is first increased to form the AlN film 7 having good crystallinity, and then the RF power is decreased to form the AlN film 7 in order to relieve stress. Good. Alternatively, by laminating a nitride film such as SiN on the AlN film 7, stress can be alleviated, film peeling does not occur, and good oxygen barrier properties can be obtained.

  Next, the operation of the semiconductor memory element in this embodiment will be described with reference to FIGS.

When the carrier concentration of the ZnO film 4 formed on the PZT film 3 was determined by hole measurement, it was 8 × 10 17 cm −3 . Since the thickness of the ZnO film 4 is 30 nm, the carrier density per unit area is 2.4 × 10 12 cm −2 . The charge density obtained by multiplying this by an elementary charge amount of 1.6 × 10 −19 C is 0.4 μC / cm 2 , which is smaller than the polarization charge density of PZT. Therefore, as shown in FIG. 5A, when a negative voltage is applied to the NSTO substrate 1 with respect to the source and drain electrodes 5 and 6, the polarization of the PZT film 3 is downward as shown by the arrows in the figure. Thus, as a result of repelling polarization and driving away carriers, the entire ZnO film 4 is depleted. On the other hand, as shown in FIG. 5B, when a positive voltage is applied to the NSTO substrate 1 with respect to the source and drain electrodes 5 and 6, the polarization of the PZT film 3 becomes upward, and the density corresponding to the polarization density is obtained. Carriers are induced at the interface.

FIG. 6 is a graph showing measurement results of capacitance-voltage (C-V) characteristics. A curve 61 in the figure shows a Pt / Ti electrode (electrode area 6.2 × 10 −5 cm 2) on the PZT film 3. ) Is directly formed (Pt / Ti / PZT / SRO / NSTO structure), a curve 62 indicates a structure in which a Pt / Ti electrode is formed on a structure in which the ZnO film 4 and the PZT film 3 are stacked (Pt / Ti). / ZnO / PZT / SRO / NSTO structure). In the Pt / Ti / PZT / SRO / NSTO structure, the capacitance values when +10 V and −10 V are applied to the NSTO substrate 1 are equal to about 40 pF, respectively. On the other hand, in the Pt / Ti / ZnO / PZT / NSTO structure, the capacitance value at −10 V application is as small as 24 pF compared to the capacitance value 40 pF at +10 V application. This is proof that the ZnO film 4 is in an accumulation state and a depletion state with respect to positive and negative of the substrate voltage.

  As described above, the voltage applied to the NSTO substrate 1 can realize two states in which electric charges are present or absent at the interface between the ferroelectric film 3 and the semiconductor film 4. In these two states, the interface conductivity changes greatly, and the current flowing between the source and drain electrodes on the ZnO film 4 also changes. The Fermi level of the Ti film 5 serving as the source and drain electrodes is at a higher energy position than the conduction band of the ZnO film 4 and is a good ohmic electrode. Therefore, the efficiency is high when a voltage is applied between the source and drain electrodes to read the conduction current due to the interface charge.

  As shown in FIG. 7, the gate voltage Vg is applied to the terminal 71 connected to the NSTO substrate 1, the source electrode terminal 72 is grounded, the drain electrode terminal 73 is applied with the drain voltage Vd = 1V, and the drain current The result of measuring Id is shown in FIG. When Vg is scanned from −10 V to +10 V and when Vg is scanned from +10 V to −10 V, different loci (hysteresis) are drawn. The drain current at each Vg = 0V is 1 nA or less and 1 μA or more, and a current ratio of 3 digits or more is obtained. The reason why the current value is different even when no voltage is applied to the gate electrode is that depletion / accumulation of the interface charge is retained by the residual polarization of the ferroelectric film 3. By making the drain current large and small correspond to the binary data “1” and “0”, this element functions as a memory. Moreover, even if the voltage is cut off, the residual polarization of the ferroelectric film 3 is preserved, so that a nonvolatile memory can be realized. Actually, when the drain current was measured after the semiconductor memory element according to the present embodiment was allowed to stand at room temperature for 16 hours, it was confirmed that the three-digit drain current ratio was maintained.

  In summary, the data “1” and “0” can be written by applying a positive voltage or a negative voltage to the NSTO substrate 1. Further, data can be read as “1” when the gate electrode is grounded and a voltage is applied between the source and drain electrodes and the flowing drain current is large and “0” when the drain current is small.

(Second Embodiment)
9A and 9B are diagrams schematically showing a configuration of a semiconductor memory cell according to the second embodiment of the present invention, where FIG. 9A is a cross-sectional view and FIG. 9B is an equivalent circuit. The semiconductor memory cell in this embodiment has a configuration in which a MISFET (selection switch) 91 and an MFSFET (ferroelectric memory element) 92 are connected in series as shown in FIG. 9B. Note that the source electrode 13b of the MISFET 91 and the drain electrode 13c of the MFSFET 92 are electrically connected to have a common potential.

  As shown in FIG. 9A, on the (100) surface of the NSTO substrate 1, the gate electrode of the MFSFET 92 made of the SRO film 2 with a thickness of 30 nm and the gate insulating film of the MFSFET 92 made of the PZT film 3 with a thickness of 450 nm. Is formed. Further, on the PZT film 3, a n-type ZnO film 4 having a thickness of 30 nm, a channel common to the MISFET 91 and the MFSFET 92, and a laminated film of a Ti film 5 having a thickness of 30 nm and a Pt film 6 having a thickness of 60 nm are formed. The source and drain electrodes common to MISFET 91 and MFSFET 92 are formed. On the ZnO film 4, a gate insulating film of a MISFET 91 made of a magnesium oxide (MgO) film 10 having a thickness of 50 nm and a gate electrode of the MISFET 91 made of a Pt film 11 having a thickness of 60 nm are formed. Further, an oxygen barrier film made of an AlN film 7 having a thickness of 100 nm is formed on the MgO film 10. On the AlN film 7, aluminum wirings 13a to 13d connected to the source and drain electrodes through tungsten plugs 12 are formed. Here, the MISFET 91 has a top gate structure in which the gate electrode 11 is disposed above the channel (ZnO film 4), and the MFSFET 92 has a bottom gate structure in which the gate electrode 2 is disposed below the channel (ZnO film 4). I am doing.

  10A to 10D are process cross-sectional views illustrating a method for manufacturing a semiconductor memory cell according to the present embodiment. Note that detailed description of steps common to the method of manufacturing the semiconductor memory element (MFSFET) in the first embodiment is omitted.

  First, as shown in FIG. 10A, the gate electrode of the MFSFET 92 made of the SRO film 2 having a thickness of 30 nm is formed on the NSTO substrate 1 using the PLD method. Thereafter, a PZT film 3 having a thickness of 450 nm and a ZnO film 4 having a thickness of 30 nm are continuously formed on the substrate 1 in the same chamber of the PLD apparatus.

  Next, as shown in FIG. 10B, a source / drain composed of a laminated film of a 30 nm thick Ti film 5 and a 60 nm thick Pt film 6 on the ZnO film 4 by using a resist lift-off method. An electrode is formed. Thereafter, a gate insulating film of the MISFET 91 made of the MgO film 10 having a thickness of 50 nm is formed on the ZnO film 4 by sputtering.

  Next, as shown in FIG. 10C, a gate electrode of a MISFET 91 composed of a Pt film 11 having a thickness of 60 nm formed by electron beam evaporation is formed on the MgO film 10 by using a resist lift-off method. . Thereafter, an oxygen barrier film made of an AlN film 7 having a thickness of 100 nm is formed on the MgO film 10 by sputtering.

  Finally, as shown in FIG. 10D, after the W plug 12 connected to the source and drain electrodes is formed in the AlN film 7, Al is formed on the AlN film 7 by sputtering. Then, the wirings 13a to 13d etched in a predetermined pattern are formed, and the semiconductor memory cell shown in FIG. 9A is completed.

  Next, the operation of the semiconductor memory cell in the present embodiment will be described with reference to FIGS. 11, 12A, and 12B.

  As shown in FIG. 11, in the non-access state, the gate electrode (first gate electrode) 2 of the MFSFET 92, the gate electrode (second gate electrode) 11 of the MISFET 91, and the source electrode 13d are grounded. By grounding the second gate electrode 11, the MISFET 91 is turned off. Even if an arbitrary voltage is applied to the drain electrode 13 a, no erroneous writing occurs in the MFSFET 92.

  In the data write operation, a positive voltage (for example, 12V) is applied to the second gate electrode 11 to turn on the MISFET 91, and then a voltage is applied to the drain electrode 13a and the first gate electrode 2, and a channel (ZnO A write voltage is applied between the film 4 and the first gate electrode 2. That is, in the case of data “1”, the drain electrode 13 a is grounded, and a positive voltage (for example, 10 V) is applied to the first gate electrode 2. In the case of data “0”, the first gate electrode 2 is grounded, and a positive voltage (for example, 10 V) is applied to the drain electrode 13a. Thus, in the case of data “1”, the polarization of the ferroelectric gate insulating film (PZT film) 3 of the MFSFET 92 is directed upward (channel 4 direction) as shown in FIG. In the case of “0”, the polarization is directed downward (in the direction of the first gate electrode 2) as shown in FIG.

  In the data read operation, the first gate electrode 2 is grounded, a positive voltage (for example, 12V) is applied to the second gate electrode 11, and the MISFET 91 is turned on. A voltage (for example, 1 V) is applied between the electrodes 13d, and “1” can be read if the flowing drain current is large, and “0” can be read if small.

(Third embodiment)
FIG. 13 is a cross-sectional view schematically showing the configuration of the semiconductor memory element according to the third embodiment of the present invention. In the first embodiment, a conductive substrate is used as the substrate 1, but in this embodiment, a silicon substrate is used as the substrate 21. Note that the basic configuration of the semiconductor memory element is the same as that of the first embodiment, and writing and reading operations can be performed in the same manner.

As shown in FIG. 13, a SiO 2 film 22 is formed on a silicon substrate 21, and a gate electrode made of a Pt film 2 having a (111) -oriented thickness of 100 nm is formed thereon. On the Pt film 2, a ferroelectric film made of a bismuth titanate (Bi 4 Ti 3 O 12 , hereinafter referred to as BIT) film 3 having a thickness of 100 nm is formed.

  Here, for example, the BIT film 3 is formed in a state where the Bi alkoxide and Ti alkoxide, which are solid, are dissolved in ethylcyclohexane and vaporized and used as a source, and the substrate temperature is set to 450 ° C. by the MOCVD method. The source flow ratio of Bi and Ti is preferably a ratio in the range of about 10% Bi rich from the stoichiometric ratio. To this, argon as a carrier gas is added and introduced into a film forming chamber, and oxygen as a reactive gas is introduced. The formed film is rapidly heated at 500 ° C. by irradiating a halogen lamp in the atmosphere for 1 minute. The BIT film 3 formed under these conditions is a film in which grains having (110) and (111) orientations are mixed.

  A semiconductor film made of a 30 nm thick ZnO film 4 is formed on the BIT film 3, and a laminated film of a 30 nm thick Ti film 5 and a 60 nm thick Pt film 6 is formed on the ZnO film 4. Source and drain electrodes are formed. Furthermore, an oxygen barrier film made of an AlN film 7 having a thickness of 100 nm is formed on the ZnO film 4 so as to cover the source and drain electrodes 5 and 6. On the AlN film 7, a wiring made of a laminated film of a 10 nm thick Ti film 8 and a 190 nm thick Pt film 9 connected to the source and drain electrodes is formed.

  In this embodiment, the oxygen barrier film 7 can prevent the semiconductor film (ZnO film) 4 from being deteriorated, and a semiconductor memory element can be formed on the silicon substrate 21 on which a CMOS circuit or the like is formed. Thus, a semiconductor integrated circuit in which the semiconductor memory element and the CMOS circuit are integrated can be realized.

As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course various modifications are possible. For example, in the above-described embodiment, the substrate itself is conductive, but a conductive material may be laminated on the substrate. In addition to the materials used in the above embodiment, for example, sapphire and lanthanum aluminum oxide (LaAlO 3 ) are used for the substrate, and WO 3 , IGZO (InGaO 3 (ZnO) 5 ), and STO are used for the semiconductor film. , LSCO (La 2-X Sr X CuO 4), LCMO (La 1-X Ca X MnO 3), being transparent such PCMO (Pr 1-X Ca X MnO 3), which exhibits superconductivity, the Mott transition As shown, nitrides such as GaN, InN, InGaN, and AlN can be used.

The oxygen barrier film may be made of a conductive material such as Ir, IrO 2 , Ru, RuO 2 , TiAlN, TaAlN, TiSiN, TaSiN. In particular, in a MFSFET having a so-called top-gate structure in which the gate electrode is formed above the channel region and at least overlaps with the channel region, the conductive oxygen barrier film covers at least the gate electrode. By forming in this way, it is possible to prevent deterioration of the semiconductor film constituting the channel due to oxygen. In this case, the conductive oxygen barrier film may constitute a part of the gate electrode.

  The present invention is useful for a semiconductor memory element including a field effect transistor in which a gate insulating film is composed of a ferroelectric film.

It is sectional drawing which showed the structure of the semiconductor memory element in the 1st Embodiment of this invention. (A)-(e) is process sectional drawing which showed the manufacturing method of the semiconductor memory element in the 1st Embodiment of this invention. (A)-(d) is process sectional drawing which showed the manufacturing method of the semiconductor memory element in the 1st Embodiment of this invention. 6 is a graph showing polarization-voltage (P-V) characteristics of a semiconductor memory element, where (a) shows the PV characteristics when a conventional protective film is used, and (b) shows the protective film (1) according to the first embodiment. It is the graph which showed the PV characteristic at the time of using an oxygen barrier film | membrane. 5A and 5B are diagrams illustrating a write operation of the semiconductor memory element according to the first embodiment. FIG. 5A illustrates a case where data “0” (depletion state) is written, and FIG. 5B illustrates a case where data “1” (accumulation state) is written. It is the figure which showed the operation | movement in the case. 5 is a graph showing CV characteristics of the semiconductor memory element in the first embodiment. 6 is a diagram illustrating a read operation of the semiconductor memory element in the first embodiment. FIG. 5 is a graph showing drain current-gate voltage characteristics of the semiconductor memory element in the first embodiment. 4A and 4B are diagrams illustrating a configuration of a semiconductor memory cell according to a second embodiment of the present invention, where FIG. 5A is a cross-sectional view, and FIG. (A)-(d) is process sectional drawing which showed the manufacturing method of the semiconductor memory cell in the 2nd Embodiment of this invention. It is a figure explaining the write-in and read-out operation | movement of the semiconductor memory cell in 2nd Embodiment. FIG. 6A is a diagram illustrating a write operation of a semiconductor memory cell according to the second embodiment. FIG. 5A illustrates a case where data “1” (accumulation state) is written, and FIG. 5B illustrates a case where data “0” (depletion state) is written. It is the figure which showed the operation | movement in the case. It is sectional drawing which showed the structure of the semiconductor memory element in the 3rd Embodiment of this invention.

Explanation of symbols

1 NSTO substrate 2 Gate electrode (SRO film or Pt film)
3 Ferroelectric film (PZT film or BIT film)
4 Semiconductor film (ZnO film)
5, 6 Source and drain electrodes (Ti film / Pt film)
7 Oxygen barrier film (AlN film)
8, 9 Wiring (Ti film / Pt film)
10 Gate insulating film (MgO film)
11 Gate electrode (Pt film)
12 W plugs 13a to 13d Wirings 14 and 15 Resist film 21 Silicon substrate 22 SiO 2 film 91 MISFET
92 MFSFET

Claims (9)

  1. A semiconductor memory element including a field effect transistor having a channel at an interface between a ferroelectric film and a semiconductor film,
    The field effect transistor is
    A gate electrode to which a voltage for controlling the polarization state of the ferroelectric film is applied;
    Source and drain electrodes provided at both ends of the channel and detecting current flowing through the channel according to the polarization state,
    The semiconductor film is made of an n-type oxide semiconductor,
    A semiconductor memory element, wherein an oxygen barrier film is formed so as to cover at least the channel portion of the semiconductor film.
  2.   The semiconductor memory element according to claim 1, wherein the semiconductor film is made of zinc oxide, tin oxide, or indium tin oxide.
  3. The oxygen barrier film is made of at least one material selected from the group consisting of AlN, AlO x , TiO x , TiAlO x , SiN, SiON, ZrO x , HfO x , and TaO x. Semiconductor memory device.
  4. The gate electrode is formed above the channel part and at least in a region overlapping with the channel part,
    The semiconductor memory element according to claim 1, wherein the oxygen barrier film is formed so as to cover at least the gate electrode.
  5.   The semiconductor memory element according to claim 4, wherein the oxygen barrier film constitutes a part of the gate electrode.
  6. 5. The semiconductor memory element according to claim 4, wherein the oxygen barrier film is made of at least one material selected from the group consisting of Ir, IrO 2 , Ru, RuO 2 , TiAlN, TaAlN, TiSiN, and TaSiN.
  7. The ferroelectric film is made of a metal oxide,
    The semiconductor memory element according to claim 1, wherein the oxygen barrier film is made of a material further having a hydrogen barrier property.
  8.   The semiconductor memory element according to claim 1, wherein the oxygen barrier film includes a stress relaxation layer that relaxes stress in the oxygen barrier film.
  9.   The semiconductor memory element according to claim 3, wherein the oxygen barrier film is made of a metal-rich metal oxide.
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