CN102208442B - 一种适合于半导体闪存器件的栅叠层结构及制备方法 - Google Patents
一种适合于半导体闪存器件的栅叠层结构及制备方法 Download PDFInfo
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims abstract description 28
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- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000002159 nanocrystal Substances 0.000 claims abstract description 16
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Abstract
本发明涉及一种适合于半导体闪存器件的栅叠层结构及其制备方法。该栅叠层结构以晶向为100的P型单晶硅片为衬底,自下而上依次为:Al2O3薄膜,作为电荷隧穿层;钌基RuOx纳米晶,作为第一电荷俘获层;高介电常数HfxAlyOz薄膜,作为第二电荷俘获层;Al2O3薄膜,充当电荷阻挡层;上电极层。本发明中,钌基RuOx纳米晶具有很好的热稳定性,在高温下不容易扩散;高介电常数HfxAlyOz薄膜具有较高的电荷陷阱密度;上电极采用金属钯,拥有较大的功函数。因此该栅叠层结构在纳米晶存储电容器中有广阔的应用前景。
Description
技术领域
本发明属于半导体集成电路制造技术领域,具体涉及一种快闪存储器的电容结构和制备方法,尤其涉及一种基于金属纳米晶和高介电常数介质构成其中新型异质电荷俘获层的栅叠层结构及制备方法。
背景技术
随着半导体工艺技术的不断发展,非挥发性快闪存储器集成密度越来越高、操作电压越来越低,这就驱使器件特征尺寸持续减小,在65 nm技术节点之后传统的多晶硅浮栅结构出现了一系列的问题,极大地影响了器件存储的性能,诸如擦写速度慢,工作电压高等。
基于非连续电荷俘获机理(如纳米晶、SONOS存储器等)的新一代非挥发性存储器最近引起了广泛关注,它们采用分离的电荷陷阱代替连续的多晶硅浮栅存储电荷,使得隧穿层中存在的局部缺陷不会引起电荷俘获层中大量的电荷流失,从而有效地提高了存储器的数据保存能力,并且可以获得更低的操作电压,实现更快的擦写速度等。
与半导体纳米晶相比,金属纳米晶在费米能级附近有更高的态密度,功函数的选择范围更广,与衬底沟道有较强的耦合等,故其能够实现较低的操作电压、较高密度的电荷存储和较长时间的电荷保留。研究表明,通过选择具有较大功函数的金属纳米晶,可以形成较深的势阱,从而有效地俘获电荷并能提供更好的数据保存特性。
另一方面,随着SONOS存储器的发展,采用高介电常数材料(High-k)代替SONOS中的氮化硅电荷俘获层,能够相应地增加降落在隧穿层上的电场强度,从而提高编程和擦除速度。但是这种结构存储器的缺点是其操作电压较高,并且操作速度较慢。
发明内容
本发明的目的是提供一种存储电荷密度高、操作电压低、擦写速度快且电荷保持特性好的适合于半导体闪存器件的栅叠层结构。本发明的再一目的是提供上述栅叠层结构的制备方法。
为了达到上述目的,本发明的技术方案是提供一种适合于半导体闪存器件的栅叠层结构及制备方法。
其中所述栅叠层结构,包含有基于金属纳米晶和高介电常数薄膜的异质电荷俘获层;所述栅叠层结构中,由下至上依次设置有:
晶向为100的P型单晶硅片,作为衬底;
原子层淀积的Al2O3薄膜,作为电荷隧穿层,厚度为5~15纳米;
所述异质电荷俘获层,其进一步包含有:
所述金属纳米晶作为第一电荷俘获层,该纳米晶为钌和氧化钌的复合物,记为钌基RuOx纳米晶;
原子层淀积的所述高介电常数薄膜作为第二电荷俘获层,厚度为5~10纳米;所述高介电常数介质为HfxAlyOz,其中x>0,z>0且y=0或y>0;
原子层淀积的Al2O3薄膜,作为电荷阻挡层,厚度为15~40纳米;
上电极层。
所述高介电常数薄膜是HfAlO薄膜,其中包含淀积循环数之比为1:1的HfO2和Al2O3;或者,所述高介电常数薄膜是HfO2薄膜。
所述上电极层包含以金属钯形成的栅电极。
上述栅叠层结构的制备方法,具体包含以下步骤:
步骤1、采用晶向为100的P型单晶硅片作为衬底;
步骤2、采用原子层淀积的方法生长5~15纳米厚的Al2O3薄膜作为电荷隧穿层;
步骤3.1、采用磁控溅射淀积的方法,在Al2O3隧穿层上淀积厚度为2~4纳米的金属钌层,然后在氮气气氛中进行快速热退火处理,形成钌基RuOx纳米晶作为异质电荷俘获层的第一电荷俘获层;所述钌基RuOx纳米晶为钌和氧化钌的复合物;
步骤3.2、采用原子层淀积的方法生长5~10纳米厚的高介电常数HfxAlyOz薄膜作为异质电荷俘获层的第二电荷俘获层:所述高介电常数HfxAlyOz薄膜中x>0,z>0,同时y=0或y>0;其中Hf与Al的组成通过原子层淀积HfO2和Al2O3的循环数来确定;
步骤4、采用原子层淀积的方法生长15~40纳米厚的Al2O3薄膜作为电荷阻挡层,然后进行快速热退火处理;
步骤5、用光刻工艺,采用剥离方法形成50~200纳米厚的栅电极作为上电极层。
所述步骤3.2中所述高介电常数HfxAlyOz薄膜是HfAlO薄膜,其中包含淀积循环数之比为1:1的HfO2和Al2O3;或者,所述高介电常数HfxAlyOz薄膜是HfO2薄膜。
所述步骤3.2中原子层淀积生长HfO2的条件是:衬底温度在250~350℃,反应前躯体为四(乙基甲胺基)铪和水蒸汽。
所述步骤2、步骤3.2或步骤4中原子层淀积生成所述Al2O3薄膜的条件是:衬底温度在250~350℃,反应前躯体为三甲基铝和水蒸汽。
所述步骤3.1中形成钌基RuOx纳米晶时的退火温度为700~900℃,退火时间为10~30秒;步骤4中形成电荷阻挡层Al2O3薄膜时的退火温度为500~800 ℃,退火时间为10~30 秒。
所述步骤5中形成所述栅电极的材料为金属钯。
所述制备方法还包含:
步骤6、先用氢氟酸去除衬底背面的自然氧化层,然后淀积一层金属铝层作为下电极,以形成良好的欧姆接触。
本发明所述适合于半导体闪存器件的栅叠层结构及制备方法,具有以下优点:
1、采用磁控溅射淀积形成超薄金属钌膜,通过调节淀积功率、时间、衬底温度等,能够在高真空度下比较精确地控制薄膜的厚度和淀积速率,以形成超薄且均匀的金属膜,这使得退火后更易形成直径小、分布均匀且密度高的纳米晶颗粒。
2、第一电荷俘获层采用钌基RuOx纳米晶作为电荷存储中心,由于它们的功函数较高(4.7~5.2 eV),所以能提供较大的势阱深度,有利于提高电荷的存储能力。本发明中该金属纳米晶的形成温度与存储器的制作工艺温度相兼容,没有超过器件制作中源、漏离子注入后的激活退火温度。
3、第二电荷俘获层采用高介电常数介质HfxAlyOz作为存储中心,由于HfxAlyOz的介电常数高(10~25),能够有效地增加了降落在隧穿层上的电场强度,从而提高了存储器的编程和擦除速度,并且降低了操作电压。同时,HfxAlyOz材料能提供足够多的电荷陷阱,用来存储电荷。
4、由高介电常数HfxAlyOz与高密度的钌基RuOx纳米晶组成的异质电荷俘获层,可以共同俘获来自衬底的电荷注入,大大提高了电荷的存储密度。此外,高密度钌基RuOx纳米晶嵌入到HfxAlyOz薄膜中,有效地抑制了HfxAlyOz介质在高温退火后发生结晶,因此减小了沿着晶粒间界的电荷泄漏,提高了存储器的电荷保持特性。
5、采用原子层淀积的方法制备HfxAlyOz薄膜,不仅可以精确地控制薄膜的组成和厚度,还能有效填充间距在纳米量级的缝隙,从而使得RuOx纳米晶能被HfxAlyOz完全隔离开。
6、采用金属钯作为电极,不仅可以和阻挡层的氧化铝介质形成利于擦写的垫垒,且钯不易被氧化,具有很好的化学稳定性和热稳定性。利用电子束蒸发设备在高真空下生长钯薄膜,此方面生长的钯膜与氧化铝介质能形成很好的接触界面,从而提高了电容存储器的性能。
因此,本发明所提出的栅叠层结构将在下一代快闪存储器上具有很好的应用前景。
附图说明
图1 是本发明中基于钌基RuOx纳米晶和高介电常数HfxAlyOz薄膜的异质电荷俘获层构成栅叠层结构存储电容器的剖面结构图;
图2 是本发明所述栅叠层结构存储电容器在不同电压下编程/擦除0.1毫秒后的平带电压变化图;
图3是本发明所述栅叠层结构存储电容器在+/-9 V编程/擦除不同时间后的平带电压变化图;
图4是本发明所述栅叠层结构存储电容器在+9 V编程、-9 V擦除1毫秒后的电荷保持特性。
具体实施方式
参见图1所示,本发明所述适合于半导体闪存器件的栅叠层结构,特别是包含有基于金属纳米晶和高介电常数薄膜的异质电荷俘获层,以此构成的所述快闪存储电容中,由下至上依次设置有:
1) 晶向为100的P型单晶硅片作为衬底;
2) 原子层淀积的Al2O3薄膜,作为电荷隧穿层,厚度为5~15纳米;
3) 所述异质电荷俘获层,其进一步包含有:
金属纳米晶作为第一电荷俘获层,该纳米晶为钌和氧化钌的复合物(记为钌基RuOx纳米晶);
原子层淀积的高介电常数薄膜作为第二电荷俘获层,厚度为3~20纳米(优选的厚度范围在5~10纳米);所述高介电常数介质为HfxAlyOz(x>0,z>0,y=0或y>0),它的介电常数在10~25之间;
4) 原子层淀积的Al2O3薄膜,充当电荷阻挡层,厚度为15~40纳米;
5) 上电极层,包含以金属钯(Pd)形成的栅电极。
上述栅叠层结构中包含异质电荷俘获层构成的存储电容,其制备方法如下:
步骤1、采用晶向为100的P型单晶硅片作为衬底,硅片的电阻率为8~12欧姆·厘米。首先对硅片进行标准清洗,并利用稀氢氟酸去除残留的自然氧化层。
步骤2、电荷隧穿层Al2O3的形成:以三甲基铝和水蒸汽为反应源,采用原子层淀积的方法生长Al2O3薄膜,衬底温度控制在250~350℃范围内。Al2O3隧穿层厚度控制在5~15纳米范围内。
步骤3.1、异质电荷俘获层中钌基RuOx纳米晶的形成:采用磁控溅射淀积的方法,在Al2O3隧穿层上淀积超薄金属钌层,钌层的厚度为2~4纳米,然后在氮气气氛中进行快速快速热退火,即可形成钌基RuOx纳米晶作为第一电荷俘获层。退火温度为700~900℃,退火时间为10~30秒。
步骤3.2、异质电荷俘获层中高介电常数介质HfxAlyOz薄膜的形成:采用原子层淀积的方法生长HfxAlyOz薄膜作为第二电荷俘获层:
所述HfxAlyOz薄膜的一种组成包含HfO2和Al2O3,两者的淀积循环数之比为1:1,记为HfAlO。所述HfxAlyOz薄膜的另一种组成中不含Al2O3,即为纯HfO2。
上述两种组成中,衬底温度控制在250~350℃范围内,HfO2的反应源为四(乙基甲胺基)铪(TEMAH)和水蒸汽。Al2O3的制备条件如步骤(2)所述。
HfAlO或HfO2薄膜的厚度均为3~20纳米(优选的厚度范围在5~10纳米)。根据所述HfxAlyOz薄膜的厚度不同,如果其厚度较小时,该HfxAlyOz薄膜会填到所述钌基RuOx纳米晶之间,但不会填满该纳米晶之间的间隙;如果其厚度较大时,所述HfxAlyOz薄膜则会填满所述钌基RuOx纳米晶之间的间隙,图1中仅示出了后一种情况。
步骤4、电荷阻挡层Al2O3薄膜的形成:采用步骤(2)中所述的方法淀积15~40纳米厚的Al2O3薄膜。然后,将所得样品在氮气中进行快速热退火处理,快速热退火温度为500~800 ℃,时间为10~30 秒。目的是获得高质量的Al2O3阻挡层,抑制电荷的泄漏。
步骤5、上电极层的形成:采用剥离(lift-off)方法形成栅电极,即首先通过光刻形成图形,接着利用电子束蒸发设备生长钯金属薄膜,膜厚为50~200纳米。最后,利用丙酮清洗剩余的光刻胶。
步骤6、为了方便器件性能的测量,先用氢氟酸去除衬底背面的自然氧化层,然后淀积一层金属铝层作为下电极,以形成良好的欧姆接触,至此完成本发明所述栅叠层结构包含异质电荷俘获层的存储电容的制作工艺。
图2为本实例中所述栅叠层结构中包含异质电荷俘获层构成的存储电容,在不同电压下编程和擦除0.1毫秒后的平带电压变化图。由图可知,随着正向偏压的增大,所得平带电压均向正方向漂移,这是由于电子注入导致负电荷的俘获造成的。随着负向偏压的增大,所得的平带电压均向负方向漂移,这是由于电荷俘获层中被俘获的电荷发生释放或来自衬底的空穴注入所造成的。此外,可以观察到在相同操作电压下,RuOx/HfO2异质电荷俘获层比RuOx/HfAlO异质电荷俘获层能提供更大的存储窗口,例如,在6 V的操作电压下,前者的存储窗口为2.6 V,后者则为1.4 V。
图3为本实例中所述存储电容在+9V编程/-9V擦除不同时间后的平带电压变化图。由图可知,两个电容在编程/擦除状态下的平带电压均随着脉冲时间的增加而增大,并最终趋向饱和。对于0.1毫秒的编程/擦除,基于RuOx/HfAlO电荷俘获层的器件所得到的存储窗口接近2V,基于RuOx/HfO2电荷俘获层的器件所得到的存储窗口达到3.5V。二者均表现出了低压下快速编程和擦除的功能。
图4为本实例中所述存储电容在+9 V、1毫秒编程和-9 V、1毫秒擦除后的保持特性。当异质电荷俘获层中的介质为HfO2时,外推至十年后该存储电容器的存储窗口约为3.4 V,显示出了优良的保持特性;当异质电荷俘获层中的介质为HfAlO时,其相应的存储窗口约为1.6 V。
上述结果表明,基于RuOx和HfxAlyOz的异质电荷俘获层的存储电容均表现出了低压下快速擦写的功能,以及良好的电荷保存特性。
综上所述,本发明充分结合了金属纳米晶和高介电常数介质的优点,并以此构成了栅叠层结构中的异质电荷俘获层:这种新型异质电荷俘获层中由于引入了高介电常数介质,所以可以增加降落在电荷隧穿层上的电场强度,达到降低电荷注入的势垒,从而提高存储器的编程和擦除速度,同时实现器件在较低的电压下操作。同时,拥有较大功函数的金属纳米晶可以形成较深的势阱,从而在俘获电荷后有较好的数据保存特性。
本发明中所述金属纳米晶为钌和氧化钌的复合物(记为钌基RuOx纳米晶),它具有很好的热稳定性,既使被氧化,也是一种良好的导体。此外,它在高温下不容易扩散,易于干法刻蚀。
本发明中所述高介电常数介质为HfxAlyOz(y=0或>0),它的介电常数在10~25之间,具有较高的电荷陷阱密度,这就使得HfxAlyOz材料可以作为理想的电荷俘获层代替氮化硅。
本发明中的上电极采用金属钯(Pd)材料,它拥有较大的功函数(5.22 eV),能与电荷阻挡层介质形成有利于电荷擦写的垫垒高度,且钯具有良好的化学稳定性和热稳定性。
因此,本发明所提出的栅叠层结构将在下一代快闪存储器上具有很好的应用前景。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (10)
1.一种适合于半导体闪存器件的栅叠层结构,其特征在于,包含有基于金属纳米晶和高介电常数薄膜的异质电荷俘获层;所述栅叠层结构中,由下至上依次设置有:
晶向为100的P型单晶硅片,作为衬底;
原子层淀积的Al2O3薄膜,作为电荷隧穿层,厚度为5~15纳米;
所述异质电荷俘获层,其进一步包含有:
所述金属纳米晶作为第一电荷俘获层,该纳米晶为钌和氧化钌的复合物,记为钌基RuOx纳米晶;
原子层淀积的所述高介电常数薄膜作为第二电荷俘获层,厚度为5~10纳米;所述高介电常数介质为HfxAlyOz,其中x>0,z>0且y=0或y>0;
原子层淀积的Al2O3薄膜,作为电荷阻挡层,厚度为15~40纳米;
上电极层。
2.如权利要求1所述栅叠层结构,其特征在于,所述高介电常数薄膜是HfAlO薄膜,其中包含淀积循环数之比为1:1的HfO2和Al2O3;或者,所述高介电常数薄膜是HfO2薄膜。
3.如权利要求1所述栅叠层结构,其特征在于,所述上电极层包含以金属钯形成的栅电极。
4.一种适合于半导体闪存器件的栅叠层结构的制备方法,其特征在于,包含以下步骤:
步骤1、采用晶向为100的P型单晶硅片作为衬底;
步骤2、采用原子层淀积的方法生长5~15纳米厚的Al2O3薄膜作为电荷隧穿层;
步骤3.1、采用磁控溅射淀积的方法,在Al2O3隧穿层上淀积厚度为2~4纳米的金属钌层,然后在氮气气氛中进行快速热退火处理,形成钌基RuOx纳米晶作为异质电荷俘获层的第一电荷俘获层;所述钌基RuOx纳米晶为钌和氧化钌的复合物;
步骤3.2、采用原子层淀积的方法生长5~10纳米厚的高介电常数HfxAlyOz薄膜作为异质电荷俘获层的第二电荷俘获层:所述高介电常数HfxAlyOz薄膜中x>0,z>0,同时y=0或y>0;其中Hf与Al的组成通过原子层淀积HfO2和Al2O3的循环数来确定;
步骤4、采用原子层淀积的方法生长15~40纳米厚的Al2O3薄膜作为电荷阻挡层,然后进行快速热退火处理;
步骤5、用光刻工艺,采用剥离方法形成50~200纳米厚的栅电极作为上电极层。
5.如权利要求4所述制备方法,其特征在于,所述步骤3.2中所述高介电常数HfxAlyOz薄膜是HfAlO薄膜,其中包含淀积循环数之比为1:1的HfO2和Al2O3;或者,所述高介电常数HfxAlyOz薄膜是HfO2薄膜。
6.如权利要求5所述制备方法,其特征在于,所述步骤3.2中原子层淀积生长HfO2的条件是:衬底温度在250~350℃,反应前躯体为四(乙基甲胺基)铪和水蒸汽。
7.如权利要求4或5或6所述制备方法,其特征在于,所述步骤2、步骤3.2或步骤4中原子层淀积生成所述Al2O3薄膜的条件是:衬底温度在250~350℃,反应前躯体为三甲基铝和水蒸汽。
8.如权利要求4所述制备方法,其特征在于,所述步骤3.1中形成钌基RuOx纳米晶时的退火温度为700~900℃,退火时间为10~30秒;步骤4中形成电荷阻挡层Al2O3薄膜时的退火温度为500~800 ℃,退火时间为10~30 秒。
9.如权利要求4所述制备方法,其特征在于,所述步骤5中形成所述栅电极的材料为金属钯。
10.如权利要求4所述制备方法,其特征在于,还包含:
步骤6、先用氢氟酸去除衬底背面的自然氧化层,然后淀积一层金属铝层作为下电极,以形成良好的欧姆接触。
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US9336919B2 (en) | 2012-08-17 | 2016-05-10 | The Trustees Of The University Of Pennsylvania | Methods for preparing colloidal nanocrystal-based thin films |
WO2014113655A2 (en) * | 2013-01-18 | 2014-07-24 | The Trustees Of The University Of Pennsylvania | Nanocrystal thin film device fabrication methods and apparatus |
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US7629641B2 (en) * | 2005-08-31 | 2009-12-08 | Micron Technology, Inc. | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection |
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KR100900569B1 (ko) * | 2007-03-29 | 2009-06-02 | 국민대학교산학협력단 | 플로팅 게이트 형성 방법 및 이를 이용한 비휘발성 메모리 장치의 제조 방법 |
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CN101887910A (zh) * | 2010-06-03 | 2010-11-17 | 复旦大学 | 一种适合于半导体闪存器件的栅叠层结构及制备方法 |
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CN102208442A (zh) | 2011-10-05 |
WO2011150670A1 (zh) | 2011-12-08 |
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