CN107482014B - 一种多级单元薄膜晶体管存储器及其制备方法 - Google Patents

一种多级单元薄膜晶体管存储器及其制备方法 Download PDF

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CN107482014B
CN107482014B CN201710538920.2A CN201710538920A CN107482014B CN 107482014 B CN107482014 B CN 107482014B CN 201710538920 A CN201710538920 A CN 201710538920A CN 107482014 B CN107482014 B CN 107482014B
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layer
electric charge
film transistor
capture layer
level unit
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CN107482014A (zh
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丁士进
钱仕兵
刘文军
张卫
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Fudan University
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Fudan University
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Priority to PCT/CN2017/119769 priority patent/WO2019007009A1/zh
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    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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Abstract

本发明公开了一种多级单元薄膜晶体管存储器及其制备方法，所述存储器的结构从下至上依次设置有：栅电极、电荷阻挡层、电荷俘获层、电荷隧穿层、有源区以及源、漏电极；其中，所述电荷隧穿层将所述电荷俘获层完全包围，以使所述电荷俘获层与外界完全隔离；所述电荷俘获层的材料为ZnO、In2O3、Ga2O3、SnO2、InSnO或IGZO中的任意一种。本发明所制备的薄膜晶体管存储器的电荷俘获层完全被电荷隧穿层包围，与外界完全隔离，防止了在工艺过程中电荷俘获层的物理性质和化学组成发生改变，减少了存储在电荷俘获层中电荷的流失，提高了数据的保持特性和器件性能的稳定性；采用金属氧化物半导体薄膜作为存储器的电荷俘获层，可以实现多级单元存储，提高了存储密度。

Description

一种多级单元薄膜晶体管存储器及其制备方法
技术领域
本发明涉及半导体集成电路制备技术领域，具体涉及一种多级单元薄膜晶体管存储器及其制备方法。
背景技术
非易失性存储器是一类重要的存储器，其广泛应用于计算机、手机、移动硬盘等电子产品以及服务器、网络互联设备等网络基础设备中。然而，传统的硅基非易失性存储器由于其制备工艺复杂且加工温度高，无法满足下一代系统面板(SOP)、未来透明和柔性电子器件等领域的发展需求。近些年来，基于新型非晶铟镓锌氧化物(a-IGZO)半导体沟道的薄膜晶体管存储器已成为国际上研究的热点。这是由于该类存储器具有简单的制备工艺(无离子注入或掺杂)、较低的加工温度、优良的可见光透过率以及其制备工艺与薄膜晶体管工艺相兼容等优点，因此使得其在未来SOP以及柔性透明电子器件等领域具有广泛的应用前景。
另一方面，存储密度也是存储器的重要参数。提高存储密度的传统方法主要是缩小存储器件的尺寸，增加单位面积内器件数目，从而增加存储密度。但随着器件尺寸不断缩小，器件制备工艺复杂度升高，导致器件的制造成本也随之增加。因此，在单个存储器单元上实现多级单元存储是提高存储密度的一种有效的方法。它不仅能够提高存储密度，还可以降低成本。
发明内容
本发明的目的是提供一种多级单元薄膜晶体管存储器及其制备方法，该存储器用于提高数据的保持特性和器件性能的稳定性，可以实现多级单元存储，提高了存储密度。
为达到上述目的，本发明提供了一种多级单元薄膜晶体管存储器，所述存储器的结构从下至上依次设置有：栅电极、电荷阻挡层、电荷俘获层、电荷隧穿层、有源区以及源、漏电极；
其中，所述电荷隧穿层将所述电荷俘获层完全包围，以使所述电荷俘获层与外界完全隔离；所述电荷俘获层的材料为ZnO、In2O3、Ga2O3、SnO2、InSnO或铟镓锌氧化物(IGZO)中的任意一种。
上述的多级单元薄膜晶体管存储器，其中，所述栅电极的材料为P型单晶硅片、玻璃或者PI柔性基板。
上述的多级单元薄膜晶体管存储器，其中，所述P型单晶硅片的电阻率为0.001～0.005Ω·cm。
上述的多级单元薄膜晶体管存储器，其中，所述电荷阻挡层的材料为Al2O3、SiO2、HfO2或ZrO2。
上述的多级单元薄膜晶体管存储器，其中，所述电荷隧穿层的材料为Al2O3、SiO2、HfO2或ZrO2。
上述的多级单元薄膜晶体管存储器，其中，所述有源区的材料为IGZO。
上述的多级单元薄膜晶体管存储器，其中，所述源、漏电极的材料为Ti/Au或Mo。
本发明还提供了一种上述多级单元薄膜晶体管存储器的制备方法，其包含以下步骤：
步骤1、制备栅电极；
步骤2、在步骤1所得到的栅电极上采用原子层沉积方法(ALD方法)生长电荷阻挡层，电荷阻挡层的厚度为30～60nm，淀积温度为150～350℃；
步骤3、在步骤2所得到的电荷阻挡层上采用原子沉积或磁控溅射沉积方法(PVD方法)生长电荷俘获层，电荷俘获层的厚度为10～40nm；
步骤4、在步骤3所得到的电荷俘获层上旋涂一层正性光刻胶，然后进行光刻(曝光和显影)，定义出电荷俘获层的区域，接着采用湿法刻蚀工艺来刻蚀所定义的电荷俘获层区域以外的部分；
步骤5、在步骤4所得到的电荷俘获层和经刻蚀后暴露在外的电荷阻挡层上采用原子层沉积方法生长电荷隧穿层，电荷隧穿层的厚度为6～15nm，淀积温度为150～350℃；
步骤6、在步骤4所得到的电荷隧穿层上采用磁控溅射沉积方法生长一层IGZO薄膜，作为器件的有源层，然后通过光刻工艺和湿法刻蚀工艺定义出有源区，形成器件的有源沟道，IGZO薄膜的厚度为30～60nm；
步骤7、在步骤6所得到的IGZO薄膜上旋涂一层负性光刻胶，通过光刻定义出源、漏电极图形区域；然后，采用磁控溅射沉积方法或者电子束热蒸发方法淀积一层金属薄膜作为源、漏电极材料，并通过剥离工艺去除源、漏电极图形区域以外的金属层，从而形成器件的源、漏电极，金属薄膜的厚度为50～200nm。
步骤8、对步骤7所得到的器件进行后续退火处理，退火气氛为氧气或空气，退火温度为150～350℃，退火时间为60s～2h；
上述的多级单元薄膜晶体管存储器的制备方法，其中，所述步骤1具体包括：将P型单晶硅片作为衬底，并通过标准清洗形成栅电极，或者，将玻璃或PI柔性基板作为衬底，并在其上沉积一层金属，通过光刻和刻蚀形成栅电极。
相对于现有技术，本发明具有以下有益效果：
(1)本发明所制备的薄膜晶体管存储器的电荷俘获层完全被电荷隧穿层包围，因而可以与外界完全隔离，进而防止了在退火过程中电荷俘获层的物理性质和化学组成发生改变，减少了存储在电荷俘获层中电荷的流失，提高了数据的保持特性和器件性能的稳定性；
(2)本发明采用金属氧化物半导体薄膜作为存储器的电荷俘获层，一个器件单元可以存储多个位(bit)，可以实现多级单元存储的功能，提高了存储密度；
(3)本发明所制备的薄膜晶体管存储器，可以在小于350℃的低温下制备，因此降低了器件制备的热预算，并且与薄膜晶体管(TFT)显示器所采用的材料、工艺温度、器件结构等一致，故其制备工艺与TFT显示器的制备工艺相兼容。此外由于IGZO薄膜具有较高的可见光透过率，使得本发明在未来SOP以及柔性透明电子器件等领域中具有广泛的应用前景。
附图说明
图1为多级单元存储器结构的剖面示意图；
图2为基于ZnO电荷俘获层的多级单元存储器的编程特性的曲线图；
图3为基于ZnO电荷俘获层的多级单元存储器的擦除特性的曲线图；
图4为基于ZnO电荷俘获层的多级单元存储器的电荷保持特性的曲线图。
具体实施方式
以下结合附图通过具体实施例对本发明作进一步的描述，这些实施例仅用于说明本发明，并不是对本发明保护范围的限制。
如图1所示，本发明提供了一种多级单元薄膜晶体管存储器，所述存储器的结构从下至上依次设置有：栅电极10、电荷阻挡层20、电荷俘获层30、电荷隧穿层40、有源区50以及源、漏电极60；
其中，所述电荷隧穿层40将所述电荷俘获层30完全包围，以使所述电荷俘获层30与外界完全隔离；所述电荷俘获层30的材料为ZnO、In2O3、Ga2O3、SnO2、InSnO或IGZO中的任意一种。
上述的多级单元薄膜晶体管存储器，其中，所述栅电极10的材料为P型单晶硅片、玻璃或者PI柔性基板。
上述的多级单元薄膜晶体管存储器，其中，所述P型单晶硅片的电阻率为0.001～0.005Ω·cm。
上述的多级单元薄膜晶体管存储器，其中，所述电荷阻挡层20的材料为Al2O3、SiO2、HfO2或ZrO2。
上述的多级单元薄膜晶体管存储器，其中，所述电荷隧穿层40的材料为Al2O3、SiO2、HfO2或ZrO2。
上述的多级单元薄膜晶体管存储器，其中，所述有源区50的材料为IGZO。
上述的多级单元薄膜晶体管存储器，其中，所述源、漏电极60的材料为Ti/Au或Mo。
本发明还提供了一种上述多级单元薄膜晶体管存储器的制备方法，其包含以下步骤：
步骤1、制备栅电极10；
步骤2、在步骤1所得到的栅电极10上采用原子层沉积方法生长电荷阻挡层20，电荷阻挡层20的厚度为30～60nm，淀积温度为150～350℃；
步骤3、在步骤2所得到的电荷阻挡层20上采用原子沉积或磁控溅射沉积方法生长电荷俘获层30，电荷俘获层30的厚度为10～40nm；
步骤4、在步骤3所得到的电荷俘获层30上旋涂一层正性光刻胶，然后进行光刻，定义出电荷俘获层30的区域，接着采用湿法刻蚀工艺来刻蚀所定义的电荷俘获层30区域以外的部分；
步骤5、在步骤4所得到的电荷俘获层30和经刻蚀后暴露在外的电荷阻挡层20上采用原子层沉积方法生长电荷隧穿层40，电荷隧穿层40的厚度为6～15nm，淀积温度为150～350℃；
步骤6、在步骤4所得到的电荷隧穿层40上采用磁控溅射沉积方法生长一层IGZO薄膜，作为器件的有源层，然后通过光刻工艺和湿法刻蚀工艺定义出有源区50，形成器件的有源沟道，IGZO薄膜的厚度为30～60nm；
步骤7、在步骤6所得到的IGZO薄膜上旋涂一层负性光刻胶，通过光刻定义出源、漏电极60图形区域(开口区)；然后，采用磁控溅射沉积方法或者电子束热蒸发方法淀积一层金属薄膜作为源、漏电极60材料，并通过剥离工艺去除源、漏电极60图形区域以外的金属层，从而形成器件的源、漏电极60，金属薄膜的厚度为50～200nm；
步骤8、对步骤7所得到的器件进行后续退火处理，退火气氛为氧气或空气，退火温度为150～350℃，退火时间为60s～2h。
上述的多级单元薄膜晶体管存储器的制备方法，其中，所述步骤1具体包括：将P型单晶硅片作为衬底，并通过标准清洗形成栅电极10，或者，将玻璃或PI柔性基板作为衬底，并在其上沉积一层金属，通过光刻和刻蚀形成栅电极10。
实施例一：
该实施例采用ZnO薄膜作为电荷俘获层30，具体制备流程如下：
步骤1，将电阻率为0.001～0.005Ω·cm的P型单晶硅片作为衬底，采用标准的RCA清洗工艺对衬底进行清洗，形成栅电极10；
步骤2，在栅电极10上采用ALD方法生长一层Al2O3薄膜作为电荷阻挡层20；淀积温度为150～350℃，优选300℃；薄膜厚度为30～60nm，优选35nm；
步骤3，在电荷阻挡层20上采用ALD方法或PVD方法生长一层ZnO薄膜，作为电荷俘获层30；淀积温度为150～350℃，优选200℃；薄膜厚度为10～40nm，优选20nm；
步骤4，在电荷俘获层30上旋涂一层正性光刻胶，然后进行曝光和显影，定义出器件中电荷俘获层30的区域；接着采用稀释的盐酸溶液来刻蚀电荷俘获层30区域以外的部分；
步骤5，在电荷俘获层30以及经稀释的盐酸溶液刻蚀后暴露在外的电荷阻挡层20上面，采用ALD方法生长一层Al2O3薄膜，作为电荷隧穿层40；淀积温度为150～350℃，优选300℃；薄膜厚度为6～15nm，优选8nm；
步骤6，在电荷隧穿层40上采用PVD方法生长一层IGZO薄膜，作为有源层；IGZO靶材中原子比为In:Ga:Zn:O＝1:1:1:4，溅射功率为110W，工作压强为0.88Pa，通入淀积腔中的Ar和O2的流量分别为50sccm和0sccm；然后通过光刻工艺和湿法刻蚀方法定义出有源区50，形成器件的有源沟道，IGZO薄膜厚度为30～60nm，优选40nm；
步骤7，在IGZO薄膜上旋涂一层负性光刻胶，利用光刻工艺定义出源、漏电极60图形区域(开口区)；采用磁控溅射沉积方法或者电子束蒸发方法地毯式淀积一层Ti/Au双层金属薄膜作为源、漏电极60材料，金属薄膜的厚度为50～200nm，优选100nm；然后采用剥离工艺去除源、漏电极60图形区域以外的金属层，从而形成器件的源、漏电极60；
步骤8，对器件进行后续退火处理，退火气氛为氧气(O2)，退火温度为150～350℃，优选温度为250℃。退火时间为60～600s，优选300s。
图2为实施例一所制备存储器的编程特性，当编程电压固定在12V，编程时间从0.001ms增加到100ms时，编程窗口(编程后阈值电压与初始状态的阈值电压之差)从1.47V增加到2.75V；当固定编程时间为10ms时，编程电压从10V增加到16V时，编程窗口从1.89V增加到3.44V。这些数据表明该器件具有良好的编程特性。图3为实施例一所制备存储器的擦除特性，当擦除电压固定在-8V，擦除时间从1μs增加到70μs时，擦除窗口(擦除后阈值电压与初始状态的阈值电压之差)从2V增加到4.99V；当固定擦除时间为1μs时，擦除电压从-8V增加到-14V时，擦除窗口从2V增加到8.5V。这表明实施例一所制备的存储器具有非常高的电擦除效率。
通过改变栅极上偏压脉冲可以实现四种状态，即“00”、“11”、“10”和“01”态。这里器件初始状态定义为“00”；器件编程状态定义为“11”态(如：15V/10ms)；较低负偏压脉冲(如：-8V/10μs)擦除状态定义为“10”；较高负偏压脉冲(如：-14V/1μs)擦除状态定义为“01”。图4显示了实施例一所制备的存储器不同存储状态的电荷保持特性。“11”态的操作条件是15V/10ms；“00”态的操作条件是器件初始态；“10”态和“01”态的操作条件分别是-8V/10μs和-14V/1μs。从图中可以看出，当保持时间达到105s后，器件的“11”态到“00”态存储窗口为2V；“00”态到“10”态存储窗口为1.1V；“10”态到“01”态存储窗口为1.6V。这使得存储器能正常区分“00”、“10”、“01”和“11”四种不同的存储态。
实施例二：
该实施例采用IGZO薄膜作为电荷俘获层30，具体制备流程如下：
步骤1，将电阻率为0.001～0.005Ω·cm的P型单晶硅片作为衬底，采用标准的RCA清洗工艺对衬底进行清洗，形成栅电极10；
步骤2，在栅电极10上采用ALD方法生长一层Al2O3薄膜作为电荷阻挡层20；淀积温度为150～350℃，优选300℃；薄膜厚度为30～60nm，优选35nm；
步骤3，在电荷阻挡层20上采用PVD方法生长一层IGZO薄膜，作为电荷俘获层30；IGZO靶材的原子比为In:Ga:Zn:O＝1:1:1:4，溅射功率为110W，工作压强为0.88Pa，通入淀积腔中的Ar和O2的流量分别为50sccm和0sccm；IGZO薄膜的厚度为10～40nm，优选20nm；
步骤4，在电荷俘获层30上旋涂一层正性光刻胶，然后进行曝光和显影，定义出器件中电荷俘获层30的区域；接着采用稀释的盐酸溶液来刻蚀电荷俘获层30区域以外的部分；
步骤5，在电荷俘获层30以及经稀释的盐酸溶液刻蚀后暴露在外的电荷阻挡层20上面，采用ALD方法生长一层Al2O3薄膜，作为电荷隧穿层40；淀积温度为150～350℃，优选300℃；薄膜厚度为6～15nm，优选8nm；
步骤6，在电荷隧穿层40上采用PVD方法生长一层IGZO薄膜，作为有源层；IGZO靶材中原子比为In:Ga:Zn:O＝1:1:1:4，溅射功率为110W，工作压强为0.88Pa，通入淀积腔中的Ar和O2的流量分别为50sccm和0sccm；然后通过光刻工艺和湿法刻蚀方法定义出有源区50，形成器件的有源沟道，IGZO薄膜厚度为30～60nm，优选40nm；
步骤7，在IGZO薄膜上旋涂一层负性光刻胶，利用光刻工艺定义出源、漏电极60图形区域(开口区)；采用磁控溅射沉积方法或者电子束蒸发方法地毯式淀积一层Mo金属薄膜作为源、漏电极60材料，金属薄膜的厚度为50～200nm，优选100nm；然后采用剥离工艺去除源、漏电极60图形区域以外的金属层，从而形成器件的源、漏电极60；
步骤8，对器件进行后续退火处理，退火气氛为空气，退火温度为150～350℃，优选温度为300℃；退火时间为0.5～2h，优选1h。
若对上述实施例二所制备的存储器进行不同电压编程可实现不同状态，例如，当栅极施加12V、10ms的脉冲，器件从初始状态变成编程状态，并且这两种状态之间可以互相转变(恢复到初始状态的电压脉冲条件为-12V、20ms)；当栅极上施加-15V、10ms的脉冲，器件从初始状态变成擦除状态，并且这两种状态之间也可以互相转变(恢复到初始状态的电压脉冲条件为11V、15ms)。表1列出了实施例二所制备的存储器不同状态的保持特性。随着保持时间从0秒延长到105s时，编程状态、初始状态、擦除状态的阈值电压(Vth)分别从2.276V、-0.09V、-2.4V变为1.574V、-0.339V、-1.634V，体现出了较好的稳定性。
表1.基于IGZO电荷俘获层的多级单元存储器的保持特性
综上所述，本发明所制备的薄膜晶体管存储器的电荷俘获层完全被电荷隧穿层包围，因此与外界完全隔离，防止了在工艺过程中电荷俘获层的物理性质和化学组成发生改变，减少了存储在电荷俘获层中电荷的流失，提高了数据的保持特性和器件性能的稳定性；本发明采用金属氧化物半导体薄膜作为存储器的电荷俘获层，可以实现多级单元存储，提高了存储密度；本发明所制备的薄膜晶体管存储器，可以在小于350℃的低温下制备，因此降低了器件制备的热预算，并且其制备工艺与薄膜晶体管工艺相兼容。此外由于IGZO薄膜具有较高的可见光透过率，使得本发明在未来SOP以及柔性透明电子器件等领域中具有广泛的应用前景。
尽管本发明的内容已经通过上述优选实施例作了详细介绍，但应当认识到上述的描述不应被认为是对本发明的限制。在本领域技术人员阅读了上述内容后，对于本发明的多种修改和替代都将是显而易见的。因此，本发明的保护范围应由所附的权利要求来限定。

Claims (9)

1.一种多级单元薄膜晶体管存储器，其特征在于，所述存储器的结构从下至上依次设置有：栅电极、电荷阻挡层、电荷俘获层、电荷隧穿层、有源区以及源、漏电极；经过退火制得所述存储器；
其中，所述电荷隧穿层将所述电荷俘获层完全包围，以使所述电荷俘获层与外界完全隔离，以防止在退火过程中电荷俘获层的物理性质和化学组成发生改变，减少存储在电荷俘获层中电荷的流失；所述电荷俘获层的材料为ZnO、In2O3、Ga2O3、SnO2、InSnO或IGZO中的任意一种。
2.如权利要求1所述的多级单元薄膜晶体管存储器，其特征在于，所述栅电极的材料为P型单晶硅片、玻璃或者PI柔性基板。
3.如权利要求2所述的多级单元薄膜晶体管存储器，其特征在于，所述P型单晶硅片的电阻率为0.001~0.005 Ω•cm。
4.如权利要求1所述的多级单元薄膜晶体管存储器，其特征在于，所述电荷阻挡层的材料为Al2O3、SiO2、HfO2或ZrO2。
5.如权利要求1所述的多级单元薄膜晶体管存储器，其特征在于，所述电荷隧穿层的材料为Al2O3、SiO2、HfO2或ZrO2。
6.如权利要求1所述的多级单元薄膜晶体管存储器，其特征在于，所述有源区的材料为IGZO。
7.如权利要求1所述的多级单元薄膜晶体管存储器，其特征在于，所述源、漏电极的材料为Ti/Au或Mo。
8.一种如权利要求1-7中任意一项所述的多级单元薄膜晶体管存储器的制备方法，其特征在于，包含以下步骤：
步骤1、制备栅电极；
步骤2、在步骤1所得到的栅电极上采用原子层沉积方法生长电荷阻挡层，电荷阻挡层的厚度为30~60 nm，淀积温度为150~350℃；
步骤3、在步骤2所得到的电荷阻挡层上采用原子沉积或磁控溅射沉积方法生长电荷俘获层，电荷俘获层的厚度为10~40 nm；
步骤4、在步骤3所得到的电荷俘获层上旋涂一层正性光刻胶，然后进行光刻，定义出电荷俘获层的区域，接着采用湿法刻蚀工艺来刻蚀所定义的电荷俘获层区域以外的部分；
步骤5、在步骤4所得到的电荷俘获层和经刻蚀后暴露在外的电荷阻挡层上采用原子层沉积方法生长电荷隧穿层，电荷隧穿层的厚度为6~15 nm，淀积温度为150~350℃；
步骤6、在步骤5所得到的电荷隧穿层上采用磁控溅射沉积方法生长一层IGZO薄膜，作为器件的有源层，然后通过光刻工艺和湿法刻蚀工艺定义出有源区，形成器件的有源沟道，IGZO薄膜的厚度为30~60 nm；
步骤7、在步骤6所得到的IGZO薄膜上旋涂一层负性光刻胶，通过光刻定义出源、漏电极图形区域；然后，采用磁控溅射沉积方法或者电子束热蒸发方法淀积一层金属薄膜作为源、漏电极材料，并通过剥离工艺去除源、漏电极图形区域以外的金属层，从而形成器件的源、漏电极，金属薄膜的厚度为50~200 nm；
步骤8、对步骤7所得到的器件进行后续退火处理，退火气氛为氧气或空气，退火温度为150~350℃，退火时间为60 s~2 h。
9.如权利要求8所述的多级单元薄膜晶体管存储器的制备方法，其特征在于，所述步骤1具体包括：将P型单晶硅片作为衬底，并通过标准清洗形成栅电极，或者，将玻璃或PI柔性基板作为衬底，并在其上沉积一层金属，通过光刻和刻蚀形成栅电极。
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Publication number Priority date Publication date Assignee Title
US10217819B2 (en) * 2015-05-20 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor device including metal-2 dimensional material-semiconductor contact
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WO2021056513A1 (en) 2019-09-29 2021-04-01 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and methods for forming the same
CN110785846B (zh) 2019-09-29 2021-03-23 长江存储科技有限责任公司 三维存储器件及其形成方法
CN112635488A (zh) 2019-09-29 2021-04-09 长江存储科技有限责任公司 三维存储器件及其形成方法
CN111009582B (zh) * 2019-12-22 2021-07-23 复旦大学 基于薄膜晶体管结构的光电编程多态存储器及其制备方法
CN112349787A (zh) * 2020-10-26 2021-02-09 复旦大学 一种光电双调制的二维柔性神经突触器件及其制备方法
CN113035882A (zh) * 2021-03-10 2021-06-25 山东大学 一种非挥发性半导体存储器的通用制备方法
CN113380881B (zh) * 2021-05-28 2022-12-27 复旦大学 非易失性存储器及其制备方法
CN113451428B (zh) * 2021-06-28 2022-10-21 复旦大学 双半浮栅光电存储器及其制备工艺
CN114927587B (zh) * 2022-03-15 2024-03-22 中国民用航空飞行学院 一种基于三元材料平面隧穿效应的光电探测器及制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593065A (zh) * 2012-03-14 2012-07-18 复旦大学 一种背栅薄膜晶体管存储器的制备方法
CN102623459A (zh) * 2012-04-10 2012-08-01 复旦大学 一种薄膜晶体管存储器及其制备方法
CN105206615A (zh) * 2015-09-28 2015-12-30 南京大学 一种高介电系数复合氧化物电荷存储介质薄膜及应用
CN106560928A (zh) * 2015-09-28 2017-04-12 河北大学 一种电荷俘获型存储元件及其制备工艺

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101206034B1 (ko) * 2006-05-19 2012-11-28 삼성전자주식회사 산소결핍 금속산화물을 이용한 비휘발성 메모리 소자 및 그제조방법
KR20180105252A (ko) * 2010-09-03 2018-09-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 전계 효과 트랜지스터 및 반도체 장치의 제조 방법
US8514626B2 (en) * 2011-07-26 2013-08-20 Micron Technology, Inc. Memory cells and methods of storing information
CN102593143A (zh) * 2012-03-31 2012-07-18 浙江大学 一种透明阻变存储器
CN103474571B (zh) * 2013-09-26 2015-04-22 河北大学 一种阻变存储元件及其制备方法
CN107482014B (zh) * 2017-07-04 2019-04-12 复旦大学 一种多级单元薄膜晶体管存储器及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593065A (zh) * 2012-03-14 2012-07-18 复旦大学 一种背栅薄膜晶体管存储器的制备方法
CN102623459A (zh) * 2012-04-10 2012-08-01 复旦大学 一种薄膜晶体管存储器及其制备方法
CN105206615A (zh) * 2015-09-28 2015-12-30 南京大学 一种高介电系数复合氧化物电荷存储介质薄膜及应用
CN106560928A (zh) * 2015-09-28 2017-04-12 河北大学 一种电荷俘获型存储元件及其制备工艺

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