CN111009582B - 基于薄膜晶体管结构的光电编程多态存储器及其制备方法 - Google Patents

基于薄膜晶体管结构的光电编程多态存储器及其制备方法 Download PDF

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CN111009582B
CN111009582B CN201911332415.8A CN201911332415A CN111009582B CN 111009582 B CN111009582 B CN 111009582B CN 201911332415 A CN201911332415 A CN 201911332415A CN 111009582 B CN111009582 B CN 111009582B
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丁士进
裴俊翔
吴小晗
张卫
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Abstract

本发明属于半导体存储器技术领域,具体为一种基于薄膜晶体管结构的光电编程多态存储器及其制备方法。本发明通过在浮栅薄膜晶体管俘获层中引入多种钙钛矿量子点,实现在光电编程条件下的多态存储器。制备方法包括:将导电衬底放入原子层沉积反应腔中,控制沉积腔温度;低温原子层沉积制备氧化铝阻挡层;溶液法制备钙钛矿量子点,并均匀旋涂于阻挡层上;低温原子层沉积制备氧化铝隧穿层;磁控溅射生长IGZO沟道层,并光刻形成沟道图形;第二次光刻,电子束蒸发Ti/Au源漏电极,得到光电可编程的多态存储器。本发明可实现在电压编程过程中通过改变波长光照实现存储器的多态存储行为。本发明为多态存储、光电探测、柔性电子等领域的研究开发提供了解决思路。

Description

基于薄膜晶体管结构的光电编程多态存储器及其制备方法
技术领域
本发明属于半导体存储器技术领域,具体涉及多态存储器及其制备方法。
背景技术
随着集成电路技术的持续快速发展,人们强烈希望提高存储芯片的数据储存密度,在更加微小的芯片上储存更大量的数据与信息。另外,人工智能正逐渐发展为新一代通用技术,加快与经济社会各领域渗透融合,已处于新科技革命和产业变革的核心前沿,成为推动经济社会发展的新引擎。在人工智能领域中,物联网、社交媒体和安全设备产生了海量的数据,存储、交换和处理这些数据都需要大量的存储器,这些发展现状和趋势迫切地要求我们尽快地开发具有高存储密度的存储器技术。通常,增加单位面积芯片存储密度的途径包括进一步减小器件尺寸和增加单个器件的存储状态[1]。前者正面临着众所周知的摩尔定律瓶颈,进一步减小器件尺寸是全行业都难以突破的技术难题。相对而言,通过增加单个器件的存储状态的方法来增加存储密度则表现出高得多的性价比,将器件存储状态从1个增加为2个,就相当于将存储密度提高了1倍。多态存储器也因此成为当下研究前沿与热点[2]
基于浮栅薄膜晶体管(Floating gate thin film transistors, FG-TFTs)的存储器件具有保持时间长等优势,是一类典型的非易失存储器,在闪存与移动存储设备等领域有着大量应用。近来,一些研究者报道了采用金属或半导体材料纳米晶作为FG-TFTs器件的俘获层,能使载流子互相独立地被捕获在每个器件的纳米晶俘获层中,进一步提高存储器的保持时间。然而,FG-TFTs存储器的多态存储性能仍亟待提高。一方面,基于一种俘获层材料的FG-TFTs,其记忆状态对应着俘获层的载流子密度,考虑到较长的保持时间后俘获层载流子的漏电流失等现象,一般要求器件在不同记忆状态时的俘获层载流子密度有很大的区别。比如,在Ding等研究者的近期工作中[3,4],将器件保持105s后阈值电压差别超过1V以上的状态的才描述为不同的记忆态。另一方面,传统的电压编程的FG-TFTs存储器,其更多的记忆状态要求更高的编程/擦除电压或更长的编程/擦除时间来实现,这又与对存储器件的低功耗要求相矛盾。因此,提高FG-TFTs存储器多态存储性能是该领域的重大挑战。
钙钛矿量子点(Perovskite quantum dots, PQDs)材料是指一种新型的、具有量子尺寸效应的钙钛矿(ABX3, X=Cl, Br, I)光电半导体材料,其表现出非常好的光吸收、光电转化性能与极高的量子荧光产率,在太阳能电池、发光二极管、光探测器等方面有巨大的应用前景[5,6]。更重要的是,当对该材料中的元素如卤素进行不同比例的Cl, Br, I之间的复合时,其能带结构能在大范围内(光吸收峰从紫外到红外光)精细地被调控,从而给出一系列物理与化学性能类似而能带不同的纳米材料[7,8]。目前,将PQDs应用于存储器件的研究较少。在仅有的相关报道中,Chen等研究者[9]将一种MAPbBr3 的PQD材料与聚苯乙烯(PS)复合薄膜置于有机半导体与氧化硅介电层之间,使MAPbBr3能俘获有机半导体的载流子,探索了器件的光致记忆性能。虽然这种器件不是真正意义上的FG-TFT,旋涂制备的MAPbBr3/PS复合薄膜厚度较厚且难以精确控制,但该工作初步证实了采用PQDs作为FG-TFTs存储器俘获层的可行性和巨大潜力。
[1]Wen-Peng Zhang, Shi-Bing Qian, Wen-Jun Liu, Shi-Jin Ding*, DavidWeiZhang, Multi-level cell nonvolatile Memory with an In-Ga-Zn-O ChargeStorageLayer and Channel, IEEE Electron Device Letters, 2015, 36(10): 1021.
[2]Shi-Bing Qian, Yan Shao, Wen-Jun Liu, David Wei Zhang, Shi-JinDing*, Erasing-Modes Dependent Performance of a-IGZO TFT Memory with Atomic-LayerDeposited Ni Nanocrystal Charge Storage Layer, IEEE Transactions onElectronDevices, 2017, 64(7): 3023.
[3]Li-Li Zheng, Qian Ma, You-Hang Wang, Wen-Jun Liu, Shi-Jin Ding*,David Wei Zhang, High-Performance Unannealed a-InGaZnO TFT with anAtomicLayer-Deposited SiO2 Insulator, IEEE Electron Device Letters, 2016, 37(6): 743.
[4]Wang, H.; Kim, D. H., Perovskite-based photodetectors: materialsand devices.Chemical Society Reviews 2017, 46 (17), 5204.
[5]Jansen-van Vuuren, R. D.; Armin, A.; Pandey, A. K.; Burn, P. L.;Meredith, P., Organic Photodiodes: The Future of Full Color Detection andImage Sensing. AdvancedMaterials 2016, 28 (24), 4766.
[6]Wu, X.; Zhou, B.; Zhou, J.; Chen, Y.; Chu, Y.; Huang, J.,Distinguishable Detectionof Ultraviolet, Visible, and Infrared Spectrum withHigh-Responsivity PerovskiteBased Flexible Photosensors. Small 2018, 14 (19),1800527.
[7]Wu, X.; Chu, Y.; Liu, R.; Katz, H. E.; Huang, J., Pursuing PolymerDielectric Interfacial Effect in Organic Transistors for PhotosensingPerformance Optimization.Advanced Science 2017, 4 (12), 1700442.
[8]Wu, X.; Mao, S.; Chen, J.; Huang, J., Strategies for Improving thePerformance ofSensors Based on Organic Field-Effect Transistors. AdvancedMaterials 2018, 30 (17),1705642.
[9]Chen, Y.; Chu, Y.; Wu, X.; Ou-Yang, W.; Huang, J., High-Performance Inorganic Perovskite Quantum Dot-Organic Semiconductor HybridPhototransistors. AdvancedMaterials2017, 29 (44), 1704062.。
发明内容
本发明的目的在于提供一种存储密度高、功耗低的基于薄膜晶体管结构(FG-TFTs)的光电编程多态存储器及其制备方法。
本发明采用CsPbBr3,CsPbI3两种具有不同能带结构的无机卤化物PQDs(CsPbX3,X=Cl, Br, I)作为FG-TFTs的俘获层,使用低温原子层沉积(ALD)工艺,低温物理气相沉积(PVD)和溶液法等工艺制备了具有光电可编程的多态存储器件,为高密度存储提供解决思路。
本发明提供的光电编程多态存储器,其结构由下至上依次是:Si衬底背栅电极,阻挡层,PQDs电荷俘获层,隧穿层,IGZO沟道层以及源漏电极;其中电荷俘获层为CsPbBr3和CsPbI3两种量子点的混合。
所述的光电编程多态存储器中,所述背栅电极为P型低阻硅衬底,电阻率<0.005Ω•cm。
所述的光电编程多态存储器中,所述原子层沉积Al2O3阻挡层,沉积温度范围为20℃-40℃,厚度范围为30nm-50nm。
所述的光电编程多态存储器中,所述原子层沉积Al2O3隧穿层,沉积温度范围为20℃-40℃,厚度范围为5nm-15nm。
所述的光电编程多态存储器中,所述电荷俘获层为溶液法制备的CsPbBr3、CsPbI3钙钛矿量子点。
所述的光电编程多态存储器中,所述源漏电极为Ti/Au源漏电极,厚度范围是10/50-40/100。
本发明还提供上述光电编程多态存储器的制备方法,其包含以下步骤:
步骤1,将电阻率<0.005 Ω•cm的低阻硅片作背栅电极,放入原子层沉积反应腔中,抽真空,沉积腔温度范围20℃-40℃;
步骤2,原子层沉积制备Al2O3阻挡层,以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫;
步骤3,溶液法分别制备CsPbBr3、CsPbI3两种量子点,混合均匀后取适量混合量子点,按照特定的转速旋涂于阻挡层上;
步骤4,原子层沉积制备Al2O3隧穿层,沉积腔温度和每个循环工艺与步骤2相同;
步骤5,磁控溅射生长IGZO沟道层,厚度范围为30nm-50nm;
步骤6,对步骤5得到的器件,进行紫外光刻,定义沟道图形,电子束蒸发Ti/Au电极,去胶,无须退火,得到光电编程多态存储器。
较佳的,步骤2原子层沉积Al2O3厚度范围为30nm-50nm。
较佳的,步骤4原子层沉积Al2O3厚度范围为5nm-15nm。
相对于现有技术,本发明具有以下优势:
1.氧化铝阻挡层和隧穿层均采用低温ALD沉积工艺生长。其中ALD工艺具有生长温度低,厚度精确可控,薄膜均匀性好等优点。同时该工艺制备的多态浮栅存储器不需要后退火处理,就可以获得优异的电学性能,既解决了钙钛矿量子点应用于浮栅存储器的工艺兼容问题,又使得本发明未来可应用于柔性电子,生物电子等领域;
2.传统的基于一种俘获层材料的FG-TFTs,为了实现较高的存储密度,一般要求器件在不同存储状态保持105s后阈值电压差别超过1V以上的状态的才描述为不同的编程态。而本发明是通过不同种类钙钛矿量子点对不同波长的光响应,而实现不同的编程态,这种多态存储是由不同波长的光照决定,因此能够在较低的编程电压下实现多态存储,更能满足对存储器件的低功耗要求;
3.本发明创新性的将钙钛矿量子点应用于浮栅存储器的电荷俘获层中,提供了光电条件下多态存储器件制备的工艺参数,为多态存储的开发和研究提供了思路与途径。
附图说明
图1为本发明所制备的光电编程多态浮栅存储器的结构示意图。其中,a为底栅结构示意图,b为顶栅结构示意图。
图2为CsPbBr3,CsPbI3两种量子点混合作为电荷俘获层器件的Id-Vg曲线。其中,a为存储器电压编程特性, b为TFT对照组电压编程特性。
图3为没有电荷俘获层的IGZO薄膜晶体管对照组器件的Id-Vg曲线。
图4为三种不同量子点作为电荷俘获层时器件阈值电压偏移∆Vth与光电编程时光照波长的关系。
具体实施方式
以下结合附图通过具体实施例对本发明作进一步的描述,这些实施例仅用于说明本发明,并不是对本发明保护范围的限制。
实施例1底栅结构
步骤1,将导电衬底放入原子层沉积反应腔中,沉积腔温度范围20℃-40℃,TMA源瓶及各管路温度范围均为20℃-40℃,抽真空;
步骤2,采用原子层沉积工艺制备氧化铝阻挡层。以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫。厚度范围30nm-50nm;
步骤3,以PbBr2,CsBr,PbI2,CsI,二甲基甲酰胺,油酸,油胺,无水甲苯,乙酸甲酯,正己烷等,溶液法制备CsPbBr3,CsPbI3钙钛矿量子点,并以特定转速均匀旋涂于阻挡层上;
步骤4,采用低温原子层沉积工艺制备氧化铝隧穿层。以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫。厚度范围5nm-15nm;
步骤5,磁控溅射生长IGZO沟道层,紫外光刻定义沟道图形,用稀盐酸刻蚀;
步骤6,第二次光刻定义源漏电极图形,丙酮去胶,电子束蒸发Ti/Au源漏电极;厚度范围70nm-130nm。
得到底栅结构光电可编程的多态浮栅存储器,结构示意如图1a所示。
实施例2顶栅结构
步骤1,将衬底放入磁控溅射生长IGZO沟道层,紫外光刻定义沟道图形,用稀盐酸刻蚀;
步骤2,再次光刻定义源漏电极图形,丙酮去胶,电子束蒸发Ti/Au源漏电极。厚度范围70nm-130nm;
步骤3,放入原子层沉积反应腔中,沉积腔温度范围20℃-40℃,TMA源瓶及各管路温度范围均为20℃-40℃,抽真空;
步骤4,采用原子层沉积工艺制备氧化铝阻挡层。以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫。厚度范围30nm-50nm;
步骤5,以PbBr2,CsBr,PbI2,CsI,二甲基甲酰胺,油酸,油胺,无水甲苯,乙酸甲酯,正己烷等,溶液法制备CsPbBr3,CsPbI3钙钛矿量子点,并以特定转速均匀旋涂于阻挡层上;
步骤6,采用低温原子层沉积工艺制备氧化铝隧穿层。以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫;厚度范围5nm-15nm;
步骤7,在隧穿层上沉积顶栅电极层;得到顶栅结构光电可编程的多态浮栅存储器,结构示意如图1b所示。
对比例
步骤1,将导电衬底放入原子层沉积反应腔中,沉积腔温度范围20℃-40℃,TMA源瓶及各管路温度范围均为20℃-40℃,抽真空;
步骤2,采用原子层沉积工艺制备氧化铝阻挡层。以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫。厚度范围35nm-65nm;
步骤3,磁控溅射生长IGZO沟道层,紫外光刻定义沟道图形,用稀盐酸刻蚀;
步骤4,第二次光刻定义源漏电极图形,丙酮去胶,电子束蒸发Ti/Au源漏电极;厚度范围70nm-130nm。
得到对照组器件,没有电荷俘获层的IGZO-TFT。
光电编程性能测试
分别对钙钛矿量子点作电荷俘获层的浮栅存储器和没有电荷俘获层的IGZO-TFT对照组器件做存储性能测试。编程电压条件均为12V10ms,光照强度均为35uw,波长从750nm-500nm。电压编程特性如图2所示,有钙钛矿量子点作电荷俘获层的存储器件,分别在纯电压编程,650nm光照,550nm光照条件时,有明显的阈值电压偏移。而对照组器件在纯电压编程,750nm-500nm光照条件下,均没有阈值电压偏移。上述对比实验证明了钙钛矿量子点作为电荷俘获层时的电荷俘获能力,并且650nm光照时是CsPbI3钙钛矿量子点的光响应,550nm光照时是CsPbBr3钙钛矿量子点的光响应。图3是以CsPbBr3钙钛矿量子点,CsPbI3钙钛矿量子点和两种量子点的混合量子点作为电荷俘获层时,器件的编程特性曲线和阈值电压与光照波长的关系。由图3可明显看出,当以混合量子点作为电荷俘获层时,由于CsPbI3量子点对650nm光照有光响应,而CsPbBr3钙钛矿量子点对550nm光照有光响应,通过改变光电编程时的光照波长可以实现多态存储的目的。
以上实施案例仅仅是对发明技术方案所做的举例说明。本发明所涉及的光电编程多态存储器的制备工艺及应用不仅仅现定于以上实施例中所描述的内容,而是以权利要求所限定的范围为准。本发明所属领域技术人员在该实施例的基础上所做的任何修改或补充或等效替换,都在本发明的权利要求所要求保护的范围内。
综上所述,本发明创新性的将多种钙钛矿量子点应用于浮栅存储器的电荷俘获层中,制备研究了光电可编程的多态存储器,为实现低功耗高密度存储提供了新的途径。而且本发明中器件无需后退火,性能稳定良好,低温原子层沉积工艺等优势可应用于未来柔性电子,生物电子等领域。
尽管本发明的内容已经通过上述优选实施例作了详细介绍,但应当认识到上述的描述不应该被认为是对发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。

Claims (4)

1.一种基于薄膜晶体管结构的光电编程多态存储器,其特征在于,器件结构由下至上依次是:Si衬底背栅电极,阻挡层,PQDs电荷俘获层,隧穿层,IGZO沟道层以及源漏电极;其中:
所述电荷俘获层为CsPbBr3、CsPbI3两种量子点的混合;
所述背栅电极为P型低阻硅衬底,电阻率<0.005 Ω•cm;
所述阻挡层为低温原子层沉积工艺制备的Al2O3阻挡层,沉积温度范围为20℃-40℃,厚度范围为30nm-50nm;所述隧穿层为低温原子层沉积工艺制备的Al2O3隧穿层,沉积温度范围为20℃-40℃,厚度范围为5nm-15nm。
2.如权利要求1所述的光电编程多态存储器,其特征在于,所述IGZO沟道层厚度范围为30-50nm。
3.如权利要求1所述的光电编程多态存储器,其特征在于,所述源漏电极为电子束蒸发制备的Ti/Au,厚度范围是10/50-40/100。
4.如权利要求1-3之一所述光电编程多态存储器的制备方法,其特征在于,具体步骤为:
步骤1,将电阻率<0.005 Ω•cm的低阻硅片作背栅电极,放入原子层沉积反应腔中,抽真空,沉积腔温度范围20℃-40℃;
步骤2,原子层沉积制备Al2O3阻挡层,以三甲基铝和氧等离子体作为反应源,每一个循环周期包括:0.1s-2s三甲基铝脉冲,10s-30s氮气吹扫,0.1s-10s氧气等离子体脉冲,10s-30s氮气吹扫;
步骤3,溶液法分别制备CsPbBr3、CsPbI3两种量子点,混合均匀后取适量混合量子点,旋涂于阻挡层上;
步骤4,原子层沉积制备Al2O3隧穿层,沉积腔温度和每个循环工艺与步骤2相同;
步骤5,磁控溅射生长IGZO沟道层,厚度范围为30nm-50nm;
步骤6,对步骤5得到的器件,进行紫外光刻,定义沟道图形,电子束蒸发Ti/Au电极,去胶,得到光电编程多态存储器。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106450009A (zh) * 2016-08-05 2017-02-22 苏州大学 一种双层钙钛矿发光二极管及其制备方法
CN107482014A (zh) * 2017-07-04 2017-12-15 复旦大学 一种多级单元薄膜晶体管存储器及其制备方法
CN109148594A (zh) * 2018-07-16 2019-01-04 复旦大学 一种高性能薄膜晶体管的近室温制备工艺及应用
KR20190052222A (ko) * 2017-11-08 2019-05-16 한국기계연구원 더블 페로브스카이트 결정 구조를 갖는 비스무스계 양자점, 그 제조 방법 및 이를 포함하는 전자 소자

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106450009A (zh) * 2016-08-05 2017-02-22 苏州大学 一种双层钙钛矿发光二极管及其制备方法
CN107482014A (zh) * 2017-07-04 2017-12-15 复旦大学 一种多级单元薄膜晶体管存储器及其制备方法
KR20190052222A (ko) * 2017-11-08 2019-05-16 한국기계연구원 더블 페로브스카이트 결정 구조를 갖는 비스무스계 양자점, 그 제조 방법 및 이를 포함하는 전자 소자
CN109148594A (zh) * 2018-07-16 2019-01-04 复旦大学 一种高性能薄膜晶体管的近室温制备工艺及应用

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Amplified Spontaneous Emission in Thin Films of CsPbX3 Perovskite Nanocrystals;J. Navarro-Arenas et al;《2019 21st International Conference on Transparent Optical Networks (ICTON)》;20190713;第1-4页 *

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