CN102593065A - Preparation method for backgate thin film transistor storage - Google Patents
Preparation method for backgate thin film transistor storage Download PDFInfo
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- CN102593065A CN102593065A CN201210066084XA CN201210066084A CN102593065A CN 102593065 A CN102593065 A CN 102593065A CN 201210066084X A CN201210066084X A CN 201210066084XA CN 201210066084 A CN201210066084 A CN 201210066084A CN 102593065 A CN102593065 A CN 102593065A
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Abstract
The invention belongs to the technical field of semiconductor integrated circuits and particularly discloses a preparation method for a backgate thin film transistor storage. The method mainly comprises the following steps of: using a heavily doped P type monocrystalline silicon piece as a substrate and an extraction electrode of a gate; growing an Al2O3 thin film by an atomic layer deposition (ALD) method, and using the Al2O3 thin film as a charge baffling layer; depositing a metal nano crystal by the ALD method, and using the metal nano crystal as a charge capturing layer; depositing a SiO2/HfO2/Al2O3 laminated structure by the ALD method, and using the laminated structure as a tunneling layer of the storage; depositing an IGZO thin film by the ALD method, forming a source area by a photoetching and wet-method etching process, and using the source area as a conducting channel; and forming source and drain areas by photoetching technology, depositing a layer of metal, and processing a source electrode and a drain electrode by lift-off technology. The electrical properties of the channel can be well adjusted and controlled by the method, the large-area uniformity of the performance of the storage can be improved, and the reliability such as data preservation property and the tolerance of the storage can be improved.
Description
Technical field
The invention belongs to the semiconductor integrated circuit technical field, be specifically related to a kind of preparation method who carries on the back the gate thin-film transistors memory.
Background technology
Along with the maturation and the development of thin-film transistor (TFT) technology, non-volatile TFT memory is just becoming domestic and international scientific research personnel's research focus.At present, the TFT memory adopts polysilicon to make conducting channel mostly.But, owing to have a large amount of crystal boundaries in the polysilicon raceway groove, can be because of capturing the inversion charge that part is induced and be positioned at the trap at crystal boundary place, and cause the cut-in voltage of memory to squint.In addition, after receiving the deviated stress of drain and gate, can show more serious threshold voltage fluctuation, thereby influence the reliability [1] of device based on the TFT memory of polysilicon raceway groove.This shows that as far as the TFT memory, polysilicon is not a kind of desirable channel material.Japanese scholar in 2004 on " nature " periodical reported first based on the TFT of amorphous indium gallium zinc oxide (a-IGZO) raceway groove, thereby from experimentally having confirmed the practical value of this amorphous oxide semiconductor.Korea S's Samsung Advanced Technology Laboratories in 2008 first public reported the electrology characteristic of the a-IGZO channel TFT memory used towards AS panel (SOP).From then on, step into people's the visual field gradually based on the TFT memory of a-IGZO raceway groove.Different with the oxide semiconductor (like ZnO film) of other polycrystalline attitude, the IGZO film can keep amorphous state in the manufacture craft temperature range, and has low temperature deposition, higher electron mobility (>=10cm
2/ Vs) and bigger bandgap voltage (＞premium properties [2] such as 3.0eV).Therefore, IGZO not only can provide device performance more uniformly as amorphous channel layer, has also omitted the necessary tediously long crystallization process of traditional polysilicon raceway groove.Yet; The preparation technology of the a-IGZO channel layer of at present relevant TFT memory is based on traditional physical vapor deposition (PVD); Like rf magnetron sputtering and pulsed laser deposition etc., the film that adopts these methods to deposit all exists deficiency on the uniformity of compactness and large tracts of land component.Based on above problem, the present invention proposes to adopt the method growth a-IGZO conducting channel of atomic layer deposition (ALD), adopts the laminated construction of ALD growth to do technologies such as electric charge tunnel layer simultaneously, thereby can improve the performance of TFT memory.
List of references
[1]?S.-C.?Chen,?T.-C.?Chang,?P.-Tsun?Liu,?Y.-C.?Wu,?P.-S.?Lin.?Characteristics?of?poly-Si?TFT?combined?with?nonvolatile?SONOS?memory?and?nanowire?channels?structure.?Surface?&?Coatings?Technology?,?202,?pp.1287-1291(2007).
[2]?Y.?S.?Jung,?K.?H.?Lee,?W.-J.?Kim,?W.-J.?Lee,?H.-W.?Choi,?K.?H.?Kim.?Properties?of?In-Ga-Zn-O?thin?films?for?thin?film?transistor?channel?layer?prepared?by?facing?targets?sputtering?method.?Ceramics?International,?38S,?S601-S604,?(2012)。
Summary of the invention
Based on above-mentioned background technology, the present invention proposes a kind of preparation method who carries on the back the gate thin-film transistors memory, its objective is the uniformity and the reliability that improve the memory electric property, obtain low operating voltage simultaneously, fast programming with premium properties such as wipe.
The preparation method of back of the body gate thin-film transistors memory proposed by the invention is to adopt IGZO (the indium gallium zinc oxide) film of ALD growth to make conducting channel; Adopt the ALD assembling SiO
2/ HfO
2/ Al
2O
3Tunnel layer done in laminated construction; Adopt the metallic nano crystal of ALD growth to do electric charge capture layer; Adopt the Al of ALD growth
2O
3Film is done electric charge barrier layer.Concrete steps are following:
(1) adopt resistivity be the heavily doped p type single crystal silicon sheet of 0.008-0.100 Ω cm as substrate, with the RCA cleaning silicon chip is cleaned, then with the oxide layer of hydrofluoric acid removal silicon chip surface;
(2) on cleaned p type single crystal silicon sheet, adopt the method deposit growth Al of ALD
2O
3Film is as the electric charge barrier layer of memory, Al
2O
3The thickness of film is 15-200nm; In the deposition process, underlayer temperature is controlled at 100-300
OCBetween; Growth Al
2O
3Reaction source be trimethyl aluminium and steam;
(3) method that adopts ALD is at Al
2O
3The deposit growing metal is nanocrystalline as electric charge capture layer on the film, and deposition temperature is controlled at 100-400
oBetween the C; The metallic nano crystal that can supply grow comprise that Pt is nanocrystalline, Ru is nanocrystalline or Pd nanocrystalline etc., but be not limited to these;
(4) method of employing ALD, SiO successively from bottom to top grows
2, HfO
2, Al
2O
3Film is to form SiO
2/ HfO
2/ Al
2O
3The laminated construction film, as the tunnel oxide of memory; SiO
2, HfO
2And Al
2O
3All be controlled at 100-300 with the deposition temperature of film
OCBetween, the thickness of each single thin film is 1-10nm;
(5) method of employing ALD, deposit IGZO film () on tunnel oxide is as the conducting channel of memory.Deposition temperature is controlled at 100-300
oIn the C scope.The composition of IGZO film can be through control ZnO, In
2O
3And Ga
2O
3The reaction cycle number realize.For example, in each growth cycle of deposit IGZO film, carry out 2 ZnO reaction cycle, 1 Ga successively
2O
3Reaction cycle, 1 In
2O
3Reaction cycle, the atom in the IGZO film of then being grown is formed near InGaZn
2O
5Entire I GZO growth for Thin Film circulates down according to this growth cycle, and the THICKNESS CONTROL of final IGZO film is between 10-120nm.
Wherein, atomic layer deposition IGZO film can adopt following three kinds of metal organic sources, is respectively cyclopentadienyl group indium, six-(dimethyl amine) gallium, diethyl zinc, and oxidant can adopt water, oxygen or ozone;
(6) spin coating one deck photoresist on the IGZO film, and utilize the method for photoetching to form by the zone of photoresist protection, this zone is the active area of device.Then, utilize wet etching that unprotected IGZO film is carried out etching.It is hydrochloric acid, nitric acid, phosphoric acid or the hydrofluoric acid of 0.01%-2% that etching agent adopts concentration, and etch period is 10-600s.At last, remove photoresist, form the active area of individual devices;
(7) spin coating one deck photoresist again utilizes the method for photoetching on photoresist, to form source, the drain electrode opening area of device;
(8) method deposit one layer thickness through electron beam evaporation is metal A l or the Ag film of 50-250nm;
(9) adopt the method for lift-off to remove photoresist, form source, the drain electrode of device.
Of the present invention having a few:
(1) adopt the ALD method IGZO film of growing, can accurately control the composition of film, improve the large-area uniformity of film, therefore very effective to the performance of improving memory.
(2) adopt the ALD technology to assemble SiO
2/ HfO
2/ Al
2O
3The laminated construction tunnel layer, not only can accurately control the physical thickness of each individual layer, can also obtain the tunnel layer that the interface is clear, defect concentration is low, effective to the performance of optimised devices with the data holding ability that improves memory.
(3) adopt the ALD technology metallic nano crystal of growing, can under less than 400 ℃ temperature, accomplish, therefore compatible mutually with the TFT process heat budget of standard, can easily realize memory integrated on system's panel.
Description of drawings
Fig. 1: on cleaned heavy doping P type silicon substrate, adopt method deposit growth one deck Al of ALD
2O
3Film.
Fig. 2: the method that adopts ALD is at Al
2O
3Growing metal is nanocrystalline on the film.
Fig. 3: adopt the method for ALD, successively deposit SiO
2, HfO
2, Al
2O
3Film forms SiO
2/ HfO
2/ Al
2O
3Laminated construction.
Fig. 4: adopt the method for ALD, deposit one deck IGZO film on laminated construction.
Fig. 5:, on the IGZO film, define active area through photoetching and wet etching.
Fig. 6: remove photoresist, form the active area of device.
Fig. 7: through photoetching process, source, the drain region of definition device.
Fig. 8: adopt electron beam evaporation depositing metal film.
Fig. 9: adopt the method for lift-off to remove photoresist, form source, the drain electrode of device.
Embodiment
Below in conjunction with accompanying drawing and instantiation detailed explanation is carried out in invention.
Step 1: the heavily doped p type single crystal silicon sheet of choosing resistivity and be 0.008-0.100 Ω cm is as substrate, and through the RCA cleaning of standard silicon chip cleaned, and removes the oxide layer of silicon chip surface afterwards with hydrofluoric acid.With reference to Fig. 1, cleaned silicon chip is shown among the figure 200.
Step 2: on cleaned silicon chip, adopt the method deposit growth Al of ALD
2O
3Film is shown among Fig. 1 201 layers.Al
2O
3The thickness of film is 15-200nm; In the deposition process, underlayer temperature is controlled at 100-300
OCBetween; Growth Al
2O
3Reaction source be trimethyl aluminium and steam.
Step 3: the method that adopts ALD is at Al
2O
3Deposit one deck Ru is nanocrystalline on the film, shown among Fig. 2 202.The nanocrystalline reaction source of deposit Ru is cyclopentenyl ruthenium (RuCp
2) and oxygen, deposition temperature is 200-400
oC, the deposit period is 100-500.
Step 4: adopt the method for ALD, from bottom to top deposit growth SiO successively
2, HfO
2, Al
2O
3Film is to form SiO
2/ HfO
2/ Al
2O
3Laminated construction, as the tunnel oxide of device, as 203 layers among Fig. 3,204 layers and 205 layers.In the deposition process, SiO
2Reaction source be three (dimethylamino) silane and oxygen, HfO
2Reaction source be four (ethylmethylamino acid) hafnium and water vapour, Al
2O
3Reaction source be trimethyl aluminium and deionized water; SiO
2, HfO
2And Al
2O
3The deposition temperature of film all is controlled at 100-300
OCBetween; The THICKNESS CONTROL of each single thin film is in the 1-10nm scope.
Step 5: adopt the method for ALD, deposit IGZO film is in order to form conducting channel, shown in 206 layers among Fig. 4 on tunnel oxide.Deposit IGZO film comprises three kinds of metal organic sources, is respectively cyclopentadienyl group indium, six-(dimethyl amine) gallium, diethyl zinc, and oxidant adopts ozone, deionized water.In reaction chamber, cyclopentadienyl group indium and ozone reaction generate In
2O
3, six-(dimethyl amine) gallium and deionized water reaction generate Ga
2O
3, diethyl zinc and deionized water reaction generate ZnO.The composition of IGZO film can be through control ZnO, In
2O
3And Ga
2O
3The reaction cycle number realize.For example, in each growth cycle of deposit IGZO film, carry out 2 ZnO reaction cycle, 1 Ga successively
2O
3Reaction cycle, 1 In
2O
3Reaction cycle, the atom in the IGZO film of then being grown is formed near InGaZn
2O
5Entire I GZO growth for Thin Film circulates down according to this growth cycle, and the THICKNESS CONTROL of final IGZO film is between 10-120nm, and the deposition temperature of whole process is controlled at 100-300
oIn the C scope.
Step 6: spin coating one deck photoresist on the IGZO film, and utilize the method for photoetching to form by the zone of photoresist protection, this zone is the active area of device, shown among Fig. 5 207 layers.Then, adopt concentration be hydrochloric acid, nitric acid, phosphoric acid or the hydrofluoric acid of 0.01%-2% as etching agent, utilize the method for wet etching that the IGZO film is carried out etching, etch period is 10-600s.Remove photoresist afterwards, form the active area of individual devices, as shown in Figure 6.
Step 7: spin coating one deck photoresist again, utilize the method for photoetching on photoresist, to form source, the drain electrode opening area of device, as shown in Figure 7, wherein 208 layers are formation source, the needed photoresist of drain region.
Step 8: method deposit one layer thickness through electron beam evaporation is metal A l or the Ag film of 50-250nm, and is as shown in Figure 8, and wherein 209 layers is metallic film.
Step 9: adopt source, the drain electrode of the method formation device of lift-off, as shown in Figure 9, wherein 209 layers is metal electrode.
Claims (3)
1. preparation method who carries on the back the gate thin-film transistors memory is characterized in that concrete steps are following:
Adopt resistivity be the heavily doped p type single crystal silicon sheet of 0.008-0.100 Ω cm as substrate, with the RCA cleaning silicon chip is cleaned, then with the oxide layer of hydrofluoric acid removal silicon chip surface;
On cleaned p type single crystal silicon sheet, adopt the method deposit growth Al of ALD
2O
3Film is as the electric charge barrier layer of memory, Al
2O
3The thickness of film is 15-200nm; In the deposition process, underlayer temperature is controlled at 100-300
OCBetween; Growth Al
2O
3Reaction source be trimethyl aluminium and steam;
The method that adopts ALD is at Al
2O
3The deposit growing metal is nanocrystalline as electric charge capture layer on the film, and deposition temperature is controlled at 100-400
oBetween the C;
Adopt the method for ALD, SiO successively from bottom to top grows
2, HfO
2, Al
2O
3Film is to form SiO
2/ HfO
2/ Al
2O
3The laminated construction film, as the tunnel oxide of memory; SiO
2, HfO
2And Al
2O
3Be controlled at 100-300 with the deposition temperature of film
OCBetween, the thickness of each single thin film is 1-10nm;
Adopt the method for ALD, deposit IGZO film on tunnel oxide is as the conducting channel of memory; Deposition temperature is controlled at 100-300
oIn the C scope, the THICKNESS CONTROL of IGZO film is between 10-120nm;
Spin coating one deck photoresist on the IGZO film, and utilize the method for photoetching to form by the zone of photoresist protection, this zone is the active area of device; Then, utilize wet etching that unprotected IGZO film is carried out etching; It is hydrochloric acid, nitric acid, phosphoric acid or the hydrofluoric acid of 0.01%-2% that etching agent adopts concentration, and etch period is 10-600s; At last, remove photoresist, form the active area of individual devices;
Spin coating one deck photoresist again utilizes the method for photoetching on photoresist, to form source, the drain electrode opening area of device;
Method deposit one layer thickness through electron beam evaporation is metal A l or the Ag film of 50-250nm;
Adopt the method for lift-off to remove photoresist, form source, the drain electrode of device.
2. preparation method according to claim 1 is characterized in that described metallic nano crystal is that Pt is nanocrystalline, Ru is nanocrystalline or Pd is nanocrystalline.
3. preparation method according to claim 1; It is characterized in that in the step (); Atomic layer deposition IGZO film adopts three kinds of metal organic sources, is respectively cyclopentadienyl group indium, six-(dimethyl amine) gallium, diethyl zinc, and oxidant adopts water, oxygen or ozone.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105359257A (en) * | 2013-07-09 | 2016-02-24 | 三菱瓦斯化学株式会社 | Liquid composition for cleaning/removing copper-containing adhering matter from surface of oxide comprising indium, gallium, zinc, and oxygen (IGZO), method for cleaning IGZO surface using said liquid composition, and substrate cleaned using said method for cleaning |
| CN107482014A (en) * | 2017-07-04 | 2017-12-15 | 复旦大学 | A kind of multi-level unit thin-film transistor memory and preparation method thereof |
| CN110211883A (en) * | 2019-05-23 | 2019-09-06 | 深圳市华星光电技术有限公司 | A kind of array substrate and preparation method thereof |
| CN110610867A (en) * | 2019-08-20 | 2019-12-24 | 深圳市华星光电技术有限公司 | Thin film transistor preparation method and thin film transistor |
| CN111463265A (en) * | 2020-04-14 | 2020-07-28 | 有研工程技术研究院有限公司 | Charge trapping memory based on two-dimensional material and preparation method thereof |
| CN112164656A (en) * | 2020-09-24 | 2021-01-01 | 山东华芯半导体有限公司 | Method for improving performance of flash memory unit by using ITO as source and drain |
| CN112300803A (en) * | 2020-10-30 | 2021-02-02 | 山东华芯半导体有限公司 | Hydrofluoric acid etching solution for etching gallium indium zinc oxide film and application thereof |
| CN112309833A (en) * | 2020-10-30 | 2021-02-02 | 山东华芯半导体有限公司 | Flash memory unit for depositing IGZO film based on ALD (atomic layer deposition), and preparation method and application thereof |
| CN113380543A (en) * | 2021-06-09 | 2021-09-10 | 广州天极电子科技股份有限公司 | High voltage-resistant thin film capacitor and preparation method thereof |
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|---|---|---|---|---|
| CN105359257B (en) * | 2013-07-09 | 2018-03-06 | 三菱瓦斯化学株式会社 | From the surface clean and the fluid composition for removing cupric attachment and the cleaning method on the IGZO surfaces for having used the fluid composition, and the substrate using cleaning method cleaning of the oxide (IGZO) being made up of indium, gallium, zinc and oxygen |
| CN105359257A (en) * | 2013-07-09 | 2016-02-24 | 三菱瓦斯化学株式会社 | Liquid composition for cleaning/removing copper-containing adhering matter from surface of oxide comprising indium, gallium, zinc, and oxygen (IGZO), method for cleaning IGZO surface using said liquid composition, and substrate cleaned using said method for cleaning |
| CN107482014A (en) * | 2017-07-04 | 2017-12-15 | 复旦大学 | A kind of multi-level unit thin-film transistor memory and preparation method thereof |
| WO2019007009A1 (en) * | 2017-07-04 | 2019-01-10 | 复旦大学 | Multilevel cell thin film transistor memory and preparation method therefor |
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| CN110211883B (en) * | 2019-05-23 | 2020-10-16 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN110211883A (en) * | 2019-05-23 | 2019-09-06 | 深圳市华星光电技术有限公司 | A kind of array substrate and preparation method thereof |
| CN110610867A (en) * | 2019-08-20 | 2019-12-24 | 深圳市华星光电技术有限公司 | Thin film transistor preparation method and thin film transistor |
| CN111463265A (en) * | 2020-04-14 | 2020-07-28 | 有研工程技术研究院有限公司 | Charge trapping memory based on two-dimensional material and preparation method thereof |
| CN112164656A (en) * | 2020-09-24 | 2021-01-01 | 山东华芯半导体有限公司 | Method for improving performance of flash memory unit by using ITO as source and drain |
| CN112300803A (en) * | 2020-10-30 | 2021-02-02 | 山东华芯半导体有限公司 | Hydrofluoric acid etching solution for etching gallium indium zinc oxide film and application thereof |
| CN112309833A (en) * | 2020-10-30 | 2021-02-02 | 山东华芯半导体有限公司 | Flash memory unit for depositing IGZO film based on ALD (atomic layer deposition), and preparation method and application thereof |
| CN113380543A (en) * | 2021-06-09 | 2021-09-10 | 广州天极电子科技股份有限公司 | High voltage-resistant thin film capacitor and preparation method thereof |
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