CN102244108A - Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer - Google Patents
Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer Download PDFInfo
- Publication number
- CN102244108A CN102244108A CN2011101716689A CN201110171668A CN102244108A CN 102244108 A CN102244108 A CN 102244108A CN 2011101716689 A CN2011101716689 A CN 2011101716689A CN 201110171668 A CN201110171668 A CN 201110171668A CN 102244108 A CN102244108 A CN 102244108A
- Authority
- CN
- China
- Prior art keywords
- sic
- layer
- annealing
- dielectric layer
- sic epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with a composite dielectric layer, and mainly solves the problem that the conventional SiC MOS capacitor has high interface-state density and weak voltage endurance. The structure of the capacitor is that: an N-type heavy doping SiC substrate layer, an N-type light doping SiC epitaxy layer, an SiO2 transition layer and an HfxAl1-xON dielectric layer are sequentially arranged from bottom to top; the back of the SiC substrate and the surface of the HfxAl1-xON are sputtered with metal Al to form positive and negative electrodes respectively; the N-type SiC epitaxy layer is 10 to 100 mu m thick, the doping concentration is 1*10<15> to 5*10<15>cm<-3>; the SiO2 transition layer is 1 to 15 mu m thick, and the HfxAl1-xON dielectric layer is 10 to 30 mu m thick. The SiO2 transition layer and the HfxAl1-xON layer form a composite dielectric layer structure so as to reduce the interface-state intensity of the dielectric layer and the SiC interface, reduce the current leakage of the dielectric layer, improve the voltage-resisting capability of the dielectric layer, and improve the reliability of the SiC MOS devices. The invention also discloses a manufacturing method for a SiC power integrated circuit and a SiC power isolation device.
Description
Technical field
The invention belongs to microelectronics technology, relate to microelectronic component, particularly a kind of SiC mos capacitance of compound medium layer can be used for the making of SiC power integrated circuit and SiC power splitter spare.
Background technology
The SiC material becomes the ideal material of making high temperature, high power, high frequency and highly anti-radiation device as the semi-conductive typical case's representative of the third generation with its good physicochemical characteristics.The SiC material has that energy gap is big, critical breakdown electric field is high, the thermal conductivity advantages of higher with comparing with the second generation semi-conducting material that with GaAs is representative with the first generation semi-conducting material of Si representative, therefore becomes the focus of microelectric technique research field for the research and development of SiC material and device, technology at present.
Compare with other wide bandgap semiconductor, a significant advantage of SiC material is exactly directly to generate SiO on its surface by the method for hot oxygen
2, this just means that the SiC material is to make SiO such as high-power MOSFET and IGBT
2The ideal material of/SiC MOS device.But, hinder SiO at present
2/ SiC MOS device reasons of development have following some:
At first, compare the SiC surface with the Si material and form SiO by dry-oxygen oxidation
2Suitable slow of speed, SiO
2Thickness can not grow too thick.
Secondly, in the process of dry-oxygen oxidation because SiO
2Interface state density in the/SiC structure is high especially, causes SiO to the greatest extent
2The mobility of raceway groove is very low in the/SiC MOS device, and conducting resistance is very high.
Because the critical breakdown electric field of SiC material is very high, be at last ,～3 * 10
6V/cm, thereby under the condition of device reverse blocking, SiO after the electric field of SiC inside reaches this critical value
2In electric field maximum just reached approximately～7.5 * 10
6V/cm, so high electric field strength can cause the no good cake that the reliability of device becomes.Therefore, which kind of new technology means research at present adopts improve SiO
2/ SiC interfacial characteristics reduces interface state density raising oxide layer reliability and becomes the field that receives much concern in the SiC device research.
At present, improve SiO
2The main means of/SiC interfacial characteristics are to SiO
2Nitrogen treatment is carried out at/SiC interface, has both adopted at NO or N
2In the environment of O to SiO
2Layer carries out annealing in process or utilizes N
+The method that ion injects is to SiO
2Nitrogenize is carried out at/SiC interface.Though these two kinds of process meanses can still exist some negative effects at the interfacial characteristics that to a certain degree improves device, as the content of the uncontrollable nitrogen at the interface of first method, technology difficulty is bigger.Though second method can be controlled the content of nitrogen at the interface accurately and effectively reduce interface state density, N
+Ion implantation process has caused oxide layer and interface crystal lattice to sustain damage, and device property is affected.And above-mentioned two kinds of methods all can not be improved the reliability of oxide layer.At the integrity problem of oxide layer, there is the researcher to adopt the high K medium material, as uses HfO in addition
2, Al
2O
3Replace SiO
2The layer as MOS device medium material, though this method at the voltage endurance capability that has to a certain degree improved dielectric layer, this technology can not effectively reduce the interface state density of device, has caused gate leak current excessive.
Summary of the invention
The object of the invention is the deficiency at above-mentioned prior art, SiC mos capacitance of a kind of compound medium layer and preparation method thereof is provided,, has reduced gate leak current to reduce interface state density, and further improve the voltage endurance capability of dielectric layer, improve the reliability of device.
For achieving the above object, SiC mos capacitance of the present invention comprises SiC substrate, gate dielectric layer and positive and negative electrode, it is characterized in that N type heavy doping SiC substrate layer is provided with the SiC epitaxial loayer that the N type is gently mixed, and the SiC epitaxial loayer is provided with SiO
2Transition zone, SiO
2Transition zone is provided with Hf
xAl
1-xThe ON layer, this SiO
2Transition zone and Hf
xAl
1-xThe ON layer is formed the composite gate dielectric layer structure, and positive and negative electrode is respectively from Hf
xAl
1-xDraw at the back side of the surface of ON and SiC substrate.
The described SiC epitaxial loayer of gently mixing, thickness are 10～100 μ m, and doping content is 1 * 10
15～5 * 10
15Cm
-3
Described SiO
2The thickness of transition zone is 1～15nm.
Described Hf
xAl
1-xThe thickness of ON layer is 10nm～30nm.
For achieving the above object, SiC mos capacitance manufacture method of the present invention comprises the steps:
(1) N type SiC epitaxial wafer being carried out clean, is that dry-oxygen oxidation one layer thickness is the SiO of 1nm～15nm under 1050 ± 5 ℃ the condition in temperature
2
(2) to N type SiC epitaxial wafer after the oxidation, finish in Ar compression ring border annealing successively, in the wet oxygen environment wet-oxygen oxidation annealing and in Ar compression ring border cooling processing;
(3) utilize the method for atomic layer deposition, deposit one layer thickness is the gate medium Hf of 10nm～30nm on the SiC epitaxial wafer after annealing and the cooling processing
xAl
1-xON is 750 ± 5 ℃ N again in temperature
28min anneals in the compression ring border;
(4) the SiC epitaxial wafer that will obtain by above-mentioned steps, the method for utilizing magnetron sputtering is at gate medium Hf
xAl
1-xL is as positive electrode for ON surface sputtering metal A, and as negative electrode, the 30min that anneals in temperature is 400 ± 5 ℃ Ar compression ring border again finishes the making of capacitor element at the back spatter metal A l of SiC epitaxial wafer.
Above-mentioned steps (2) is described anneals in Ar compression ring border, and its process conditions are: annealing temperature is 1050 ± 5 ℃, and annealing time is 30min.
The described wet-oxygen oxidation annealing in the wet oxygen environment of above-mentioned steps (2), its process conditions are: annealing temperature is 950 ± 5 ℃, annealing time is 1h.
Above-mentioned steps (2) is described cools off cold treatment in Ar compression ring border, be the speed cooling according to 3 ℃/min.
The described method of utilizing atomic layer deposition of above-mentioned steps (3), deposit one layer thickness is the gate medium Hf of 10nm～30nm on the SiC epitaxial wafer after annealing and the cooling processing
xAl
1-xON, its process conditions are: deposition temperature is 200 ℃-300 ℃, and deposition time is 1h-2h.
The present invention has following advantage:
1) the present invention since on the SiC epitaxial wafer, adopt atomic layer deposition the method deposit Hf
xAl
1-xON is as the gate medium of SiC mos capacitance, and the N essence in this gate dielectric material can with the interface of SiC epitaxial wafer and gate medium and near the Si of Cheng Jian and C form Si ≡ N, N ≡ C at the interface, thereby mitigation interfacial stress, reduce dangling bonds, improve interfacial characteristics, reduce gate leak current;
2) the present invention is owing to adopt gate dielectric material Hf
xAl
1-xThe dielectric constant of ON is greater than 20, thereby improved the maximum critical electric field of this dielectric layer, improved the voltage endurance capability of device, improved the reliability of device;
3) the present invention is owing to adopt the wet-oxygen oxidation annealing process, and the hydrogen ion that has ionization in this annealing process procedure is passivation SiC epitaxial wafer and gate medium interface and nearly existence at the interface C bunch effectively, plays the effect of further reduction interface state density.
Description of drawings
Fig. 1 is a structure chart of the present invention;
Fig. 2 is a process chart of the present invention.
Embodiment
With reference to Fig. 1, device architecture of the present invention is followed successively by N type heavy doping SiC substrate layer, the lightly doped SiC epitaxial loayer of N type, SiO from bottom to top
2Transition zone and Hf
xAl
1-xThe ON dielectric layer.Wherein N type heavy doping SiC substrate layer thickness is that 380 μ m doping contents are 5 * 10
18Cm
-3, the lightly doped SiC epitaxy layer thickness of N type is 10～100 μ m, doping content is 1 * 10
15～5 * 10
15Cm
-3, SiO
2Transition region thickness is 1～15nm, Hf
xAl
1-xThe ON thickness of dielectric layers is 10nm～30nm.This SiO
2Transition zone and Hf
xAl
1-xThe ON layer is formed the composite gate dielectric layer structure, to reduce the interface state density at gate dielectric layer and SiC interface, reduces the gate dielectric layer leakage current, improves the voltage endurance capability of gate dielectric layer, improves the reliability of device; The back side of SiC substrate and Hf
xAl
1-xThe surface sputtering metal A l of ON, thickness is 200nm, respectively as the positive and negative electrode of this electric capacity.
With reference to Fig. 2, manufacture method of the present invention provides following three kinds of embodiment:
Embodiment 1
Step 1, growth N type SiC epitaxial loayer.
With thickness is 380 μ m, and doping content is 5 * 10
18Cm
-3N type SiC backing material place the SiC epitaxial furnace, 1570 ℃ of growth temperatures, the layer thickness of growing is 10 μ m, doping content is 5 * 10
15Cm
-3 N type SiC epitaxial wafer.
Step 2 is carried out preliminary treatment to the N type SiC epitaxial wafer of being grown.
2.1) with deionized water N type SiC epitaxial wafer is carried out ultrasonic cleaning;
2.2) be that 80% sulfuric acid cleans the SiC epitaxial wafer with dense crossing, boil 10min after, soak 30min;
2.3) with washed with de-ionized water SiC epitaxial wafer number time;
2.4) with ratio 5: 1: 1 H
2O, H
2O
2And the mixed liquor formed of hydrochloric acid, the SiC epitaxial wafer in being 80 ℃ mixed liquor, temperature is soaked 5min, cleans with hydrofluoric acid solution, with washed with de-ionized water number time, dry with infrared lamp at last again.
Step 3, dry-oxygen oxidation SiO
2Layer.
Pretreated N type SiC epitaxial wafer is placed oxidation furnace, and oxidizing temperature is 1050 ± 5 ℃, and oxidation one layer thickness is the SiO of 1nm in dried oxygen atmosphere
2
Step 4, annealing and cooling processing.
At first, the N type SiC epitaxial wafer after the oxidation is placed at Ar atmosphere encloses middle annealing, annealing temperature is 1050 ± 5 ℃, and annealing time is 30min;
Then, place the wet oxygen atmosphere to carry out wet-oxygen oxidation annealing the SiC epitaxial wafer after the annealing, annealing temperature is 950 ± 5 ℃, and annealing time is 1h;
At last, the SiC epitaxial wafer after the annealing being placed Ar atmosphere enclose with the speed of 3 ℃/min cools off.
Step 5, deposit gate dielectric material Hf
xAl
1-xON and annealing.
5.1) the thick Hf of method deposit one deck 30nm of employing atomic layer deposition on the SiC epitaxial wafer after the cooling processing
xAl
1-xON, deposition temperature are 300 ℃, and deposition time is 2h;
5.2) with the SiC epitaxial wafer after the deposit at N
2Anneal in the atmosphere, annealing temperature is 750 ± 5 ℃, and annealing time is 8min.
Step 7, splash-proofing sputtering metal Al electrode and annealing.
6.1) on the SiC epitaxial wafer after the annealing, the method for utilizing magnetron sputtering is at gate medium Hf
xAl
1-xL is as positive electrode for ON surface sputtering metal A, at the back spatter metal A l of SiC epitaxial wafer as negative electrode;
6.2) the SiC epitaxial wafer behind the sputtering electrode is placed temperature is 400 ± 5 ℃ the Ar compression ring border 30min that anneals, and finishes the making of whole capacitor.
Embodiment 2
Step 1, growth N type SiC epitaxial loayer.
With thickness is 380 μ m, and doping content is 5 * 10
18Cm
-3N type SiC backing material place the SiC epitaxial furnace, 1570 ℃ of growth temperatures, the layer thickness of growing is 50 μ m, doping content is 2 * 10
15Cm
-3N type SiC epitaxial wafer.
Step 2 is carried out preliminary treatment to the N type SiC epitaxial wafer of being grown.
At first, with deionized water N type SiC epitaxial wafer is carried out ultrasonic cleaning;
Then, be that 80% sulfuric acid cleans the SiC epitaxial wafer with dense crossing, boil 10min after, soak 30min;
Then, with washed with de-ionized water SiC epitaxial wafer number time;
Then, with ratio be 5: 1: 1 H
2O, H
2O
2And the mixed liquor formed of hydrochloric acid, described SiC epitaxial wafer in being 80 ℃ mixed liquor, temperature is soaked 5min, cleans with hydrofluoric acid solution, with washed with de-ionized water number time, dry with infrared lamp at last again.
Step 3, dry-oxygen oxidation SiO
2Layer.
Pretreated N type SiC epitaxial wafer is placed oxidation furnace, and oxidizing temperature is 1050 ± 5 ℃, and oxidation one layer thickness is the SiO of 8nm in dried oxygen atmosphere
2
Step 4, annealing and cooling processing.
4a) the N type SiC epitaxial wafer after the oxidation is placed at Ar atmosphere and encloses middle annealing, annealing temperature is 1050 ± 5 ℃, and annealing time is 30min;
4b) the SiC epitaxial wafer after will annealing places the wet oxygen atmosphere to carry out wet-oxygen oxidation annealing, and annealing temperature is 950 ± 5 ℃, and annealing time is 1h;
4c) the SiC epitaxial wafer after will annealing places Ar atmosphere to enclose speed cooling with 3 ℃/min.
Step 5, deposit gate dielectric material Hf
xAl
1-xON and annealing.
5a) the thick Hf of method deposit one deck 20nm of employing atomic layer deposition on the SiC epitaxial wafer after the cooling processing
xAl
1-xON, deposition temperature are 250 ℃, and deposition time is 1.5h;
5b) with the SiC epitaxial wafer after the deposit at N
2Anneal in the atmosphere, annealing temperature is 750 ± 5 ℃, and annealing time is 8min.
Step 6, sputter Al electrode and annealing.
6a) on the SiC epitaxial wafer after the annealing, the method for utilizing magnetron sputtering is at gate medium Hf
xAl
1-xL is as positive electrode for ON surface sputtering metal A, at the back spatter metal A l of SiC epitaxial wafer as negative electrode;
6b) the SiC epitaxial wafer behind the sputtering electrode being placed temperature is 400 ± 5 ℃ the Ar compression ring border 30min that anneals, and finishes the making of whole capacitor.
Embodiment 3
Steps A, N type SiC outer layer growth.
With thickness is that 380 μ m doping contents are 5 * 10
18Cm
-3N type SiC substrate slice place SiC epitaxial furnace growth, 1600 ℃ of growth temperatures, the layer thickness of growing is 100 μ m, doping content is 1 * 10
15Cm
-3N type SiC epitaxial loayer.
Step B carries out preliminary treatment to the N type SiC epitaxial wafer of being grown.
B1) with deionized water N type SiC epitaxial wafer is carried out ultrasonic cleaning;
B2) be that 80% sulfuric acid cleans the SiC epitaxial wafer with dense crossing, boil 10min after, soak 30min;
B3) with washed with de-ionized water SiC epitaxial wafer number time;
B4) ratio is 5: 1: 1 H
2O, H
2O
2And the mixed liquor formed of hydrochloric acid, be to soak 5min in 80 ℃ of mixed liquors with described SiC epitaxial wafer in temperature, clean with hydrofluoric acid solution, with washed with de-ionized water number time, dry with infrared lamp at last again.
Step C, dry-oxygen oxidation SiO
2Layer.
Pretreated N type SiC epitaxial wafer is placed oxidation furnace, and oxidizing temperature is 1050 ± 5 ℃, and oxidation one layer thickness is the SiO of 15nm in dried oxygen atmosphere
2
Step D, annealing and cooling processing.
D1) the N type SiC epitaxial wafer after the oxidation is placed at Ar atmosphere and encloses middle annealing, annealing temperature is 1050 ± 5 ℃, and annealing time is 30min;
D2) the SiC epitaxial wafer after will annealing places the annealing of wet oxygen atmosphere wet-oxygen oxidation, and annealing temperature is 950 ± 5 ℃, and annealing time is 1h;
D3) the SiC epitaxial wafer after will annealing places Ar atmosphere to enclose speed cooling with 3 ℃/min.
Step e, deposit gate dielectric material Hf
xAl
1-xON and annealing.
E1) the thick Hf of method deposit one deck 10nm of employing atomic layer deposition on the SiC epitaxial wafer after the cooling processing
xAl
1-xON, deposition temperature are 200 ℃, and deposition time is 1h;
E2) with the SiC epitaxial wafer after the deposit at N
2Anneal in the atmosphere, annealing temperature is 750 ± 5 ℃, and annealing time is 8min.
Step F, sputter Al electrode and annealing.
F1) on the SiC epitaxial wafer after the annealing, the method for utilizing magnetron sputtering is at gate medium Hf
xAl
1-xL is as positive electrode for ON surface sputtering metal A, at the back spatter metal A l of SiC epitaxial wafer as negative electrode;
F2) the SiC epitaxial wafer behind the sputtering electrode being placed temperature is 400 ± 5 ℃ the Ar compression ring border 30min that anneals, and finishes the making of whole capacitor.
Method of the present invention is not limited to above-mentioned 3 kinds of embodiment, obviously anyly can carry out the replacing of different parameters per capita under technical conceive of the present invention, but these are all within protection scope of the present invention.
Claims (9)
1. the SiC mos capacitance of a compound medium layer comprises SiC substrate, gate dielectric layer and positive and negative electrode, it is characterized in that N type heavy doping SiC substrate layer is provided with the SiC epitaxial loayer that the N type is gently mixed, and the SiC epitaxial loayer is provided with SiO
2Transition zone, SiO
2Transition zone is provided with Hf
xAl
1-xThe ON layer, this SiO
2Transition zone and Hf
xAl
1-xThe ON layer is formed the composite gate dielectric layer structure, and positive and negative electrode is respectively from Hf
xAl
1-xDraw at the back side of the surface of ON and SiC substrate.
2. SiC mos capacitance according to claim 1 is characterized in that the SiC epitaxial loayer that described nothing is mixed, and thickness is 10～100 μ m, and doping content is 1 * 10
15～5 * 10
15Cm
-3
3. according to the described SiC mos capacitance of claim 1, it is characterized in that described SiO
2The thickness of transition zone is 1～15nm.
4. according to the described SiC mos capacitance of claim 1, it is characterized in that described Hf
xAl
1-xThe thickness of ON layer is 10nm～30nm.
5. the SiC mos capacitance manufacture method of a compound medium layer comprises the steps:
(1) N type SiC epitaxial wafer being carried out clean, is that dry-oxygen oxidation one layer thickness is the SiO of 1nm～15nm under 1050 ± 5 ℃ the condition in temperature
2
(2) to N type SiC epitaxial wafer after the oxidation, finish in Ar compression ring border annealing successively, in the wet oxygen environment wet-oxygen oxidation annealing and in Ar compression ring border cooling processing;
(3) utilize the method for atomic layer deposition, deposit one layer thickness is the gate medium Hf of 10nm～30nm on the SiC epitaxial wafer after annealing and the cooling processing
xAl
1-xON is 750 ± 5 ℃ N again in temperature
28min anneals in the compression ring border;
(4) the SiC epitaxial wafer that will obtain by above-mentioned steps, the method for utilizing magnetron sputtering is at gate medium Hf
xAl
1-xL is as positive electrode for ON surface sputtering metal A, and as negative electrode, the 30min that anneals in temperature is 400 ± 5 ℃ Ar compression ring border again finishes the making of whole capacitor at the back spatter metal A l of SiC epitaxial wafer.
6. SiC mos capacitance manufacture method according to claim 5, wherein step (2) is described anneals in Ar compression ring border, and its process conditions are: annealing temperature is 1050 ± 5 ℃, and annealing time is 30min.
7. SiC mos capacitance manufacture method according to claim 5, the wherein described wet-oxygen oxidation annealing in the wet oxygen environment of step (2), its process conditions are: annealing temperature is 950 ± 5 ℃, annealing time is 1h.
8. SiC mos capacitance manufacture method according to claim 5, wherein step (2) is described cools off cold treatment in Ar compression ring border, be the speed cooling according to 3 ℃/min.
9. SiC mos capacitance manufacture method according to claim 5, the described method of utilizing atomic layer deposition of step (3) wherein, deposit one layer thickness is the gate medium Hf of 15nm～30nm on the SiC epitaxial wafer after annealing and the cooling processing
xAl
1-xON, its process conditions are: deposition temperature is 200 ℃-300 ℃, and deposition time is 1h-2h.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101716689A CN102244108A (en) | 2011-06-23 | 2011-06-23 | Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101716689A CN102244108A (en) | 2011-06-23 | 2011-06-23 | Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102244108A true CN102244108A (en) | 2011-11-16 |
Family
ID=44962060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101716689A Pending CN102244108A (en) | 2011-06-23 | 2011-06-23 | Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102244108A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102629559A (en) * | 2012-04-20 | 2012-08-08 | 西安电子科技大学 | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor |
| CN102842489A (en) * | 2012-09-10 | 2012-12-26 | 西安电子科技大学 | Preparation method for low excursion flat belt voltage silicon carbide (SiC) metal oxide semiconductor (MOS) capacitance |
| CN102867754A (en) * | 2012-09-07 | 2013-01-09 | 清华大学 | Two-dimensional material nanometer device based on inversion process and forming method of two-dimensional material nanometer device |
| CN103326234A (en) * | 2012-03-20 | 2013-09-25 | 山东华光光电子有限公司 | High-power semiconductor laser transition heat sink and preparation method thereof |
| CN104037238A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104037240A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104037239A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104600127A (en) * | 2015-01-07 | 2015-05-06 | 西安电子科技大学 | SiC metal oxide semiconductor (MOS) capacitor of Al2O3/LaScO3/SiO2 stacked gate dielectric layer and production method of SiC MOS capacitor |
| CN105244264A (en) * | 2015-10-28 | 2016-01-13 | 株洲南车时代电气股份有限公司 | Composite gate structure capacitor and manufacturing method thereof |
| US9373691B2 (en) | 2013-08-07 | 2016-06-21 | GlobalFoundries, Inc. | Transistor with bonded gate dielectric |
| CN107093548A (en) * | 2017-04-20 | 2017-08-25 | 泰科天润半导体科技（北京）有限公司 | The method for preparing SiC base MOS device gate dielectric membranes |
| CN110212031A (en) * | 2019-05-24 | 2019-09-06 | 华中科技大学 | A kind of carbide MOS devices and preparation method thereof |
| CN113555441A (en) * | 2021-06-09 | 2021-10-26 | 浙江芯国半导体有限公司 | SiC-based MIS device and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540279A (en) * | 2009-04-14 | 2009-09-23 | 西安电子科技大学 | Method for manufacturing SiC MOS capacitor with low interface state density |
| CN101620990A (en) * | 2009-07-17 | 2010-01-06 | 西安电子科技大学 | Method for reducing 4H-SiC intrinsic deep energy level defects |
-
2011
- 2011-06-23 CN CN2011101716689A patent/CN102244108A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540279A (en) * | 2009-04-14 | 2009-09-23 | 西安电子科技大学 | Method for manufacturing SiC MOS capacitor with low interface state density |
| CN101620990A (en) * | 2009-07-17 | 2010-01-06 | 西安电子科技大学 | Method for reducing 4H-SiC intrinsic deep energy level defects |
Non-Patent Citations (3)
| Title |
|---|
| L. M. LIN 等: "High-k gate stack HfxTi1-xON/SiO2 for SiC MOS devices", 《J MATER SCI: MATER ELECTRON》, vol. 19, 31 December 2008 (2008-12-31) * |
| M. WOLBORSKI等: "Improved Properties of AlON/4H-SiC Interface for Passivation Studies", 《MATERIALS SCIENCE FORUM 》, vol. 600603, 26 September 2008 (2008-09-26) * |
| TAKUJI HOSOI 等: "AlON/SiO2 Stacked Gate Dielectrics for 4H-SiC MIS Devices", 《MATERIALS SCIENCE FORUM》, vol. 615617, 2 March 2009 (2009-03-02), pages 542 - 1 * |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103326234A (en) * | 2012-03-20 | 2013-09-25 | 山东华光光电子有限公司 | High-power semiconductor laser transition heat sink and preparation method thereof |
| CN103326234B (en) * | 2012-03-20 | 2016-01-06 | 山东华光光电子有限公司 | A kind of high-power semiconductor laser transition heat sink and preparation method thereof |
| CN102629559B (en) * | 2012-04-20 | 2014-07-09 | 西安电子科技大学 | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor |
| CN102629559A (en) * | 2012-04-20 | 2012-08-08 | 西安电子科技大学 | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor |
| CN102867754A (en) * | 2012-09-07 | 2013-01-09 | 清华大学 | Two-dimensional material nanometer device based on inversion process and forming method of two-dimensional material nanometer device |
| CN102842489A (en) * | 2012-09-10 | 2012-12-26 | 西安电子科技大学 | Preparation method for low excursion flat belt voltage silicon carbide (SiC) metal oxide semiconductor (MOS) capacitance |
| US9373691B2 (en) | 2013-08-07 | 2016-06-21 | GlobalFoundries, Inc. | Transistor with bonded gate dielectric |
| CN104037238A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104037240A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104037239A (en) * | 2014-06-26 | 2014-09-10 | 西安电子科技大学 | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method |
| CN104600127A (en) * | 2015-01-07 | 2015-05-06 | 西安电子科技大学 | SiC metal oxide semiconductor (MOS) capacitor of Al2O3/LaScO3/SiO2 stacked gate dielectric layer and production method of SiC MOS capacitor |
| CN105244264A (en) * | 2015-10-28 | 2016-01-13 | 株洲南车时代电气股份有限公司 | Composite gate structure capacitor and manufacturing method thereof |
| CN107093548A (en) * | 2017-04-20 | 2017-08-25 | 泰科天润半导体科技（北京）有限公司 | The method for preparing SiC base MOS device gate dielectric membranes |
| CN107093548B (en) * | 2017-04-20 | 2019-09-03 | 泰科天润半导体科技（北京）有限公司 | The method for preparing SiC base MOS device gate dielectric membrane |
| CN110212031A (en) * | 2019-05-24 | 2019-09-06 | 华中科技大学 | A kind of carbide MOS devices and preparation method thereof |
| CN113555441A (en) * | 2021-06-09 | 2021-10-26 | 浙江芯国半导体有限公司 | SiC-based MIS device and preparation method thereof |
| CN113555441B (en) * | 2021-06-09 | 2023-06-27 | 浙江芯科半导体有限公司 | SiC-based MIS device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102244108A (en) | Silicon carbide (SiC) metal oxide semiconductor (MOS) capacitor with composite dielectric layer and manufacturing method for SiC MOS capacitor with composite dielectric layer | |
| US20210043778A1 (en) | Gallium Oxide SBD Terminal Structure and Preparation Method | |
| CN104037239A (en) | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method | |
| TW201234593A (en) | Semiconductor device | |
| CN109616523B (en) | 4H-SiC MOSFET power device and manufacturing method thereof | |
| CN102938413A (en) | Algan/gan heterojunction enhanced device and manufacturing method thereof | |
| CN108417617B (en) | Silicon carbide groove type MOSFETs and preparation method thereof | |
| CN110164769B (en) | Gallium oxide field effect transistor and preparation method thereof | |
| CN101540279B (en) | Method for manufacturing SiC MOS capacitor with low interface state density | |
| US20160190375A1 (en) | Hetero-junction solar cell and manufacturing method thereof | |
| CN102104074B (en) | Semiconductor device and manufacturing method thereof | |
| CN106847881A (en) | Mos field effect transistor and preparation method thereof | |
| CN103928320A (en) | Method for preparing bipolar transistor of silicon carbide insulated gate of groove gate | |
| CN104037238A (en) | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method | |
| CN110993503A (en) | N-type transistor based on gallium oxide/perovskite transmission layer heterojunction and preparation method thereof | |
| JP5266996B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN106898644A (en) | High-breakdown-voltage field-effect transistor and preparation method thereof | |
| CN103928321A (en) | Preparation method for silicon carbide insulated gate bipolar transistor | |
| CN104576766A (en) | SiC MOS capacitor of Al2O3/LaAlO3/SiO2 stacking gate medium layer and manufacturing method | |
| CN104037240A (en) | SiC MOS (metal oxide semiconductor) capacitor and manufacturing method | |
| CN103646865A (en) | Method for preparing ultra-thin germanium oxide interface repairing layer on Ge substrate | |
| CN115295407A (en) | Preparation method of gate oxide structure of SiC power device and gate oxide structure | |
| CN101552192B (en) | Method for manufacturing Sic MOS capacitor | |
| CN112599408A (en) | Preparation method of silicon carbide metal oxide semiconductor with composite oxide layer | |
| CN107863389A (en) | Nmos device and computer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111116 |