CN207852681U

CN207852681U - Transistor arrangement and memory cell array

Info

Publication number: CN207852681U
Application number: CN201721605524.9U
Authority: CN
Inventors: 不公告发明人
Original assignee: Ruili Integrated Circuit Co Ltd
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-11-27
Filing date: 2017-11-27
Publication date: 2018-09-11
Anticipated expiration: 2027-11-27

Abstract

A kind of transistor arrangement of the utility model offer and memory cell array, transistor arrangement include：Semiconductor substrate has active area；Groove structure is located in active area；Dielectric layer is located at bottom and the side wall of groove structure；Wordline superficial layer, is located at bottom and the partial sidewalls of dielectric layer, and top is less than the upper surface of semiconductor substrate；Wordline physical layer, is located at wordline surface layer surface, including filling part and lug boss, and the top of lug boss higher than wordline superficial layer top and is less than semiconductor substrate upper surface, lateral sulcus is formed between the lateral wall and dielectric layer of lug boss；Filling perforation insulating layer is filled in the top of groove structure, and the top of bottom covering wordline physical layer and lateral sulcus top are to form air chamber.Through the above scheme, the utility model prepares transistor arrangement by deposition and wet-etching technology, forms the transistor with insulation lateral sulcus, changes the middle dielectric layer of capacitance, to reduce parasitic capacitance, can also reduce the resistance of transistor.

Description

Transistor arrangement and memory cell array

Technical field

The utility model belongs to ic manufacturing technology field, more particularly to a kind of transistor arrangement and its preparation side Method.

Background technology

Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer Semiconductor storage unit, be made of the storage unit of many repetitions.Each storage unit is mainly by a transistor and one It is a to be made of the capacitor that transistor is manipulated, and storage unit can be arranged in array format, each storage unit passes through Wordline is electrically connected to each other with bit line.As electronic product is increasingly towards light, thin, short, small development, dynamic random access memory The design of component also have to comply with high integration, it is highdensity require towards miniaturization trend development, for improve dynamic with Machine accesses the integration of memory to accelerate the service speed of component, and meets need of the consumer for miniaturized electronic device It asks, develops buried gate wordline dynamic random access memory in recent years, to meet above-mentioned various demands.

However, in above structure, the parasitic capacitance in the presence of the transistor arrangement of memory still constructs device junction At prodigious influence, in addition, the array with dynamic RAM constantly reduces, the resistance of the buried gate wordline by It is cumulative to add, affect the final performance of device.

Therefore, how to provide a kind of transistor arrangement, storage unit and its composition memory cell array and above-mentioned knot The preparation method of structure is necessary with solving the above problems.

Utility model content

In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of transistor arrangement, deposit Storage unit array, for solving the problems, such as the parasitic capacitance in transistor in the prior art and transistor circuit resistance.

In order to achieve the above objects and other related objects, the utility model provides a kind of preparation method of transistor arrangement, Including step：

1) semiconductor substrate with active area is provided, and in forming groove structure in the active area；

2) dielectric layer is formed in the bottom of the groove structure and side wall；

3) wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and in the wordline surface layer surface shape At wordline physical layer, the wordline physical layer includes being incorporated into the filling part of wordline surface layer surface and positioned at the filling Lug boss on portion top, wherein the top of the wordline superficial layer is less than the upper surface of the semiconductor substrate, the lug boss Top of the top higher than the wordline superficial layer and the upper surface less than the semiconductor substrate, and the outside of the lug boss Lateral sulcus is formed between wall and the dielectric layer；And

4) in forming filling perforation insulating layer in the groove structure, the bottom of the filling perforation insulating layer covers the wordline entity The top of layer and the top of the lateral sulcus, close the lateral sulcus to form air chamber.

As a kind of preferred embodiment of the utility model, the thickness of the wordline superficial layer between 0.8~5 nanometer, to Limit the width of the air chamber.

As a kind of preferred embodiment of the utility model, in step 1), the size of the opening of the groove structure is between 10 ~50 nanometers；In step 2), the thickness of the dielectric layer is between 1~9 nanometer；In step 4), the height of the air chamber is between 1 ~40 nanometers.

As a kind of preferred embodiment of the utility model, in step 1), the step of forming the groove structure, includes：

1-1) form one layer of mask layer with window in the semiconductor substrate surface, wherein the window with it is described Groove structure is corresponding up and down；And

1-2) semiconductor substrate is performed etching based on the window, to form the groove structure.

As a kind of preferred embodiment of the utility model, in step 2), formed using steam in situ (ISSG) technique described Dielectric layer.

Further include step in step 3) as a kind of preferred embodiment of the utility model：In the wordline superficial layer and institute It states and forms one layer of adhesion layer between wordline physical layer.

As a kind of preferred embodiment of the utility model, in step 3), forms the wordline superficial layer and the wordline is real The step of body layer include：

3-1) the semiconductor substrate surface around the bottom of the groove structure, side wall and the groove structure Form one layer of first conductive material layer；

3-2) one layer of second conductive material layer, second conductive material layer are formed in the first conductive material layer surface The full groove structure of filling simultaneously extends over first conductive material layer on the semiconductor substrate surface；

3-3) first conductive material layer and second conductive material layer are performed etching, led with being respectively formed first Electric material portion and the second conductive material part, top to the upper surface of the semiconductor substrate of first conductive material part and institute Top to the upper surface of the semiconductor substrate for stating the second conductive material part all has the first spacing；And

3-4) first conductive material layer and second conductive material layer are continued by wet-etching technology Etching, Yi Fen Do form the wordline superficial layer and the wordline physical layer, the wordline superficial layer and the semiconductor substrate There is the second spacing, the wordline physical layer to have third spacing, second spacing with the semiconductor substrate surface on surface More than the third spacing, to define the height of the protrusion.

As a kind of preferred embodiment of the utility model, first spacing is between 30~70 nanometers；Second spacing Difference with the third spacing is between 1~40 nanometer.

As a kind of preferred embodiment of the utility model, step 3-4) in, the reagent for carrying out the wet etching includes ammonia Water (NH₄OH), hydrogen peroxide (H₂O₂) and water composition mixed liquor, wherein ammonium hydroxide in the mixed liquor, hydrogen peroxide and water Ratio is sequentially 1 to 0.01~2 to 5~150.

As a kind of preferred embodiment of the utility model, step 3-3) in, by the technique of alternately etching to described first Conductive material layer and second conductive material layer perform etching, wherein the etching gas of the alternately etching includes lithium Arbitrary two or three of combination in sulphur, chlorine and the constituted group of argon gas.

Further include step before step 4) as a kind of preferred embodiment of the utility model：Using dilute hydrogen fluoride acid (DHF) Reagent cleans the surface of the wordline physical layer to remove surface by-product, and the dilute hydrogen fluoride acid reagent includes hydrofluoric acid (HF) and the mixed liquor of water, wherein the ratio of hydrofluoric acid and water includes 1 to 50~1000.

As a kind of preferred embodiment of the utility model, in step 2), the material of the dielectric layer includes silica, step 3) in, the material of the wordline superficial layer includes titanium nitride, and in step 3), the material of the wordline physical layer includes tungsten, step 4) in, the material of the filling perforation insulating layer includes silicon nitride.

As a kind of preferred embodiment of the utility model, in step 4), the filling perforation is formed by atom layer deposition process Insulating layer, to not destroy the air chamber.

As a kind of preferred embodiment of the utility model, the deposition of the atom layer deposition process is between 200~1000 Nm/minute.

The utility model also provides a kind of preparation method of memory cell array, includes the following steps：

A) multiple storage units with transistor arrangement are formed, and each storage unit is configured as cell row and list Member row, wherein the transistor arrangement is prepared using the preparation method as described in above-mentioned any one scheme, the crystalline substance Body pipe structure connects two capacitances without active area；And

B) the wordline physical layer for connecting each storage unit in addressed line to the cell row or the cell columns, with Prepare memory cell array, wherein the addressed line is for controlling the storage unit.

The utility model also provides a kind of transistor arrangement, including：

Semiconductor substrate has active area；

Groove structure is located in the active area of the semiconductor substrate；

Dielectric layer is located at bottom and the side wall of the groove structure；

Wordline superficial layer is located at bottom and the partial sidewalls of the dielectric layer, and the top of the wordline superficial layer is less than The upper surface of the semiconductor substrate；

Wordline physical layer is located at wordline surface layer surface, including the filling part being incorporated into the wordline superficial layer And the lug boss on the filling part top, the top of the lug boss are higher than the top of the wordline superficial layer and are less than institute The upper surface of semiconductor substrate is stated, lateral sulcus is formed between the lateral wall of the lug boss and the dielectric layer；And

Filling perforation insulating layer is filled in the top of the groove structure, and the bottom of the filling perforation insulating layer covers the word The top of line physical layer and the top of the lateral sulcus are to form the air chamber for being located at the lug boss both sides.

As a kind of preferred embodiment of the utility model, the size of the opening of the groove structure is between 10~50 nanometers； The thickness of the dielectric layer is between 1~9 nanometer；The height of the air chamber is between 1~40 nanometer.

As a kind of preferred embodiment of the utility model, the material of the dielectric layer includes silica, the wordline surface The material of layer includes titanium nitride, and the material of the wordline physical layer includes tungsten, and the material of the filling perforation insulating layer includes silicon nitride.

The utility model also provides a kind of memory cell array, including：

Several storage units, the storage unit include the transistor arrangement as described in above-mentioned any one scheme, and Each memory cell arrangements respectively connect two electricity at cell row and cell columns, each active area of the transistor arrangement Hold；And

Addressed line is connected to the wordline physical layer of each storage unit in the cell row or the cell columns, institute Addressed line is stated for controlling the storage unit.

The utility model also provides a kind of memory construction, includes the storage unit battle array as described in above-mentioned any one scheme Row.

As described above, the transistor arrangement of the utility model, memory cell array and preparation method thereof, have beneficial below Effect：

The utility model prepares transistor arrangement by deposition and wet-etching technology, is formed a kind of with insulation lateral sulcus (void) transistor, the other parts in device architecture are identical, are compared to the part for the lateral sulcus that insulate, due to The presence of insulation lateral sulcus, makes original Conductive layer portions be changed into the air of insulation lateral sulcus, changes the middle dielectric layer of capacitance, To reduce parasitic capacitance；In addition, using the technical solution of the utility model, it can also be ensured that increase while small leakage current The height for adding the metal layer as grid wordline, to reduce the resistance of transistor.

Description of the drawings

Fig. 1 is shown as the flow chart of the transistor arrangement preparation process of the utility model.

Fig. 2 is shown as providing the structural schematic diagram of semiconductor substrate in the transistor arrangement preparation of the utility model.

Fig. 3 is shown as the structural schematic diagram of mask layer in the transistor arrangement preparation of the utility model.

Fig. 4 is shown as forming the structural schematic diagram of groove structure in the transistor arrangement preparation of the utility model.

Fig. 5 is shown as forming the structural schematic diagram of dielectric layer in the transistor arrangement preparation of the utility model.

Fig. 6 is shown as forming the structural schematic diagram of the first conductive material layer in the transistor arrangement preparation of the utility model.

Fig. 7 is shown as forming the structural schematic diagram of the second conductive material layer in the transistor arrangement preparation of the utility model.

Fig. 8 be shown as the utility model transistor arrangement prepare in etching the one the second conductive material layer to the first spacing Schematic diagram.

Fig. 9 is shown as forming the structure of wordline superficial layer and wordline physical layer in the transistor arrangement preparation of the utility model Schematic diagram.

Figure 10 is shown as forming the structural schematic diagram of filling perforation insulating layer in the transistor arrangement preparation of the utility model.

Figure 11 is shown with the schematic diagram of the storage unit connection of the transistor arrangement of the utility model.

Figure 12 is shown with the schematic diagram of the memory construction of the transistor arrangement of the utility model.

Figure 13 is shown as ringing present in existing device architecture.

The capacitance variations that Figure 14 (a) and Figure 14 (b) is shown as in the transistor arrangement of the prior art and the utility model are shown It is intended to.

Figure 15 is shown as a kind of product schematic diagram of the transistor arrangement including the utility model.

Component label instructions

100 semiconductor substrates

101 active areas

102 isolation structures

103 isolation structure filled layers

104 mask layers

105 windows

106 groove structures

107 dielectric layers

108 first conductive material layers

109 second conductive material layers

110 first conductive material parts

111 second conductive material parts

112 wordline superficial layers

113 wordline physical layers

1131 filling parts

1132 lug bosses

114 lateral sulcus

1141 air chambers

115 filling perforation insulating layers

116 capacitances

117 wordline

118 amplifiers

119 channel regions

120 shallow junction regions

121 doped drains

S1~S4 steps 1)~step 4)

Specific implementation mode

Illustrate that the embodiment of the utility model, those skilled in the art can be by this theorys below by way of specific specific example Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition Different specific implementation modes are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer With carrying out various modifications or alterations under the spirit without departing from the utility model.

It please refers to Fig.1 to Figure 15.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can be a kind of random change Become, and its assembly layout form may also be increasingly complex.

As shown in Figure 1, the utility model provides a kind of preparation method of transistor arrangement, include the following steps：

3) wordline superficial layer is formed in the bottom of the dielectric layer and partial sidewalls, and in the wordline surface layer surface shape At wordline physical layer, the wordline physical layer includes being incorporated into the filling part of wordline surface layer surface and positioned at the filling The lug boss that portion is pushed up, wherein the top of the wordline superficial layer is less than the upper surface of the semiconductor substrate, the protrusion Top of the top in portion higher than the wordline superficial layer and the upper surface less than the semiconductor substrate, and the lug boss is outer Lateral sulcus is formed between side wall and the dielectric layer；And

The preparation method of the transistor arrangement of the utility model is described in detail below in conjunction with attached drawing.

As in Fig. 1 S1 and Fig. 2~4 shown in, first carry out step 1), provide one with active area 101 semiconductor serve as a contrast Bottom 100, and in formation groove structure 106 in the active area 101；

Specifically, the present embodiment provides a semiconductor substrate 100 with active area 101, the semiconductor substrate first 100 material includes but not limited to monocrystalline or polycrystalline semiconductor material, furthermore it is also possible to be that intrinsic monocrystalline substrate is either light The silicon substrate of micro- doping, further, it is possible to be N-type polycrystalline silicon substrate or p-type polysilicon substrate, in the present embodiment, described half Conductor substrate 100 is the substrate of P+ type polycrystalline silicon material.

Wherein, in this example, the active area 101 is isolated structure 102 and separates, and the isolation structure 102 is preferably shallow Groove isolation construction, internal to have isolation structure filled layer 103, material includes but not limited to silica.Then, have described The groove structure 106 is etched in source region, there are two groove knots as shown in figure 4, being shown as the formation in the active area 101 The schematic diagram of structure 106, in addition, the cross sectional shape of the groove structure 106 is preferably U-shaped, it is, of course, also possible to be applicable in for rectangle etc. The arbitrary shape of device performance.

As an example, in step 1), the step of forming the groove structure 106, includes：

1-1) as shown in figure 3, forming one layer of mask layer 104 with window 105 in 100 surface of the semiconductor substrate, Wherein, the window 105 is corresponding with about 106 groove structure；And

1-2) as shown in figure 4, being performed etching to the semiconductor substrate 100 based on the window 105, to form the ditch Slot structure 106.

Specifically, this example provides a kind of formation process of the groove structure 106, it should be noted that in this example Preparation process in, preferably retain the isolation structure filled layer 103 for filling the isolation structure 102, i.e., served as a contrast in the semiconductor The surface at bottom 100 is there are one layer of isolation structure filled layer, such as silicon oxide layer, as shown in Figure 2, certainly, and in other examples, This one silica layer on surface can also be removed, and is not particularly limited, then, the preparation of groove structure 106 is carried out, using light Carve and etching technique is formed in the semiconductor substrate 100 have window 105 the mask layer 104, wherein first in Mask layer is formed in the semiconductor substrate 100, and uses the photoresist with opening as mask to the mask material The bed of material performs etching, and forms the mask layer 104 with the window 105, and continues to etch the semiconductor substrate, with Form the groove structure 106.

As shown in the S2 and Fig. 5 in Fig. 1, step 2) is then carried out, is formed in the bottom of the groove structure 106 and side wall Dielectric layer 107；

As an example, in step 2), using steam in situ (ISSG) technique in the bottom of the groove structure 106 and side wall Form the dielectric layer 107.

Specifically, the material of the dielectric layer 107 can be but not limited to silica, silicon nitride, the silica can be with Resistivity for silicon monoxide or silica, and material is preferably 2 × 10¹¹~1 × 10²⁵Ω m, naturally it is also possible to be other The material selection of material medium layer, the dielectric layer 107 in this example is silica.The dielectric layer 107 can be by atom Deposition manufacture process (Atomic Layer Deposition) or plasma vapor deposition (Chemical Vapor Deposition) Film or quick heated oxide (Rapid Thermal Oxidation) and formed, it is preferable that the dielectric layer 107 is using former Position steam (in-situ stream generation, ISSG) technique is prepared, and a large amount of gas-phase activity is generated in preparation certainly By base, the oxidation of silicon chip is taken part in, so as to obtain the less film of defect, by insulation lateral sulcus 114 in this present embodiment The surface of dielectric layer described in expose portion, so as to obtain good device performance.

As in Fig. 1 S3 and Fig. 6~9 shown in, carry out step 3), in the bottom of the dielectric layer 107 and partial sidewalls shape Wordline physical layer 113, the wordline physical layer 113 are formed at wordline superficial layer 112, and in 112 surface of wordline superficial layer Filling part 1131 including being incorporated into 112 surface of wordline superficial layer and the lug boss on the top of the filling part 1131 1132, wherein the top of the wordline superficial layer 112 is less than the upper surface of the semiconductor substrate 100, the lug boss 1132 Top of the top higher than the wordline superficial layer 112 and the upper surface less than the semiconductor substrate 100, and the lug boss Lateral sulcus 114 is formed between 1132 lateral wall and the dielectric layer 107；

Specifically, by the technique of this step, two conductive layers, the wordline table are formed in the groove structure 106 The material of face layer 112 includes but not limited to titanium nitride, and the material of the wordline physical layer 113 includes but not limited to tungsten metal, and And lateral sulcus 114 is formed between wordline physical layer 113 and dielectric layer 107, further, the thickness of the wordline superficial layer 112 is used In the width for limiting the air chamber, the thickness range of the wordline superficial layer 112 is including 0.8~5 nanometer.

Further include step as an example, in step 3)：In the wordline superficial layer 112 and the wordline physical layer 113 it Between formed one layer of adhesion layer.

Specifically, the material of the adhesion layer can be selected as silane (SiH₄) and tetrachloro silicane (SiCl₄) at least one Kind, it is of course also possible to for the laminated structural layers of the two, so as to so that wordline superficial layer (such as TiN) and wordline physical layer (such as W) Between form good interface, allow the gap in the wordline superficial layer to fill up the wordline physical layer.

As an example, in step 3), the step of forming the wordline superficial layer 112 and wordline physical layer 113, includes：

3-1) the semiconductor lining around the bottom of the groove structure 106, side wall and the groove structure 106 100 surface of bottom forms one layer of first conductive material layer 108；

One layer of second conductive material layer 109 3-2) is formed in 108 surface of the first conductive material layer, described second is conductive The full groove structure 106 of the filling of material layer 109 simultaneously extends over first conduction material on the semiconductor substrate surface The bed of material；

3-3) first conductive material layer 108 and second conductive material layer 109 are performed etching, to be respectively formed First conductive material part 110 and the second conductive material part 111, the top of first conductive material part 110 to the semiconductor The upper surface of substrate 100 and the top of second conductive material part 111 to the upper surface of the semiconductor substrate 100 all have First spacing Z1；And

3-4) by wet-etching technology to first conductive material layer 108 and second conductive material layer 109 after It is continuous to perform etching, to be respectively formed the wordline superficial layer 112 and the wordline physical layer 113, the wordline superficial layer 112 Top to the upper surface of the semiconductor substrate 100 has the second spacing Z2, the top of the wordline physical layer 113 to described half There is third spacing Z3, the second spacing Z2 to be more than the third spacing Z3 for the upper surface of conductor substrate 100, described to define The height of protrusion 1132.

As an example, the first spacing Z1 is between 30~70 nanometers；The second spacing Z2 and third spacing Z3 Difference between 1~40 nanometer.

As an example, step 3-3) in, by the technique of alternately etching to first conductive material layer 108 and described the Two conductive material layers 109 perform etching, wherein the etching gas of the alternately etching includes sulfur hexafluoride, chlorine and argon gas (SF₆), chlorine (Cl₂) and argon gas (Ar) constituted group in arbitrary two or three of combination.

Specifically, this example provides the preparation process of a kind of wordline superficial layer 112 and the wordline physical layer 113, need Illustrate, shown in the drawings of the isolation structure filled layer 103 and mask layer 104 mentioned in the example for retaining the utility model In the case of carry out technique the case where, first, formed one layer of first conductive material layer 108, as shown in fig. 6, covering in the above again One layer of second conductive material layer 109 of lid, as shown in fig. 7, first conductive material layer 108 and second conductive material layer 109 preparation includes but not limited to the depositing operations such as plating, chemical vapor deposition, physical vapour deposition (PVD) or atomic layer deposition, this In example, it is selected as chemical vapor deposition (CVD) technique.

Then, further include by chemical-mechanical planarization (Chemical-Mechanical Planarization, CMP) The technique that the two layers of material on 100 surface of the semiconductor substrate is planarized.Then using the technique pair of alternately etching Two layers of material is once etched, as shown in figure 8, etching the result is that first conductive material layer 108 becomes first leads Electric material portion 110, second conductive material layer 109 become the second conductive material part 111, certainly, the first conductive material part 110 Can there can be different spacing from 100 surface of the semiconductor substrate with the second conductive material part 111, pass through subsequent technique The structure needed is formed, in this example, both preferably away from 100 surface of semiconductor substrate spacing Z1 having the same, from And being conducive to the control of subsequent technique, the etching of the step is preferably dry etching, and alternating is passed through to the first, second conductive material Layer has the gas of different etching rate, and using the first conductive material layer as titanium nitride, the second conductive material layer is quarter for tungsten metal It loses gas and uses SF₆/Cl₂, by adjusting flow proportional or a other etching period to perform etching.

Finally, as shown in figure 9, again by an etching technics, the etch rate to two kinds of materials is controlled, word is finally obtained Line superficial layer 112 and wordline physical layer 113, and insulation lateral sulcus is formed between wordline physical layer 113 and dielectric layer 107 114, wherein wordline superficial layer 112 has the second spacing Z2, wordline physical layer 113 and institute with 100 surface of the semiconductor substrate It is also the height of the protrusion 1132 to state 100 surface of semiconductor substrate to have the difference of third spacing Z3, Z3 and Z2, is also The length of the insulation lateral sulcus 114, and the thickness of the wordline superficial layer 112 is the width of the insulation lateral sulcus 114.

As an example, step 3-4) in, the reagent for carrying out the wet etching includes what ammonium hydroxide, hydrogen peroxide and water formed Mixed liquor, wherein ammonium hydroxide (NH in the mixed liquor₄OH), hydrogen peroxide (H₂O₂) and water (H₂O ratio) is sequentially 1 to 0.01 ~2 to 5~150；The temperature range for carrying out the wet etching includes 4~25 DEG C.

Specifically, giving the technique that a kind of wet etching forms wordline superficial layer and wordline physical layer in this example, adopt Wet etching is carried out with APM reagents, reagent includes ammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂) and water (H₂O), the dense of APM is adjusted Range and temperature range are spent, the etch rate to the first conductive material layer (such as TiN) is improved, is reduced to the second conductive material layer The etch rate of (such as W), the structure to be needed, it is preferable that ammonium hydroxide (NH in the mixed liquor₄OH), hydrogen peroxide (H₂O₂) And water (H₂O ratio) includes 1:(0.1~1.5):(20~100) are selected as 1 in this example:1:50；In addition, carrying out wet The temperature of method etching is preferably 10~20 DEG C, and 15 DEG C are selected as in this example.

Further include step as an example, before step 4)：Using dilute hydrogen fluoride acid (DHF) reagent to the wordline physical layer 113 surface is cleaned to remove surface by-product, and the DHF reagents include the mixed liquor of hydrofluoric acid and water, the mixing The ratio of hydrofluoric acid (HF) and water includes 1 than (50~1000) in liquid.

Specifically, using DHF reagents so as to remove the oxide layer formed by oxidation in operation process, as formed WO, to reduce the impedance of word line structure.Preferably, the ratio of hydrofluoric acid (HF) and water includes 1 in the mixed liquor:(100~ 500) it is 1 that thief, is selected in this example:300.

As shown in the S4 and Figure 10 in Fig. 1, step 4) is carried out, in formation filling perforation insulating layer in the groove structure 106 115, the bottom of the filling perforation insulating layer 115 covers the top of the wordline physical layer 113 and the top of the lateral sulcus 114, The closing of the lateral sulcus 114 is formed air chamber 1141；

As an example, in step 4), the filling perforation insulating layer 115 is formed by atom layer deposition process, to not destroy The insulation lateral sulcus 114.

As an example, the deposition of the atom layer deposition process is between 200~1000 nm/minutes.

Specifically, finally carrying out step 4), filling perforation insulating layer 115 is formed, as shown in Figure 10, and controls the filling perforation insulation Layer 115 is not deposited in the insulation lateral sulcus 114, to ensure the integrality of insulation lateral sulcus 114, may be used CVD's or ALD Method forms filling perforation insulating layer 115 and fills up GAP (in the top of groove structure), wherein deposition is controlled in 200~1000nm/ Min, preferably 220~500nm/min are selected as 250nm/min in this example, and the material of the filling perforation insulating layer 115 includes But it is not limited to silicon nitride.

It should be noted that by the step, lateral sulcus 114 is enclosed to form air chamber in the device structure (void) 1141, the other parts in device architecture are identical, are compared to the part of air chamber (void), due to The presence of air chamber 1141, it is sky to make original conductive layer (being such as equivalent to the wordline surface layer part in this example) portions turn The air of air cavity changes the middle dielectric layer of capacitance, to reduce parasitic capacitance, gives one kind as shown in figure 14 and shows Example, it is shown that the capacitance variations situation in device, wherein Figure 14 (a) is shown as capacitance situation in the prior art, Figure 14 (b) The capacitance situation being shown as in the device architecture of the utility model.

In addition, it should also be noted that, using the technical solution of the utility model, since the wordline superficial layer 112 is straight The surface for being formed in the dielectric layer 107 is connect, therefore, the wordline superficial layer 112 is as functional structure layer (work Function), the threshold voltage vt of device architecture is determined, meanwhile, the wordline being formed in inside the wordline superficial layer 112 is real Body layer 113 has the function of current lead-through, since it may include the lug boss for protruding from the wordline superficial layer 112 1132, then its height can have more flexible selection, so as to reduce the resistance in transistor, it is ensured that small leakage current While reduce transistor resistance, in addition, the wordline superficial layer 112 is also used as the expansion of the wordline physical layer 113 Dissipate barrier layer.The dual electric layer structure 111 is both used as grid, is also used as wordline, the grid wordline of this flush type that can save Device space is saved, device size is reduced, improves device speed.

As an example, in step 1), the size of the opening of the groove structure 106 is between 10~50 nanometers；In step 2), The thickness of the dielectric layer 107 is between 1~9 nanometer；In step 3), the width of the air chamber 1141 between 0.8~5 nanometer, The height of the air chamber 1141 is between 1~40 nanometer.

Specifically, in this example, the opening of the groove structure 106 is preferably dimensioned to be 20~40 nanometers, wherein opening Size refers to the opening width in its sectional view, and 30 nanometers are selected as shown in the D in Fig. 4, in this example；The dielectric layer 107 thickness is preferably 2~8 nanometers, and 6 nanometers are selected as in this example；Width (the wordline superficial layer of the air chamber 1141 112 thickness) it is preferably 1~4 nanometer, 2 nanometers are selected as in this example, the height (lug boss of the air chamber 1141 Height) be preferably 10~30 nanometers, 20 nanometers are selected as in this example.

It should also be noted that, due to the presence of parasitic capacitance in device, wherein in systems, these undesirable electricity Hold and come from every aspect, such as the material of PCB, thickness, layer structure, the cabling depth of parallelism, these are all the parasitisms for influencing pcb board Capacitance, the also parasitic capacitance of component itself, most hateful, which is these things, is also influenced by environment temperature.In high speed circuit On, since frequency is higher and higher, the influence of parasitic capacitance cannot ignore, and as shown in figure 12, can make device exists " to shake Bell " phenomenon, and the structure for using the preparation process of the utility model to obtain can be effectively improved this phenomenon.

A) multiple storage units with transistor arrangement are formed, and each storage unit is configured as cell row and list Member row, wherein the transistor arrangement is prepared using any one of the present embodiment transistor arrangement preparation method, institute The each active area for stating transistor arrangement respectively connects two capacitances；And

In addition, as shown in figure 11, the utility model also provides a kind of using transistor arrangement disclosed in the utility model The method that the transistor that preparation process is prepared prepares storage unit, wordline superficial layer 112 and wordline physical layer 113 are common As grid word line structure, it is connected with the driving of wordline 117, source region is connected with capacitance 116, and drain region connects amplifier 118, and And a kind of connection type of storage array is shown in FIG. 12, specifically, during data are read, data is exported via capacitance It is exported to weld pad (pad), during data are write, data are via weld pad and are stored in capacitance.

In addition, as shown in figure 15, the utility model also provides a kind of production including transistor arrangement provided in this embodiment The preparation method of product and the product being prepared, wherein the preparation method of the product include prepare the present embodiment provides Transistor the step of, further include the steps that preparing channel region 119, shallow junction region 120 and doped drain 121, wherein described In active area 101 carry out B (boron) adulterate to prepare the channel region 119, in the active area 101 carry out As (arsenic) adulterate with The shallow junction region 120 is prepared, P (phosphorus) is carried out in the active area 101 and is adulterated to prepare the doped drain 121.

The utility model also provides a kind of transistor arrangement, wherein the transistor arrangement preferably uses the present embodiment The preparation method of the transistor arrangement of offer is prepared, but is not limited in this approach, as shown in Figure 10, the transistor arrangement Including：

Semiconductor substrate 100 has active area 101；

Groove structure 106 is located in the active area 101 of the semiconductor substrate 100；

Dielectric layer 107 is located at bottom and the side wall of the groove structure 106；

Wordline superficial layer 112 is located at bottom and the partial sidewalls of the dielectric layer 107, and the wordline superficial layer 112 Top is less than the upper surface of the semiconductor substrate 100；

Wordline physical layer 113 is located at 112 surface of wordline superficial layer, and includes being incorporated into the wordline superficial layer 112 The filling part 1131 on surface and the lug boss 1132 on the top of the filling part 1131, the top of the lug boss 1132 is higher than The top of the wordline superficial layer 112 and the upper surface for being less than the semiconductor substrate 100, the lateral wall of the lug boss 1132 Lateral sulcus 114 is formed between the dielectric layer 107；And

Filling perforation insulating layer 115 is filled in the top of the groove structure 106, and the bottom of the filling perforation insulating layer 115 The top on the top and the lateral sulcus 114 that cover the wordline physical layer 113 is located at 1132 both sides of the lug boss to be formed Air chamber 1141.

As an example, the thickness of the wordline superficial layer is between 0.8~5 nanometer, to limit the air chamber 1141 Width.

As an example, the material of the dielectric layer 107 includes silica, the material of the wordline superficial layer 112 includes nitrogen Change titanium, the material of the wordline physical layer 113 includes tungsten, and the material of the filling perforation insulating layer 115 includes silicon nitride.

Specifically, in this example, the active area 101 is isolated structure 102 and separates, and the isolation structure 102 is preferably Fleet plough groove isolation structure, internal to have isolation structure filled layer 103, material includes but not limited to silica.The dielectric layer 107 material can be but not limited to silica, silicon nitride, and the silica can be silicon monoxide or silica.

It should be noted that the material of the wordline superficial layer 112 includes but not limited to titanium nitride, the wordline physical layer 113 material includes but not limited to tungsten metal, and forms air chamber between wordline physical layer 113 and dielectric layer 107 (void) 1141, to, the other parts in device architecture are identical, are compared to the part of air chamber, due to The presence of air chamber 1141, it is sky to make original conductive layer (being such as equivalent to the wordline surface layer part in this example) portions turn The air of air cavity changes the middle dielectric layer of capacitance, to reduce parasitic capacitance.

In addition, since the wordline superficial layer 112 is formed directly into the surface of the dielectric layer 107, the wordline Superficial layer 112 determines the threshold voltage vt of device architecture as functional structure layer (work function), meanwhile, it is formed in Wordline physical layer 113 inside the wordline superficial layer 112 has the function of current lead-through, since it may include protruding from institute The lug boss 1132 of wordline superficial layer 112 is stated, then its height there can be more flexible selection, so as to reduce transistor In resistance, it is ensured that the resistance for reducing transistor while small leakage current, in addition, the wordline superficial layer 112 may be used also Using the diffusion impervious layer as the wordline physical layer 113.The dual electric layer structure 111 is both used as grid, is also used as wordline, The grid wordline of this flush type can save device space, reduce device size, improve device speed.

As an example, being also formed with one layer of adhesion layer between the wordline superficial layer 112 and the wordline physical layer 113. The material of the adhesion layer can be selected as silane (SiH₄) and tetrachloro silicane (SiCl₄At least one of), it is of course also possible to For the laminated structural layers of the two, so as to so as to be formed between wordline superficial layer (such as TiN) and wordline physical layer (such as W) good Interface allows the gap in the wordline superficial layer to fill up the wordline physical layer.

As an example, the size of the opening of the groove structure is between 10~50 nanometers；The thickness of the dielectric layer is between 1 ~9 nanometers；The width of the air chamber is between 0.8~5 nanometer, and the height of the air chamber is between 1~40 nanometer.

Specifically, in this example, the opening of the groove structure 106 is preferably dimensioned to be 20~40 nanometers, wherein opening Size refers to the opening width in its sectional view, and 30 nanometers are selected as shown in the D in Fig. 4, in this example；The dielectric layer 107 thickness is preferably 2~8 nanometers, and 6 nanometers are selected as in this example；Width (the wordline superficial layer 112 of the air chamber 114 Thickness) be preferably 1~4 nanometer, 2 nanometers are selected as in this example, the height (height of the lug boss of the air chamber 114 Degree) it is preferably 10~30 nanometers, 20 nanometers are selected as in this example.

The utility model also provides a kind of memory cell array, including：

Several storage units, the storage unit include the transistor junction described in any one of the present embodiment scheme Structure, and each memory cell arrangements are at cell row and cell columns, each active area respectively connection two of the transistor arrangement A capacitance；And

The utility model also provides the storage list described in any one of a kind of memory construction, including the present embodiment scheme Element array.

Further, in the memory construction further include several fleet plough groove isolation structures, wherein the adjacent shallow trench It is active area between isolation structure, there are two the transistor arrangements being spaced apart for setting.

In conclusion a kind of transistor arrangement of the utility model offer, memory cell array, transistor arrangement include：Half Conductor substrate has active area；Groove structure is located in the active area of the semiconductor substrate；Dielectric layer is located at described The bottom of groove structure and side wall；Wordline superficial layer is located at bottom and the partial sidewalls of the dielectric layer, and the wordline surface The top of layer is less than the upper surface of the semiconductor substrate；Wordline physical layer is located at the surface of the wordline superficial layer, the word Line physical layer includes the filling part being incorporated into the wordline superficial layer and the lug boss on the filling part top, described convex The top in the portion of rising is higher than the top of the wordline superficial layer and is less than the upper surface of the semiconductor substrate, outside the lug boss It is formed with lateral sulcus between side wall and the dielectric layer；And filling perforation insulating layer, it is filled in the top of the groove structure, and described The bottom of filling perforation insulating layer covers the top of the wordline physical layer and the top of the lateral sulcus and is located at the protrusion to be formed The air chamber of portion both sides.Through the above scheme, the utility model prepares transistor arrangement, shape by deposition and wet-etching technology At a kind of transistor with air chamber (void), to which the other parts in device architecture are identical, to air chamber Part be compared, due to the presence of air chamber, so that original Conductive layer portions is changed into the air of air chamber, change electricity The middle dielectric layer of appearance, to reduce parasitic capacitance；In addition, using the technical solution of the utility model, it can also be ensured that small Leakage current while increase as grid wordline metal layer height, to reduce the resistance of transistor.So this practicality It is novel effectively to overcome various shortcoming in the prior art and have high industrial utilization.

The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model All equivalent modifications completed under refreshing and technological thought or change, should be covered by the claim of the utility model.

Claims

1. a kind of transistor arrangement, which is characterized in that including：

Semiconductor substrate has active area；

Wordline superficial layer is located at bottom and the partial sidewalls of the dielectric layer, and the top of the wordline superficial layer is less than described The upper surface of semiconductor substrate；

Wordline physical layer, is located at the surface of the wordline superficial layer, and the wordline physical layer includes being incorporated into the wordline surface Filling part in layer and the lug boss on the filling part top, the top of the lug boss is higher than the wordline superficial layer Top and the upper surface for being less than the semiconductor substrate, side is formed between the lateral wall of the lug boss and the dielectric layer Ditch；And

Filling perforation insulating layer is filled in the top of the groove structure, and the bottom of the filling perforation insulating layer covers the wordline reality The top of body layer and the top of the lateral sulcus are to form the air chamber for being located at the lug boss both sides.

2. transistor arrangement according to claim 1, which is characterized in that the thickness of the wordline superficial layer is between 0.8~5 Nanometer, to limit the width of the air chamber.

3. transistor arrangement according to claim 2, which is characterized in that the size of the opening of the groove structure is between 10 ~50 nanometers；The thickness of the dielectric layer is between 1~9 nanometer；The height of the air chamber is between 1~40 nanometer.

4. transistor arrangement according to claim 1, which is characterized in that the wordline superficial layer and the wordline physical layer Between be also formed with one layer of adhesion layer.

5. transistor arrangement according to claim 1, which is characterized in that the material of the dielectric layer includes silica, institute The material for stating wordline superficial layer includes titanium nitride, and the material of the wordline physical layer includes tungsten, the material of the filling perforation insulating layer Including silicon nitride.

6. a kind of memory cell array, which is characterized in that including：

Several storage units, the storage unit includes transistor arrangement as described in claim 1, and each storage is single Member is configured to cell row and cell columns, and each active area of the transistor arrangement respectively connects two capacitances；And

Addressed line is connected to the wordline physical layer of each storage unit in the cell row or the cell columns, described to seek Location line is for controlling the storage unit.

7. a kind of memory construction, which is characterized in that including memory cell array as claimed in claim 6.