CN209216972U - A kind of semiconductor unit contact structures - Google Patents
A kind of semiconductor unit contact structures Download PDFInfo
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- CN209216972U CN209216972U CN201821785107.1U CN201821785107U CN209216972U CN 209216972 U CN209216972 U CN 209216972U CN 201821785107 U CN201821785107 U CN 201821785107U CN 209216972 U CN209216972 U CN 209216972U
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Abstract
A kind of semiconductor unit contact structures are provided, semiconductor devices is applied to, wherein unit contact is formed on a substrate, and substrate has the isolated area formed by shallow trench isolation channels and the multiple active areas defined by isolated area；There are the multiple wordline grooves intersected with corresponding active area in the substrate and in the word line structure being embedded in wordline groove；Also there are the multiple bit line structures intersected with corresponding active area on substrate, the part between bit line structure and two adjacent word line structures of substrate is electrically connected；Opening is formed between two adjacent bit line structures.By increasing by one layer of silica in polysilicon layer, the leakage mechanisms of unit contact are reduced using the property that oxidation silicon resistor is higher than polysilicon.
Description
Technical field
The utility model relates to organization of semiconductor memory.In particular to the structure that unit contacts in DRAM device.
Background technique
In semiconductor devices, especially DRAM device, for unit contact structure formation, in the prior art usually
It is the high concentration polysilicon and low concentration polysilicon for first successively depositing a thickness respectively, dry etching then is carried out to polysilicon.
Then redeposited one layer of silicon nitride, then etch silicon nitride and polysilicon.However, due to polysilicon and silicon nitride etch speed difference
It is different, more defect can be caused to polysilicon surface during dry etching.In addition, overetch can also etch near isolated area
Silicon causes defect.Polysilicon side and bottom defect are easily caused when dry etching, this type defect will form leakage path, make
It stores and leaks electricity at charge, device performance is adversely affected.
Utility model content
The utility model protected by improving the formation process of unit contact polysilicon and shallow trench isolation channels (STI,
Shallow Trench Isolation) neighbouring silicon, to reduce the surface defect of silicon near polysilicon and STI, to finally subtract
Few unit contact deficiency, improves device performance.
The utility model provides a kind of semiconductor unit contact, is applied to semiconductor devices, wherein be formed in a substrate
On, the substrate has the isolated area formed by shallow trench isolation channels and the multiple active areas defined by isolated area；It is serving as a contrast
There are the multiple wordline grooves intersected with corresponding active area and in the word line structure being embedded in wordline groove in bottom；It is serving as a contrast
Also there are the multiple bit line structures intersected with corresponding active area, two adjacent institutes of institute's bit line structures and the substrate on bottom
State the part electrical connection between word line structure；Opening is formed between two adjacent institute's bit line structures；Opening is by polysilicon or oxygen
SiClx or silicon nitride filling.
In some embodiments of the utility model, polysilicon deposition with a thickness of 150nm.
In some embodiments of the utility model, silica separation layer with a thickness of 1.5nm.
In some embodiments of the utility model, silica separation layer surround open depression part by silica/
Silicon nitride filling.
In some embodiments of the utility model, dielectric layer with a thickness of 1.5nm.
In some embodiments of the utility model, isolated area with a thickness of 10nm.
The beneficial effects of the utility model are, by depositing one layer of silica in polysilicon layer, utilize silica electricity
Resistance is higher than the property of polysilicon, and when current distributing only has lesser electric current by silicon oxide layer, so that leakage mechanisms can drop
It is low.Meanwhile when carrying out exposing the etch step of contact portion, both silica and polysilicon etching speed are different, bottom polysilicon
Etch rate is very fast, and lateral oxidation silicon etch rate is slower, therefore can be reduced destruction of the overetch to silicon near STI slot, also can
The destruction to side polysilicon is reduced, the defect of unit contact structures is finally reduced.
Detailed description of the invention
Figure 1A is the structural schematic diagram of the substrate of the unit to be formed contact of the utility model.
Figure 1B is the structural schematic diagram carried out after step a to the structure of Figure 1A.
Fig. 1 C is the structural schematic diagram carried out after step b to the structure of Figure 1B.
Fig. 1 D is the structural schematic diagram carried out after step c to the structure of Fig. 1 C.
Fig. 1 E is the structural schematic diagram carried out after step d to the structure of Fig. 1 D.
Fig. 1 F is the structural schematic diagram carried out after step e to the structure of Fig. 1 E.
Fig. 2 is the schematic diagram of the semiconductor unit contact of the utility model.
Specific embodiment
It is to be illustrated disclosed in the utility model by specific specific example in relation to the " shape of semiconductor unit contact below
At method " and " semiconductor unit contact " embodiment, those skilled in the art can be by content disclosed in this specification
The advantages of solving the utility model and effect.The utility model can be implemented or be applied by other different specific embodiments,
The various details in this specification may be based on different viewpoints and application, carry out under the design for not departing from the utility model various
Modification and change.The relevant technologies content of the utility model will be explained in further detail in the following embodiments and the accompanying drawings, but disclosed
Content is not to limit the protection scope of the utility model.
Referring to Figure 1A-Fig. 1 F and Fig. 2.Figure 1A is the structural representation of the substrate of the unit to be formed contact of the utility model
Figure；Figure 1B is the structural schematic diagram carried out after step a to the structure of Figure 1A.Fig. 1 C be the structure of Figure 1B is carried out step b it
Structural schematic diagram afterwards.Fig. 1 D is the structural schematic diagram carried out after step c to the structure of Fig. 1 C.Fig. 1 E is the structure to Fig. 1 D
Carry out the structural schematic diagram after step d.Fig. 1 F is the structural schematic diagram carried out after step e to the structure of Fig. 1 E.Fig. 2 is this
The schematic diagram of the unit contact of utility model.The utility model provides a kind of formation side of semiconductor unit contact C (see Fig. 2)
Method, specific in the present embodiment, provide first a DRAM device unit to be formed contact substrate 100, substrate 100 have by
The isolated area 120 and the multiple active areas 110 defined by isolated area 120 that shallow trench isolation channels (STI) are formed.Have each
Source region 110 can form the storage unit of memory such as DRAM.It is formd in substrate 100 and corresponding 110 phase of active area
Hand over multiple wordline grooves 101 and in the word line structure 130 being embedded in wordline groove 101.Word line structure 130, which can be used as, to be deposited
The source/drain region 150 of the grid of transistor in reservoir, transistor is located in the active area 110 of 130 two sides of word line structure.In substrate
The multiple bit line structures 140 intersected with corresponding active area 110 are yet formed on 100, so that a source/drain region of transistor
150 (parts i.e. on substrate between two adjacent word line structures 130) are electrically connected with corresponding bit line structure 140.Two is adjacent
Opening 102 is formed between bit line structure.
Specifically, the material of substrate 100 may include the semiconductor of silicon, germanium or silicon-on-insulator (SOI), or including germanium
III, V compounds of group such as silicon compound, silicon carbide or other known materials, such as GaAs.It can be with root in substrate 100
Certain Doped ions are injected according to design requirement to change electrical parameter.Substrate 100 is formed with isolated material in isolated area 120,
Such as silica.Preferably, substrate 100 is silicon substrate.
The word line structure 130 being formed in substrate 100 can be used as the grid of corresponding transistor in memory, and in shape
During at word line structure 130 or after being formed, can with a source/drain region 150 wherein, such as two word line structures 130 it
Between source/drain region 150, the source electrode as corresponding transistor；And in another source/drain region 150, such as word line structure 130 and isolation
Source/drain region 150 between area 120, can be used as the drain electrode of corresponding transistor.Word line structure 130 is formed in wordline groove 101
When, gate dielectric layer 131, wordline 132 and covering gate dielectric layer and wordline can be sequentially formed in wordline groove 101
Buried insulator layer 133.The material of gate dielectric layer 131 may include silica, silicon nitride, nitrogen oxides, silicon nitride, oxidation
One of object/nitride/oxide (ONO) and high-k dielectric material are a variety of.Gate dielectric layer 131 can be by all
Wet or xeothermic oxidation technology such as in the environment for including oxide, vapor, nitric oxide or their combination is formed, or
(ISSG) Process Production is generated by the situ steam in the environment of oxygen, vapor, nitric oxide or their combination, or
Person is formed by using ethyl orthosilicate (TEOS) and oxygen as chemical vapor deposition (CVD) technology of presoma.Wordline
132 material may include one of Ti, TiN, Ta, TaN, W, WN, TiSiN and WSiN or a variety of.Buried insulator layer
Material may include the combination of one or more of silica, silicon nitride, silicon oxynitride and silicon nitrogen oxides.
Bit line structure 140 may include the bit line contact 141 and bit line conductive layer 142 being sequentially overlapped.Bit line contact 141 with
The source/drain region 150 being disposed below is electrically connected.In some embodiments, bit line contact 141 can be partially protruded into substrate 100, i.e.,
The bottom surface of bit line contact 141 can be lower than the surface of substrate 100 and the top surface of bit line contact 141 is higher than the table of substrate 100
Face.In some other embodiment, the bottom surface of bit line contact 141 and the flush of substrate 110.The material of bit line contact 141
It may include polysilicon or metal.Bit line conductive layer 142 is formed in 141 surface of bit line contact, thus passes through bit line contact 141, position
Line conductive layer 142 can be formed with the first source/drain region 150 and is electrically connected.The material of bit line conductive layer 142 may include W, Ti, Ni, Al,
Pt、TiO2, one of TiN and polysilicon or two or more combinations.Bit line structure 140 also may include other layers,
Such as it may also include the work-function layer for being directly covered in 141 top surface of bit line contact.
Depositing operation among the above, those skilled in the art can select to be suitable for the present embodiment purpose according to the prior art
Depositing operation, for example, the depositing operation of wordline 132 and buried insulator layer 133 can chemically be vapor-deposited, physical vapor
Deposition, atomic layer deposition, high-density plasma CVD, metallorganic CVD, plasma enhanced CVD or other suitable depositions
It is selected in technique, the utility model is not limited thereto.
Deposition-etch step is carried out later:
A. one layer of polysilicon is deposited with the deposition rate of 50nm/hr along the shape of opening 102, forms fitting opening shape
Polysilicon deposition 160 (refers to Fig. 2).The thickness of polysilicon deposition 160 is preferably 150nm.In the selection of depositional mode originally
Field technical staff can chemically be vapor-deposited, physical vapour deposition (PVD), atomic layer deposition, high-density plasma CVD, metal have
It is selected in machine CVD, plasma enhanced CVD or other suitable depositing operations, the utility model is not limited thereto.Equally
, in the selection of the thickness of deposition rate and polysilicon deposition 160, those skilled in the art can also select according to actual needs
Select other suitable rates and thickness.
B. one layer of silica is deposited on polysilicon layer surface using the deposition method of ALD, control reaction carries out 6 reactions
Circulation forms silica separation layer 170.The thickness of silica separation layer 170 is preferably 1.5nm.Furthermore those skilled in the art
It can also be from other depositional modes such as chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition, high-density plasma CVD, gold
Belong to and being selected in organic C VD, plasma enhanced CVD or other suitable depositing operations, the utility model is not limited thereto.
Likewise, those skilled in the art can select suitable thickness according to actual needs in the selection of the thickness of silica separation layer 170
Degree.
C. deposit polycrystalline silicon is continued on silicon oxide layer surface with the deposition rate of 50nm/hr, forms polysilicon blanket layer
180.The thickness of polysilicon blanket layer 180 is preferably 150nm.Those skilled in the art can be chemically in the selection of depositional mode
Vapor deposition, physical vapour deposition (PVD), atomic layer deposition, high-density plasma CVD, metallorganic CVD, plasma enhanced CVD
Or selected in other suitable depositing operations, the utility model is not limited thereto.Likewise, deposition rate and polysilicon cover
In the selection of the thickness of cap rock 180, those skilled in the art can also select other suitable rates and thickness according to actual needs
Degree.
D. use gas phase etches polycrystalline silicon covering layer 180 and silica separation layer 170, remove polysilicon blanket layer 180 and
The silica separation layer 170 on bit line structure top exposes 120 top of isolated area in 102 recess substrates 100 of opening
Polysilicon deposition 160, and leave 130 side wall polysilicon of bit line structure deposition layer surface silica separation layer 170.It carves
Losing gas is preferably fluoro-gas, more preferably hydrogen fluoride gas.
E. the remaining polysilicon deposition 160 in overetch bit line structure top, silica separation layer 170 and open depression
The polysilicon deposition 160 above isolated area that part exposes makes the contact portion (virtual coil part in Fig. 1 F) of unit contact C
It is exposed.
F. the portion that remaining silica separation layer 170 surrounds in the isolated area 120 exposed in the opening that etching is completed
Cvd silicon oxide/silicon nitride in point forms complete unit contact C.
This method passes through in one layer of oxidation of deposition (i.e. between polysilicon deposition and polysilicon blanket layer) in polysilicon layer
Silicon (silica separation layer) is higher than the property of polysilicon using oxidation silicon resistor, and when current distributing only has lesser electric current
By silica separation layer, so that leakage mechanisms can reduce.Meanwhile carry out expose contact portion etch step when, silica and
Both polysilicons etching speed is different, and bottom polysilicon etch rate is very fast, and lateral oxidation silicon etch rate is slower, therefore can be reduced
Destruction to side polysilicon, while destruction of the overetch to the neighbouring silicon of isolated area (STI slot) can be also reduced, finally reduce
The defect of unit contact structures.
Using above-mentioned forming method, the utility model provides a kind of semiconductor unit contact.Referring to fig. 2.Fig. 2 is that this is practical
The schematic diagram of novel semiconductor unit contact C.Unit contact C can be the unit contact of DRAM device.Unit contacts C
The dielectric layer 190 surrounded including silica separation layer 170 and 120 Oxygen Above SiClx separation layer 170 of isolated area.Unit contacts C-shaped
On Cheng Yuyi substrate 100.Substrate 100 has the isolated area 120 formed by shallow trench isolation channels (STI) and by the isolated area
The 120 multiple active areas 110 defined.In the storage unit that each active area 110 can be memory such as DRAM.It is serving as a contrast
There are the multiple wordline grooves 101 intersected with corresponding active area 110 and in being embedded in wordline groove 101 in bottom 100
Word line structure 130.Word line structure 130 can be used as the grid of transistor in memory, and the source/drain region 150 of transistor is located at wordline
In the active area 110 of 130 two sides of structure.Also there are the multiple bitline junctions intersected with corresponding active area 110 on substrate 100
Structure 140 so that a source/drain region 150 (part i.e. on substrate between two adjacent word line structures 130) for transistor with it is right
The bit line structure 140 answered is electrically connected.Opening 102 is formed between adjacent bit line structure.The side wall of opening 102 is close to bitline junction
The part of structure is polysilicon deposition 160, and the surface of polysilicon layer is silica separation layer 170,120 Oxygen Above SiClx of isolated area
The part that separation layer 170 surrounds is dielectric layer 190.Dielectric layer 190 is filled by silica/nitride deposition.
Specifically, the material of substrate 100 may include the semiconductor of silicon, germanium or silicon-on-insulator (SOI), or including germanium
III, V compounds of group such as silicon compound, silicon carbide or other known materials, such as GaAs.It can be with root in substrate 100
Certain Doped ions are injected according to design requirement to change electrical parameter.Substrate 100 is formed with isolated material in isolated area 120,
Such as silica.Preferably, substrate 100 is silicon substrate.The thickness (i.e. the width of shallow trench isolation channels) of isolated area is preferably
10nm。
The word line structure 130 being formed in substrate 100 can be used as the grid of corresponding transistor in memory, and in shape
During at word line structure 130 or after being formed, can with a source/drain region 150 wherein, such as two word line structures 130 it
Between source/drain region 150, the source electrode as corresponding transistor；And in another source/drain region 150, such as word line structure 130 and isolation
Source/drain region 150 between area 120, can be used as the drain electrode of corresponding transistor.Word line structure 130 is formed in wordline groove 101
When, gate dielectric layer 131, wordline 132 and covering gate dielectric layer 131 and wordline can be sequentially formed in wordline groove 101
132 buried insulator layer 133.The material of gate dielectric layer 131 may include silica, silicon nitride, nitrogen oxides, silicon nitride,
One of oxide/nitride/oxide (ONO) and high-k dielectric material are a variety of.Gate dielectric layer 131 can lead to
The wet or xeothermic oxidation technology such as in the environment for including oxide, vapor, nitric oxide or their combination is crossed to be formed,
Or the life of (ISSG) technique is generated by the situ steam in the environment of oxygen, vapor, nitric oxide or their combination
At, or formed as chemical vapor deposition (CVD) technology of presoma by using ethyl orthosilicate (TEOS) and oxygen.
The material of wordline 132 may include one of Ti, TiN, Ta, TaN, W, WN, TiSiN and WSiN or a variety of.Buried insulation
The material of layer may include the combination of one or more of silica, silicon nitride, silicon oxynitride and silicon nitrogen oxides.
Bit line structure 140 may include the bit line contact 141 and bit line conductive layer 142 being sequentially overlapped.Bit line contact 141 and position
It is electrically connected in source/drain region 150 (for example, source electrode) below.In some embodiments, bit line contact 141 can partially protrude into lining
In bottom 100, i.e., the bottom surface of bit line contact 141 can be lower than the surface of substrate 100 and the top surface of bit line contact 141 is higher than substrate
100 surface.In some other embodiment, the bottom surface of bit line contact 141 and the flush of substrate 100.Bit line contact 141
Material may include polysilicon or metal.Bit line conductive layer 142 is formed in 141 surface of bit line contact, thus passes through bit line contact
141, bit line conductive layer 142 can be formed with the first source/drain region 150 and is electrically connected.The material of bit line conductive layer 142 may include W, Ti,
Ni、Al、Pt、TiO2, one of TiN and polysilicon or two or more combinations.Bit line structure 140 also may include it
His layer, such as may also include the work-function layer for being directly covered in 141 top surface of bit line contact.
Wherein, the thickness of polysilicon deposition 160 is preferably 150nm.Thickness refers to side wall and the oxidation of bit line structure herein
The distance between silicon separation layer 170 H1.In the selection of the thickness of polysilicon deposition 160, those skilled in the art can also basis
Actual needs selects other suitable thickness.
Wherein, the thickness of silica separation layer 170 is preferably 1.5nm.Thickness refers to 190 side of dielectric layer with it most herein
The distance between the close boundary of polysilicon deposition 160 H2.In the selection of the thickness of silica separation layer 170, this field
Technical staff can also select other suitable thickness according to actual needs.
It is filled by polycrystalline silicon/oxidative silicon/silicon nitride and is formed medium in the open depression part that silica separation layer 170 surrounds
Layer 190.Wherein, the thickness of dielectric layer 190 is preferably 1.5nm.Thickness refers to 170 shape of silica separation layer of dielectric layer 190 herein
At two sidewalls between linear distance.In the selection of the thickness of dielectric layer 190, those skilled in the art can also be according to practical need
Select other suitable thickness.
The dielectric layer of unit contact is kept apart by one layer of silica separation layer with silicon oxide deposited layer, to form guarantor
Shield, so that leakage mechanisms reduce.And the surface roughness of silica separation layer is compared with polysilicon layer conventional in the prior art
Roughness is lower.Nearby silicon is relatively more complete for isolated area, is destroyed less, defect is smaller.And silicon is complete near isolated area
Degree is also more preferable.
As described above, the beneficial effects of the utility model are, provide the forming method of semiconductor unit contact, lead to
It crosses and is depositing one layer of silica (silica separation layer) in polysilicon layer (i.e. between polysilicon deposition and polysilicon blanket layer),
The property of polysilicon is higher than using oxidation silicon resistor, when current distributing, only has lesser electric current by silica separation layer,
To which leakage mechanisms can reduce.Meanwhile when carrying out exposing the etch step of contact portion, both silica and polysilicon etching speed
Difference, bottom polysilicon etch rate is very fast, and lateral oxidation silicon etch rate is slower, therefore can be reduced and break to side polysilicon
It is bad, while destruction of the overetch to silicon near STI region can be also reduced, finally reduce the defect of unit contact structures.Pass through
The dielectric layer for the unit contact that such method is formed is protected by one layer of silica separation layer, so that leakage mechanisms can reduce.And
And the surface roughness of silica separation layer is lower compared with polysilicon layer roughness conventional in the prior art, defect is smaller.And
The integrated degree of silicon is also more preferable near isolated area.
The above are some embodiments of semiconductor unit provided by the utility model contact and forming method thereof, pass through reality
Apply the explanation of example, it is believed that those skilled in the art can understand the technical solution of the utility model and its operation principles.However with
Upper is only the preferred embodiment of the utility model, is not limited to the utility model.Those skilled in the art can be according to reality
Demand technical solution provided to the utility model in border is appropriately modified, and makes an amendment and equivalent transformation is practical all without departing from this
Novel range claimed.The utility model interest field claimed, when being subject to appended claims.
Claims (7)
1. a kind of semiconductor unit contact structures are applied to semiconductor devices, which is characterized in that the unit contact is formed in one
On substrate, the substrate has the isolated area formed by shallow trench isolation channels and the multiple active areas defined by isolated area；
There are the multiple wordline grooves intersected with corresponding active area in the substrate and in the word line structure being embedded in wordline groove；
Also there are the multiple bit line structures intersected with corresponding active area, two phases of institute's bit line structures and the substrate on substrate
Part electrical connection between the adjacent word line structure；Opening is formed between two adjacent institute's bit line structures.
2. semiconductor unit contact structures as described in claim 1, which is characterized in that the position directly above of the isolated area is
Dielectric layer, the two sidewalls of dielectric layer are silica separation layer, are polysilicon between silica separation layer and the side wall of bit line structure
Sedimentary.
3. semiconductor unit contact structures as claimed in claim 2, which is characterized in that the polysilicon deposition with a thickness of
150nm。
4. semiconductor unit contact structures as claimed in claim 2, which is characterized in that the silica separation layer with a thickness of
1.5nm。
5. semiconductor unit contact structures as claimed in claim 2, which is characterized in that the dielectric layer is by silicon nitride or oxygen
SiClx is filled.
6. semiconductor unit contact structures as claimed in claim 2, which is characterized in that the dielectric layer with a thickness of 1.5nm.
7. semiconductor unit contact structures as described in claim 1, which is characterized in that the isolated area with a thickness of 10nm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115988877A (en) * | 2023-03-16 | 2023-04-18 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN116540048A (en) * | 2023-03-13 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor test method and test structure |
-
2018
- 2018-10-31 CN CN201821785107.1U patent/CN209216972U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116540048A (en) * | 2023-03-13 | 2023-08-04 | 长鑫存储技术有限公司 | Semiconductor test method and test structure |
| CN116540048B (en) * | 2023-03-13 | 2023-12-01 | 长鑫存储技术有限公司 | Semiconductor test method and test structure |
| CN115988877A (en) * | 2023-03-16 | 2023-04-18 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115988877B (en) * | 2023-03-16 | 2023-09-08 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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