CN107104103A - A kind of transistor arrangement and preparation method thereof - Google Patents

A kind of transistor arrangement and preparation method thereof Download PDF

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Publication number
CN107104103A
CN107104103A CN201710359158.1A CN201710359158A CN107104103A CN 107104103 A CN107104103 A CN 107104103A CN 201710359158 A CN201710359158 A CN 201710359158A CN 107104103 A CN107104103 A CN 107104103A
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China
Prior art keywords
layer
conductive
conductive layer
etching
transistor arrangement
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不公告发明人
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Ruili Integrated Circuit Co Ltd
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Ruili Integrated Circuit Co Ltd
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Priority to CN201710359158.1A priority Critical patent/CN107104103A/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10805Dynamic random access memory structures with one-transistor one-capacitor memory cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10873Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10885Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10891Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a word line

Abstract

The present invention provides a kind of transistor arrangement and preparation method thereof, and preparation method comprises the following steps:1) substrate is provided, in forming groove structure in substrate;2) dielectric layer is formed in the bottom of groove structure and side wall;3) dual electric layer structure is formed in dielectric layer surface, dual electric layer structure includes being formed at the first conductive layer of dielectric layer bottom and partial sidewalls, and second conductive layer, second conductive layer includes and is incorporated into the filling part in the first conductive layer and the lug boss on filling part top, wherein, the top of first conductive layer is less than the upper surface of the substrate, top of the top higher than first conductive layer of the lug boss and the upper surface less than the substrate.By such scheme, transistor arrangement of the invention improves the height of grid wordline, reduces the resistance of grid wordline, reduces the access time of device;The distance between P/N knots and drain electrode are added, the electric field near grid is reduced, reduces gate induced drain leakage current.

Description

A kind of transistor arrangement and preparation method thereof
Technical field
The invention belongs to ic manufacturing technology field, more particularly to a kind of transistor arrangement and preparation method thereof.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as:DRAM) commonly used in computer Semiconductor storage unit, be made up of the memory cell of many repetitions.Each memory cell is main by a transistor AND gate one The individual capacitor manipulated by transistor is constituted, and memory cell can be arranged in array format, and each memory cell passes through Wordline is electrically connected to each other with bit line.As electronic product is increasingly towards light, thin, short, small development, dynamic random access memory The design of component also have to comply with high integration, highdensity requirement towards miniaturization trend development, for improve dynamic with Machine accesses the integration of memory to accelerate the service speed of component, and meets need of the consumer for miniaturized electronic device Ask, buried gate wordline dynamic random access memory is developed in recent years, to meet above-mentioned a variety of demands.
However, in above-mentioned this structure, constantly reducing with the array of dynamic RAM, there is reduction wordline Resistance and the problem of reduce balanced between gate induced drain leakage electric current, wherein, with the reduction of device size, wordline electricity Resistance can gradually increase, and which increase the access time of device, the low electricity of itself can be typically realized by increasing the height of wordline Resistance, but at the same time, Electric Field Distribution of the grid (wordline) between source and drain will change, and be produced below buried gate wordline Higher electric field, so that the overlapping region between source/drain and grid causes higher grid to be led to drain leakage (GIDL Current), and the storage time (retention time) of embedded type word line dynamic random access memory is reduced.
Therefore it provides one kind can be solved, above-mentioned grid word line resistance reduces and grid is led to that drain leakage flow phenomenon produces it Between conflicting scheme be necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of transistor arrangement and its preparation Method, particularly for solving, grid word line resistance in the prior art reduces and grid is led between the generation of drain leakage flow phenomenon It is conflicting the problem of.
In order to achieve the above objects and other related objects, the present invention provides a kind of preparation method of transistor arrangement, including Following steps:
1) substrate is provided, in forming groove structure in the substrate;
2) dielectric layer is formed in the bottom of the groove structure and side wall;And
3) dual electric layer structure is formed in the dielectric layer surface, and the dual electric layer structure includes being formed at the dielectric Layer bottom and the first conductive layer and the second conductive layer of partial sidewalls, second conductive layer are led comprising being incorporated into described first Filling part in electric layer and the lug boss on the filling part top, wherein the top of first conductive layer is less than the lining The upper surface at bottom, top of the top higher than first conductive layer of the lug boss and the upper surface less than the substrate.
It is used as a preferred embodiment of the present invention, step 3) in, the material of first conductive layer is conductive with described second The material of layer is different, and resistance value of the resistance value more than second conductive layer of first conductive layer;Step 3) in institute's shape Into the height of the lug boss account for the 0.01%~50% of the described second conductive layer height;The top of the lug boss relative to The altitude range on the top of first conductive layer is 0.01~50nm.
It is used as a preferred embodiment of the present invention, step 1) include:
The surface insulation layer with window 1-1) is formed on the substrate, wherein, the window and the groove structure Correspondence;
Substrate described in the opening etch 1-2) is based on to form the groove structure;
Step 3) in, forming the dual electric layer structure includes:
The first conductive material layer 3-1) is formed in the bottom of the dielectric layer, the side wall of the dielectric layer, the window On side wall and the surface insulation layer of the window both sides;
The second conductive material layer 3-2) is formed on first conductive material layer, the second conductive material layer filling is full The groove structure and the window, and extend over first conductive material layer on the surface insulation layer;And
3-3) first conductive material layer and the second conductive material layer are performed etching, to form first conductive layer And second conductive layer.
It is used as a preferred embodiment of the present invention, step 3-3) in, the etching includes:
Etch for the first time:Quarter first time is carried out to first conductive material layer and second conductive material layer Erosion, makes the etching depth of first conductive material layer be more than the etching depth of second conductive material layer, so that part institute The second conductive material layer is stated to protrude from above first conductive material layer.
It is used as a preferred embodiment of the present invention, step 3-3) in, the etching also includes:
Second of etching:To protruding from described in second conductive material layer progress above first conductive material layer Second of etching, to obtain the lug boss of the cross sectional shape as polygon, circle, semicircle or spheroid shape.
It is used as a preferred embodiment of the present invention, step 3-3) in, the etching includes:
Etch for the first time:The quarter of same depth is carried out to first conductive material layer and second conductive material layer Erosion;And
Second of etching:Structure after being etched to the first time proceeds described second and etched, and makes described first Conductive material layer etches a predetermined depth to form first conductive layer, while making second conductive material layer etch to be formed Second conductive layer, the cross sectional shape of the lug boss of second conductive layer is polygon, circle, semicircle or ellipsoid Type.
It is used as a preferred embodiment of the present invention, step 3-3) in, the etching gas of the etching include sulfur hexafluoride (SF6), any two or three of combination in chlorine (Cl2) and argon gas (Ar), the etch period of the etching is 60~250s, In the etching gas of the etching, the flow of sulfur hexafluoride is 0~150 ml/min (sccm), and the flow of chlorine is 0~250 Ml/min, the flow of argon gas is 0~400 ml/min;Step 3-3) in, by the flow-rate ratio for adjusting different etching gas Example to etch the dual electric layer structure, or by cycle alternation to be passed through different etching gas described double to etch Conductive coating structure.
It is used as a preferred embodiment of the present invention, step 3) after, in addition to step:
4) fill insulant is in the groove structure, and to form filling perforation insulating barrier, the filling perforation insulating barrier covers institute State the top of the first conductive layer and the top of second conductive layer.
The present invention also provides a kind of preparation method of memory cell array, comprises the following steps:
A) multiple memory cell with the transistor arrangement are formed, and each memory cell is configured with list The memory cell array of first row and cell columns, wherein, the transistor arrangement is using the system as described in above-mentioned any one scheme Preparation Method is prepared, and the transistor arrangement is used as buried gate wordline;And
B) flush type of each memory cell of one addressed line of connection into the cell row or the cell columns Grid wordline, the addressed line is used to control the memory cell.
The present invention also provides a kind of transistor arrangement, including:
Substrate;
Groove structure, in the substrate;
Dielectric layer, positioned at the bottom of the groove structure and side wall;And
Dual electric layer structure, including the first conductive layer and the second conductive layer, wherein:
First conductive layer is located at bottom and the partial sidewalls of the dielectric layer, and the top of first conductive layer is low In the upper surface of the substrate;
Second conductive layer includes being filled in the bottom of the groove structure and surface covers first conductive layer Filling part and the lug boss on the filling part, wherein, the top of the lug boss is higher than first conductive layer Top and less than the substrate upper surface, between the both sides of the lug boss and the dielectric layer have insulation lateral sulcus.
As a preferred embodiment of the present invention, the material of the material of first conductive layer and second conductive layer is not Together, and first conductive layer resistance value be more than second conductive layer resistance value.
As a preferred embodiment of the present invention, the cross sectional shape of the lug boss is polygon, circle, semicircle or ellipse Ball-type.
As a preferred embodiment of the present invention, the height of the lug boss accounts for the height of second conductive layer 0.01%~50%, the altitude range on top of the top relative to first conductive layer of the lug boss for 0.01~ 50nm。
As a preferred embodiment of the present invention, the width of the insulation lateral sulcus is the thickness institute by first conductive layer Define.
As a preferred embodiment of the present invention, the both side edges of the lug boss of second conductive layer have breach Groove so that the width of the insulation lateral sulcus is more than the thickness of first conductive layer.
As a preferred embodiment of the present invention, the transistor arrangement, in addition to:
In filling perforation insulating barrier, the top for being filled in the groove structure, with cover first conductive layer top and The top of second conductive layer, the filling perforation insulating barrier is more filled in the insulation lateral sulcus.
The present invention also provides a kind of memory cell array, with multiple storage lists for being configured to cell row and cell columns Member, the memory cell includes the transistor arrangement as described in above-mentioned any one scheme, and the transistor arrangement is used as embedment Formula grid wordline, wherein, the buried gate wordline is connected to an addressed line, and the addressed line is used to control the storage single Member.
The present invention also provides a kind of memory construction, including the storage list as described in preceding claim any one scheme Element array.
The present invention also provides a kind of memory construction, including the memory cell battle array as described in above-mentioned any one scheme Row.
As described above, transistor arrangement of the present invention and preparation method thereof, in specific operation process, with following beneficial Effect:
1) transistor arrangement of the invention improves the height of grid wordline, the resistance of grid wordline is reduced, so as to subtract The access time of device is lacked;
2) transistor arrangement of the invention changes the distribution of grid wordline surrounding electric field, reduces grid and source-drain electrode Contact area, adds the distance between P/N knots and drain electrode, the electric field near grid is reduced, so as to reduce gate induced The phenomenon of drain leakage.
Brief description of the drawings
Fig. 1 is shown as the flow chart for the transistor arrangement preparation method that the present invention is provided.
Fig. 2 is shown as being formed the signal of the mask layer with opening in the transistor arrangement preparation method that the present invention is provided Figure.
Fig. 3 is shown as being formed the schematic diagram of groove structure in the transistor arrangement preparation method that the present invention is provided.
Fig. 4 is shown as being formed the schematic diagram of dielectric layer in the transistor arrangement preparation method that the present invention is provided.
Fig. 5 is shown as being formed the schematic diagram of the first conductive material layer in the transistor arrangement preparation method that the present invention is provided.
Fig. 6 is shown as being formed the schematic diagram of the second conductive material layer in the transistor arrangement preparation method that the present invention is provided.
Fig. 7 to Figure 10 is shown as being formed the signal of dual electric layer structure in the transistor arrangement preparation method that the present invention is provided Figure;Wherein, the cross sectional shape in Fig. 7 protrusions portion is rectangle, and the cross sectional shape in Fig. 8 protrusions portion is triangle, Fig. 9 protrusions portion Cross sectional shape be circular arc, the cross sectional shape in Figure 10 protrusions portion is convex.
Figure 11 is shown as filling the schematic diagram of filling perforation insulating barrier in the transistor arrangement preparation method that the present invention is provided.
Figure 12 is shown as the schematic diagram for the memory cell structure that the present invention is provided.
Reference numerals explanation
100 substrates
101 surface insulation layers
1011 insulation material layers
102 mask layers
103 openings
104 windows
105 groove structures
106 dielectric layers
107 first conductive material layers
108 second conductive material layers
109 first conductive layers
110 second conductive layers
1101 filling parts
1102 lug bosses
111 dual electric layer structures
112 filling perforation insulating barriers
113 source electrodes
114 drain electrodes
115 bit lines
116 capacitor cells
117 separation layers
Ditch is surveyed in 118 insulation
119 gap slots
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from Various modifications or alterations are carried out under the spirit of the present invention.
Fig. 1 is referred to Figure 12.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only display is with relevant component in the present invention rather than according to package count during actual implement in diagram Mesh, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its Assembly layout form may also be increasingly complex.
Referring to Fig. 1, the present invention provides a kind of preparation method of transistor arrangement, the preparation method includes following step Suddenly:
1) substrate is provided, in forming groove structure in the substrate;
2) dielectric layer is formed in the bottom of the groove structure and side wall;And
3) dual electric layer structure is formed in the dielectric layer surface, and the dual electric layer structure includes being formed at the dielectric Layer bottom and the first conductive layer and the second conductive layer of partial sidewalls, second conductive layer are led comprising being incorporated into described first Filling part in electric layer and the lug boss on the filling part top, wherein the top of first conductive layer is less than the lining The upper surface at bottom, top of the top higher than first conductive layer of the lug boss and the upper surface less than the substrate.
The preparation method of the transistor arrangement of the present invention is discussed in detail with reference to specific accompanying drawing.
As shown in S1 and Fig. 2 to Fig. 3 in Fig. 1, step 1 is carried out) there is provided a substrate 100, in formation in the substrate Groove structure 105.
Specifically, the material of the substrate 100 includes but is not limited to monocrystalline or polycrystalline semiconductor material, in addition, the lining Bottom 100 can also be the silicon substrate of intrinsic monocrystalline substrate either light dope, further, it is possible to be N-type polycrystalline silicon substrate Or p-type polysilicon substrate, in the present embodiment, the substrate 100 are the substrate of P+ type polycrystalline silicon material.In addition, the substrate The resistivity of 100 material is preferably 2 × 10-8~1 × 102Ωm。
As an example, step 1) in, the cross sectional shape of the groove structure 105 is U-shaped.
Specifically, in other embodiments, the cross sectional shape of the groove structure 105 can also be the applicable devices such as rectangle The arbitrary shape of performance.
As an example, in step 1) in formed before the groove structure 105, in addition to form the table with window 104 Face insulating barrier 101 in the step on the substrate 100, wherein, the window 104 is corresponding with the opening of the groove structure 105, As shown in Figures 2 and 3.
Specifically, it is exhausted that the surface with window 104 is formed on the substrate 100 using the technique of photoetching and etching Edge layer 101, wherein, first in formation insulation material layer 1011 on the substrate 100, and using the photoresist with opening 103 Performed etching as 102 pairs of insulation material layers 1011 of mask layer, form the surface insulation layer with the window 104 101, and continue etching, to form the groove structure 105.
As shown in S2 and Fig. 4 in Fig. 1, step 2 is carried out), dielectric layer 106 is formed in the bottom of the groove structure 105 Portion and side wall.
Specifically, the material of the dielectric layer 106 can be but not limited to silica, silicon nitride, the silica can be with It is preferably 2 × 10 for the resistivity of silicon monoxide or silica, and material11~1 × 1025Ω m, the dielectric layer 106 can By atomic deposition processing procedure (Atomic Layer Deposition) or plasma vapor deposition (Chemical Vapor Deposition) film or quick heated oxide (Rapid Thermal Oxidation) and formed, its thickness is about in 0.1nm To between 10nm.
As shown in S3 and Fig. 5 to Figure 11 in Fig. 1, step 3 is carried out), dual electric layer structure 111 is formed in the dielectric 106 surface of layer, the dual electric layer structure 111 includes the first conduction for being formed at the bottom of dielectric layer 106 and partial sidewalls Layer 109, and the second conductive layer 110, second conductive layer 110 include the filling being incorporated into first conductive layer 109 Portion 1101 and the lug boss 1102 on the filling part 1101 top, wherein, the top of first conductive layer 109 is less than institute The upper surface of substrate 100 is stated, the top of the lug boss 102 is higher than the top of first conductive layer 109 and less than the lining The upper surface at bottom 100, in the present embodiment, the dual electric layer structure 111 is as grid wordline, it is of course also possible to be used for it The design of the active region of his different structure.
As an example, step 3) in, the material of the material of first conductive layer 109 and second conductive layer 110 is not Together, and first conductive layer 109 resistance value be more than second conductive layer 110 resistance value.
Specifically, the material of first conductive layer 109 be the germanium of silicon, P or the As that P or As or B adulterate or B doping, W, Any one in Ti, TiN, Ru;The material of second conductive layer 110 is W (Tungsten), Ti (Titanium), Ni (Nickel), any one in Al (Aluminum), Pt (Platinum), and the material of first conductive layer 109 with it is described The material of second conductive layer 110 is different, and then can select at least one etching gas different to two conductive layer etch rates Perform etching, to obtain the structure obtained required for the application.In addition, first conductive layer 109 and second conductive layer 110 can be by atomic deposition processing procedure (Atomic Layer Deposition) or plasma vapor deposition (Chemical Vapor Deposition) film or quick heated oxide (Rapid Thermal Oxidation) and formed.
Further, it is preferable that the resistance value of first conductive layer 109 is more than the resistance value of second conductive layer 110, The thickness of first conductive layer 109 is thicker, and the lug boss 1102 also can be thinner.
As an example, step 3) in, the height of the lug boss formed accounts for the height of second conductive layer 110 0.01%~50%, it is preferable that the height of the lug boss accounts for the height 30% of second conductive layer.Specifically, described The height of two conductive layers 110 refers to bottom (namely the filling part 1101 being located in the groove structure of the second conductive layer Bottom) the distance between with the top of the lug boss 1102.
As an example, step 3) in, top of the top relative to first conductive layer 109 of the lug boss 1102 Altitude range is 0.01~50nm, preferably 2~40nm or 5~30nm, it is further preferred that the height of the lug boss 1102 Scope is 10~30nm.Preferably, in the present embodiment, the height of the lug boss 1102 is 20nm.
As an example, step 3) in, the step of forming dual electric layer structure 111 includes:
The first conductive material layer 107 3-1) is formed in the bottom of the dielectric layer 106, the side wall of the dielectric layer 106, institute State on the side wall of window 104 and the surface insulation layer 101 of the both sides of the window 104, as shown in Figure 5;
The second conductive material layer 108 3-2) is formed on first conductive material layer 107, second conductive material layer 108 the filling full groove structures 105 and the window 104, and extend on the surface insulation layer 101 described the One conductive material layer 107, as shown in Figure 6;
3-3) conductive material layer 108 of the first conductive material layer 107 and second is performed etching, to form described first Conductive layer 109 and second conductive layer 110, as shown in Figure 7 to 9.
Specifically, first conductive material layer 107 and second conductive material layer 108 include but is not limited to electroplate, The depositing operations such as chemical vapor deposition, physical vapour deposition (PVD) or ald.
It should be noted that the dual electric layer structure 111 is both as grid, wordline, the grid of this flush type are also served as Pole wordline can save device space, reduce device size, improve device speed, and the dual electric layer structure 111 is by described the One conductive layer 109 and second conductive layer 110 are constituted, wherein, the one side of the first conductive layer 109 can improve described double Adhesive force between conductive coating structure 11 and the dielectric layer 106, on the other hand, also serves as second conductive layer 110 and institute Give an account of the barrier layer between electric layer 106, it is to avoid the element of second conductive layer 110 diffuses to described in ensuing processing procedure Dielectric layer 106, so as to avoid the shift phenomenon of component starting voltage, in the present embodiment, the dielectric layer 106 namely grid are situated between Matter layer, second conductive layer 110 is also referred to as gate metal.
As an example, step 3-3) in, the etching includes:
Etch for the first time:Quarter first time is carried out to first conductive material layer 107 and second conductive material layer 108 Erosion, makes the etching depth of first conductive material layer 107 be more than the etching depth of second conductive material layer 108, so that Part second conductive material layer 108 protrudes from the top of the first conductive material layer 107, as shown in Figure 7.
Specifically, in the present embodiment, the purpose of the first time etching is to be formed to make second conductive material layer 108 The structure of the top of the first conductive material layer 107 is protruded from, in the present embodiment or other embodiment, the first time etching Resulting structure can be as transistor structure application in device afterwards.
As an example, step 3-3) in, the etching also includes:
Second of etching:Second conductive material layer 108 for protruding from the top of the first conductive material layer 107 is entered Second of etching of row, to obtain the lug boss 1102 of the cross sectional shape as polygon, circle, semicircle or spheroid shape, such as Fig. 8 With shown in Fig. 9.
Specifically, in described second etches, selecting suitable etching gas, making to protrude from first conductive material Second conductive material layer 108 of the top of layer 107 obtains different cross sectional shapes, so as to be applicable different devices.
It should be noted that in the present embodiment, grid word line structure, namely the dual electric layer structure 111 are designed as Structure with raised (Fin Shape), i.e., described first conductive layer 109 and comprising being incorporated into first conductive layer 109 Filling part 1101 and the lug boss 1102 on the filling part 1101 the second conductive layer 110, wherein, the projection Portion 1102 adds the height of wordline, so as to reduce the resistance of wordline, reduces the access time of device, further, since institute Stating between the both sides of lug boss 1102 and the dielectric layer 106 has insulation lateral sulcus 118, reduces contact of the grid with source-drain electrode Area, adds the distance between P/N knots and drain electrode and (for details, reference can be made to Figure 12, refer between dotted box portion drain electrode adjacent thereto Distance), the electric field of grid annex is also reduced, so as to alleviate the phenomenon of gate induced drain leakage current.
In the present embodiment, the material of first conductive layer 109 is TiN, and the material of second conductive layer 110 is W, In the prior art, first conductive layer is concordant with the top of second conductive layer, and its distance of top away from substrate is about 40 ~150nm, and the distance of the first conductive layer 109 away from substrate in the present embodiment is about 35~150nm, described second is conductive 110 distance away from substrate of layer are 40~150nm.Referring now to prior art, the application is while word line resistance is reduced, increase The distance between P/N knots and drain electrode, alleviate the phenomenon of gate induced drain leakage current.
As an example, step 3-3) in, the etching includes:
Etch for the first time:Same depth is carried out to first conductive material layer 107 and second conductive material layer 108 Etching (not shown);
Second of etching:Structure after being etched to the first time proceeds described second and etched, and makes described first Conductive material layer 107 etches a predetermined depth to form first conductive layer 109, while making second conductive material layer 108 etchings form second conductive layer 110, and the cross sectional shape of the lug boss 1102 of second conductive layer 110 is many Side shape, circle, semicircle or spheroid shape, as shown in Figure 7 to 9.
Specifically, in this embodiment, carrying out the first time etching, two layers of conductive material layer etching is formd identical Depth, and when carrying out described second and etching, by first conductive material layer 107 and second conductive material Layer 108 is performed etching simultaneously again, has obtained required dual electric layer structure 111.
As an example, step 3-3) in, the etching gas of the etching include sulfur hexafluoride (SF6), chlorine (Cl2) and argon Any two or three of combination in gas (Ar), the etch period of the etching is 60~250s.
As an example, in the etching gas of the etching, SF6Flow be 0~150sccm, Cl2Flow for 0~ 250sccm, Ar flow are 0~400sccm.
Specifically, in the etching gas, for SF6/Cl2(based on chemical reaction etching), by adjusting flow proportional Or individual other etching period is to perform etching, for Ar flows, in addition to as diluent gas, mainly as Ions Bombardment to enter Row etching, further, controls Source RF power (source power) and adds to Bias Power (the RF biass for being added in chip) to come The different depth of first conductive layer 109 and second conductive layer 110 is etched, and the lug boss 1102 is not Similar shape.In the present embodiment, SF6Flow be 0~150sccm, Cl2Flow be 0~250sccm, Ar flow for 0~ 400sccm;Source power:0~1500Watts (watt), preferably 300~800Watts;Bias Power:0~150Watts, The pressure that etching is implemented is 2~30Torr, wherein, sccm (standard cubic centimeter per minute) is gas Weight flux unit, in addition, the etch period is depending on actual conditions, in etching process, preferably under the high temperature conditions Carry out, its temperature of electrostatic chuck is 20~80 DEG C.
In one embodiment, same depth is carried out to the first metal layer 109 and second metal layer 110 first Etching, then, is further etched to the first metal layer 109, during the further etching, with Cl2To carve Gas is lost, is performed etching under the high temperature conditions, preferably 60~80 DEG C, meanwhile, increase etch period is to 30~150s, to obtain Required dual electric layer structure.
As an example, step 3-3) in, it is described double conductive to etch by adjusting the flow proportional of different etching gas Rotating fields 111, or different etching gas are passed through to etch the dual electric layer structure 111 by cycle alternation.
Specifically, the lithographic method for obtaining the dual electric layer structure 111, on the one hand can be by adjusting etching The flow proportional of reacting gas to first conductive material layer 107 and second conductive material layer 108 to carry out selectivity Etching obtained by, wherein, be TiN with first conductive layer 109, second conductive layer be W (Tungsten) exemplified by, lead to Cross adjustment etching gas SF6(fast compared with TiN to W rate of etch) and Cl2The etching reaction gas flow of (fast compared with W to TiN rate of etch) comes Reach and etch the dual electric layer structure 111, i.e., finally make the first conductive layer TiN etch depths relatively large.
On the other hand, can also etching reaction gas cycle alternation formula etching, be still with first conductive layer 109 TiN, exemplified by second conductive layer is W (Tungsten), it is specifically passed through mode and is:SF6And Cl2Alternating is passed through, and is controlled Etching gas are passed through time, i.e. SF6(4~20sec)-Cl2(2~20sec)-SF6(4~20sec)-Cl2(2~20sec)- SF6(4~20sec)-Cl2(2~20sec) etc. carries out multistep circulation etching.
As an example, step 3) also include step 4 afterwards), fill insulant is in the groove structure 105, with shape Into filling perforation insulating barrier 112, the filling perforation insulating barrier 112 covers the top of first conductive layer 109 and second conduction The top of layer 110, as shown in figure 11.
Specifically, the insulating materials can be to include oxide (for example, silica, Al2O3、HfO2Deng), silicon nitride and Any suitable insulating materials including silicon oxynitride etc., is not limited herein.
The present invention also provides a kind of preparation method of memory cell array, comprises the following steps:
A) multiple memory cell with the transistor arrangement are formed, and each memory cell is configured with list The memory cell array of first row and cell columns;Wherein, the buried gate wordline is used such as institute in above-mentioned any one scheme The preparation method for the transistor arrangement stated is prepared, transistor arrangement buried gate wordline the most;
B) flush type of each memory cell of one addressed line of connection into the cell row or the cell columns Grid wordline, the addressed line is used to control the memory cell.
Specifically, present invention also offers a kind of preparation method of memory cell array, as shown in figure 12, including preparation is deposited The step of storage unit, wherein, in the present embodiment, the memory cell uses P+ type substrate, in the grid word line structure both sides N+ types source electrode 113 and N+ types drain electrode 114 are formed, in addition, being also included in formation bit line 115 on the source electrode 113, in the leakage Formed and insulated between capacitor cell 116, each part by separation layer 117 on pole 114.It should be noted that the present invention is prepared Transistor arrangement can apply to different structure active region design, according to depending on actual conditions, be such as applied in Figure 12 The shown U being made up of first conductive material layer 107 is majority and is arranged in array.
The present invention also provides a kind of preparation method of memory construction, the memory cell described in above-mentioned any one scheme The preparation process of the preparation method of array.
Further, the step of forming several fleet plough groove isolation structures in the memory construction is additionally included in, wherein, phase Two transistor arrangements being spaced apart are provided between the adjacent fleet plough groove isolation structure.
Please continue to refer to Fig. 7 to Figure 12, the present invention also provides a kind of transistor arrangement, and the transistor arrangement is using upper Stating the preparation-obtained structure of preparation method of the transistor arrangement includes:
Substrate 100;
Groove structure 105, in the substrate 100;
Dielectric layer 106, positioned at the bottom of the groove structure 105 and side wall;And
Dual electric layer structure 111, the dual electric layer structure 111 includes the first conductive layer 109 and the second conductive layer 110, Wherein,
First conductive layer 109 is located at bottom and the partial sidewalls of the dielectric layer 106, and first conductive layer 109 top is less than the upper surface of the substrate 100;
Second conductive layer 110 includes being filled in the bottom of the groove structure and surface covering described first is conductive The filling part 1101 of layer 109 and the lug boss 1102 on the filling part 1101 top, wherein, the lug boss 1102 Top of the top higher than first conductive layer 109 and the upper surface less than the substrate 100, the both sides of the lug boss 1102 There is insulation lateral sulcus 118 between the dielectric layer 106, in the present embodiment, the dual electric layer structure 111 is used as grid word Line, it is of course also possible to the design of the active region for other different structures.
Specifically, the substrate 100 includes but is not limited to the substrate of single-crystal semiconductor material, it is in the present embodiment, described Substrate 100 is the monocrystalline substrate of intrinsic monocrystalline substrate either light dope.In addition, the material of the dielectric layer 106 can Think but be not limited to silica.
As an example, the cross sectional shape of the groove structure 105 is U-shaped.
Specifically, in other embodiments, the cross sectional shape of the groove structure 105 can also be the applicable devices such as rectangle The arbitrary shape of performance.
As an example, the material of first conductive layer 109 is different and described from the material of second conductive layer 110 The resistance value of first conductive layer 109 is more than the resistance value of second conductive layer 110.
Specifically, the material of first conductive layer 109 be the germanium of silicon, P or the As that P or As or B adulterate or B doping, Ti, Any one in TiN, Ru;The material of second conductive layer 110 be silicon, P or the As that P or As or B adulterate or B doping germanium, Any one in Ti, TiN, Ru, and the material of first conductive layer 109 is different from the material of second conductive layer 110, enters And at least one etching gas different to two conductive layer etch rates can be selected to perform etching, with required for obtaining the application Obtained structure.
Further, it is preferable that the resistance value of first conductive layer 109 is more than the resistance value of second conductive layer 110, The thickness of first conductive layer 109 is thicker, and the lug boss 1102 also can be thinner.
As an example, the longitudinal section shape of the lug boss 1102 is polygon, circle, semicircle or spheroid shape;Its In, using the cross sectional shape of the lug boss 1102 as rectangle as an example, with the section of the lug boss 1102 in Fig. 8 in Fig. 7 Triangle is shaped as an example, using the cross sectional shape of the lug boss 1102 as semicircular arc as an example, in Figure 10 in Fig. 9 The cross sectional shape of lug boss is convex as an example, wherein, the both sides of lug boss 1102 are recessed, and the filling part is cut together 1101。
As an example, the height of the lug boss accounts for the 0.01%~50% of the height of second conductive layer, it is preferable that The height of the lug boss accounts for the height 30% of second conductive layer.
As an example, altitude range of the top of the lug boss 1102 relative to the top of first conductive layer 109 For 0.01~50nm.Specifically, in the present embodiment, the height of the lug boss 1102 is preferably 10nm.
As an example, as shown in Fig. 9 and 11, the width of the insulation lateral sulcus 118 is by the thickness of first conductive layer 109 Degree is defined.
As an example, as shown in Figure 10, the both side edges of the lug boss 1102 of second conductive layer 110 have breach Groove 119 so that the width of the insulation lateral sulcus 118 is more than the thickness of first conductive layer 109.
Specifically, the width of the insulation lateral sulcus 118 refer to the lateral margin of the lug boss 1102 and the dielectric layer 106 it Between distance, when first conductive layer 109 of formation is thicker, the width of the insulation lateral sulcus 118 is wider, additionally, it is preferred that Ground, the gap slot 119 is provided with the side wall of the lug boss 1102, further to increase the width of the insulation lateral sulcus 118 Degree, so that the width of the insulation lateral sulcus 118 is more than the thickness of first conductive layer 109, wherein, the gap slot 119 shape can not specifically be limited for arc, square, triangle etc., the depth of the gap slot 119 depending on actual demand, That is, the distance between lug boss 1102 and the dielectric layer 106 for being formed after gap slot 119 are depending on actual demand, It is not specifically limited, the gap slot 119 can be that can realize any gap slot of above-mentioned functions.
As an example, as shown in figure 11, the transistor arrangement also includes:Filling perforation insulating barrier 112, is filled in the groove It is described to cover the top of first conductive layer 109 and the top of second conductive layer 110 in the top of structure 105 Filling perforation insulating barrier 112 is more filled in the insulation lateral sulcus 118.As a change example, the filling perforation insulating barrier 112 can be not filled with It is the air chamber covered by the filling perforation insulating barrier 112 in space in the insulation lateral sulcus 118, the insulation lateral sulcus 118, also has Good electric insulating effect.
The square-section lug boss 1102 of larger topside area as shown in Figure 7, can control the filling perforation insulating barrier 112 Filling proportion in the insulation lateral sulcus 118.The lug boss 1102 of tapered cross-section as shown in Figure 8, can increase described fill out Filling effect of the hole insulating barrier 112 in the both sides of lug boss 1102.Circle, semicircle or spheroid shape section as shown in Figure 9 Lug boss 1102, can be conducive to the etching depth of first conductive layer 109, increase the depth in the insulation lateral sulcus 118 Degree.The square-section lug boss 1102 of smaller topside area as shown in Figure 10, it can be ensured that the filling perforation insulating barrier 112 is filled up The insulation lateral sulcus 118.
Specifically, the filling perforation insulating barrier 112 can by including oxide (for example, silica, Al2O3、HfO2Deng), nitrogen Any suitable insulating materials including SiClx and silicon oxynitride etc. is made, and is not limited herein, and the filling perforation insulating barrier 112 can To realize device isolation.
As an example, the surface of substrate 100 is also formed with the surface insulation layer 101 with window 104, wherein, it is described Window 104 is corresponding with the opening of the groove structure 105.
It should be noted that in the present embodiment, grid word line structure, namely the dual electric layer structure 111 are designed as Structure with raised (Fin Shape), i.e., described first conductive layer 109 and comprising being incorporated into first conductive layer 109 Filling part 1101 and the lug boss 1102 on the filling part 1101 the second conductive layer 110, wherein, the projection Portion 1102 adds the height of wordline, so as to reduce the resistance of wordline, reduces the access time of device, further, since institute Stating between the both sides of lug boss 1102 and the dielectric layer 106 has insulation lateral sulcus 118, reduces contact of the grid with source-drain electrode Area, adds the distance between P/N knots and drain electrode, the electric field of grid annex is also reduced, so as to alleviate gate induced The phenomenon of drain leakage.
The present invention also provides a kind of memory cell array, with multiple storage lists for being configured to cell row and cell columns Member, the memory cell includes transistor arrangement as described in above-mentioned any one example, and the transistor arrangement is as burying Enter formula grid wordline, wherein, the buried gate wordline is connected to an addressed line, and the addressed line is used to control the storage Unit.
The present invention also provides a kind of memory construction, including the memory cell array described in above-mentioned any one scheme.
Further, several fleet plough groove isolation structures are also included in the memory construction, wherein, the adjacent shallow trench Two transistor arrangements being spaced apart are provided between isolation structure.
In summary, the present invention provides a kind of transistor arrangement and preparation method thereof, and the preparation method includes following step Suddenly:1) substrate is provided, in forming groove structure in the substrate;2) dielectric layer is formed in the bottom and side of the groove structure Wall;And 3) dual electric layer structure is formed in the dielectric layer surface, the dual electric layer structure includes being formed at the dielectric Layer bottom and the first conductive layer and the second conductive layer of partial sidewalls, second conductive layer are led comprising being incorporated into described first Filling part in electric layer and the lug boss on the filling part top, wherein the top of first conductive layer is less than the lining The upper surface at bottom, top of the top higher than first conductive layer of the lug boss and the upper surface less than the substrate.It is logical Such scheme is crossed, transistor arrangement of the invention improves the height of grid wordline, reduces the resistance of grid wordline, so as to subtract The access time of device is lacked;The distribution of grid wordline surrounding electric field is changed, the contact area of grid and source-drain electrode is reduced, The distance between P/N knots and drain electrode are added, the electric field near grid is reduced, so as to reduce gate induced drain leakage current Phenomenon.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as Into all equivalent modifications or change, should by the present invention claim be covered.

Claims (18)

1. a kind of preparation method of transistor arrangement, it is characterised in that comprise the following steps:
1) substrate is provided, in forming groove structure in the substrate;
2) dielectric layer is formed in the bottom of the groove structure and side wall;And
3) dual electric layer structure is formed in the dielectric layer surface, and the dual electric layer structure includes being formed at the dielectric layer bottom Portion and the first conductive layer and the second conductive layer of partial sidewalls, second conductive layer include and are incorporated into first conductive layer Interior filling part and the lug boss on the filling part, wherein the top of first conductive layer is upper less than the substrate Surface, top of the top higher than first conductive layer of the lug boss and the upper surface less than the substrate.
2. the preparation method of transistor arrangement according to claim 1, it is characterised in that step 3) in, described first leads The material of electric layer is different from the material of second conductive layer, and the resistance value of first conductive layer is more than the described second conduction The resistance value of layer;Step 3) formed in the lug boss height account for the described second conductive layer height 0.01%~ 50%;Step 3) in, the altitude range on top of the top relative to first conductive layer of the lug boss for 0.01~ 50nm。
3. the preparation method of transistor arrangement according to claim 1, it is characterised in that step 1) include:
The surface insulation layer with window 1-1) is formed on the substrate, wherein, the window is corresponding with the groove structure;
Substrate described in the opening etch 1-2) is based on to form the groove structure;
Step 3) in, the step of forming the dual electric layer structure includes:
3-1) formed the first conductive material layer in the bottom of the dielectric layer, the side wall of the dielectric layer, the window side wall And on the surface insulation layer of the window both sides;
The second conductive material layer 3-2) is formed on first conductive material layer, the second conductive material layer filling is full described Groove structure and the window, and extend over first conductive material layer on the surface insulation layer;And
3-3) first conductive material layer and the second conductive material layer are performed etching, to form first conductive layer and institute State the second conductive layer.
4. the preparation method of transistor arrangement according to claim 3, it is characterised in that step 3-3) in, the etching Including:
Etch for the first time:The first time etching is carried out to first conductive material layer and second conductive material layer, made The etching depth of first conductive material layer is more than the etching depth of second conductive material layer, so that part described second Conductive material layer is protruded from above first conductive material layer.
5. the preparation method of transistor arrangement according to claim 4, it is characterised in that step 3-3) in, the etching Also include:
Second of etching:Described second is carried out to protruding from second conductive material layer above first conductive material layer Secondary etching, to obtain the lug boss of the cross sectional shape as polygon, circle, semicircle or spheroid shape.
6. the preparation method of transistor arrangement according to claim 3, it is characterised in that step 3-3) in, the etching Including:
Etch for the first time:The etching of same depth is carried out to first conductive material layer and second conductive material layer;With And
Second of etching:Structure after being etched to the first time proceeds described second and etched, and makes first conduction Material layer etches a predetermined depth to form first conductive layer, while making second conductive material layer etch to form described Second conductive layer, the cross sectional shape of the lug boss of second conductive layer is polygon, circle, semicircle or spheroid shape.
7. the preparation method of transistor arrangement according to claim 3, it is characterised in that step 3-3) in, the etching Etching gas include sulfur hexafluoride (SF6), chlorine (Cl2) and argon gas (Ar) in it is any two or three combination, the etching Etch period be 60~250s, in the etching gas of the etching, the flow of sulfur hexafluoride is 0~150 ml/min (sccm), the flow of chlorine is 0~250 ml/min, and the flow of argon gas is 0~400 ml/min;Step 3-3) in, lead to The flow proportional of adjustment different etching gas is crossed to etch the dual electric layer structure, or being passed through not by cycle alternation With etching gas to etch the dual electric layer structure.
8. the preparation method of the transistor arrangement according to any one in claim 1~7, it is characterised in that step 3) Afterwards, in addition to step:
4) fill insulant is in the groove structure, to form filling perforation insulating barrier, the filling perforation insulating barrier covering described the The top of one conductive layer and the top of second conductive layer.
9. a kind of preparation method of memory cell array, it is characterised in that comprise the following steps:
A) multiple memory cell with the transistor arrangement are formed, and each memory cell is configured with cell row And the memory cell array of cell columns, wherein, the transistor arrangement is using preparation method as claimed in claim 1 preparation Obtain, the transistor arrangement is used as buried gate wordline;And
B) buried gate of each memory cell of one addressed line of connection into the cell row or the cell columns Wordline, the addressed line is used to control the memory cell.
10. a kind of transistor arrangement, it is characterised in that including:
Substrate;
Groove structure, in the substrate;
Dielectric layer, positioned at the bottom of the groove structure and side wall;And
Dual electric layer structure, including the first conductive layer and the second conductive layer, wherein:
First conductive layer is located at bottom and the partial sidewalls of the dielectric layer, and the top of first conductive layer is less than institute State the upper surface of substrate;
Second conductive layer includes being filled in filling out in the bottom of the groove structure and surface covering first conductive layer Portion and the lug boss on the filling part are filled, wherein, the top of the lug boss is higher than the top of first conductive layer End and the upper surface for being less than the substrate, have insulation lateral sulcus between the both sides of the lug boss and the dielectric layer.
11. transistor arrangement according to claim 10, it is characterised in that the material of first conductive layer and described the The material of two conductive layers is different, and resistance value of the resistance value more than second conductive layer of first conductive layer.
12. transistor arrangement according to claim 10, it is characterised in that the cross sectional shape of the lug boss is polygon Shape, circle, semicircle or spheroid shape.
13. transistor arrangement according to claim 10, it is characterised in that the height of the lug boss accounts for described second and led The 0.01%~50% of the height of electric layer, the altitude range on top of the top relative to first conductive layer of the lug boss For 0.01~50nm.
14. transistor arrangement according to claim 10, it is characterised in that the width of the insulation lateral sulcus is by described The thickness of one conductive layer is defined.
15. transistor arrangement according to claim 10, it is characterised in that the lug boss of second conductive layer Both side edges have gap slot so that the width of the insulation lateral sulcus is more than the thickness of first conductive layer.
16. the transistor arrangement according to any one in claim 10~15, it is characterised in that also include:
In filling perforation insulating barrier, the top for being filled in the groove structure, to cover the top of first conductive layer and described The top of second conductive layer, the filling perforation insulating barrier is more filled in the insulation lateral sulcus.
17. a kind of memory cell array, it is characterised in that with multiple memory cell for being configured to cell row and cell columns, The memory cell includes transistor arrangement as claimed in claim 10, and the transistor arrangement is used as buried gate word Line, wherein, the buried gate wordline is connected to an addressed line, and the addressed line is used to control the memory cell.
18. a kind of memory construction, it is characterised in that including memory cell array as claimed in claim 17.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978605A (en) * 2017-11-16 2018-05-01 长江存储科技有限责任公司 The substep circulation lithographic method of 3D NAND gate polar curve slit grooves

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124854A1 (en) * 2010-10-06 2014-05-08 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
CN104103638A (en) * 2013-04-01 2014-10-15 三星电子株式会社 Semiconductor device and semiconductor module
US9224619B2 (en) * 2014-02-04 2015-12-29 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US20160093710A1 (en) * 2014-01-02 2016-03-31 SK Hynix Inc. Semiconductor device and method for forming the same
US20170084615A1 (en) * 2015-09-18 2017-03-23 Samsung Electronics Co., Ltd. Semiconductor device having a gate and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140124854A1 (en) * 2010-10-06 2014-05-08 Samsung Electronics Co., Ltd. Semiconductor devices and methods of forming the same
CN104103638A (en) * 2013-04-01 2014-10-15 三星电子株式会社 Semiconductor device and semiconductor module
US20160093710A1 (en) * 2014-01-02 2016-03-31 SK Hynix Inc. Semiconductor device and method for forming the same
US9224619B2 (en) * 2014-02-04 2015-12-29 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
US20170084615A1 (en) * 2015-09-18 2017-03-23 Samsung Electronics Co., Ltd. Semiconductor device having a gate and method of forming the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978605A (en) * 2017-11-16 2018-05-01 长江存储科技有限责任公司 The substep circulation lithographic method of 3D NAND gate polar curve slit grooves
CN107978605B (en) * 2017-11-16 2020-07-21 长江存储科技有限责任公司 Step-by-step circular etching method for slit groove of 3D NAND gate line

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Application publication date: 20170829