CN102097374B - Phase change random access memory and manufacturing method thereof - Google Patents
Phase change random access memory and manufacturing method thereof Download PDFInfo
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- CN102097374B CN102097374B CN 200910201197 CN200910201197A CN102097374B CN 102097374 B CN102097374 B CN 102097374B CN 200910201197 CN200910201197 CN 200910201197 CN 200910201197 A CN200910201197 A CN 200910201197A CN 102097374 B CN102097374 B CN 102097374B
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Abstract
The invention discloses a phase change random access memory and a manufacturing method thereof. The manufacturing method comprises the following steps of: sequentially forming an insulating middle layer on a semiconductor substrate, wherein a conductive plug passing through the thickness of the insulating middle layer is arranged in the insulating middle layer; forming an insulating dielectric layer on the insulating middle layer; etching the insulating dielectric layer, and forming a trench exposing out of partial width of the adjacent conductive plug; forming a side wall on the side wall of the trench, wherein the side wall is contacted with the conductive plug; fully filling an insulating layer in the trench; etching the side wall so that the surface of the side wall is finished to form a lower electrode; etching the insulating dielectric layer and the insulating layer above the lower electrode to form a shallow trench; fully filling a phase change layer in the shallow trench; and forming an upper electrode above the phase change layer, the partial insulating dielectric layer and the insulating layer. The contact area of the phase change layer and the lower electrode is reduced, the size of a phase change region electrode and the volume of a phase change region are equivalently reduced, the current density of the electrodes is increased, and the power consumption is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of phase-change random access memory and preparation method thereof.
Background technology
Phase-change random access memory has high reading speed, low-power, high power capacity, high-reliability, height and writes characteristics such as wiping number of times, low-work voltage/electric current and low cost, and be fit to very much be combined with CMOS technology, can be used as stand alone type or the Embedded memory of higher density.
At present, phase change random access memory devices comprises the memory node with phase change layer, the transistor that is connected to this memory node and the PN junction diode that connects with transistor.According to the voltage that is applied on it, phase change layer becomes noncrystalline attitude from crystalline state, or in contrast.If the voltage that applies is for arranging voltage, phase change layer becomes crystalline state from noncrystalline attitude.If the voltage that applies is reset voltage, phase change layer is transformed into noncrystalline attitude from crystalline state.
The phase-change random access memory that forms in Chinese patent application 200810008555 is doped with the ion with Semiconductor substrate 10 conductivity type opposite as shown in Figure 1 in source electrode 12 and the drain electrode 14; Grid structure 20 be formed at source electrode 12 and the Semiconductor substrate 10 between 14 of draining on, grid structure 20 can comprise gate insulation layer 18 and gate electrode 19, gate insulation layer 18 and gate electrode 19 can sequence stack on Semiconductor substrate 10; Zone in the Semiconductor substrate 10 under the grid structure 20 can be channel region 16.Source electrode 12 and drain electrode 14, but grid structure 20 and channel region 16 transistor formeds or switching device.First insulating intermediate layer 22 can be formed on the Semiconductor substrate 10, first insulating intermediate layer, 22 covering transistors; The first contact hole h1 is formed in first insulating intermediate layer 22 to expose at least a portion of drain electrode 14; The first contact hole h1 can be filled with conductive materials, forms conductive plunger 24.Bottom electrode 30 is formed on first insulating intermediate layer 22, and covers the top surface of conductive plug 24.
Continuation is formed on first insulating intermediate layer 22 with reference to figure 1, the second insulating intermediate layer 32 and covers bottom electrode 30; The second contact hole h2 is formed in second insulating intermediate layer 32, and the second contact hole h2 exposes at least a portion of bottom electrode 30; Be filled with bottom electrode contact layer 34 in the second contact hole h2, as the bottom electrode conductive plunger.Seed layer 36 is formed on second insulating intermediate layer 32 and covers the top surface of bottom electrode contact layer 34, and phase change layer 38 is formed on the seed layer 36.The insulating barrier 40 that seed layer 36 and phase change layer 38 are formed on second insulating intermediate layer 32 centers on.Top electrode 42 is formed on insulating barrier 40 and covers the top surface of phase change layer 38.
Along with improving constantly of semiconductor device integrated level, the electrode size that has the phase-change random access memory of method making for employing now reduces further and obtains better phase variable that higher requirement has also been arranged.But, because the limitation of photoetching technique causes reducing the electrode critical dimension of phase-change random access memory and the size experience bottleneck of contact hole.
Summary of the invention
The problem that the present invention solves provides a kind of phase-change random access memory and preparation method thereof, prevents that the electrode critical dimension of phase-change random access memory and the size of contact hole from can't reduce with the raising of integrated level.
For addressing the above problem, the invention provides a kind of manufacture method of phase-change random access memory, comprising: on Semiconductor substrate, be formed with insulating intermediate layer successively, have the conductive plunger that runs through its thickness in the described insulating intermediate layer; Form insulating medium layer at insulating intermediate layer; The etching insulating medium layer forms the groove that exposes adjacent conductive plug section width; Form side wall at trenched side-wall, described side wall contacts with conductive plunger; In groove, fill full insulating barrier; Side wall is carried out etching, make its surfacing, form bottom electrode; Insulating medium layer and the insulating barrier of etching bottom electrode top form shallow channel; In shallow channel, fill full phase change layer; Form top electrode at phase change layer, SI semi-insulation dielectric layer and insulating barrier.
Optionally, described formation side wall comprises: on insulating medium layer and trench wall form side wall layer; With eat-backing method etching side wall layer, remove on the insulating medium layer and the side wall layer of channel bottom.
Optionally, the material of described side wall layer is titanium nitride.
Optionally, the method for described etching side wall formation bottom electrode is the selectivity wet etching.
Optionally, the lithographic method of described formation shallow channel is chemical drying method etching or wet etching.
Optionally, the cross section of described shallow channel is bowl-shape, contacts with bottom electrode point.
Optionally, the method for described formation phase change layer is sputtering method or chemical vapour deposition technique.The material of described phase change layer is the GeSbTe chalcogenide material.
The present invention also provides a kind of phase-change random access memory, comprising: Semiconductor substrate; Be positioned at the insulating intermediate layer on the Semiconductor substrate; The conductive plunger that runs through insulating intermediate layer thickness; Be positioned on the insulating intermediate layer and cover the insulating medium layer of conductive plunger, have the groove that exposes adjacent conductive plug section width in the described insulating medium layer; Fill the insulating barrier of full groove; Bottom electrode between insulating medium layer and insulating barrier, described bottom electrode contacts with conductive plunger; Phase change layer above bottom electrode between insulating medium layer and the insulating barrier; Be positioned at the top electrode on phase change layer, SI semi-insulation dielectric layer and the insulating barrier.
Optionally, the cross section of described phase change layer is bowl-shape, contacts with bottom electrode point.
Compared with prior art, the present invention has the following advantages: form the groove that exposes adjacent conductive plug section width in insulating medium layer; Form side wall as bottom electrode at trenched side-wall, reduced the contact area of bottom electrode and conductive plunger; Simultaneously, form phase change layer in the insulating medium layer of bottom electrode top and the insulating barrier, because the area of bottom electrode reduces, also reduced simultaneously the contact area of phase change layer and bottom electrode, be equivalent to the size that reduced the phase change zone electrode and the volume of phase change zone, increase the current density of electrode, reduced power consumption.
In addition, the cross section of phase change layer is made bowl-shape, make it to contact with bottom electrode point, further reduced the contact area of phase change layer and bottom electrode, be equivalent to the size that reduced the phase change zone electrode and the volume of phase change zone, increased the current density of electrode, reduced power consumption.
Description of drawings
Fig. 1 is the schematic diagram of the phase-change random access memory of prior art formation;
Fig. 2 is the embodiment flow chart that the present invention forms phase-change random access memory;
Fig. 3 to Figure 10 is the schematic diagram that the present invention forms phase-change random access memory.
Embodiment
Fig. 2 is the embodiment flow chart that the present invention forms phase-change random access memory.As shown in Figure 2, execution in step S11 is formed with insulating intermediate layer successively on Semiconductor substrate, have the conductive plunger that runs through its thickness in the described insulating intermediate layer; Execution in step S12 forms insulating medium layer at insulating intermediate layer; Execution in step S13, the etching insulating medium layer forms the groove that exposes adjacent conductive plug section width; Execution in step S14 forms side wall at trenched side-wall, and described side wall contacts with conductive plunger; Execution in step S15 fills full insulating barrier in groove; Execution in step S16 carries out etching to side wall, makes its surfacing, forms bottom electrode; Execution in step S17, insulating medium layer and the insulating barrier of etching bottom electrode top form shallow channel; Execution in step S18 fills full phase change layer in shallow channel; Execution in step S19 forms top electrode at phase change layer, SI semi-insulation dielectric layer and insulating barrier.
Phase-change random access memory based on above-described embodiment forms comprises: Semiconductor substrate; Be positioned at the insulating intermediate layer on the Semiconductor substrate; The conductive plunger that runs through insulating intermediate layer thickness; Be positioned on the insulating intermediate layer and cover the insulating medium layer of conductive plunger, have the groove that exposes adjacent conductive plug section width in the described insulating medium layer; Fill the insulating barrier of full groove; Bottom electrode between insulating medium layer and insulating barrier, described bottom electrode contacts with conductive plunger; Phase change layer above bottom electrode between insulating medium layer and the insulating barrier; Be positioned at the top electrode on phase change layer, SI semi-insulation dielectric layer and the insulating barrier.
Be described in detail below in conjunction with structure and the formation method of accompanying drawing to phase-change random access memory of the present invention.
As shown in Figure 3, provide Semiconductor substrate 100; Form transistor in Semiconductor substrate 100, described transistor comprises: be positioned at gate insulation layer 104 and gate electrode 106 on the Semiconductor substrate 100; Be positioned at source electrode 101 and the drain electrode 102 of gate electrode 106 semiconductor substrates on two sides 100, ion and Semiconductor substrate 100 conductivity type opposite injected in described source electrode 101 and the drain electrode 102.Form first insulating intermediate layer 108 with chemical vapour deposition technique in Semiconductor substrate 100, the material of described first insulating intermediate layer 108 is silica or silicon oxynitride or tetraethoxysilane etc.
Continuation forms the conductive plunger 110 with drain electrode 102 conductings with reference to figure 3 in first insulating intermediate layer 108.Concrete formation technology is as follows: spin coating photoresist layer (not shown) on first insulating intermediate layer 108, and behind overexposure, developing process, the corresponding contact hole graph in 102 positions forms and drains; Be mask with the photoresist layer, to exposing drain electrode 102, form contact hole along contact hole graph etching first insulating intermediate layer 108; After removing photoresist layer, form conductive material layer at first insulating intermediate layer 108, and electric conducting material is filled full contact hole; The process CMP (Chemical Mechanical Polishing) process is planarized to be exposed at first insulating intermediate layer 108.
With reference to figure 3, form the metal wiring layer 112 of memory at first insulating intermediate layer 108 again.Concrete implementing process is as follows: form the first metal layer with sputtering method or chemical vapour deposition technique at first insulating intermediate layer 108; Then form the photoresist layer (not shown) with spin-coating method at the first metal layer, through after the photoetching process, define metal wiring pattern; Be mask with the photoresist layer, along electrode pattern etching the first metal layer, form metal wiring layer 112; Then, remove photoresist layer.
As shown in Figure 4, form second insulating intermediate layer 113 with Low Pressure Chemical Vapor Deposition or plasma enhanced chemical vapor deposition method at first insulating intermediate layer 108 and metal wiring layer 112, the material of described second insulating intermediate layer 113 is silica or silicon oxynitride or tetraethoxysilane etc.Spin coating photoresist layer (not shown) on second insulating intermediate layer 113 behind overexposure, developing process, forms the bottom electrode contact hole graph corresponding with metal wiring layer 112 positions; Be mask with the photoresist layer, to exposing metal wiring layer 112, form contact hole along bottom electrode contact hole graph etching second insulating intermediate layer 113; Form conductive material layer at second insulating intermediate layer 113, and electric conducting material is filled full bottom electrode contact hole, described conductive material layer can be tungsten; The process CMP (Chemical Mechanical Polishing) process is planarized to exposes second insulating intermediate layer 113, forms conductive plunger 114.
Present embodiment can also be the diffusion impervious layer of material forming with the titanium nitride at bottom electrode contact hole inwall before bottom electrode contact hole filled conductive material, prevents that the electric conducting material of follow-up filling from diffusing to insulating intermediate layer.
As shown in Figure 5; form etching barrier layer 116 with chemical vapour deposition technique at second insulating intermediate layer 113; and etching barrier layer 116 covers conductive plunger 114; the thickness of described etching barrier layer is 100 dusts～1000 dusts; material is silicon nitride, and it act as in the subsequent etching process rete of protection below it and is not destroyed.Form insulating medium layer 118 with chemical vapour deposition technique at etching barrier layer 116, the material of described insulating medium layer 118 is silica, and thickness is 1000 dusts～10000 dusts.
Continuation forms the subregion of exposing adjacent two conductive plungers 114 with reference to figure 5 in insulating medium layer 118 and etching barrier layer 116, and the groove of second insulating intermediate layer 113 between adjacent two conductive plungers 114.Concrete formation technology is as follows: spin coating photoresist layer on insulating medium layer 118 after exposure imaging technology, forms groove figure; Be mask with the photoresist layer, along groove figure etching insulating medium layer 118 and etching barrier layer 116 to the subregion of exposing adjacent two conductive plungers 114, and second insulating intermediate layer 113 between adjacent two conductive plungers 114.
As shown in Figure 6, form side wall 120 at trenched side-wall, the material of described side wall 120 is titanium nitride, and described side wall 120 contacts conducting with conductive plunger 114.The technology of concrete formation side wall 120 is as described below: form side wall layer with trench wall with chemical vapour deposition technique on insulating medium layer 118, the thickness of described side wall layer is 5 dusts～500 dusts; Employing is eat-back method side wall layer is carried out etching, removes the side wall layer on channel bottom and the insulating medium layer 118, keeps the side wall layer of trenched side-wall.
As shown in Figure 7, fill full insulating barrier 122 in groove, the material of described insulating barrier 122 is silica or silicon nitride or other insulating material, is used for the isolation between the side wall 120.Concrete technological process is as follows: form insulating barrier 122 with chemical vapour deposition technique at insulating medium layer 118, and insulating barrier 122 is filled the groove of 120 of full side walls; With chemical mechanical polishing method insulating barrier 122 is planarized to and exposes insulating medium layer 118.
Continuation is carried out the selectivity wet etching with reference to figure 7 to side wall, makes the side wall surfacing, forms bottom electrode 120a.The solution that adopts at insulating medium layer 118 described wet etchings is the metal etch nitration mixture, and concentration is 5%～50%.Through behind the wet etching, between insulating medium layer 118 above the bottom electrode 120a and insulating barrier 122, present the gap.
In the present embodiment, in insulating medium layer 118, form the groove that exposes adjacent conductive connector 114 partial widths; Form side wall as bottom electrode 120a at trenched side-wall, reduced the contact area of bottom electrode 120a and conductive plunger 114, increased the current density of electrode, reduced power consumption.
As shown in Figure 8, along the gap between bottom electrode 120a top insulating medium layer 118 and the insulating barrier 122 insulating medium layer 118 and insulating barrier 122 are carried out etching, above bottom electrode 120a, form shallow channel 124; Because the effect of etching agent, it can be arbitrary shape that the cross section of shallow channel forms, and wherein the optimum shape in the cross section of shallow channel 124 is " bowl-shape ", the contact-making surface minimum of itself and bottom electrode 120a.
In the present embodiment, described lithographic method is chemical drying method etching (CDE) or wet etching.If adopt chemical drying method etching (CDE) method, the gas of employing is CF
4With the O2 mist, flow-rate ratio is 3: 1; If adopt the wet etching method, the solution of employing is diluted hydrofluoric acid, and concentration is 1%～10%.
In the present embodiment, make the cross section of shallow channel 124 bowl-shape, follow-up filling phase change layer is wherein contacted with bottom electrode 120a point, further reduced the contact area of phase change layer and bottom electrode 120a, be equivalent to the size that reduced the phase change zone electrode and the volume of phase change zone, increase the current density of electrode, reduced power consumption.
With reference to figure 9, form phase change layer 125 with physical vaporous deposition (for example sputter) at insulating medium layer 118 and insulating barrier 122, and phase change layer 125 is filled full shallow channel; Then, adopt chemical mechanical polishing method or etching method planarization phase change layer 125, remove the phase change layer 125 on insulating medium layer 118 and the insulating barrier 122, keep the phase change layer 125 in the shallow channel, make phase change layer 125 by bottom electrode 120a and conductive plunger 114 conductings; The material of phase change layer 125 is GeSbTe (GST) chalcogenide material, for example is: germanium-antimony-tellurium (Ge-Sb-Te), nitrogen-germanium-antimony-tellurium (N-Ge-Sb-Te), arsenic-antimony-tellurium (As-Sb-Te), indium-antimony-tellurium (In-Sb-Te) etc.
With reference to Figure 10, form metal level with sputtering method or chemical vapour deposition technique at insulating medium layer 118 and insulating barrier 122 and phase change layer 125; Then, to exposing insulating barrier 118 and insulating barrier 122, form top electrode 126 with dry etching method etching sheet metal.Concrete technological process is: after forming metal level, forming with the silicon nitride at metal level is the barrier layer of material; Following spin coating photoresist layer on etching stop layer again, after exposure imaging technology, define the top electrode figure at photoresist layer, is mask with the photoresist layer, along top electrode pattern etching barrier layer and metal level then; Then, remove photoresist layer, the metal level after the described etching is top electrode 126.
Wherein top electrode 126, phase change layer 125 and bottom electrode 120a constitute phase-change random access memory.
Among other embodiment, can behind the conductive plunger 110 of formation and drain electrode 102 conductings, can be formed directly in top electrode 126, phase change layer 125 and the bottom electrode 120a of phase-change random access memory.Perhaps after forming multi-layer metal wiring, insulating intermediate layer and conductive plunger, form the phase-change random access memory that is constituted by top electrode 126, phase change layer 125 and bottom electrode 120a again.
Formed phase-change random access memory, also need carry out follow-up connecting line technics: between the barrier layer after top electrode 126 and the etching, filled insulating barrier, and carry out CMP (Chemical Mechanical Polishing) process and make the insulating barrier planarization; Form etching stop layer and interlayer dielectric layer on insulating barrier, barrier layer; Form the through hole that runs through this threeply degree in interlayer dielectric layer, etching stop layer and barrier layer, described through hole exposes top electrode 126; Form conductive material layer at interlayer dielectric layer, and electric conducting material is filled full through hole, described conductive material layer can be tungsten; The process CMP (Chemical Mechanical Polishing) process is planarized to exposes interlayer dielectric layer, forms conductive plunger, described conductive plunger and top electrode 126 conductings; Form metal wiring layer on interlayer dielectric layer, each metal wiring layer covers corresponding conductive plunger, and is connected with phase-change random access memory by conductive plunger.
The phase-change random access memory that forms based on above-described embodiment comprises: Semiconductor substrate 100, be formed with transistor on the described Semiconductor substrate 100, and wherein transistor comprises: be positioned at gate insulation layer 104 and gate electrode 106 on the Semiconductor substrate 100; Be positioned at source electrode 101 and the drain electrode 102 of gate electrode 106 semiconductor substrates on two sides 100, ion and Semiconductor substrate 10 conductivity type opposite injected in described source electrode 101 and the drain electrode 102.
First insulating intermediate layer 108 is positioned on the Semiconductor substrate 100; Conductive plunger 110, run through first insulating intermediate layer 108 and with the drain electrode 102 conductings; Metal wiring layer 112 is positioned on conductive plunger 110 and part first insulating intermediate layer 108; Second insulating intermediate layer 113 is positioned on first insulating intermediate layer 108 and covering metal wiring layer 112; Conductive plunger 114 runs through second insulating intermediate layer 113 and contacts conducting with metal wiring layer 112; Etching barrier layer 116 is positioned on second insulating intermediate layer 113, and covers conductive plunger 114; Insulating medium layer 118 is positioned on the etching barrier layer 116; Insulating barrier 122 is positioned on the etching barrier layer 116, with insulating medium layer 118 consistency of thickness; Bottom electrode 120a between insulating medium layer 118 and insulating barrier 122, contacts with the part of conductive plunger 114, and its critical dimension is less than the critical dimension of conductive plunger; Phase change layer 125, on the bottom electrode 120a between insulating medium layer 118 and the insulating barrier 122, and phase change layer 125 forms and is preferably " bowl-shape ", contacts with bottom electrode 120a point; Top electrode 126 is positioned on phase change layer 125 and partial insulative layer 122 and the insulating medium layer 118.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. the manufacture method of a phase-change random access memory is characterized in that, comprising:
On Semiconductor substrate, be formed with insulating intermediate layer successively, have the conductive plunger that runs through its thickness in the described insulating intermediate layer;
Form insulating medium layer at insulating intermediate layer;
The etching insulating medium layer forms the groove that exposes adjacent conductive plug section width;
Form side wall at trenched side-wall, described side wall contacts with conductive plunger;
In groove, fill full insulating barrier;
Side wall is carried out etching, make its surfacing, form bottom electrode;
Insulating medium layer and the insulating barrier of etching bottom electrode top form shallow channel, and the cross section of described shallow channel is bowl-shape, contacts with bottom electrode point;
In shallow channel, fill full phase change layer;
Form top electrode at phase change layer, SI semi-insulation dielectric layer and insulating barrier.
2. according to the manufacture method of the described phase-change random access memory of claim 1, it is characterized in that described formation side wall comprises:
On insulating medium layer, form side wall layer with trench wall;
With eat-backing method etching side wall layer, remove on the insulating medium layer and the side wall layer of channel bottom.
3. according to the manufacture method of the described phase-change random access memory of claim 2, it is characterized in that the material of described side wall layer is titanium nitride.
4. according to the manufacture method of the described phase-change random access memory of claim 1, it is characterized in that the method that described etching side wall forms bottom electrode is the selectivity wet etching.
5. according to the manufacture method of the described phase-change random access memory of claim 1, it is characterized in that the lithographic method of described formation shallow channel is chemical drying method etching or wet etching.
6. according to the manufacture method of the described phase-change random access memory of claim 1, it is characterized in that the method for described formation phase change layer is sputtering method or chemical vapour deposition technique.
7. according to the manufacture method of the described phase-change random access memory of claim 6, it is characterized in that the material of described phase change layer is the GeSbTe chalcogenide material.
8. a phase-change random access memory comprises: Semiconductor substrate; Be positioned at the insulating intermediate layer on the Semiconductor substrate; The conductive plunger that runs through insulating intermediate layer thickness; Be positioned on the insulating intermediate layer and cover the insulating medium layer of conductive plunger, have the groove that exposes adjacent conductive plug section width in the described insulating medium layer; Fill the insulating barrier of full groove; Bottom electrode between insulating medium layer and insulating barrier, described bottom electrode contacts with conductive plunger; Phase change layer above bottom electrode between insulating medium layer and the insulating barrier, the cross section of described phase change layer are bowl-shape, contact with bottom electrode point; Be positioned at the top electrode on phase change layer, SI semi-insulation dielectric layer and the insulating barrier.
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| CN104465986B (en) * | 2013-09-17 | 2017-12-05 | 华邦电子股份有限公司 | Resistance-type memory and its manufacture method |
| CN104617217B (en) * | 2013-11-01 | 2018-01-26 | 华邦电子股份有限公司 | Resistance-type nonvolatile memory device and preparation method thereof |
| CN110546778A (en) * | 2018-03-16 | 2019-12-06 | 深圳市汇顶科技股份有限公司 | Memristor manufacturing method, memristor and resistive random access memory RRAM |
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| CN1901217A (en) * | 2006-07-20 | 2007-01-24 | 复旦大学 | Novel channel structure phase change storage |
| CN101232036A (en) * | 2007-01-23 | 2008-07-30 | 三星电子株式会社 | Phase change memory and manufacturing method thereofs |
| CN101364633A (en) * | 2007-08-10 | 2009-02-11 | 财团法人工业技术研究院 | Phase changing memory element and manufacturing method therefor |
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| CN1901217A (en) * | 2006-07-20 | 2007-01-24 | 复旦大学 | Novel channel structure phase change storage |
| CN101232036A (en) * | 2007-01-23 | 2008-07-30 | 三星电子株式会社 | Phase change memory and manufacturing method thereofs |
| CN101364633A (en) * | 2007-08-10 | 2009-02-11 | 财团法人工业技术研究院 | Phase changing memory element and manufacturing method therefor |
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