CN110546778A - Memristor manufacturing method, memristor and resistive random access memory RRAM - Google Patents
Memristor manufacturing method, memristor and resistive random access memory RRAM Download PDFInfo
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Abstract
The embodiment of the application provides a manufacturing method of a memristor, the memristor and a resistive random access memory RRAM, and the manufacturing method of the memristor comprises the following steps: depositing a lower electrode of the memristor; preparing a resistance layer of the memristor on a section along the deposition direction of a lower electrode of the memristor; and preparing an upper electrode of the memristor on a resistance layer of the memristor.
Description
The embodiment of the application relates to the field of memory manufacturing, and in particular relates to a manufacturing method of a memristor, the memristor and a resistive random access memory RRAM.
A Resistive Random Access Memory (RRAM) is a Non-volatile Memory that stores information by using a variable resistance characteristic of a material, and has the advantages of low power consumption, high density, high read/write speed, good durability, and the like.
The RRAM is characterized in that a basic storage unit is a memristor, the memristor mainly comprises a lower electrode, a resistance layer and an upper electrode, and the working principle of the memristor is as follows: when a positive voltage is applied between the two electrodes, a conductive Filament (Filament) is formed in the resistance layer and presents a low resistance state; when a reverse current (RESET current) is generated between the two electrodes, the conductive filament in the resistive layer will break to assume a high resistance state, and this variable resistance characteristic effectively achieves the switching of RRAM '0' and '1'.
The magnitude of the peak of the generated reverse current is related to the area of the bottom electrode of the memristor, and generally speaking, the smaller the bottom electrode area, the lower the power consumption of the memory. The area of the lower electrode is generally determined by the minimum size allowed by the process platform, because the minimum size of the existing process platform is limited, the electrode area of the memristor cannot be made smaller, and in order to prepare the memristor with the smaller electrode area, the higher process platform can be used only to increase the process cost, so that a manufacturing method of the memristor is needed, and the memristor with the smaller electrode area can be manufactured on the basis of not increasing the process cost.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of a memristor, the memristor and a resistive random access memory RRAM, and the memristor with a smaller electrode area can be manufactured on the basis of not increasing the process cost.
In a first aspect, a method of fabricating a memristor is provided, including:
depositing a lower electrode of the memristor;
preparing a resistance layer of the memristor on a section along the deposition direction of a lower electrode of the memristor;
and preparing an upper electrode of the memristor on a resistance layer of the memristor.
In one possible implementation, the method further includes:
preparing a first conductive path electrically connected with a lower electrode of the memristor; and
preparing a second conductive path electrically connected to an upper electrode of the memristor.
In one possible implementation, the depositing the lower electrode of the memristor includes:
preparing a first conductive path on the upper surface of a Complementary Metal Oxide Semiconductor (CMOS) substrate;
depositing a first dielectric layer on the upper surface of the CMOS substrate, the first dielectric layer encapsulating the first conductive via;
etching the upper surface of the first dielectric layer to form a through hole reaching the first conductive path;
filling a conductive material in the through hole, wherein the conductive material is used for electrically connecting a lower electrode of the memristor and the first conductive path;
depositing a lower electrode of the memristor over the via.
In one possible implementation, the preparing the resistive layer of the memristor at a section along a deposition direction of a lower electrode of the memristor includes:
depositing a second dielectric layer on the upper surface of the first dielectric layer, wherein the second dielectric layer covers the lower electrode of the memristor;
manufacturing a blind hole in the upper surface of the second dielectric layer along the deposition direction of the lower electrode of the memristor to obtain the section of the lower electrode of the memristor, wherein the bottom of the blind hole is abutted to the first dielectric layer;
depositing a resistive layer of the memristor on an upper surface of the second dielectric layer and an inner surface of the blind via.
In one possible implementation, the preparing the upper electrode of the memristor on the resistive layer of the memristor includes:
depositing an upper electrode material of the memristor on the surface of the resistance layer of the memristor, so that the upper electrode material is injected into the blind hole.
In one possible implementation, the method further includes:
preparing a third dielectric layer on the upper surface of the second dielectric layer and the upper surface of the upper electrode of the memristor;
etching the third dielectric layer to form a groove reaching the upper electrode of the memristor;
preparing a second conductive path on the inner surface of the trench, wherein the second conductive path is electrically connected with the upper electrode of the memristor.
In one possible implementation, the depositing the lower electrode of the memristor includes:
preparing a first dielectric layer on the upper surface of the CMOS substrate;
depositing a second dielectric layer on the upper surface of the first dielectric layer;
depositing a lower electrode of the memristor on the second dielectric layer, the lower electrode of the memristor wrapping an upper surface and a side surface of the second dielectric layer;
depositing a third dielectric layer on a lower electrode of the memristor;
thinning the third dielectric layer to expose the cross section of the lower electrode of the memristor on the side surface of the second dielectric layer.
In one possible implementation, the preparing the resistive layer of the memristor at a section along a deposition direction of a lower electrode of the memristor includes:
depositing a resistive layer of the memristor over the cross-section of a lower electrode of the memristor.
In one possible implementation, the preparing the upper electrode of the memristor on the resistive layer of the memristor includes:
and depositing an upper electrode of the memristor on the upper surface of the resistance layer of the memristor.
In one possible implementation, the method further includes:
depositing a fourth dielectric layer on an upper surface of an upper electrode of the memristor;
etching the fourth dielectric layer to form a first through hole reaching the lower electrode of the memristor;
filling a conductive material in the first through hole;
preparing a first conductive path above the first via;
depositing a fifth dielectric layer on an upper surface of the fourth dielectric layer, the fifth dielectric layer encapsulating the first conductive via;
etching the fifth dielectric layer to form a second through hole reaching the upper electrode of the memristor;
filling a conductive material in the second through hole;
a second conductive via is prepared over the second via.
In one possible implementation, a ratio of an etch rate of the second dielectric layer to an etch rate of the first dielectric layer is greater than a particular threshold.
In a second aspect, a memristor manufactured according to the first aspect and a manufacturing method of the memristor in any possible implementation manner of the first aspect is provided.
In a third aspect, a memristor is provided, including an upper electrode, a resistive layer, and a lower electrode;
wherein a cross section along a deposition direction of the lower electrode is in contact with the resistive layer surface, and the resistive layer is in contact with the upper electrode surface.
In a possible implementation manner, the lower electrode is electrically connected to a first conductive path, and the upper electrode is electrically connected to a second conductive path, where the first conductive path is used to electrically connect the lower electrode to the outside, and the second conductive path is used to electrically connect the upper electrode to the outside.
In a fourth aspect, there is provided a resistive random access memory RRAM, including:
the memristor is prepared according to the first aspect and the manufacturing method of the memristor in any possible implementation manner of the first aspect.
In a fifth aspect, there is provided a resistive random access memory RRAM, including:
the memristor in any one of the possible implementations of the third aspect and the fourth aspect.
FIG. 1 is a schematic diagram of a typical structure of a memristor.
FIG. 2 is a schematic diagram of a three-dimensional structure of a memristor.
FIG. 3 is a schematic flow chart diagram of a method of fabricating a memristor in accordance with an embodiment of the present application.
FIG. 4 is a schematic diagram of preparing a first conductive path according to an embodiment of the present application.
FIG. 5 is a schematic diagram of preparing a via according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a lower electrode of a fabricated memristor according to an embodiment of the present application.
FIG. 7 is a schematic illustration of the preparation of blind vias according to an embodiment of the present application.
Fig. 8 is a schematic diagram of preparing a resistive layer according to an embodiment of the present application.
FIG. 9 is a schematic illustration of preparing an upper electrode according to an embodiment of the present application.
FIG. 10 is a schematic diagram of preparing a second conductive path according to an embodiment of the present application.
Fig. 11 is a schematic illustration of preparing a dielectric layer according to another embodiment of the present application.
FIG. 12 is a schematic view of forming a support structure according to another embodiment of the present application.
FIG. 13 is a schematic illustration of preparing a lower electrode according to another embodiment of the present application.
Fig. 14 is a schematic illustration of preparing a dielectric layer according to another embodiment of the present application.
FIG. 15 is a schematic diagram of forming a cross-section of a lower electrode according to another embodiment of the present application.
Fig. 16 is a schematic diagram of forming a prepared resistive layer and an upper electrode according to another embodiment of the present application.
Fig. 17 is a schematic illustration of preparing a dielectric layer according to another embodiment of the present application.
Fig. 18 is a schematic illustration of preparing a first conductive via according to another embodiment of the present application.
FIG. 19 is a schematic illustration of preparing a second conductive path according to another embodiment of the present application.
FIG. 20 is a structural schematic of a memristor according to an embodiment of the present application.
Fig. 21 is a schematic structural diagram of a RRAM according to an embodiment of the present application.
The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application.
Fig. 1 is a cross-sectional view of a typical structure of a memristor, and as shown in fig. 1, the memristor may include a lower electrode 106, a resistive layer 108, and an upper electrode 110, the lower electrode 106 may be connected with a first conductive via 103, and the upper electrode 110 is connected with a second conductive via 111, so that the memristor 11 and the memristor 12 may form a crossbar structure through the first conductive via 103 and the second conductive via 111, and as shown in fig. 2, the memristor may be addressed through the crossbar structure.
Hereinafter, a method for manufacturing a memristor according to an embodiment of the present application is described in detail with reference to fig. 3 to 12.
FIG. 3 is a schematic flow chart diagram of a method 400 of fabricating a memristor in accordance with an embodiment of the present application,
it should be understood that fig. 3 shows the main steps or operations of the manufacturing method of the microlens of the embodiment of the present application, but these steps or operations are merely examples, and the embodiment of the present application may also perform other operations or variations of the various operations of fig. 3. Moreover, the various steps in method 400 may also be performed in a different order than described in the method embodiments, and not all of the operations in the method embodiments may be performed.
As shown in fig. 3, the method 400 may include:
s410, depositing a lower electrode of the memristor;
specifically, the lower electrode material of the memristor may be deposited by using a Deposition process, which may be, alternatively, a Physical Vapor Deposition (PVD) Atomic Layer Deposition (ALD) process, a Metal-organic Chemical Vapor Deposition (MOCVD) process, or other Deposition processes, and this is not limited in this embodiment of the application. Optionally, the deposited lower electrode material may be further processed, for example, the deposited lower electrode material may be processed by using a photolithography process and an etching process, so as to obtain a desired profile of the lower electrode.
Optionally, in this application embodiment, the lower electrode material of the memristor may be a material with stronger reactivity, for example, the lower electrode material may be at least one of the following materials: titanium (Ti), copper (Cu), tungsten (W), hafnium (Hf), and chromium (Cr), or other reactive materials may be used, which is not limited in the embodiments of the present application.
Further, in S420, preparing a resistive layer of the memristor at a cross section along a deposition direction of a lower electrode of the memristor;
that is to say, in the embodiment of the present application, the resistive layer of the memristor may be prepared along the cross section of the lower electrode of the memristor in the deposition direction, so that the effective region where the lower electrode of the memristor is in contact with the resistive layer of the memristor is the cross section along the deposition direction of the lower electrode of the memristor, since the thickness of the cross section is determined by the deposition process and is not limited by the minimum size of the process platform, the purpose of reducing the area of the lower electrode of the memristor may be achieved only by controlling the thickness of the lower electrode of the memristor through the deposition process, and therefore, the electrode area of the memristor prepared according to the manufacturing method of the memristor of the embodiment of the present application is not limited by the minimum size of the process platform, and the memristor with a smaller electrode area may be manufactured on the basis of not increasing the process cost, so that the power consumption of the memory may be.
Assuming that the lower electrode of the memristor is prepared on the first surface, the lower electrode of the memristor gradually becomes thicker on the first surface in the process of depositing the lower electrode material, where the direction in which the lower electrode material gradually becomes thicker (i.e., the direction of the thickness of the lower electrode of the memristor) may be understood as the deposition direction of the lower electrode of the memristor, in other words, the growth direction or the accumulation direction of the lower electrode material may be understood as the deposition direction of the lower electrode of the memristor.
It should be noted that, in the embodiment of the present application, the cross section of the contact between the resistive layer of the memristor and the lower electrode of the memristor may be parallel to the deposition direction of the lower electrode of the memristor, or approximately parallel to the deposition direction of the lower electrode of the memristor, for example, the cross section may have an angle with the deposition direction of the lower electrode, where the angle is smaller than a certain threshold value. For example, if the lower electrode of the memristor is deposited on the first surface, the deposition direction of the lower electrode of the memristor may be considered to be perpendicular to the first surface, and accordingly, the cross section along the deposition direction may also be considered to be perpendicular to the first surface, or approximately perpendicular to the first surface, which is not limited in the embodiments of the present application.
Optionally, in this embodiment of the present application, the material of the resistive layer of the memristor may be a transition metal oxide, and by way of example and not limitation, the material of the resistive layer may be at least one of the following materials: titanium oxide (TiO)x) Tantalum oxide (TaO)x) Niobium oxide (NbO)x) Zirconium oxide (ZrO)x) Zinc oxide (ZnO)x) Scandium oxide (ScO)x) YO (YO)x) Nickel oxide (NiO)x) Tungsten oxide (WO)x) Vanadium pentoxide (VO)x) Alternatively, the transition metal oxide may be another transition metal oxide, which is not limited in the examples of the present application.
Optionally, in this embodiment of the application, a deposition process (for example, PVD, ALD, MOCVD, or the like) may also be used to deposit the resistive layer material of the memristor on the cross section of the lower electrode of the memristor, and optionally, the deposited resistive layer material of the memristor may be further processed, for example, the deposited resistive layer material may be processed by a photolithography process and an etching process, so as to obtain a desired shape of the resistive layer of the memristor.
Further, in S430, an upper electrode of the memristor is prepared on a resistive layer of the memristor.
Specifically, a deposition process (e.g., PVD, ALD, MOCVD, or the like) may be used to deposit the upper electrode material of the memristor on the resistance layer, and optionally, the deposited upper electrode material of the memristor may be further processed, for example, the upper electrode material may be processed by a photolithography process and an etching process, so as to obtain a shape of the upper electrode of the memristor.
Alternatively, in the embodiment of the present application, the material of the upper electrode may be a simple noble metal having a work function of about 5eV, or may be a chemically stable metal compound. For example, if a metal element is selected, alternative metal element materials include, but are not limited to, palladium (Pd), iridium (Ir), gold (Au), nickel (Ni), ruthenium (Ru), or, if a metal compound is selected, alternative metal compounds include, but are not limited to, tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC).
Therefore, according to the manufacturing method of the memristor, the resistive layer of the memristor can be prepared on the cross section of the lower electrode of the memristor in the deposition direction, and further, the upper electrode of the memristor can be prepared on the resistive layer of the memristor, namely, the resistive layer of the memristor and the upper electrode of the memristor are sequentially prepared outwards by taking the cross section of the lower electrode of the memristor in the deposition direction as a reference, so that the purpose of controlling the area of the lower electrode of the memristor can be achieved by controlling the thickness of the deposited lower electrode of the memristor in the deposition direction, the thickness of the lower electrode of the memristor is determined by a deposition process and is not limited by the minimum size of a process platform, and therefore, the memristor with a smaller electrode area can be manufactured without increasing the process cost, and the effect of reducing the power consumption of the memory can be achieved.
Optionally, in some embodiments, the method 400 may further include:
preparing a first conductive path electrically connected with a lower electrode of the memristor; and
preparing a second conductive path electrically connected to an upper electrode of the memristor.
Specifically, the memristor can be connected to an external circuit, such as a transistor circuit, through the first conductive path and the second conductive path, so that operations of controlling reading, writing, erasing and the like of the memory can be realized. The lower electrode and the upper electrode of the memristor can form a crossbar structure through the first conductive path and the second conductive path respectively, and the crossbar structure can be used for addressing of the memristor.
Hereinafter, a method for manufacturing a memristor according to an embodiment of the present application will be described in detail with reference to the manufacturing steps shown in fig. 4 to 19.
It should be understood that fig. 4 to fig. 19 exemplify the fabrication of two memristors, and of course, a single memristor, or a plurality of memristors, or a memristor array, etc. may also be obtained according to the steps shown in fig. 4 to fig. 19, which is not limited in this application.
Here, the manufacturing steps shown in fig. 4 to 10 are described as example 1, and the manufacturing steps shown in fig. 11 to 19 are described as example 2. Embodiments 1 and 2 will be described below with reference to the drawings.
First, a method of manufacturing a memristor according to embodiment 1 is described with reference to fig. 4 to 10. The manufacturing method may include the following:
first, step 1a is performed to prepare a first conductive via 202 on an upper surface of a Complementary Metal Oxide Semiconductor (CMOS) substrate 20, as shown in fig. 4;
in the embodiment of the present application, a deposition process (e.g., PVD) may be used to deposit the material of the first conductive via 202 on the upper surface of the CMOS substrate 20, and optionally, the deposited material of the first conductive via 202 may be further processed, for example, the material of the first conductive via 202 may be processed by a photolithography process and an etching process to obtain a desired pattern of the first conductive via 202. For example, a photoresist may be first spun on the surface of the deposited material of the first conductive via 202, and then the photoresist is exposed and developed to obtain a desired pattern of the first conductive via 202, and then the material of the first conductive via 202 is etched to obtain a thickness (e.g., 250 nm) of the first conductive via 202.
Optionally, in this embodiment of the application, the material of the first conductive via 202 may be a conductive material, for example, aluminum, or copper, or may also be another conductive material, and if the material of the first conductive via 202 is copper, the first conductive via 202 may be prepared by a damascene process, which is not limited in this embodiment of the application.
It should be understood that in the embodiment of the present application, the first conductive via 202 and the CMOS substrate 20 may be connected by means of a conductive via, which connection relationship is not shown in fig. 4 to 19.
Thereafter, step 1b is performed to deposit a first dielectric layer 201 on the upper surface of the CMOS substrate 20, as shown in fig. 5;
optionally, the deposition process for depositing the first dielectric layer 201 is CVD, which is not described herein.
The deposited first dielectric layer 201 covers the first conductive via 202, that is, the first conductive via 202 is located in the first dielectric layer 201, and due to the existence of the first conductive via 202, the surface of the first dielectric layer 201 may be uneven, and further, the upper surface of the first dielectric layer 201 may be planarized, for example, a Chemical-Mechanical Planarization (CMP) process may be used to planarize the upper surface of the first dielectric layer 201, so that the thickness of the planarized first dielectric layer 201 is reduced, in one possible embodiment, the original thickness of the first dielectric layer 201 may be 1000 nm, and the thickness of the planarized first dielectric layer 201 may be 350 nm.
Optionally, the material of the first dielectric layer 201 may be an oxide of silicon, or a nitride of silicon, or may also be other compounds of silicon, which is not limited in this embodiment of the application.
Thereafter, step 1c is performed to process the upper surface of the first dielectric layer 201 to form a via 203 reaching the first conductive via 202, as shown in fig. 5.
Specifically, the upper surface of the first dielectric layer 201 may be processed by a photolithography process and an etching process to form a through hole 203 reaching the first conductive via 202, that is, the bottom of the through hole 203 reaches the first conductive via 202, or the bottom of the through hole 203 is connected to the first conductive via 202.
Further, step 1d is performed, and a conductive material is filled in the through hole 203, as shown in fig. 5.
Specifically, a conductive material may be deposited on the upper surface of the first dielectric layer 201, so that the conductive material is injected into the through hole 203, and then the conductive material on the other region of the upper surface of the first dielectric layer 201 except for the through hole 203 is removed, that is, only the conductive material at the position of the through hole 203 remains, and the conductive material in the through hole may be used to electrically connect the first conductive via and the lower electrode.
Thereafter, step 1e is performed, depositing the lower electrode 206 of the memristor on the upper surface of the first dielectric layer 201, as shown in fig. 6;
at this time, the electrical connection of the lower electrode 206 and the first conductive path 202 may be achieved through the through hole 203.
Optionally, the material of the lower electrode 206 may be the material exemplified in the foregoing embodiments, and is not described herein again.
In this embodiment, the deposition direction of the memristor lower electrode 206 may be the deposition direction 216 shown in fig. 6, and the deposition direction 216 may be considered to be perpendicular or approximately perpendicular to the upper surface of the first dielectric layer 201, and then a cross section along the deposition direction of the memristor lower electrode may also be perpendicular or approximately perpendicular to the upper surface of the first dielectric layer 201.
Further, step 1f is performed to deposit a second dielectric layer 205 on the upper surface of the first dielectric layer 201, as shown in fig. 6;
alternatively, the material of the second dielectric layer 205 may be an oxide of silicon, or a nitride of silicon, or may also be other compounds of silicon, which is not limited in this embodiment.
Optionally, the materials of the second dielectric layer 205 and the first dielectric layer 201 may be the same or different, and the embodiment of the present application is not limited thereto.
Optionally, after step 1f, a planarization process may be performed on the upper surface of the second dielectric layer 205, for example, the CMP process may be used to planarize the upper surface of the second dielectric layer 205, or a subsequent process may be performed directly without planarizing the second dielectric layer 205, which is not limited in this embodiment of the application.
Thereafter, step 1g is performed to prepare a blind via 207 in the deposition direction of the lower electrode 206 on the upper surface of the second dielectric layer 205, as shown in fig. 7.
In particular, in order to make the lower electrode 206 effectively contact with the subsequently prepared resistive layer, the blind via 207 may be controlled to penetrate a portion of the lower electrode material, and the bottom of the blind via 207 may be pressed against the first dielectric layer 201.
Here, the section 266 of the blind via 207 penetrating the lower electrode 206 can be considered as a section of the lower electrode 206 in the deposition direction, i.e., a section of the lower electrode 206 effectively contacting the resistive layer.
Optionally, the bottom of the blind via 207 may be located below the contact surface of the first dielectric layer 201 and the second dielectric layer 205, for example, the bottom of the blind via 207 may be located 10 to 50 nanometers below the upper surface of the first dielectric layer 201, and optionally, a Reactive Ion Etch (RIE) process may be used to control the etching depth of the blind via 207.
In a possible implementation manner, if the materials of the first dielectric layer 201 and the second dielectric layer 205 are the same, the etching time required by etching can be determined according to the etching depth of the blind hole 207 and the etching rate corresponding to the material of the dielectric layer, and the etching is stopped when the etching time required by etching is reached; alternatively, if the materials of the first dielectric layer 201 and the second dielectric layer 205 are different, in this case, the stop time of the etching can be controlled by the stop point detection system of the etching apparatus, that is, the etching can be stopped when the required etching depth is reached.
Thereafter, step 1h is performed to deposit a resistive layer 208 on the upper surface of the second dielectric layer 205, so that the material of the resistive layer is injected into the blind via 207, thereby achieving the contact of the resistive layer 208 and the cross section of the lower electrode 206 along the deposition direction, as shown in fig. 8.
Optionally, the deposition process and the material used for preparing the resistive layer may refer to the description in the foregoing embodiments, and are not repeated here.
Thereafter, step 1i is performed, and an upper electrode 210 of the memristor is deposited on the upper surface of the second dielectric layer 205, so that the material of the upper electrode is injected into the blind hole 207, and thus the contact between the resistance layer 208 and the upper electrode 210 is realized, as shown in fig. 9.
Alternatively, the deposition process and the material for preparing the top electrode can refer to the related descriptions in the foregoing embodiments, and the noble metal material can be further processed by a stripping process, which is known in the art and will not be described herein again.
Further, step 1j is performed to deposit a third dielectric layer 211 on the upper surface of the second dielectric layer 205 and the upper surface of the upper electrode 210, as shown in fig. 10.
Alternatively, in step 1j, the third dielectric layer 211 may be planarized, or a subsequent process may be performed without planarizing the third dielectric layer.
Thereafter, step 1k is performed, and the upper surface of the third dielectric layer 211 is etched, so that the trench 213 reaching the upper electrode of the memristor is obtained, that is, the bottom of the formed trench 213 is in contact with the upper electrode.
Further, step 1l may also be performed to prepare a second conductive via 212 on the inner surface of the trench 213 and the upper surface of the third dielectric layer 211.
Alternatively, the method and material for preparing the second conductive path 212 may refer to the method and material for preparing the first conductive path 202, which are not described herein.
To this end, the memristor unit 21 and the memristor unit 22 may be obtained, as shown in fig. 10, the memristor unit 21 and the memristor unit 22 are memristors with a lateral structure, and the memristor unit 21 and the memristor unit 22 may be connected to corresponding transistor circuits on the CMOS substrate 20 through the first conductive path 202 and the second conductive path 212, so that operations of controlling reading, writing, erasing and the like of the memory may be realized.
Hereinafter, a method of manufacturing the memristor according to embodiment 2 is described with reference to fig. 11 to 19. Unlike the fabrication method of the memristor according to embodiment 1, in which both the first conductive path and the second conductive path in embodiment 2 are finally prepared, the fabrication method may include the following:
first, step 2a is performed to deposit a first dielectric layer 301 on the upper surface of the CMOS substrate 30, as shown in fig. 11;
optionally, the deposition process used for depositing the first dielectric layer 301 may also be the deposition process described above, and is not described here again.
Optionally, the material of the first dielectric layer 301 may be an oxide of silicon, or a nitride of silicon, or may also be other compounds of silicon, which is not limited in this embodiment, and in one possible embodiment, the material of the first dielectric layer 301 may be a nitride of silicon, and the thickness may be 100 nanometers.
Next, step 2b is performed to deposit a second dielectric layer 302 on the upper surface of the first dielectric layer 301, as shown in fig. 11;
optionally, the deposition process used for depositing the second dielectric layer 302 may also be the deposition process described above, and is not described here again.
Optionally, the material of the second dielectric layer 302 may be an oxide of silicon, or a nitride of silicon, or may also be other compounds of silicon, which is not limited in this embodiment, and in one possible embodiment, the material of the second dielectric layer 302 may be an oxide of silicon, and the thickness may be 400 nm.
Further, the second dielectric layer 302 may also be processed by using a photolithography process and an etching process to form a support structure for the second dielectric layer 302, that is, a projection area of the second dielectric layer 302 on the upper surface of the first dielectric layer 301 is smaller than an area of the upper surface of the first dielectric layer 301, for example, a cross section of the support structure may be rectangular or trapezoidal, as shown in fig. 12.
In the embodiment of the present application, the ratio of the etching rate of the second dielectric layer 302 to the etching rate of the first dielectric layer 301 is greater than a specific threshold, for example, the specific threshold may be 3 or may also be 5, which is not limited in the embodiment of the present application. In this way, the first dielectric layer 301 may act as an etch stop for the second dielectric layer 302, thereby making the etching process for the second dielectric layer 302 more controllable.
Thereafter, step 2c is performed, depositing the lower electrode 303 of the memristor on the surfaces of the first dielectric layer 301 and the second dielectric layer 302, as shown in fig. 13.
At this time, the lower electrode material of the memristor covers the upper surface of the first dielectric layer 301, the upper surface of the second dielectric layer 302, and the side surfaces.
In this embodiment 2, reference may be made to the description related to the foregoing embodiment for implementation of depositing the lower electrode 303 of the memristor, and details are not described here.
Here, the deposition direction of the memristor lower electrode 303 may include the deposition direction 313 and the deposition direction 323 shown in fig. 13, where the deposition direction 313 is perpendicular or approximately perpendicular to the upper surface of the support structure formed by the second dielectric layer 302, and the deposition direction 323 is perpendicular or approximately perpendicular to the side surface of the support structure formed by the second dielectric layer 302.
Further, step 2d is performed, a third dielectric layer 304 is deposited on the surface of the lower electrode 303 of the memristor, as shown in fig. 14;
alternatively, the material of the third dielectric layer 304 may be an oxide of silicon, or a nitride of silicon, or may also be other compounds of silicon, which is not limited in this embodiment.
Optionally, the material of the third dielectric layer 304 may be the same as or different from the material of the second dielectric layer 302, which is not limited in this embodiment.
Optionally, to avoid damage to the bottom electrode material during deposition of the third dielectric layer 304, a tetraethyl siloxane (TEOS) thermal decomposition process may be used to reduce the plasma density and bombardment energy during deposition.
Further, step 2e may be performed to perform a planarization process and a thinning process on the upper surface of the third dielectric layer 304, so as to expose a cross section 333 of the lower electrode of the memristor located on the side surface of the second dielectric layer 302, where in this embodiment 2, the cross section 333 is a cross section along the deposition direction 323, and the cross section 333 is a surface in effective contact with the resistive layer, as shown in fig. 15.
Alternatively, in this embodiment 2, the third dielectric layer 304 may be planarized and thinned by using a CMP process, wherein the slurry used in the CMP process has the same or similar polishing rate for the material of the third dielectric layer and the material of the lower electrode, so as to facilitate the control of the CMP process.
Thereafter, step 2f is performed to deposit the resistive layer 305 of the memristor over the cross-section 333 of the memristor's lower electrode 303, as shown in fig. 16.
In this embodiment 2, reference may be made to the relevant description of the foregoing embodiments for the deposition process used for depositing the resistive layer 305 and the resistive layer material used for the resistive layer 305, which are not described herein again.
Thereafter, step 2g is performed to deposit the upper electrode 307 of the memristor on the upper surface of the resistor 305 of the memristor, as shown in fig. 16.
In embodiment 2, reference may be made to the relevant description of the foregoing embodiments for the deposition process used for depositing the upper electrode 307 and the upper electrode material used for the upper electrode, and details are not repeated here.
Further, the upper electrode 307 and the resistive layer 305 may be patterned by a photolithography process and an etching process to form the memristor cell 31 and the memristor cell 32.
Hereinafter, a method of manufacturing a first conductive path corresponding to a lower electrode and a second conductive path corresponding to an upper electrode will be described. It should be understood that, in the subsequent preparation process, the first conductive path corresponding to the lower electrode may be prepared first, and then the second conductive path corresponding to the upper electrode may be prepared, or the second conductive path corresponding to the upper electrode may be prepared first, and then the first conductive path corresponding to the lower electrode may be prepared.
After step 2g, step 2h may also be performed, depositing a fourth dielectric layer 308 on the upper surface of the upper electrode 307 of the memristor, as shown in fig. 17;
optionally, the material and deposition process of the fourth dielectric layer may refer to those of other dielectric layers, which are not described herein.
Further, step 2i may also be performed, etching is performed on the fourth dielectric layer 308, so as to form a first via 309 reaching the lower electrode 303 of the memristor, that is, a bottom of the first via 309 reaches the lower electrode 303 of the memristor, as shown in fig. 18;
then, step 2j is performed, a conductive material is deposited on the upper surface of the fourth dielectric layer 308, so that the first via 309 is filled with the conductive material, further, the conductive material on the upper surface of the fourth dielectric layer 308 except the position of the first via 309 is removed, that is, the conductive material is only remained at the position of the first via 309, and the lower electrode 303 of the memristor and the first conductive via can be electrically connected by filling the conductive material in the first via 309, as shown in fig. 18.
The conductive material may be tungsten or other conductive materials, and the embodiments of the present application are not limited thereto.
Thereafter, step 2k is performed to prepare a first conductive via 310 above the first via 309;
for example, the first conductive via 310 may be formed over the first through hole 309 by a sputtering deposition, a photolithography process, and an etching process, and the first conductive via 310 is electrically connected to the first through hole 309, so that the electrical connection of the lower electrode 303 and the first conductive via 310 can be achieved.
Optionally, the material and the preparation process for the first conductive path may refer to the description in the foregoing embodiments, and are not repeated here.
Further, step 2l is performed to deposit a fifth dielectric layer 312 on the upper surface of the fourth dielectric layer 308, wherein the fifth dielectric layer 312 covers the first conductive via 310, as shown in fig. 19;
optionally, the material and deposition process of the fifth dielectric layer 312 may refer to those of other dielectric layers, which are not described herein.
Optionally, in this step 2l, the fifth dielectric layer 312 may also be planarized, for example, the fifth dielectric layer 312 may be planarized by using a CMP process.
Further, step 2m is performed, and the fifth dielectric layer 312 is subjected to etching processing to form a second via hole 311 reaching the upper electrode of the memristor, as shown in fig. 19;
specifically, the fifth dielectric layer 312 may be processed by a photolithography process and an etching process to form a second via 311 reaching the upper electrode 307 of the memristor, that is, the bottom of the second via 311 is connected to the upper electrode 307 of the memristor.
Then, step 2n may be performed, filling the second via hole 311 with a conductive material;
specifically, a conductive material is deposited on the upper surface of the fifth dielectric layer 312, so that the second via 311 is filled with the conductive material, further, the conductive material on the upper surface of the fifth dielectric layer 312 except for the position of the second via 311 may be removed, that is, the conductive material is only remained at the position of the second via 311, and the conductive material is filled in the second via 311, so that the upper electrode 307 of the memristor and the second conductive via 314 may be electrically connected, as shown in fig. 19.
Finally, step 2k is performed to prepare a second conductive via 314 above the second via 311.
Specifically, the second conductive via 314 may be formed above the second via 311 by a sputtering deposition, a photolithography process, and an etching process, and the second conductive via 314 is electrically connected to the second via 311, so that the upper electrode 307 and the second conductive via 314 can be electrically connected.
At this point, the memristor unit 31 and the memristor unit 32, and the first conductive path 310 and the second conductive path 314 may be obtained, so that the memristor unit 31 and the memristor unit 32 may be connected to corresponding transistor circuits on the CMOS substrate 30 through the first conductive path 310 and the second conductive path 314, and thus, operations of controlling reading, writing, erasing and the like of the memory may be realized.
It should be noted that, while embodiments 1 and 2 are possible implementations, or preferred implementations, of the memristor manufacturing method 400 according to the embodiments of the present application, other implementations derived from the memristor manufacturing method 400 according to the embodiments of the present application also fall within the scope of the embodiments of the present application.
It should be understood that the method for manufacturing the memristor according to the embodiments of the present application may also be other alternative or equivalent variants of various operations in the above steps, and the embodiments of the present application are not limited to the operation process or the operation manner adopted in each step.
It should also be understood that the above-listed embodiments of the memristor manufacturing method may be performed by robotic or numerically controlled machining, and that the device software or processes used to perform the memristor manufacturing method may perform the memristor manufacturing method by executing computer program code stored in the memory.
The embodiment of the present application further provides a memristor, as shown in fig. 20, the memristor 500 may include a lower electrode 510, a resistive layer 520, and an upper electrode 530.
Wherein, a cross section 511 along the deposition direction 512 of the lower electrode 510 is in surface contact with the resistive layer 520, i.e. the cross section 511 is an area where the lower electrode 510 and the resistive layer 520 are effectively in contact, and the resistive layer 520 and the upper electrode 530 are in surface contact.
It is understood that in the present embodiment, the cross section 511 may be parallel or approximately parallel to the deposition direction 512, i.e. the cross section 511 may have an angle with the deposition direction 512.
Optionally, in some embodiments, the lower electrode 510 is electrically connected to a first conductive path, and the upper electrode is electrically connected to a second conductive path, where the first conductive path is used to electrically connect the lower electrode to the outside, and the second conductive path is used to electrically connect the upper electrode to the outside.
Optionally, in some embodiments, the memristor 500 is a memristor or memristor array fabricated according to the fabrication methods of memristors described above.
An embodiment of the present application further provides a RRAM, as shown in fig. 21, the RRAM600 may include a memristor 601, where the memristor 601 may be a memristor or a memristor array prepared according to the above-described memristor manufacturing method, or may also be the memristor 500.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It will also be appreciated that the various embodiments of the manufacturing method enumerated above, may be performed by robotic or numerical control machining, and that the apparatus software or processes used to perform the manufacturing method may perform the manufacturing method described above by executing computer program code stored in memory.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (16)
- A method of fabricating a memristor, comprising:depositing a lower electrode of the memristor;preparing a resistance layer of the memristor on a section along the deposition direction of a lower electrode of the memristor;and preparing an upper electrode of the memristor on a resistance layer of the memristor.
- The method of manufacturing of claim 1, further comprising:preparing a first conductive path electrically connected with a lower electrode of the memristor; andpreparing a second conductive path electrically connected to an upper electrode of the memristor.
- The method of manufacturing of claim 1 or 2, wherein the depositing the lower electrode of the memristor comprises:preparing a first conductive path on the upper surface of a Complementary Metal Oxide Semiconductor (CMOS) substrate;depositing a first dielectric layer on the upper surface of the CMOS substrate, the first dielectric layer encapsulating the first conductive via;etching the upper surface of the first dielectric layer to form a through hole reaching the first conductive path;filling a conductive material in the through hole, wherein the conductive material is used for electrically connecting a lower electrode of the memristor and the first conductive path;depositing a lower electrode of the memristor over the via.
- The manufacturing method according to claim 3, wherein the preparing the resistive layer of the memristor at a cross section along a deposition direction of a lower electrode of the memristor comprises:depositing a second dielectric layer on the upper surface of the first dielectric layer, wherein the second dielectric layer covers the lower electrode of the memristor;manufacturing a blind hole in the upper surface of the second dielectric layer along the deposition direction of the lower electrode of the memristor to obtain the section of the lower electrode of the memristor, wherein the bottom of the blind hole is abutted to the first dielectric layer;depositing a resistive layer of the memristor on an upper surface of the second dielectric layer and an inner surface of the blind via.
- The method of manufacturing according to claim 4, wherein the fabricating the upper electrode of the memristor on the resistive layer of the memristor comprises:depositing an upper electrode material of the memristor on the surface of the resistance layer of the memristor, so that the upper electrode material is injected into the blind hole.
- The method of manufacturing of claim 5, further comprising:preparing a third dielectric layer on the upper surface of the second dielectric layer and the upper surface of the upper electrode of the memristor;etching the third dielectric layer to form a groove reaching the upper electrode of the memristor;preparing a second conductive path on the inner surface of the trench, wherein the second conductive path is electrically connected with the upper electrode of the memristor.
- The method of manufacturing of claim 1 or 2, wherein the depositing the lower electrode of the memristor comprises:preparing a first dielectric layer on the upper surface of the CMOS substrate;depositing a second dielectric layer on the upper surface of the first dielectric layer;depositing a lower electrode of the memristor on the second dielectric layer, the lower electrode of the memristor wrapping an upper surface and a side surface of the second dielectric layer;depositing a third dielectric layer on a lower electrode of the memristor;thinning the third dielectric layer to expose the cross section of the lower electrode of the memristor on the side surface of the second dielectric layer.
- The manufacturing method of claim 7, wherein the preparing the resistive layer of the memristor at a cross section along a deposition direction of a lower electrode of the memristor comprises:depositing a resistive layer of the memristor over the cross-section of a lower electrode of the memristor.
- The method of manufacturing according to claim 8, wherein the fabricating the upper electrode of the memristor on the resistive layer of the memristor comprises:and depositing an upper electrode of the memristor on the upper surface of the resistance layer of the memristor.
- The method of manufacturing of claim 9, further comprising:depositing a fourth dielectric layer on an upper surface of an upper electrode of the memristor;etching the fourth dielectric layer to form a first through hole reaching the lower electrode of the memristor;filling a conductive material in the first through hole;preparing a first conductive path above the first via;depositing a fifth dielectric layer on an upper surface of the fourth dielectric layer, the fifth dielectric layer encapsulating the first conductive via;etching the fifth dielectric layer to form a second through hole reaching the upper electrode of the memristor;filling a conductive material in the second through hole;a second conductive via is prepared over the second via.
- The manufacturing method according to any one of claims 7 to 10, characterized in that a ratio of an etching rate of the second dielectric layer to an etching rate of the first dielectric layer is greater than a certain threshold value.
- A memristor is characterized by comprising an upper electrode, a resistance layer and a lower electrode;wherein a cross section along a deposition direction of the lower electrode is in contact with the resistive layer surface, and the resistive layer is in contact with the upper electrode surface.
- The memristor according to claim 12, wherein the lower electrode is electrically connected to a first conductive path, and the upper electrode is electrically connected to a second conductive path, wherein the first conductive path is used to electrically connect the lower electrode to the outside, and the second conductive path is used to electrically connect the upper electrode to the outside.
- A memristor, characterized in that it is prepared according to the manufacturing method of any one of claims 1 to 11.
- A Resistive Random Access Memory (RRAM) comprising:a memristor as in claims 12 or 13.
- A Resistive Random Access Memory (RRAM) comprising:a memristor as in claim 14.
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| PCT/CN2018/079279 WO2019174032A1 (en) | 2018-03-16 | 2018-03-16 | Memristor fabrication method, memristor and resistive random access memory rram |
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| US20160248008A1 (en) * | 2013-01-21 | 2016-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | One Transistor and One Resistive Random Access Memory (RRAM) Structure with Spacer |
| CN104733608A (en) * | 2013-12-18 | 2015-06-24 | 华邦电子股份有限公司 | Resistive memory and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116507195A (en) * | 2023-06-21 | 2023-07-28 | 武汉大学 | Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor |
| CN116507195B (en) * | 2023-06-21 | 2023-10-17 | 武汉大学 | Based on WO x /YO y Preparation method of double-heterojunction structure analog memristor |
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| WO2019174032A1 (en) | 2019-09-19 |
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