CN112786780B - Resistive random access memory array and manufacturing method thereof - Google Patents

Resistive random access memory array and manufacturing method thereof Download PDF

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Publication number
CN112786780B
CN112786780B CN201911086645.0A CN201911086645A CN112786780B CN 112786780 B CN112786780 B CN 112786780B CN 201911086645 A CN201911086645 A CN 201911086645A CN 112786780 B CN112786780 B CN 112786780B
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region
diffusion barrier
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random access
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CN112786780A (en
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傅志正
林铭哲
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices

Abstract

The invention provides a resistive random access memory array and a manufacturing method thereof. The resistive random access memory array comprises a substrate, wherein an array region of the substrate comprises a first region and a second region. The resistive random access memory array comprises a bottom electrode layer on a substrate, an oxygen ion storage layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion storage layer, a resistance conversion layer on the diffusion barrier layer and a top electrode layer on the resistance conversion layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.

Description

Resistive random access memory array and manufacturing method thereof
Technical Field
The present invention relates to a memory device, and more particularly, to a resistive random access memory array and a method for fabricating the same.
Background
In a conventional Resistive Random Access Memory (RRAM), a plurality of memory cells are included in an array region of one chip, and each memory cell includes a patterned bottom electrode layer, a resistive switching layer, and a top electrode layer. When a forming voltage or a writing voltage is applied to the memory cell, oxygen ions are driven by the voltage to leave the resistance conversion layer. The equivalent positive oxygen vacancies left in the resistive switching layer form conductive paths (or conductive filaments) that switch the resistive switching layer from a high resistance state to a low resistance state. When an erase voltage is applied, the oxygen ions return to the resistive switching layer and combine with the equivalent positive valence oxygen vacancies. Therefore, the conductive path disappears, and the resistance conversion layer is converted from a low resistance state to a high resistance state. In general, a high resistance state corresponds to a logic state "0", and a low resistance state corresponds to a logic state "1".
When a specific operating voltage is applied to a chip, the difference between the maximum and minimum values of the current values read from the memory cells is defined as the "operating window" of the chip at the specific operating voltage. In conventional RRAM, the layers on the same chip are typically of uniform thickness, so that the high and low resistance states of the memory cells are distributed over a specific range, and it is desirable to configure the operating window to be smaller and better in order to obtain logic states "0" and "1", respectively. However, existing RRAMs are limited to smaller operating windows and specific ranges, which may be detrimental to configuration into multi-state storage.
In some application areas (e.g., artificial intelligence, encryption, etc.), a large operating window is required for multi-state storage. Furthermore, in these fields of application, the current values read from these memory cells are preferably difficult to predict. That is, the higher the disorder (random) of the memory cell, the better. Therefore, in the existing RRAM, the operation window and the mess degree are not enough to meet the requirements of application fields such as artificial intelligence and the like.
In order to increase the operation window and disorder of the resistive random access memory array, the conventional method uses additional control circuits to apply different voltages to the memory cells at different locations. However, such methods require complex circuit designs, greatly increasing process complexity, production time, and production costs. Furthermore, the additional control circuitry also occupies a larger available space, which is detrimental to the miniaturization of the memory device.
For the memory industry, there is still a need for improvement of the resistive random access memory and the process thereof in order to meet the demands of the application fields such as artificial intelligence, encryption, etc., and to reduce the process complexity, production time and production cost.
Disclosure of Invention
The embodiment of the invention provides a resistive random access memory array and a manufacturing method thereof, which can obviously increase the operation window and disorder degree of the resistive random access memory and reduce the complexity, the production cost and the production time of the process.
An embodiment of the invention discloses a resistive random access memory array, comprising: the array region of the substrate comprises a first region and a second region; a bottom electrode layer on the substrate; an oxygen ion storage layer on the bottom electrode layer; a diffusion barrier layer on the oxygen ion storage layer, wherein the diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region; a resistance conversion layer located on the diffusion barrier layer; and a top electrode layer on the resistance conversion layer.
An embodiment of the invention discloses a method for manufacturing a resistive random access memory array, which comprises the following steps: providing a substrate, wherein an array region of the substrate comprises a first region and a second region; forming a bottom electrode layer on a substrate; forming an oxygen ion storage layer on the bottom electrode layer; forming a diffusion barrier layer on the oxygen ion storage layer, wherein the diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region; forming a resistance conversion layer on the diffusion barrier layer; and forming a top electrode layer on the resistance conversion layer.
In the resistive random access memory array provided by the embodiments of the present invention, the diffusion barrier layers in different memory cells may have different thicknesses and/or materials. Therefore, the operation window and disorder of the resistance random access memory can be greatly increased. In addition, the manufacturing method of the resistive random access memory array provided by the embodiment of the invention does not need to use an extra control circuit. Therefore, the complexity of the process, the production cost and the production time can be reduced.
Drawings
Fig. 1A-1F are schematic cross-sectional views of steps in the fabrication of a resistive random access memory array according to some embodiments of the present invention.
Fig. 2A and 2B are schematic cross-sectional views illustrating steps in fabricating a resistive random access memory array according to further embodiments of the present invention.
Symbol description:
100. 200-resistance random access memory array
10 to first region 20 to second region
102 to substrate 104 to insulating layer
106 to contact plug 112 to bottom electrode layer
114-oxygen barrier layer 115, 125-mask layer
116-oxygen ion reservoir 120-diffusion barrier
120a to first sub-layer 120b to second sub-layer
132-resistance conversion layer 134-top electrode layer
136-hard mask layer 142-protective layer
144-dielectric 146-conductive plug
150a, 250 a-first memory cell 150b, 250 b-second memory cell
T1 to first thickness T2 to second thickness
Ta to third thickness Tb to fourth thickness
Detailed Description
The present invention will be more fully understood by reference to the following detailed description and examples, which are given in connection with the accompanying drawings.
Fig. 1A to 1F are schematic cross-sectional views illustrating steps of a method for manufacturing a resistive random access memory array 100 according to some embodiments of the present invention. Referring to fig. 1A, a substrate 102 is provided, and an array region of the substrate 102 includes a first region 10 and a second region 20. Next, an insulating layer 104 is formed on the substrate 102. The material of the substrate 102 may include bulk semiconductor substrates (e.g., silicon substrates), compound semiconductor substrates (e.g., group IIIA-VA semiconductor substrates), silicon-on-insulator (silicon on insulator, SOI) substrates, and the like. The substrate 102 may be a doped or undoped semiconductor substrate. In some embodiments, the substrate 102 is a silicon substrate. The insulating layer 104 may comprise a suitable insulating material, such as a nitride, oxide, or oxynitride. In some embodiments, the first insulating layer 104 is silicon oxide.
Next, a patterning process is performed on the insulating layer 104 to form an opening. A metal material is filled into the opening, and excess metal material on the insulating layer 104 is removed by a planarization process (e.g., a cmp process) to form a contact plug 106 in the insulating layer 104. In some embodiments, the contact plug 106 is a single layer structure and includes tungsten, aluminum, copper, other suitable metals, or combinations thereof. In other embodiments, the contact plug 106 includes a conductive layer and a liner conformally formed inside the opening. The liner layer may improve adhesion of the conductive layer to the substrate 102 or the insulating layer 104 and may prevent metal atoms from diffusing into the substrate 102 or the first insulating layer 104. The material of the liner may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof. The material of the conductive layer may include tungsten, aluminum, copper, other suitable metals, or combinations thereof.
Next, a bottom electrode layer 112, an oxygen barrier layer 114, and an oxygen ion storage layer 116 are sequentially formed on the insulating layer 104 in the array region. The bottom electrode layer 112, the oxygen barrier layer 114, and the oxygen ion reservoir layer 116 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or other suitable deposition process.
The bottom electrode layer 112 may be electrically connected to other devices (not shown) through the contact plug 106. By applying a voltage to the bottom electrode layer 112 and the subsequently formed top electrode layer 134, the resistive switching layer 132 can be switched to a different resistive state. The material of the bottom electrode layer 112 may include titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. The bottom electrode layer 112 may be a single layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. In some embodiments, the bottom electrode layer 112 is a bilayer structure that includes a titanium layer and a titanium nitride layer formed thereon.
To avoid oxygen ions from entering bottom electrode layer 112, thereby causing oxidation of bottom electrode layer 112, oxygen barrier layer 114 may be disposed between bottom electrode layer 112 and oxygen ion storage layer 116 to avoid oxygen ions located in oxygen ion storage layer 116 from entering bottom electrode layer 112. The material of the oxygen barrier layer 114 may include aluminum oxide (Al x O y ) Hafnium oxide (Hf) x O y ) Titanium oxide (Ti) x O y ) Or titanium oxynitride (Ti) x O y N z ). In some embodiments, the material of the oxygen barrier layer 114 is aluminum oxide (Al 2 O 3 )。
Oxygen ion reservoir 116 may be used to store oxygen ions from the resistive switching layer. The material of the oxygen ion reservoir 116 may include titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr). In some embodiments, the material of oxygen ion reservoir 116 is titanium. In some embodiments, the oxygen ion storage layer 116 has a thickness of 15-35nm.
Next, a diffusion barrier material is deposited over the oxygen ion reservoir 116 to form a diffusion barrier 120. The diffusion barrier 120 may be used to block oxygen ions, making movement of the oxygen ions more difficult. Oxygen ions stored in the oxygen ion reservoir 116 are less likely to diffuse back into the subsequently formed resistive switching layer 132 (shown in fig. 1D), and thus, the memory cell can be stably maintained in a low resistance state. The material of the diffusion barrier layer 120 may include aluminum oxide (Al x O y ) Titanium oxide (Ti) x O y ) Tantalum oxide (Ta) x O y ) Hafnium oxide (Hf) x O y ) Nickel oxide (Ni) x O y ) Zirconia (Zr) x O y ) Or a combination of the foregoing. In some embodiments, the material of the diffusion barrier layer 120 is aluminum oxide (Al 2 O 3 )。
Next, a mask layer 115 is formed and patterned to cover the first region 10 and expose the second region 20. Mask layer 115 may be any suitable material (e.g., photoresist), and mask layer 115 may be patterned using any suitable process.
Referring to fig. 1B, a first etching process is performed to remove the diffusion barrier layer 120 located in the second region 20. After the first etching process, the diffusion barrier layer 120 located in the first region 10 is not removed but remains. The first etching process may be a dry etching process, a wet etching process, or a combination thereof.
Referring to fig. 1C, the mask layer 115 is removed to expose the diffusion barrier layer 120 in the first region. Next, the diffusion barrier material is redeposited in the array region to form a diffusion barrier layer 120 in the first region 10 and the second region 20. The diffusion barrier layer 120 in the first region 10 has a first thickness T1, the diffusion barrier layer 120 in the second region 20 has a second thickness T2, and the first thickness T1 is greater than the second thickness T2.
Referring to fig. 1D, a resistance conversion layer 132, a top electrode layer 134 and a hard mask layer 136 are sequentially formed on the diffusion barrier layer 120 in the array region. The resistive switching layer 132, the top electrode layer 134, and the hard mask layer 136 may be formed using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or other suitable deposition process. The resistive switching layer 132, the top electrode layer 134, and the hard mask layer 136 are conformally deposited over the diffusion barrier layer 120. Thus, the resistance conversion layer 132 (the top electrode layer 134 or the hard mask layer 136) has the same thickness in the first region 10 and the second region 20.
The resistive switching layer 132 may determine the resistive state of the memory cell. Furthermore, when a specific voltage is applied, the resistance value of the resistance conversion layer 132 can determine the logic state of the memory cell. The material of the resistive switching layer 132 may include a transition metal oxide, for example, aluminum oxide (Al x O y ) Titanium oxide (Ti) x O y ) Nickel oxide (Ni) x O y ) Tantalum oxide (Ta) x O y ) Hafnium oxide (Hf) x O y ) Or zirconia (Zr) x O y ). In some embodiments, the material of the resistive switching layer 132 is hafnium oxide (HfO 2 ). To block oxygen ions from returning from oxygen ion reservoir 116 to resistive switching layer 132, the material of diffusion barrier layer 120 may be different from the material of resistive switching layer 132.
The material of top electrode layer 134 may include titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. The top electrode layer 134 may be a single layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. In some embodiments, top electrode layer 134 is a single layer structure formed of titanium nitride.
The hard mask layer 136 may protect the layers below it, reducing or avoiding damage to the layers below it from subsequent processes. The hard mask layer 136 may be nitride, oxynitride or carbonitride. For example, the hard mask layer 136 may be silicon oxynitride, silicon nitride, silicon dioxide. In some embodiments, the hard mask layer 136 is silicon oxynitride.
Next, a mask layer 125 is formed and patterned to partially cover the first region 10 and the second region 20. The material of mask layer 125 may be the same or similar to the material of mask layer 115.
Referring to fig. 1E, a second etching process is performed to form a first stacked structure and a second stacked structure in the first region 10 and the second region 20, respectively. The first and second stacked structures each include a bottom electrode layer 112, an oxygen barrier layer 114, an oxygen ion reservoir layer 116, a diffusion barrier layer 120, a resistive switching layer 132, a top electrode layer 134, and a hard mask layer 136. To avoid shorting between the first and second stacked structures, the second etching process may have an etch depth lower than the top surface of the insulating layer 104. In some embodiments, the second etching process is a dry etching process.
Next, a passivation layer 142 is formed in the array region to conformally cover the first and second stacked structures. The protective layer 142 may be formed by an atomic layer deposition method. The protective layer 142 may be a single layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. In some embodiments, the protective layer 142 is a bilayer structure formed of an oxyhydrogen barrier layer and a spacer layer formed on the oxyhydrogen barrier layer. In such embodiments, the oxyhydrogen barrier layer may prevent hydrogen and oxygen from entering the substrate 102, the bottom electrode layer 112, the oxygen barrier layer 114, the oxygen ion storage layer 116, the diffusion barrier layer 120, the resistive switching layer 132, and the top electrode layer 134, thereby preventing deterioration or failure of the resistive random access memory array. The material of the oxyhydrogen barrier layer may be a metal oxide (e.g., aluminum oxide), a metal nitride, a metal oxynitride, a nitride, an oxynitride, or a combination thereof. The spacer layer may reduce or prevent the memory cell from being damaged in subsequent processes. The material of the spacer layer may be a nitride or oxynitride, for example silicon dioxide. In other embodiments, the function and material of the oxyhydrogen barrier layer may be the same as or similar to the function and material of the spacer layer. In the present embodiment, the protective layer 142 is made of aluminum oxide (Al 2 O 3 ) A single layer structure is formed.
Next, a dielectric layer 144 is formed on the substrate 102, wherein the dielectric layer 144 covers the first and second stacked structures and fills the gap between the first and second stacked structures. Thereafter, a planarization process is performed to make the dielectric layer 144 have a flat top surface. In some embodiments, the material of the dielectric layer 144 is an oxide and is formed by chemical vapor deposition.
Referring to fig. 1F, openings are formed on the first and second stacked structures. Next, a conductive material is filled into the opening to form a conductive plug 146 on the first stacked structure and the second stacked structure. The conductive plugs 146 may be similar to the contact plugs 106 and will not be described in detail herein. Thereafter, other conventional processes may be performed to complete the resistive random access memory array 100, which will not be described in detail herein.
In some embodiments, a resistive random access memory array 100 is provided. Referring to fig. 1F, the resistive random access memory array 100 includes a substrate 102, and an array region of the substrate 102 includes a first region 10 and a second region 20. The first memory cell 150a is located in the first region 10 and the second memory cell 150b is located in the second region 20. The first memory cell 150a and the second memory cell 150b each include a bottom electrode layer 112, an oxygen barrier layer 114, an oxygen ion storage layer 116, a diffusion barrier layer 120, a resistive switching layer 132, a top electrode layer 134, a hard mask layer 136 and a conductive plug 146, which are stacked in this order from bottom to top. The diffusion barrier 120 of the first memory cell 150a is different from the diffusion barrier 120 of the second memory cell 150 b. Thus, the operation window of the first memory unit 150a is different from that of the second memory unit 150 b. In the present embodiment, the diffusion barrier layer 120 of the first memory cell 150a has a first thickness T1, the diffusion barrier layer 120 of the second memory cell 150b has a second thickness T2, and the first thickness T1 is greater than the second thickness T2. Other layers of the first memory cell 150a are identical to other layers of the second memory cell 150b except for the thickness of the diffusion barrier layer 120.
When a voltage is applied to the memory cell in the low resistance state, a portion of the oxygen ions residing in the oxygen ion reservoir 116 return to the resistive switching layer 132. Thus, the conductive path decreases and the resistance value of the memory cell increases. As the number of oxygen ions returned into the resistive switching layer 132 is different, the resistance values of the memory cells are also different from each other. The thickness of the diffusion barrier 120 is one of the important parameters that determines the number of oxygen ions back into the resistive switching layer 132. If the thickness of the diffusion barrier layer 120 is large, oxygen ions are more difficult to pass through the diffusion barrier layer 120. Therefore, the number of oxygen ions returned to the resistance conversion layer 132 will be smaller, and the resistance value of the memory cell will be lower. Furthermore, when the thickness of the diffusion barrier layer 120 is larger, oxygen ions are more difficult to pass through the diffusion barrier layer 120, so that the operation window of the resistive random access memory array 100 is smaller.
When the resistive random access memory array 100 includes only the first memory cell 150a, the operation window is in the first range. When the resistive random access memory array 100 includes only the second memory cell 150b, the operation window is in the second range. In the present embodiment, the resistive random access memory array 100 includes the first memory cell 150a and the second memory cell 150b, and the operation window is a third range, and the third range covers the first range and the second range. In other words, the lower limit of the third range is the minimum value of the first range and the second range, and the upper limit of the third range is the maximum value of the first range and the second range. Therefore, the structure of the embodiment can greatly increase the operation window of the resistance random access memory array.
In order to verify the technical efficacy of the resistive random access memory array 100 of the present embodiment, the present inventors have conducted experiments. Details and results of the experiment are briefly described below.
First, resistive random access memory arrays (a), (B) and (C) are prepared. The thickness of the diffusion barrier layer of all memory cells in array (a) was 0.7nm. The thickness of the diffusion barrier layer of all memory cells in array (B) was 1.3nm. The thickness of the diffusion barrier layer of half of the memory cells located in array (C) is 0.7nm and the thickness of the diffusion barrier layer of the other half of the memory cells is 1.3nm. The remaining structures of arrays (A), (B) and (C) are identical except for the thickness of the diffusion barrier. The resistive random access memory arrays of arrays (a), (B) and (C) are all the same or similar to the resistive random access memory array 100 of fig. 1F.
An operating voltage of 2.5-3 Volt is applied to the array (A), the current values of the memory cells are read, and the difference between the read maximum current value and the read minimum current value is defined as an "operating window" of the array (A) at the specific operating voltage. The same is done for arrays (B) and (C).
The experimental results showed that the maximum and minimum current values for array (A) were 41 μA and 27 μA, respectively, and the operating window was 14 μA. The maximum and minimum current values for array (B) were 46 μA and 35 μA, respectively, and the operating window was 11 μA. The maximum and minimum current values for array (C) were 46 μA and 27 μA, respectively, and the operating window was 19 μA. The experimental results prove that the resistive random access memory array 100 of the present embodiment can greatly increase the operation window even without using an additional control circuit.
In the method for manufacturing the resistive random access memory array 100 according to the present embodiment, the relative positions of the first memory cell 150a and the second memory cell 150b can be changed by the pattern of the mask layer 115. In some embodiments, in the top view, the first memory cells 150a and the second memory cells 150b are adjacent to each other and staggered. In other embodiments, the first memory cell 150a and the second memory cell 150b are arranged irregularly or randomly in the top view. Therefore, even without using additional control circuitry, the disorder of the resistive random access memory array 100 can be greatly increased.
Methods of forming the diffusion barrier 120 may include atomic layer deposition, chemical vapor deposition, or physical vapor deposition. In some embodiments, the diffusion barrier layer 120 is formed using atomic layer deposition, so that the first thickness T1, the second thickness T2, and the difference (T1-T2) between them can be precisely controlled. In other embodiments, the diffusion barrier 120 is formed using chemical vapor deposition. Since the diffusion barrier layer 120 with non-uniform thickness can be easily formed by chemical vapor deposition, it is advantageous to increase the disorder of the resistive random access memory array 100. In still other embodiments, the diffusion barrier 120 is formed using physical vapor deposition. The atomic ratio of the diffusion barrier material can be controlled relatively easily using physical vapor deposition. For example, al of the formula x O y Alumina represented by formula (I), wherein x and y are each a suitable integer。
In this embodiment, the low resistance state of the resistive random access memory array 100 is configured as multiple states for writing and reading. For example, the low resistance states may include a first low resistance state LRS1 and a second low resistance state LRS2 corresponding to different logic states, respectively. That is, when a set voltage is applied to the memory cell located in the first region and the memory cell located in the second region, a current read from one of the memory cell located in the first region and the memory cell located in the second region is determined to correspond to the first low resistance state LRS1, and a current read from the other is determined to correspond to the second low resistance state LRS2. The resistance value of the first low resistance state LRS1 is smaller than the resistance value of the second low resistance state LRS2. In the low resistance state, oxygen ions are located in the ion storage layer 116, so that the ambient temperature is not likely to affect the diffusion of oxygen ions in the low resistance state (e.g., the oxygen ions located in the ion storage layer 116 are returned to the resistance conversion layer 132), and thus the resistive random access memory array 100 of the present embodiment has better high temperature data retention (high temperature data retention, HTDR) than if the resistive random access memory array is configured in multiple states for writing and reading in the high resistance state. In another embodiment, the resistance random access memory array 100 performs multi-state writing and reading only in the low resistance state, thereby improving the high temperature data retention.
If the thickness of the diffusion barrier layer 120 is controlled within a suitable range, oxygen ions diffusing back into the resistive switching layer 132 can be reduced, which is advantageous for improving high temperature data retention. Furthermore, if the thickness of the diffusion barrier layer 120 is controlled within a proper range, the operating voltage can be reduced, thereby improving the yield of the resistive random access memory array 100. In some embodiments, the second thickness T2 of the diffusion barrier 120 is
If the thickness of the diffusion barrier 120 is too large, it may result in some memory cells requiring very large voltages to be driven. As a result, it is difficult to use the same operation voltage for the whole wafer, and additional circuit design is required. Furthermore, if the overall thickness of the memory cells varies too much, it may not be possible to form all of the memory cells on the same wafer using the same process. For example, memory cells having different thicknesses may require the use of different deposition or etching conditions. In this way, the process complexity is greatly increased.
The inventors have found that the operating window of the memory cell is extremely sensitive to the thickness of the diffusion barrier 120. In other words, the thickness of the diffusion barrier layer 120 (less than 1 nm) is only slightly adjusted, so that the operation window can be greatly widened. If the difference between the first thickness T1 and the second thickness T2 is controlled within a proper range, the operation window can be easily controlled within a desired range, and the manufacturing method of the present embodiment can be easily integrated into the existing process. As shown in fig. 1F, the diffusion barrier layer 120 located in the first region 10 has a first thickness T1, and the diffusion barrier layer 120 located in the second region 20 has a second thickness T2. In some embodiments, the ratio T1/T2 of the first thickness T1 to the second thickness T2 is 1.2-5.5.
Fig. 2A and 2B are schematic cross-sectional views illustrating steps in fabricating a resistive random access memory array 200 according to further embodiments of the present invention. The resistive random access memory array 200 shown in fig. 2B is similar to the resistive random access memory array 100 shown in fig. 1F, except that the diffusion barrier 120 of fig. 2B comprises two different materials. For simplicity of illustration, the same elements and process steps for forming the same are shown in fig. 1F and will not be described in detail herein.
The structure shown in fig. 2A may be formed by the following steps. First, a first diffusion barrier material is deposited in the array region. Next, a mask layer 125 is formed and patterned to cover the first region 10 and expose the second region 20. Next, a first etching process is performed as shown in fig. 1B to remove the first diffusion barrier material located in the second region 20 and to leave the first diffusion barrier material located in the first region 10, so as to form a first sub-layer 120a in the first region 10. Next, a second diffusion barrier material, different from the first diffusion barrier material, is deposited in the array region to form a second sub-layer 120b in the first region 10 and the second region 20, as shown in fig. 2A. After forming the structure shown in fig. 2A, the process steps described in fig. 1D-1F may be continued to complete the resistive random access memory array 200 shown in fig. 2B.
Referring to fig. 2B, in the first region 10, the diffusion barrier layer 120 includes a first sub-layer 120a and a second sub-layer 120B. In the second region 20, the diffusion barrier layer 120 includes only the second sub-layer 120b and does not include the first sub-layer 120a. In this embodiment, the first diffusion barrier material is different from the second diffusion barrier material. Thus, the oxygen ion blocking capability of the diffusion barrier 120 can be controlled by selecting the diffusion barrier material. For example, if the first diffusion barrier material has a better oxygen ion blocking capability than the second diffusion barrier material, only a very small thickness is required (e.g., ) The operation window can also be greatly increased. In this way, the difference between the total thickness of the first memory cell 250a and the second memory cell 250b can be reduced. In some embodiments, the first diffusion barrier material is aluminum oxide (Al 2 O 3 ) And the second diffusion barrier material is tantalum oxide (Ta 2 O 5 )。
Referring to fig. 2B, the thickness of the first sub-layer 120a of the diffusion barrier 120 is Ta. The thickness Ta of the first sub-layer 120a is equal to the difference between the total thicknesses of the first memory cell 250a and the second memory cell 250 b. If the thickness Ta of the first sub-layer 120a is controlled within a suitable range, the overall thickness uniformity of the memory cell can be improved, which is advantageous for reducing the process complexity. In some embodiments, the thickness Ta of the first sublayer 120a is
Referring to fig. 2B, the second sub-layer 120B of the diffusion barrier 120 has a thickness Tb. If the ratio (Tb/Ta) of the thickness Tb of the second sub-layer 120b to the thickness Ta of the first sub-layer 120a is controlled to be within a proper range, the operation window can be easily controlled to be within a desired range. In some embodiments, the ratio of the thickness Tb of the second sub-layer 120b to the thickness Ta of the first sub-layer 120a (Tb/Ta) is 1.5-10.0.
It should be noted that two memory cells are shown in the cross-section for illustration only and are not intended to limit the present invention. Based on the technical concepts provided by the embodiments of the present invention, a person having ordinary skill in the art should make appropriate modifications. For example, the steps described in fig. 1B and 1C may be repeated to create diffusion barriers of three different thicknesses and/or materials prior to performing the steps of fig. 1D. Thus, the operation window and disorder of the resistance random access memory array can be further increased. In addition, in another embodiment, which is not shown, in the step of forming the structure shown in fig. 2A, a mask layer may be formed to cover the first region 10 and expose the second region 20 after removing the first diffusion barrier material located in the second region 20. Next, a second diffusion barrier material, different from the first diffusion barrier material, is deposited in the second region 20. Thus, the diffusion barrier layer 120 located in the first region 10 and the diffusion barrier layer 120 located in the second region 20 may be formed of two different diffusion barrier materials, respectively. In this way, even though the diffusion barrier layer 120 in the first region 10 and the diffusion barrier layer 120 in the second region 20 have the same thickness, the operation window and disorder of the resistive random access memory array can be increased.
In addition, if the resistance conversion layer 132 of the first memory cell 150a is different from the resistance conversion layer 132 of the second memory cell 150b, an additional control circuit is required to apply different voltages to the first memory cell 150a and the second memory cell 150b to complete the setting or resetting. This would be detrimental to the miniaturization of the resistive random access memory array. In the resistive random access memory array provided by the embodiment of the invention, the diffusion barrier layers in different memory cells have different thicknesses and/or materials. When a set voltage or a reset voltage is applied to the resistive random access memory array, the first current read from the memory cells of the first region is different from the second current read from the memory cells of the second region, and both the first current and the second current meet a predetermined condition (i.e., a threshold current of a low resistance state or a high resistance state). In some embodiments, when a set voltage is applied to the resistive random access memory array, a first set current read from the memory cells of the first region is different from a second set current read from the memory cells of the second region, and both the first set current and the second set current are greater than a threshold current of the low resistance state. Therefore, the operation window and disorder of the resistance random access memory array can be greatly increased. In addition, the resistive random access memory array and the manufacturing method thereof provided by the embodiment of the invention do not need to use an extra control circuit and can be easily integrated into the existing process. Therefore, the complexity of the process, the production cost and the production time can be reduced.
While the present invention has been described with reference to the preferred embodiments, it should be understood that the invention is not limited thereto, but may be embodied with various changes and modifications without departing from the spirit or scope of the present invention as defined by the appended claims.

Claims (14)

1. A resistive random access memory array, comprising:
a substrate, wherein an array region of the substrate comprises a first region and a second region;
a bottom electrode layer on the substrate;
an oxygen ion storage layer located on the bottom electrode layer;
a diffusion barrier layer on the oxygen ion storage layer, wherein the diffusion barrier layer in the first region has a first thickness T1, and the diffusion barrier layer in the second region has a second thickness T2, and the first thickness T1 is greater than the second thickness T2;
a resistance conversion layer positioned on the diffusion barrier layer; and
and the top electrode layer is positioned on the resistance conversion layer.
2. The resistive random access memory array of claim 1, wherein the material of the diffusion barrier layer comprises aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, nickel oxide, zirconium oxide, or a combination thereof.
3. The resistive random access memory array of claim 1, wherein a ratio T1/T2 of the first thickness T1 to the second thickness T2 is 1.2-5.5.
4. The resistive random access memory array of claim 1, wherein the diffusion barrier layer in the first region comprises a first diffusion barrier material, the diffusion barrier layer in the second region comprises a second diffusion barrier material, and the first diffusion barrier material is different than the second diffusion barrier material.
5. The array of claim 1, wherein the diffusion barrier layer in the first region comprises a first sub-layer and a second sub-layer, the first sub-layer being on the oxygen ion storage layer, the second sub-layer being on the first sub-layer, wherein the second sub-layer is of a material different from the material of the first sub-layer,
wherein the diffusion barrier layer in the second region includes the second sub-layer and does not include the first sub-layer.
6. The resistive random access memory array of claim 5, wherein the first sub-layer has a third thickness T3, the second sub-layer has a fourth thickness T4, and wherein a ratio T4/T3 of the fourth thickness T4 to the third thickness T3 is 1.5-10.0.
7. The resistive random access memory array of claim 1, wherein a first current read from the first region is different from a second current read from the second region when a set voltage or a reset voltage is applied to the resistive random access memory array.
8. A method of fabricating a resistive random access memory array, comprising:
providing a substrate, wherein an array region of the substrate comprises a first region and a second region;
forming a bottom electrode layer on the substrate;
forming an oxygen ion storage layer on the bottom electrode layer;
forming a diffusion barrier layer on the oxygen ion storage layer, wherein the diffusion barrier layer in the first region has a first thickness T1, the diffusion barrier layer in the second region has a second thickness T2, and the first thickness T1 is larger than the second thickness T2;
forming a resistance conversion layer on the diffusion barrier layer; and
a top electrode layer is formed on the resistance conversion layer.
9. The method of claim 8, wherein forming the diffusion barrier layer comprises:
depositing a diffusion barrier material in the array region;
performing a patterning process to remove the diffusion barrier material in the second region and to retain the diffusion barrier material in the first region; and
redeposit the diffusion barrier material in the array region to form the diffusion barrier layer in the first region and the second region.
10. The method of claim 8, wherein forming the diffusion barrier layer comprises:
depositing a first diffusion barrier material in the array region;
performing a patterning process to remove the first diffusion barrier material in the second region and to leave the first diffusion barrier material in the first region to form a first sub-layer in the first region; and
depositing a second diffusion barrier material in the array region to form a second sub-layer in the first region and the second region,
wherein the first diffusion barrier material is different from the second diffusion barrier material,
wherein in the first region, the diffusion barrier layer comprises the first sub-layer and the second sub-layer,
and wherein in the second region, the diffusion barrier layer includes the second sub-layer and does not include the first sub-layer.
11. A resistive random access memory array, comprising:
a substrate, wherein an array region of the substrate comprises a first region and a second region;
a bottom electrode layer on the substrate;
an oxygen ion storage layer located on the bottom electrode layer;
a diffusion barrier layer on the oxygen ion storage layer, the diffusion barrier layer in the first region comprising a first diffusion barrier material, the diffusion barrier layer in the second region comprising a second diffusion barrier material, and the first diffusion barrier material being different from the second diffusion barrier material;
a resistance conversion layer positioned on the diffusion barrier layer; and
and the top electrode layer is positioned on the resistance conversion layer.
12. The resistive random access memory array of claim 11, wherein a first current read from the first region is different from a second current read from the second region when a set voltage or a reset voltage is applied to the resistive random access memory array.
13. A resistive random access memory array, comprising:
a substrate, wherein an array region of the substrate comprises a first region and a second region;
a bottom electrode layer on the substrate;
an oxygen ion storage layer located on the bottom electrode layer;
a diffusion barrier layer on the oxygen ion storage layer, the diffusion barrier layer in the first region comprising a first sub-layer on the oxygen ion storage layer and a second sub-layer on the first sub-layer, wherein the second sub-layer is of a material different from the material of the first sub-layer,
wherein the diffusion barrier layer in the second region includes the second sub-layer and does not include the first sub-layer;
a resistance conversion layer positioned on the diffusion barrier layer; and
and the top electrode layer is positioned on the resistance conversion layer.
14. The resistive random access memory array of claim 13, wherein a first current read from the first region is different from a second current read from the second region when a set voltage or a reset voltage is applied to the resistive random access memory array.
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