CN117729777A

CN117729777A - Resistive random access memory and manufacturing method thereof

Info

Publication number: CN117729777A
Application number: CN202211093778.2A
Authority: CN
Inventors: 许博砚; 吴伯伦
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2022-09-08
Filing date: 2022-09-08
Publication date: 2024-03-19

Abstract

The invention provides a Resistive Random Access Memory (RRAM) and a manufacturing method thereof, which can effectively control the position and shape of a conductive path, thereby improving the uniformity of reliability and efficiency. The RRAM includes a plurality of bottom contact structures formed in a substrate, a plurality of memory cells formed on the substrate, and an insulating structure formed between adjacent memory cells. The memory cell includes a bottom electrode layer, two L-shaped resistive switching layers, a plurality of oxygen ion diffusion barrier layers, and a top electrode layer. The bottom electrode layer is formed on one of the bottom contact structures. The L-shaped resistance conversion layer comprises a horizontal portion and a vertical portion and is formed on the bottom electrode layer. An oxygen ion diffusion barrier layer is formed on the inner and outer sidewalls of the vertical portion of the L-shaped resistive switching layer. The L-shaped resistance conversion layer is positioned between the top electrode layer and the bottom electrode layer.

Description

Resistive random access memory and manufacturing method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a resistive random access memory and a method for fabricating the same.

Background

In a conventional Resistive Random Access Memory (RRAM), a plurality of memory cells are included in an array region of a chip, and each memory cell includes a patterned bottom electrode layer, a resistive switching layer, and a top electrode layer. When a forming voltage or a writing voltage is applied to the memory cell, oxygen ions are driven by the voltage to leave the resistance conversion layer. The equivalent positive oxygen vacancies left in the resistive switching layer form conductive pathways (or filaments) that in turn switch the resistive switching layer from a High Resistance State (HRS) to a Low Resistance State (LRS). When an erase voltage is applied, the oxygen ions return to the resistive switching layer and combine with the equivalent positive valence oxygen vacancies. Therefore, the conductive path disappears, and the resistance conversion layer is converted from LRS to HRS.

When a write voltage is applied to convert the resistive switching layer to LRS, oxygen ions typically migrate to the oxygen ion storage layer above the resistive switching layer. However, in the conventional RRAM, some oxygen ions may move horizontally and remain in the resistive switching layer. If these oxygen ions left in the resistive switching layer gain energy from a high temperature environment (e.g., a high temperature environment for durability screening), they recombine with oxygen vacancies in adjacent conductive vias. In this way, the resistance value of the low resistance state is increased, that is, low resistance state degradation (LRS degradation) occurs.

On the other hand, when the resistive switching layer is in HRS, if oxygen ions in the resistive switching layer acquire energy from a high temperature environment (e.g., a high temperature environment for durability screening), a portion of the oxygen ions may diffuse in the horizontal direction, leaving oxygen vacancies to form conductive paths. In this way, the resistance value of the high resistance state is reduced, that is, high resistance state degradation (HRS degradation) occurs. When low resistance state degradation or high resistance state degradation occurs, the yield and reliability of the memory device will be reduced.

In the conventional RRAM, each time a voltage is applied, the conductive path in the resistance conversion layer is formed randomly and cannot be controlled, and the resistance value of the resistance conversion layer of the memory cell at a different position is also different when the voltage is applied. Therefore, the reliability and performance uniformity of the memory device are poor.

Disclosure of Invention

The embodiment of the invention provides an RRAM and a manufacturing method thereof, which can increase the yield and reliability of a memory device and improve the uniformity of reliability and efficiency.

An embodiment of the present invention discloses an RRAM comprising: a plurality of bottom contact structures formed in the substrate; a plurality of memory cells formed on a substrate, wherein each of the memory cells comprises: a bottom electrode layer formed on one of the bottom contact structures; two L-shaped resistance conversion layers formed on the bottom electrode layer, wherein each of the L-shaped resistance conversion layers includes a horizontal portion and a vertical portion; a plurality of oxygen ion diffusion barrier layers formed on inner and outer sidewalls of each of the vertical portions of the L-type resistive switching layer; and a top electrode layer, wherein the L-shaped resistance conversion layer and the oxygen ion diffusion barrier layer are positioned between the top electrode layer and the bottom electrode layer; and an insulating structure formed between two adjacent memory cells.

An embodiment of the invention discloses a method for manufacturing RRAM, comprising: forming a plurality of bottom contact structures in the substrate; forming a bottom electrode material on a substrate; forming a sacrificial pattern layer on the bottom electrode material, wherein the sacrificial pattern layer comprises a plurality of first openings; conformally forming a resistive switching material on the sacrificial pattern layer; conformally forming a first oxygen ion diffusion barrier material over the resistive switching material; performing a first planarization process to make the top surface of the first oxygen ion diffusion barrier material, the top surface of the resistance conversion material and the top surface of the sacrificial pattern layer coplanar; removing the sacrificial pattern layer to form a plurality of second openings, wherein the second openings expose the side walls of the resistance conversion material; forming a second oxygen ion diffusion barrier layer on the side wall of the resistance conversion material; forming a top electrode material on the resistance conversion material, the first oxygen ion diffusion barrier material and the second oxygen ion diffusion barrier layer; patterning to form insulating structure openings penetrating the bottom electrode material, the resistance conversion material, the first oxygen ion diffusion barrier material and the top electrode material to define a plurality of memory cells on the substrate; and forming an insulating structure in the insulating structure opening.

In the RRAM provided by the embodiment of the invention, the resistance conversion layer with specific shape (for example, L type and U type) and size is formed. Therefore, the position and the shape of the conductive path can be effectively controlled, and the uniformity of reliability and performance can be further improved. In the RRAM provided by the embodiment of the invention, the oxygen ion diffusion barrier layer is disposed on the inner and outer sidewalls of the vertical portion of the resistive switching layer. The oxygen ion diffusion barrier layer can limit the horizontal movement of oxygen ions in the resistance conversion layer, and can prevent oxygen ions from the insulating layer from entering the resistance conversion layer to influence the number and the size of the conductive paths. In other words, the low resistance state degradation or the high resistance state degradation can be avoided, and the yield and the reliability can be improved.

Drawings

Fig. 1A to 1G are schematic cross-sectional views corresponding to steps in manufacturing an RRAM according to some embodiments of the invention.

Fig. 2 is a schematic cross-sectional view of an RRAM according to other embodiments of the invention.

Fig. 3A and 3B are schematic cross-sectional views corresponding to steps in manufacturing an RRAM according to other embodiments of the present invention.

Fig. 4 is a schematic cross-sectional view of an RRAM according to other embodiments of the invention.

[ symbolic description ]

10 first region

20 second region

100,200,300,400:RRAM

102 substrate

101 bottom contact structure

104 bottom electrode material

104' bottom electrode layer

105 first opening

106 sacrificial pattern layer

108 resistance conversion material

108': resistance conversion layer

108A,108B,108C, resistance-switching layer

110 first oxygen ion diffusion barrier material

110A,110B,110C first oxygen ion diffusion barrier layer

112 first insulating layer

114,114 second oxygen ion diffusion barrier layer

115 second opening

116 second insulating layer

118 third oxygen ion diffusion barrier material

118': third oxygen ion diffusion barrier layer

120 oxygen ion storage material

120' oxygen ion storage layer

122 fourth oxygen ion diffusion barrier material

122': fourth oxygen ion diffusion barrier layer

124 top electrode material

124' top electrode layer

125 third opening

130 insulating structure

132 fifth oxygen ion diffusion barrier layer

W1 first width

W2 second width

W3 third width

W4 fourth width

W5 fifth width

T1 first thickness

T2 second thickness

θ1 included angle

Theta 2 included angle

Detailed Description

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. Furthermore, repeated reference characters and/or words may be used in various examples of the invention. These repeated symbols or words are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structures.

The terms "about" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given herein are about amounts, i.e., without specific recitation, the meaning of "about" may still be implied. In the present specification, "X is equal to or close to Y" means that the absolute value of the difference between the two is within 5.0% of the larger one.

Fig. 1A-1G are schematic cross-sectional views of steps in the fabrication of a Resistive Random Access Memory (RRAM) 100 according to some embodiments of the invention. Referring to fig. 1A, a plurality of bottom contact structures 101 are formed in a substrate 102. The substrate 102 includes a first region 10 and a second region 20, and has a bottom contact structure 101 in each of the first region 10 and the second region 20. In fig. 1A to 1G, the boundary between the first region 10 and the second region 20 is indicated by a dotted line.

The material of the substrate 102 may include bulk semiconductor substrates (e.g., silicon substrates), compound semiconductor substrates (e.g., group IIIA-VA semiconductor substrates), silicon-on-insulator (silicon on insulator, SOI) substrates, and the like. The substrate 102 may be a doped or undoped semiconductor substrate. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the bottom contact structure 101 is a single layer structure formed from a conductive layer, and the conductive layer comprises tungsten, aluminum, copper, silver, other suitable metals, or combinations thereof. In other embodiments, the bottom contact structure 101 is a dual layer structure and includes a liner layer and a conductive layer. The liner layer may improve adhesion of the conductive layer to the substrate 102 and may prevent metal atoms from diffusing into the substrate 102. The material of the liner may comprise titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof.

Next, a bottom electrode material 104 is formed on the substrate 102. The bottom electrode material 104 may comprise titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. Next, a sacrificial pattern layer 106 is formed on the bottom electrode material 104. The sacrificial pattern layer 106 includes a plurality of first openings 105 and a plurality of second openings 115. The first opening 105 and the second opening 115 expose the top surface of the bottom electrode material 104. In the present embodiment, the first opening 105 has a first width W1, and the second opening 115 has a second width W2 that is greater than the first width W1. The sacrificial pattern layer 106 may include a suitable material, for example: nitride, oxide, carbide, oxynitride or polysilicon. In some embodiments, the sacrificial pattern layer 106 is silicon nitride.

Then, the resistance conversion material 108 is conformally formedOn the sacrificial pattern layer 106. The resistive switching material 108 may determine the resistive state of the memory cell. The resistive switching material 108 may comprise a transition metal oxide, for example, alumina (Al _x O _y ) Titanium oxide (Ti) _x O _y ) Nickel oxide (Ni) _x O _y ) Tantalum oxide (Ta) _x O _y ) Hafnium oxide (Hf) _x O _y ) Or zirconia (Zr) _x O _y ). The resistive switching material 108 may be formed using a chemical vapor deposition process, atomic layer deposition, or other suitable deposition process. In some embodiments, the resistive switching material 108 is hafnium oxide (HfO ₂ )。

Next, a first oxygen ion diffusion barrier material 110 is conformally formed over the resistive switching material 108. The first oxygen ion diffusion barrier material 110 may be used to block oxygen ions, making movement of oxygen ions more difficult. Thus, the horizontal movement of oxygen ions can be reduced or avoided. That is, diffusion of oxygen ions from the resistive switching material 108 into the subsequently formed first insulating layer 112 (shown in fig. 1B) may be avoided, and diffusion of oxygen ions from the subsequently formed first insulating layer 112 into the resistive switching material 108 may be avoided. To block the horizontal movement of oxygen ions, the first oxygen ion diffusion barrier material 110 may be different from the resistive switching material 108. The first oxygen ion diffusion barrier material 110 may include aluminum oxide (Al _x O _y ) Titanium oxynitride (Ti) _x O _y N _z ) Titanium oxide (Ti) _x O _y ) Tantalum oxide (Ta) _x O _y ) Hafnium oxide (Hf) _x O _y ) Nickel oxide (Ni) _x O _y ) Zirconia (Zr) _x O _y ) Or a combination of the foregoing. In some embodiments, the first oxygen ion diffusion barrier material 110 is titanium oxynitride (ton). The first oxygen ion diffusion barrier material 110 may be formed using a chemical vapor deposition process, atomic layer deposition, or other suitable deposition process. In some embodiments, the aluminum oxide (Al ₂ O ₃ ) To form the first oxygen ion diffusion barrier material 110.

Referring to fig. 1B, a first insulating layer 112 is formed in the first opening 105 and the second opening 115, and divides the resistive switching material 108 into a plurality of discontinuous resistive switching layers 108A,108B and 108C, and the first oxygen ion diffusion barrier material 110 into a plurality of discontinuous first oxygen ion diffusion barrier layers 110A,110B and 110C. The step of forming the first insulating layer 112 may include forming a first insulating material on the substrate 102 and filling in the first opening 105 and the second opening 115. Next, a planarization process (e.g., a chemical mechanical polishing process) is performed to partially remove the first insulating material, the first oxygen ion diffusion barrier material 110, and the resistance conversion material 108 on the sacrificial pattern layer 106 with the sacrificial pattern layer 106 as a stop layer. The first insulating layer 112 may comprise a suitable insulating material, such as a nitride, oxide, or oxynitride. In some embodiments, the first insulating layer 112 is black diamond. The first insulating layer 112 may be formed using a chemical vapor deposition process, an atomic layer deposition process, a spin-on process, or other suitable deposition process.

Referring to fig. 1C, a first etching process is performed to remove the sacrificial pattern layer 106 and form a plurality of third openings 125. The third opening 125 exposes the sidewalls of the resistive switching layers 108A,108B, 108C. The first etching process may comprise a wet etching process, a dry etching process, or a combination thereof. In order to completely remove the sacrificial pattern layer 106 and avoid damage to the resistive switching material 108, the first oxygen ion diffusion barrier material 110, and the first insulating layer 112, during the first etching process, the etching rate of the sacrificial pattern layer 106 may be greater than the etching rate of the resistive switching material 108, the etching rate of the first oxygen ion diffusion barrier material 110, and the etching rate of the first insulating layer 112. Furthermore, the material of the sacrificial pattern layer 106 may be different from the material of the first insulating layer 112. In some embodiments, in the first etching process, the ratio R1a/R1b of the etching rate R1a of the sacrificial pattern layer 106 to the etching rate R1b of the resistive switching material 108 is 3.0-20.0, and the ratio R1a/R1c of the etching rate R1a of the sacrificial pattern layer 106 to the etching rate R1c of the first oxygen ion diffusion barrier material 110 is 3.0-20.0.

Referring to fig. 1D, a second oxygen ion diffusion barrier 114 is conformally formed in the third opening 125. In the present embodiment, the second oxygen ion diffusion barrier layer 114 formed in the third opening 125 has a U-shaped cross-sectional profile. In the present embodiment, each of the second oxygen ion diffusion barrier layers 114 is formed between adjacent two of the resistive switching layers 108A,108B,108C, so that the inner and outer sidewalls of the resistive switching layers 108A,108B,108C can be covered by the oxygen ion diffusion barrier material (i.e., the first oxygen ion diffusion barrier layer 110A,110B,110C or the second oxygen ion diffusion barrier layer 114), which is beneficial to increase the yield and reliability of the RRAM 100. The material of the second oxygen ion diffusion barrier layer 114 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

Referring to fig. 1E, a second insulating layer 116 is formed on the second oxygen ion diffusion barrier layer 114 to fill the third opening 125. In the present embodiment, the second oxygen ion diffusion barrier layer 114 and the second insulating layer 116 may be planarized independently or simultaneously such that the top surface of the second insulating layer 116, the top surface of the second oxygen ion diffusion barrier layer 114, the top surface of the first insulating layer 112, the top surfaces of the first oxygen ion diffusion barrier layers 110A,110B,110C, and the top surfaces of the resistive switching layers 108A,108B, and 108C are coplanar. The material of the second insulating layer 116 may be the same or similar to the material of the first insulating layer 112.

In addition, in order to reduce stress between the resistance conversion material 108 and the oxygen ion diffusion barrier material (e.g., the material of the first oxygen ion diffusion barrier layers 110A,110B,110C or the material of the second oxygen ion diffusion barrier layer 114), the material of the second insulating layer 116 may be different from the material of the sacrificial pattern layer 106. In this embodiment, the second insulating layer 116 is black diamond. In other embodiments, the second insulating layer 116 is an oxide and is a different material than the first insulating layer 112.

Referring to fig. 1F, a third oxygen ion diffusion barrier material 118, an oxygen ion storage material 120, a fourth oxygen ion diffusion barrier material 122, and a top electrode material 124 are sequentially formed on the substrate 102.

The third oxygen ion diffusion barrier material 118 may be used to reduce or avoid vertical movement of oxygen ions. More specifically, in the high resistance state, the third oxygen ion diffusion barrier material 118 may prevent oxygen ions from diffusing from the resistive switching layers 108A,108B, and 108C into the oxygen ion storage material 120 to maintain the stability of the high resistance state. On the other hand, in the low resistance state, the third oxygen ion diffusion barrier material 118 can prevent oxygen ions from diffusing from the oxygen ion storage material 120 into the resistive switching layers 108A,108B, and 108C to maintain the stability of the low resistance state. To block the vertical movement of oxygen ions, the third oxygen ion diffusion barrier material 118 may be different from the resistive switching material 108. The third oxygen ion diffusion barrier material 118 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

When a forming voltage or a writing voltage is applied to the RRAM 100, the oxygen ion storage material 120 can be used to store oxygen ions from the resistive switching layers 108A,108B, and 108C. When an erase voltage is applied to the RRAM 100, oxygen ions stored in the oxygen ion storage material 120 may be driven back into the resistive switching layers 108A,108B, and 108C. Oxygen ion storage material 120 may comprise titanium (Ti), tantalum (Ta), hafnium (Hf), zirconium (Zr). In some embodiments, the material of the oxygen ion storage material 120 is titanium.

The fourth oxygen ion diffusion barrier material 122 may be used to reduce or avoid vertical movement of oxygen ions. More specifically, in the low resistance state, the fourth oxygen ion diffusion barrier material 122 may prevent oxygen ions from diffusing from the oxygen ion storage material 120 into the top electrode material 124. Therefore, oxidation of the top electrode material 124 may be avoided, thereby improving performance and yield of the memory device. The fourth oxygen ion diffusion barrier material 122 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

The top electrode material 124 may comprise titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. In some embodiments, the bottom electrode material 104 is titanium and the top electrode material 124 is titanium nitride. In other embodiments, the bottom electrode material 104 is titanium nitride and the top electrode material 124 is titanium.

Referring to fig. 1G, a patterning process is performed to form a plurality of memory cells on a substrate 102. Next, an insulating structure 130 is formed between two adjacent memory cells. Specifically, a suitable dry etching process (e.g., a plasma etching process) may be performed to form openings (or trenches) through the bottom electrode material 104, the resistive switching material 108 (e.g., portions of the resistive switching layers 108A and 108C), the first oxygen ion diffusion barrier material 110 (e.g., portions of the first oxygen ion diffusion barrier layers 110A and 110C), the first insulating layer 112, the third oxygen ion diffusion barrier material 118, the oxygen ion storage material 120, the fourth oxygen ion diffusion barrier material 122, and the top electrode material 124 at the interfaces between the different regions (e.g., the first region 10 and the second region 20), and to form the bottom electrode layer 104', the third oxygen ion diffusion barrier layer 118', the oxygen ion storage layer 120', the fourth oxygen ion diffusion barrier layer 122', and the top electrode layer 124'. Then, an insulating material is filled into the opening. Next, a planarization process is performed to remove excess insulating material located on top electrode layer 124' to form insulating structure 130. The material and forming method of the insulating structure 130 may be the same as or similar to the material and forming method of the first insulating layer 112.

In the present embodiment, the resistive switching material 108 in the second opening 115 is patterned to form two mirror-symmetrical L-shaped structures (i.e., the L-shaped resistive switching layer 108C in the first region 10 and the L-shaped resistive switching layer 108A in the second region 20). Similarly, the first oxygen ion diffusion barrier material 110 in the second opening 115 is also patterned to form two mirror-symmetrical L-shaped structures (i.e., an L-shaped first oxygen ion diffusion barrier layer 110C in the first region 10 and an L-shaped first oxygen ion diffusion barrier layer 110A in the second region 20).

Thereafter, other conventional processes (e.g., contact structures may be formed on top electrode layer 124') may be performed to complete RRAM 100, which will not be described in detail herein.

Referring to fig. 1G, in some embodiments, the RRAM 100 includes a plurality of bottom contact structures 101 formed in a substrate 102, a plurality of memory cells formed on the substrate 102, and an insulating structure 130 formed between two adjacent memory cells. Each memory cell is located in the first region 10 or the second region 20 and includes a bottom electrode layer 104', a resistive switching layer (e.g., 108A,108B, and 108C), a first oxygen ion diffusion barrier layer (e.g., 110A,110B, and 110C), a third oxygen ion diffusion barrier layer 118', an oxygen ion storage layer 120', a fourth oxygen ion diffusion barrier layer 122', and a top electrode layer 124' sequentially formed on the substrate 102. In addition, each memory cell also includes a U-shaped second oxygen ion diffusion barrier 114 between adjacent resistive switching layers 108A,108B, 108C. By applying voltages to the bottom electrode layer 104 'and the top electrode layer 124', the resistive switching layers 108A,108B,108C can be switched to different resistive states.

In the present embodiment, the resistance conversion layers 108A and 108C are L-shaped, and the resistance conversion layer 108B is U-shaped. The U-shaped resistive switching layer 108B includes two vertical portions and a horizontal portion. The L-shaped resistive switching layer 108A or 108C includes a vertical portion and a horizontal portion. In the first region 10, the horizontal portion of the resistance conversion layer 108A extends from the vertical portion thereof toward a direction away from the center of the memory cell, and the horizontal portion of the resistance conversion layer 108C extends from the vertical portion thereof toward a direction away from the center of the memory cell. That is, the horizontal portions of the resistance-converting layer 108A and the resistance-converting layer 108C are located on opposite sides of the vertical portion thereof, respectively. In other words, the resistance conversion layers 108A and 108C in the same memory cell are horizontally arranged in a back-to-back manner.

In some embodiments, the length of the horizontal portion of the resistive switching layer 108A is different from the length of the horizontal portion of the resistive switching layer 108C. In other embodiments, the length of the horizontal portion of the resistive switching layer 108A is the same as the length of the horizontal portion of the resistive switching layer 108C, i.e., the resistive switching layer 108A and the resistive switching layer 108C are mirror images of each other.

In the present embodiment, the first oxygen ion diffusion barrier layers 110A and 110C are L-shaped, and the first oxygen ion diffusion barrier layer 110B is U-shaped. The first oxygen ion diffusion barrier layer 110A is formed on the groove formed by the resistance conversion layer 108A, the first oxygen ion diffusion barrier layer 110B is formed on the groove formed by the resistance conversion layer 108B, and the first oxygen ion diffusion barrier layer 110C is formed on the groove formed by the resistance conversion layer 108C. First oxygen ion diffusion barrier layers (110A, 110B, 110C) and second oxygen ion diffusion barrier layers 114 are formed on the inner and outer sidewalls of the vertical portions of the respective resistive switching layers 108A,108B,108C, respectively.

A bottom electrode layer 104' is formed on one of the bottom contact structures 101. In the present embodiment, between the top electrode layer 124 'and the bottom electrode layer 104', there are one resistance-switching layer 108A with an L-shaped cross-sectional profile, two resistance-switching layers 108B with a U-shaped cross-sectional profile, one resistance-switching layer 108C with an L-shaped cross-sectional profile, and a plurality of second oxygen ion diffusion barrier layers 114 with a U-shaped cross-sectional profile. More specifically, the resistive switching layers 108A,108B,108C, the first oxygen ion diffusion barrier layers 110A,110B,110C, and the second oxygen ion diffusion barrier layer 114 are located in an overlapping region of the vertical projection of the top electrode layer 124 'and the vertical projection of the bottom electrode layer 104'.

In the method for manufacturing the RRAM 100 provided in the embodiment, the position and shape of the conductive path can be effectively controlled by controlling the shape and size of the resistance conversion layer, so as to improve the reliability and uniformity of the performance of the memory device.

In more detail, referring to fig. 1G, specifically, when a voltage is applied, the resistive switching layers 108A,108B, and 108C of the present embodiment are capable of confining the conductive paths in the vertical portions of the respective resistive switching layers 108A,108B, and 108C, relative to the conventional planar resistive switching layers. In other words, by forming the resistance conversion layers 108A,108B, and 108C, the position and shape of the conductive path can be effectively controlled. In this way, the reliability and uniformity of performance of the RRAM 100 can be improved. In some embodiments, the top surface of the vertical portion of each of the resistive switching layers 108A,108B, and 108C has a height that is betweenIs shown in fig. 1E).

On the other hand, in the present embodiment, the inner and outer sidewalls of the vertical portion of each of the resistance conversion layers 108A,108B, and 108C are covered with the oxygen ion diffusion barrier layer. Therefore, when a voltage is applied, the horizontal movement of oxygen ions can be greatly reduced or avoided, and oxygen ions from the insulating layers (i.e., the first insulating layer 112 and the second insulating layer 116) can be prevented from entering the resistance conversion layer, thereby affecting the number and size of the conductive paths. In other words, the resistance values of the high-resistance state and the low-resistance state can be easily expected and controlled by the resistance conversion layers 108A,108B, and 108C, the first oxygen ion diffusion barrier layers 110A,110B, and 110C, and the second oxygen ion diffusion barrier layer 114 of the present embodiment. In this way, low resistance state degradation or high resistance state degradation can be avoided, and the yield and reliability of the RRAM 100 can be improved.

To avoid oxygen ions entering or exiting the vertical portions of the resistive switching layers 108A,108B, and 108C horizontally, referring to fig. 1E, in some embodiments, the top surfaces of the vertical portions of each of the first oxygen ion diffusion barrier layers 110A,110B, and 110C have a fourth width W4, and the fourth width W4 is 10-50nm. The top surface of the vertical portion of the second oxygen ion diffusion barrier layer 114 has a fifth width W5, and the fifth width W5 is 10-50nm. In other embodiments, materials with high oxygen ion barrier capability may be selected to form the first oxygen ion diffusion barrier layers 110A,110B, and 110C and the second oxygen ion diffusion barrier layer 114, so that the fourth width W4 and the fifth width W5 may be reduced, which is advantageous for miniaturization of the RRAM 100.

Referring to fig. 1F, in the present embodiment, the third oxygen ion diffusion barrier material 118 and the fourth oxygen ion diffusion barrier material 122 may have a smaller thickness relative to the thicknesses of the vertical portions of the first oxygen ion diffusion barrier layers 110A,110B, and 110C and the second oxygen ion diffusion barrier layer 114. This may facilitate movement (i.e., vertical movement) of oxygen ions between the oxygen ion storage layer 120' and the resistive switching layers 108A,108B, and 108C. On the other hand, to further avoid the oxygen ions from diffusing differently than expected, the third oxygen ion diffusion barrier material 118 may have a first thickness T1 between 1 and 5nm, and the fourth oxygen ion diffusion barrier material 122 may have a second thickness T2 between 1 and 5 nm.

In other embodiments, more first openings 105 may be formed in the first region 10, so that the memory cells in the first region 10 may have more U-shaped resistance-switching layers 108B. Thus, the area available for forming the conductive path may be increased. In this way, the performance and yield of the RRAM 100 can be further improved.

Referring to fig. 1G, top surfaces of the resistive switching layers 108A,108B, and 108C are coplanar, and bottom surfaces of the resistive switching layers 108A,108B, and 108C are coplanar. By the resistive switching layers 108A,108B, and 108C each including oxygen ions in a horizontal portion that is electrically connected to the bottom electrode layer 104', some of the oxygen ions can enter a vertical portion from the horizontal portion of the resistive switching layers 108A,108B, and 108C when an erase voltage is applied. Therefore, it is easier to recombine all oxygen vacancies with oxygen ions. In this way, the reset efficiency can be improved, and the performance of the RRAM 100 can be further improved.

Referring to fig. 1A, in the present embodiment, since the second opening 115 has the second width W2 greater than the first width W1, after the insulating structure 130 is formed, the L-type resistance conversion layer 108C located in the first region 10 and the L-type resistance conversion layer 108A located in the second region 20 can still remain with the horizontal portion having the proper length to store oxygen ions. It should be understood that the number and size of the first openings 105 and the second openings 115 shown in fig. 1A are only for illustration, and are not intended to limit the present invention.

Referring to fig. 1A, an included angle θ1 is formed between the bottom and the sidewall of the sacrificial pattern layer 106. Since the resistance conversion material 108 and the first oxygen ion diffusion barrier material 110 are conformally formed on the sacrificial pattern layer 106, the bottom and the sidewalls of the first opening 105 and the second opening 115 have an angle θ2 substantially complementary to the angle θ1. To facilitate filling the first insulating layer 112 into the first opening 105 and the second opening 115, the included angle θ2 is, in some embodiments, 75 degrees to 105 degrees. Furthermore, referring to fig. 1C, since the position and the shape of the third opening 125 correspond to the sacrificial pattern layer 106, an included angle θ1 is formed between the bottom and the sidewall of the third opening 125. To facilitate filling the second insulating layer 116, the second oxygen ion diffusion barrier 114, or the second oxygen ion diffusion barrier 114 (shown in fig. 3B and 4) into the third opening 125, the included angle θ2 is, in some embodiments, 75 to 105 degrees. Referring to fig. 1A, in the present embodiment, the sidewalls of the sacrificial pattern layer 106 are substantially perpendicular to the surface of the bottom electrode material 104. In other words, the included angle θ1 and the included angle θ2 are both about 90 degrees.

It should be noted that, in the present specification, the "L-shape" may include "L-shape" and "L-like shape", and the "U-shape" may include "U-shape" and "U-like shape". In other words, when the included angle θ1 is 75 to 105 degrees, the formed resistive switching layers 108A, 108C and the first oxygen ion diffusion barrier layers 110A and 110C can be regarded as having an "L-shaped" cross-sectional profile. Similarly, when the included angle θ2 is 75 ° to 105 °, the formed resistive switching layer 108B, the first oxygen ion diffusion barrier layer 110B, and the second oxygen ion diffusion barrier layer 114 can be regarded as having a cross-sectional profile of "U-shape".

In the present embodiment, the second insulating layer 116 is removed and the top surfaces of the resistive switching layers 108A,108B,108C are exposed not by an etching process (e.g., a plasma etching process) but by a planarization process. This prevents the top surfaces of the resistive switching layers 108A,108B,108C from being damaged during the etching process. Therefore, the performance and yield of the RRAM 100 can be further improved.

The RRAM 200 depicted in FIG. 2 is similar to the RRAM 100 depicted in FIG. 1G, except that the RRAM 200 of FIG. 2 further comprises a fifth oxygen ion diffusion barrier 132. For simplicity of illustration, the device and its process steps that are identical to those depicted in fig. 1G are not described in detail herein.

Referring to fig. 2, the fifth oxygen ion diffusion barrier 132 has a U-shaped cross-sectional profile, and the insulating structure 130 fills the recess formed by the fifth oxygen ion diffusion barrier 132. In the process of fig. 1G, after forming openings or trenches at the interfaces between the different regions (e.g., the first region 10 and the second region 20), an oxygen ion diffusion barrier material may be conformally formed over the memory cells. Then, an insulating material is filled into the opening or the trench. Next, a planarization process is performed to remove the excess insulating material and oxygen ion diffusion barrier material on top electrode layer 124' to form insulating structure 130 and fifth oxygen ion diffusion barrier layer 132. The material and thickness of the fifth oxygen ion diffusion barrier layer 132 may be the same as or similar to the first oxygen ion diffusion barrier material 110 and its thickness.

In the first region 10, a fifth oxygen ion diffusion barrier layer 132 is formed between the horizontal portion of the resistance conversion layer 108C and the insulating structure 130. In the second region 20, a fifth oxygen ion diffusion barrier layer 132 is formed between the horizontal portion of the resistive switching layer 108A and the insulating structure 130. The fifth oxygen ion diffusion barrier 132 may prevent oxygen ions from diffusing from the insulating structure 130 into the resistive switching layer 108C located in the first region 10 and into the resistive switching layer 108A located in the second region 20. Therefore, the performance and yield of the RRAM 200 can be further improved.

Fig. 3A and 3B are similar to fig. 1D and 1G, respectively. The RRAM 300 depicted in fig. 3B is similar to the RRAM 100 depicted in fig. 1G, except that the cross-sectional profile of the second oxygen ion diffusion barrier layer 114 of fig. 3B is different from the cross-sectional profile of the second oxygen ion diffusion barrier layer 114 of fig. 1G. For simplicity of illustration, the same devices, process steps and advantages as those depicted in fig. 1G are not described in detail herein.

The position of the top surface of the second oxygen ion diffusion barrier 114 may be controlled by adjusting the duration of the planarization process. As shown in fig. 3A, after the planarization process, the top surface of the second oxygen ion diffusion barrier layer 114 is higher than the top surfaces of the first insulating layer 112, the first oxygen ion diffusion barrier layers 110A,110B, and 110C, and the top surfaces of the resistive switching layers 108A,108B, and 108C. The material of the second oxygen ion diffusion barrier layer 114 may be the same as or similar to the material of the second oxygen ion diffusion barrier layer 114.

In this embodiment, the second oxygen ion diffusion barrier layer 114 is formed to completely fill the third opening 125. The second oxygen ion diffusion barrier layer 114 is thermally conductive over the second insulating layer 116. Therefore, the heat dissipation capability of the memory cell can be improved, thereby improving the performance of the RRAM 300. Furthermore, the forming step and the planarization step of the second insulating layer 116 may be omitted in this embodiment. Therefore, the manufacturing method provided by the embodiment can simplify the process and reduce the time and cost for production.

The RRAM 400 depicted in FIG. 4 is similar to the RRAM 300 depicted in FIG. 3B, except that the RRAM 400 of FIG. 4 further comprises a fifth oxygen ion diffusion barrier 132. For simplicity of illustration, the same devices, process steps and advantages as those illustrated in fig. 3B are not described in detail herein.

By forming the fifth oxygen ion diffusion barrier layer 132, oxygen ions can be prevented from diffusing from the insulating structure 130 into the L-shaped resistance conversion layer 108C located in the first region 10 and into the L-shaped resistance conversion layer 108A located in the second region 20. Therefore, the performance and yield of the RRAM 400 can be further improved.

In summary, in the method for manufacturing the RRAM according to the embodiment of the invention, the sacrificial pattern layer is formed, so that the plurality of L-type resistance conversion layers and the plurality of U-type resistance conversion layers can be formed between the top electrode layer and the bottom electrode layer of the same memory cell. The L-shaped resistance conversion layer and the vertical part of the U-shaped resistance conversion layer can effectively control the position and the shape of the conductive path. Thus, the reliability and the uniformity of the performance of the RRAM can be improved.

Furthermore, the horizontal portions of the L-type and U-type resistance conversion layers can store part of oxygen ions. In this way, the reset efficiency can be improved, and the performance of the RRAM can be further improved. In the method for manufacturing the RRAM provided by the embodiment of the invention, the number and the size of the resistance conversion layers with specific shapes can be controlled by controlling the shape and the size of the sacrificial pattern layer and the process condition for depositing the resistance conversion layers. Thus, the flexibility of the process is high.

In addition, in the RRAM provided by the embodiment of the invention, the oxygen ion diffusion barrier layer is provided on the inner and outer sidewalls of the vertical portion of the resistance conversion layer. The horizontal movement of oxygen ions in the resistance conversion layer can be restricted. Therefore, occurrence of low resistance state degradation or high resistance state degradation can be avoided. In this way, the yield and reliability of RRAM can be improved. In addition, the manufacturing method provided by the embodiment of the invention can be easily integrated into the existing RRAM process.

Although the present invention has been described with respect to several preferred embodiments, it should be understood by those skilled in the art that the present invention is not limited thereto, and that various changes and modifications can be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A resistive random access memory, comprising:

a plurality of bottom contact structures formed in the substrate;

a plurality of memory cells formed on the substrate, wherein each of the memory cells comprises:

a bottom electrode layer formed on one of the bottom contact structures;

two L-shaped resistance conversion layers formed on the bottom electrode layer, wherein each of the L-shaped resistance conversion layers includes a horizontal portion and a vertical portion;

a plurality of oxygen ion diffusion barrier layers formed on inner and outer sidewalls of each of the vertical portions of the L-type resistive switching layer; and

A top electrode layer, wherein the L-shaped resistive switching layer and the oxygen ion diffusion barrier layer are located between the top electrode layer and the bottom electrode layer; and

and an insulating structure formed between two adjacent memory cells.

2. The resistive random access memory of claim 1, wherein in each of the memory cells, the horizontal portion of each of the L-shaped resistive switching layers extends from the vertical portion toward a direction away from a center of the memory cell.

3. The resistive random access memory of claim 1 wherein each of said memory cells further comprises:

and at least one U-shaped resistance conversion layer formed on the bottom electrode layer and located between the L-shaped resistance conversion layers, wherein the U-shaped resistance conversion layer is located between the top electrode layer and the bottom electrode layer.

4. The resistive random access memory of claim 3, wherein a top surface of the U-shaped resistive switching layer is coplanar with a top surface of the L-shaped resistive switching layer and a bottom surface of the U-shaped resistive switching layer is coplanar with a bottom surface of the L-shaped resistive switching layer.

5. The resistive random access memory of claim 3 wherein the U-shaped resistive switching layer comprises two vertical portions and one horizontal portion, and the oxygen ion diffusion barrier layer is also formed on the inner and outer sidewalls of each of the vertical portions of the U-shaped resistive switching layer.

6. The resistive random access memory of claim 3 wherein in each of said memory cells, said oxygen ion diffusion barrier layer between one of said L-shaped resistive switching layers and said U-shaped resistive switching layer has a U-shaped cross-sectional profile.

7. The resistive random access memory of claim 5 wherein a space between one of the L-shaped resistive switching layers and the U-shaped resistive switching layer is completely filled with the oxygen ion diffusion barrier layer.

8. The resistive random access memory of claim 1, further comprising:

and the U-shaped oxygen ion diffusion barrier layer is used for filling the groove formed by the U-shaped oxygen ion diffusion barrier layer with the insulating structure.

9. The resistive random access memory of claim 1 wherein a top surface of the vertical portion of each of the L-shaped resistive switching layers has a height betweenIs a width of (c).

10. The resistive random access memory of claim 1, wherein a top surface of the oxygen ion diffusion barrier layer on a sidewall of the vertical portion of the L-shaped resistive switching layer has a first width, and the first width is 10-50nm.

11. The resistive random access memory of claim 1, comprising:

a third oxygen ion diffusion barrier layer formed on the oxygen ion diffusion barrier layer and the L-shaped resistance conversion layer;

an oxygen ion storage layer formed on the third oxygen ion diffusion barrier layer; and

A fourth oxygen ion diffusion barrier layer formed on the oxygen ion storage layer,

wherein the top electrode layer is formed on the fourth oxygen ion diffusion barrier layer.

12. A method of manufacturing a resistive random access memory, comprising:

forming a plurality of bottom contact structures in the substrate;

forming a bottom electrode material on the substrate;

forming a sacrificial pattern layer on the bottom electrode material, wherein the sacrificial pattern layer comprises a plurality of first openings;

conformally forming a resistive switching material on the sacrificial pattern layer;

conformally forming a first oxygen ion diffusion barrier material over the resistive switching material;

performing a first planarization process to make the top surface of the first oxygen ion diffusion barrier material, the top surface of the resistance conversion material, and the top surface of the sacrificial pattern layer coplanar;

removing the sacrificial pattern layer to form a plurality of second openings, wherein the second openings expose the side walls of the resistance conversion material;

forming a second oxygen ion diffusion barrier layer on the side wall of the resistance conversion material;

forming a top electrode material on the resistance conversion material, the first oxygen ion diffusion barrier material and the second oxygen ion diffusion barrier layer;

patterning to form insulating structure openings through the bottom electrode material, the resistive switching material, the first oxygen ion diffusion barrier material and the top electrode material to define a plurality of memory cells on the substrate;

an insulating structure is formed in the insulating structure opening.

13. The method of manufacturing a resistive random access memory of claim 12, wherein each of the memory cells comprises:

a bottom electrode layer formed on one of the bottom contact structures;

a top electrode layer, wherein the L-shaped resistive switching layer and the oxygen ion diffusion barrier layer are located between the top electrode layer and the bottom electrode layer.

14. The method of claim 12, wherein forming the second oxygen ion diffusion barrier layer comprises:

the second oxygen ion diffusion barrier layer is conformally formed over the resistive switching material and in the second opening.

15. The method of manufacturing a resistive random access memory of claim 14, comprising:

forming a first insulating material to fill the first opening after forming the first oxygen ion diffusion barrier material;

forming a second insulating material to fill the second opening after forming the second oxygen ion diffusion barrier layer; and

a second planarization process is performed to co-plane a top surface of the first oxygen ion diffusion barrier material, a top surface of the second oxygen ion diffusion barrier layer, a top surface of the resistive switching material, a top surface of the first insulating material, and a top surface of the second insulating material.

16. The method of manufacturing a resistive random access memory according to claim 15, wherein a material of the sacrificial pattern layer is different from the first insulating material, and a material of the sacrificial pattern layer is different from the second insulating material.

17. The method of claim 12, wherein forming the second oxygen ion diffusion barrier layer comprises:

and forming the second oxygen ion diffusion barrier layer to completely fill the second opening.

18. The method of manufacturing a resistive random access memory of claim 17, comprising:

forming a first insulating material to fill the first opening after forming the first oxygen ion diffusion barrier material; and

a second planarization process is performed to planarize a top surface of the second oxygen ion diffusion barrier layer, wherein after the second planarization process, the top surface of the second oxygen ion diffusion barrier layer is higher than the top surface of the first oxygen ion diffusion barrier material and the top surface of the resistive switching material.