CN104733608A - Resistive memory and manufacturing method thereof - Google Patents
Resistive memory and manufacturing method thereof Download PDFInfo
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- CN104733608A CN104733608A CN201310699111.1A CN201310699111A CN104733608A CN 104733608 A CN104733608 A CN 104733608A CN 201310699111 A CN201310699111 A CN 201310699111A CN 104733608 A CN104733608 A CN 104733608A
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Abstract
The invention provides a resistive memory and a manufacturing method thereof. The memory comprises a substrate, a stack, a resistance state transition layer, multiple second electrode pairs, a first contact plug and multiple second contact plugs, wherein the stack comprises a first insulated layer, a first electrode, and a second insulated layer; the resistance state transition layer compliantly covers the stack and the substrate; each of the multiple second electrode pairs comprises two second electrodes which respectively compliantly cover the substrate of opposite side walls and opposite edges of the resistance state transition layer; the first contact plug is arranged between the multiple second electrode pairs and is electrically connected with the first electrode; and each of the multiple second contact plugs is respectively electrically connected with each second electrode. Thus, the area of an element in the resistive memory can be narrowed, and capacity of the memory is increased.
Description
Technical field
The present invention has about resistance-type memory and manufacture method thereof, and relates to a kind of resistance-type memory and the manufacture method thereof with the contact plunger be located between electrode pair especially.
Background technology
Popular (such as mobile phone, digital camera, the notebook computer etc.) of portable electronic product impel the use amount of memory to increase in recent years.Generally speaking, memory component can be divided into two large classes usually, i.e. volatile memory and nonvolatile memory (non-volatile memory) two kinds.Volatile memory refers to that the data in memory need rely on routinely power supply supply and could maintain and preserve, even and if nonvolatile memory power interruptions, still can keep the data of memory inside.And in various nonvolatile memory, generally all using can no write de-lay and the flash memory (flash RAM) of erasing.
But each memory block only can be erased certain number of times in flash memory.When the number of times of erasing of a memory block is more than a critical value, this memory block cannot be correctly written, and may make a mistake when reading out data by this memory block.And constantly reduce along with element, flash memory also faces excessive write voltage, long write time and grid gradually and crosses thin and predicament that is that cause shorten memory time.
In order to overcome aforesaid drawbacks, each side constantly makes great efforts in developing new nonvolatile memory to replace flash memory, wherein resistance-type memory (resistive random access memory, RRAM) one of numerous novel memory developed for current industry, it utilizes variable-resistance principle to make nonvolatile memory, there is write erase time short, operating voltage and electric current low, memory time is long, multimode stores, structure is simple, the write simplified and playback mode and the advantage such as required area is little, it is a kind of potential product, be subject to the attention of all circles.Therefore, and how further to reduce the area of element in resistance-type memory and increase the capacity of memory, especially the industry target that need develop at present.
Summary of the invention
The technical problem to be solved in the present invention is: provide a kind of resistance-type memory and manufacture method thereof, to solve the defect in prior art existing for nonvolatile memory.
The scheme that the present invention solves the problems of the technologies described above comprises: provide a kind of resistance-type memory, comprises a substrate; One is stacking, and this is stacking comprises the first insulating barrier, the first electrode and the second insulating barrier; Resistance transition layer, compliance is covered in stacking with in substrate; Multiple second electrode pair, above-mentioned second electrode pair respectively has two the second electrodes, and compliance is covered in the opposite side walls of resistance transition layer and the substrate of opposite edge respectively; First contact plunger, to be located between multiple second electrode pair and electrical connection the first electrode; And multiple second contact plunger, be electrically connected above-mentioned each second electrode respectively.
The present invention also provides a kind of manufacture method of resistance-type memory, comprising: provide a substrate; Being formed one is stacked in substrate, stackingly comprises the first insulating barrier, the first electrode and the second insulating barrier; Form a resistance transition layer, this resistance transition layer compliance is covered in stacking with in substrate; Form multiple second electrode pair, above-mentioned second electrode pair respectively has two the second electrodes, and compliance is covered in the opposite side walls of resistance transition layer and the substrate of opposite edge respectively; Form the first contact plunger between multiple second electrode pair, this first contact plunger is electrically connected the first electrode; And forming multiple second contact plunger, above-mentioned second contact plunger is electrically connected above-mentioned each second electrode respectively.
Because the first contact plunger of the present invention is located between multiple second electrode pair, its do not need to occupy stacking beyond area, therefore the space shared by memory component can be reduced, further this memory component of microminiaturization increase the capacity of this resistance-type memory.In addition, the present invention is the same with general resistance-type memory technique, all use three road Patternized technique steps, therefore manufacture method of the present invention does not increase extra process costs, can reach the object increasing memory span.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate institute's accompanying drawings, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the stereogram of the resistance-type memory according to the embodiment of the present invention;
Fig. 2,3,4A, 4B, 5A, 5B, 6,7 be resistance-type memories of drawing according to the embodiment of the present invention in the profile of each operation stage or stereogram.
Main element label declaration
Embodiment
Elaborate for resistance-type memory of the present invention below.Describing it is to be understood that provides many different embodiments or example, in order to implement different pattern of the present invention.The specific element of the following stated and arrangement mode are to the greatest extent for simply to describe the present invention.Certainly, these are only in order to illustrate but not restriction of the present invention.In addition, label or the sign of repetition may be used in different embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any association.Moreover, when address one first material layer to be positioned on one second material layer or on time, comprise the situation that the first material layer directly contacts with the second material layer.Or, be also separated with the situation of other material layer one or more between possibility, in this case, may not directly contact between the first material layer with the second material layer.
At this, term " about ", " approximately " ordinary representation, within 20% of a set-point or scope, are preferably within 10%, and better be within 5%.Be about quantity in this given quantity, represent when not having certain illustrated, it can imply the term of " about ", " approximately ".
Unless otherwise defined, as used herein all term (comprising technology and scientific words) have a section therewith disclose belonging to the identical connotation usually understood of general those skilled in the art.Accessible is these terms, the term such as defined in normally used dictionary, should be interpreted to and there is a meaning consistent with the background of correlation technique and this exposure or context, and mode that should be idealized or excessively informal with one is understood, unless defined especially at this.
The manufacture method of resistance-type memory provided by the invention, is located between electrode pair by a contact plunger, to reduce the space shared by it, reaches microminiaturization and the object of increase memory span.In addition, the present invention also by an electrode layer pattern to form electrode pair, to increase the memory span of resistance-type memory of the present invention.
Fig. 1 is the stereogram of the resistance-type memory of the embodiment of the present invention.As shown in FIG., resistance-type memory 100 comprises substrate 110, stacking 120, and this stacking 120 comprises the first insulating barrier 130, first electrode 140 and the second insulating barrier 150.Resistance-type memory 100 also comprises resistance transition layer 160, multiple second electrode pair 180, first contact plunger 200, multiple second contact plunger 210.Resistance transition layer 160 compliance is covered in stacking 120 with in substrate 110.Second electrode pair 180 respectively has two second electrodes 175A, 175B, compliance is covered in the opposite side walls of resistance transition layer 160 and the substrate 110 of opposite edge respectively, and the first contact plunger 200 is located between multiple second electrode pair 180 and electrical connection the first electrode 140.The manufacture method of this resistance-type memory 100 will be described in detail below.
First, see Fig. 2, provide substrate 110, this substrate 110 can be silicon base, silicon-Germanium base, other semiconducting compound substrate, silicon-on-insulator (SOI) or other any applicable substrate.In one embodiment, substrate can be through cleaned silicon base.It should be noted, below " substrate " one word can comprise established element on semiconductor wafer and the various retes covered on wafer.
Continue see Fig. 2, form the first insulating barrier 130 in substrate 110.First insulating barrier 130 can use high temperature furnace pipe oxidizing process or chemical vapour deposition technique to be formed.Such as, the first insulating barrier 130 can be and uses high temperature furnace pipe oxidizing process to grow up in silicon base silicon oxide film.Or, the first insulating barrier 130 can be use chemical vapour deposition (CVD) (CVD) method to be formed silicon oxide layer, silicon nitride layer, silicon oxynitride layer or other any applicable insulating barrier or above-mentioned combination.Chemical vapour deposition technique such as can be Low Pressure Chemical Vapor Deposition (low pressure chemical vapordeposition, LPCVD), low temperature chemical vapor deposition method (low temperature chemical vapor deposition, LTCVD), be rapidly heated chemical vapour deposition technique (rapid thermal chemical vapor deposition, RTCVD), plasma auxiliary chemical vapor deposition method (plasma enhanced chemical vapor deposition, PECVD), atomic layer deposition method (the atomic layer deposition of atomic layer chemical vapor deposition method, or other conventional method ALD).In one embodiment, the first insulating barrier 130 can be the tetraethyl orthosilicate salt silicon dioxide layer formed with chemical vapour deposition (CVD).The thickness of the first insulating barrier 130 is about 10nm to about 500nm, such as, be about 50nm to about 300nm.
Then, continue see Fig. 2, form the first electrode 140 on the first insulating barrier 130.The material of this first electrode 140 can be TaN, TiN, TiAlN, TiW, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni or above-mentioned combination.This first electrode 140 can use sputtering method, resistive heating evaporation, e-beam evaporation or other depositional mode be applicable to be formed.The thickness of the first electrode 140 is about 1nm to about 100nm, such as, be about 1nm to about 50nm.
Then, on the first electrode 140, the second insulating barrier 150 is formed.Second insulating barrier 150 can be use chemical vapour deposition (CVD) (CVD) method to be formed silicon oxide layer, silicon nitride layer, silicon oxynitride layer or other any applicable insulating barrier or above-mentioned combination.Chemical vapour deposition technique such as can be Low Pressure Chemical Vapor Deposition (low pressurechemical vapor deposition, LPCVD), low temperature chemical vapor deposition method (low temperature chemicalvapor deposition, LTCVD), be rapidly heated chemical vapour deposition technique (rapid thermal chemical vapordeposition, RTCVD), plasma auxiliary chemical vapor deposition method (plasma enhanced chemical vapordeposition, PECVD), atomic layer deposition method (the atomic layer deposition of atomic layer chemical vapor deposition method, or other conventional method ALD).In one embodiment, the second insulating barrier 150 can be the tetraethyl orthosilicate salt silicon dioxide layer formed with chemical vapour deposition (CVD).The thickness of the second insulating barrier 150 is about 10nm to about 500nm, such as, be about 50nm to about 300nm.
Then, see Fig. 3, the first patterning step patterning first insulating barrier 130, first electrode 140 and the second insulating barrier 150 is carried out to form stacking 120.Patterning can comprise micro-shadow and etch process with the step forming stacking 120.In one embodiment, lithography process comprises photoresist patterned, this photoresist patterned more comprises photoresist coating, soft roasting, photomask alignings, exposing patterns, expose to the sun after roasting (post-exposure baking), photoresist developing and the processing step such as firmly to bake.This etching step can comprise reactive ion etching (reactive ion etch, RIE), plasma etching or other suitable etching steps.After etching step terminates, divest method, plasma incineration or its combination by wet type and remove any used photoresist pattern layer (not illustrating).The width of stacking 120 is about 50nm to about 500nm, such as, be about 100nm to about 300nm.
Continue see Fig. 3, form resistance transition layer 160, this resistance transition layer 160 compliance is covered in stacking 120 with in substrate 110.The material of resistance transition layer 160 can be oxide, the PrCaMnO of Al, Hf, Cr, Cu, Ti, Co, Zn, Mo, Nb, Fe, Ni, W, Pb, Ta, La, Zr
3(PCMO), SrTiO
3(STO), SrZrO
3, other any applicable resistance transition material or above-mentioned combination.The formation method of resistance transition layer 160 can be ald (atomic layer deposition, ALD), sputtering method, resistive heating evaporation, e-beam evaporation or other any applicable depositional mode and is formed.Such as, in one embodiment, resistance transition layer 160 uses rf magnetron sputtering (radiofrequency magnetron sputtering, RF) to be formed.The thickness of resistance transition layer 160 is about 1nm to about 100nm, such as, be about 1nm to about 50nm.The voltage that this resistance transition layer 160 can be applied thereto according to second electrode 175A, 175B of the first electrode 140 and follow-up formation changes its resistance value and (such as changes into low-resistance value by high resistance, or change into high resistance by low-resistance value), and be used as 0 of this resistance-type memory or the memorizer information of 1 by the difference of this resistance value.Such as, can apply to be not enough to the small voltage changing its resistance value on resistance transition layer 160, and under this voltage, judge that its memory signals as 0 or 1 by the electric current of resistance transition layer 160 by reading.
Then, see Fig. 4 A-Fig. 4 B, form a second electrode lay 170, this second electrode lay 170 compliance is covered on resistance transition layer 160.The material of this second electrode lay 170 can be TaN, TiN, TiAlN, TiW, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni or above-mentioned combination.This second electrode lay 170 can use sputtering method, resistive heating evaporation, e-beam evaporation or other depositional mode be applicable to be formed.
Then, see Fig. 5 A-Fig. 5 B, carry out the second patterning step pattern second electrode layer 170 to form multiple second electrode pair 180, each second electrode pair 180 respectively has two the second electrode 175A and 175B, and compliance is covered in the opposite side walls of resistance transition layer 160 and the substrate 110 of opposite edge respectively.Second patterning step comprises micro-shadow and etch process.This etching step can comprise reactive ion etching (reactive ion etch, RIE), plasma etching or other suitable etching steps.In addition, this etching step is preferably the dry etching steps such as tropism such as grade not applying applying bias, effectively to etch the upper part that the second electrode lay 170 is positioned at resistance transition layer 160 sidewall.After this dry etching steps terminates, divest method, plasma incineration or its combination by wet type and remove any used photoresist pattern layer (not illustrating).The thickness T of second electrode 175A, 175B is about 1nm to about 100nm, such as, be about 1nm to about 50nm.The length L of second electrode 175A, 175B is about 50nm to about 500nm, such as, be about 100nm to about 300nm.The width W of second electrode 175A, 175B is about 50nm to about 300nm, such as, be about 100nm to about 200nm.
Compared to tradition do not have this pattern second electrode to 180 resistance-type memory, the present invention utilizes this Patternized technique step the second electrode lay 170 to be patterned to second electrode 175A, 175B of two electrically insulated from one another, making the memory span of resistance-type memory of the present invention increase to about 1.2 times to about 2 times of the memory span of traditional resistive memory, such as, is about 1.5 times to about 1.9 times.
Then, see Fig. 6, on second electrode 175A, 175B and resistance transition layer 160, the blanket property covered forms interlayer dielectric layer 190, and this interlayer dielectric layer 190 has smooth upper surface.Interlayer dielectric layer 190 can make silica into using chemical vapour deposition (CVD) (CVD) method to be formed, silicon nitride, silicon oxynitride or other any applicable dielectric material or above-mentioned combination.Chemical vapour deposition technique such as can be Low Pressure Chemical Vapor Deposition (low pressure chemicalvapor deposition, LPCVD), low temperature chemical vapor deposition method (low temperature chemical vapordeposition, LTCVD), be rapidly heated chemical vapour deposition technique (rapid thermal chemical vapordeposition, RTCVD), plasma auxiliary chemical vapor deposition method (plasma enhanced chemical vapordeposition, PECVD), atomic layer deposition method (the atomic layer deposition of atomic layer chemical vapor deposition method, or other conventional method ALD).
Then, see Fig. 7, the 3rd patterning step is carried out to form multiple contact hole to expose the first electrode 140 and each second electrode 175A, 175B.The contact hole corresponding to the first electrode 140 to be directly located on stacking 120 and between the contact hole that second electrode 175A, 175B is corresponding.Then, chemical vapour deposition (CVD) or physical vapour deposition (PVD) is carried out, with deposit metallic material in the contact hole corresponding to the first electrode 140 and each second electrode 175A, 175B to form one first contact plunger 200 and multiple second contact plunger 210.This first contact plunger 200 is electrically connected the first electrode 140, and this second contact plunger 210 is electrically connected each second electrode 175A, 175B respectively.The material of the first contact plunger 200 and the second contact plunger 210 can comprise Cu, Al, W, other any applicable metal material or above-mentioned combination.In one embodiment, the material of the first contact plunger 200 and the second contact plunger 210 can be different.
Then, carry out reflow or chemical mechanical milling tech with planarization first contact plunger 200 and the second contact plunger 210, and complete resistance-type memory 100 as shown in Figure 1.
As shown in Fig. 1 and Fig. 7, the first contact plunger 200 is located between multiple second electrode pair 180, and electrical connection the first electrode 140.It should be noted, in the figure 7, the first contact plunger 200 and the second contact plunger 210 are not positioned at same profile, therefore Fig. 7 is represented by dotted lines the first contact plunger 200.Because the first contact plunger 200 of the present invention is located between multiple second electrode pair 180, it does not need to occupy the area beyond stacking 120, therefore the space can reduced shared by memory component, further this memory component of microminiaturization increase the capacity of this resistance-type memory.In addition, the present invention is the same with general resistance-type memory technique, all use three road Patternized technique steps, therefore manufacture method of the present invention does not increase extra process costs, can reach the object increasing memory span.
In addition, although in Fig. 7, the first contact plunger 200 to be positioned on the first electrode 140 and to contact the upper surface of the first electrode 140, but, in another embodiment, it is also extensible enters among the first electrode 140, or runs through the first electrode 140 and contact the upper surface of the first insulating barrier 130.In another embodiment, the first contact plunger 200 is extensible to be entered among the first insulating barrier 130, or runs through the first insulating barrier 130 and contact the upper surface of substrate 110.It should be noted although Fig. 1 only illustrates two group of second electrode pair 180, but to have in the art and usually know that the knowledgeable also can form the second electrode pair 180 more than two.
In sum, the present invention is by being located between multiple second electrode pair by the first contact plunger, and the second electrode lay is patterned to two the second electrodes, can when not increasing Patternized technique step, further this memory component of microminiaturization increase the capacity of this resistance-type memory, such as, increase the capacity of about 1.2 times to about 2 times.
Although embodiments of the invention and advantage thereof have disclosed as above; but will be appreciated that; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when changing, substitute and retouching, therefore protection scope of the present invention is when being as the criterion depending on the claim person of defining.
Claims (12)
1. a resistance-type memory, is characterized in that, described resistance-type memory comprises:
One substrate;
One is stacking, comprising:
One first insulating barrier, is located in this substrate;
One first electrode, is located on this first insulating barrier; And
One second insulating barrier, is located on this first electrode;
One resistance transition layer, compliance is covered in that this is stacking with in this substrate;
Multiple second electrode pair, above-mentioned second electrode pair respectively has two the second electrodes, and compliance is covered in the opposite side walls of this resistance transition layer and this substrate of opposite edge respectively;
One first contact plunger, to be located between the plurality of second electrode pair and to be electrically connected this first electrode; And
Multiple second contact plunger, is electrically connected above-mentioned each second electrode respectively.
2. resistance-type memory according to claim 1, is characterized in that, the material of this first electrode and this second electrode comprises TaN, TiN, TiAlN, TiW, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni or above-mentioned combination independently of one another.
3. resistance-type memory according to claim 1, is characterized in that, the material of this resistance transition layer comprises the oxide of Al, Hf, Cr, Cu, Ti, Co, Zn, Mo, Nb, Fe, Ni, W, Pb, Ta, La, Zr, PrCaMnO
3, SrTiO
3, SrZrO
3, or above-mentioned combination.
4. resistance-type memory according to claim 1, is characterized in that, the thickness of this first electrode, this second electrode and this resistance transition layer is respectively 1nm to 50nm.
5. resistance-type memory according to claim 1, is characterized in that, this first contact plunger and this second contact plunger comprise Cu, Al or W independently of one another.
6. resistance-type memory according to claim 1, is characterized in that, this first contact plunger runs through this first electrode and contacts the upper surface of this first insulating barrier.
7. resistance-type memory according to claim 1, is characterized in that, this first contact plunger runs through this first insulating barrier and contacts the upper surface of this substrate.
8. a manufacture method for resistance-type memory, is characterized in that, the manufacture method of described resistance-type memory comprises:
One substrate is provided;
Being formed one is stacked in this substrate, and this is stacking comprises:
One first insulating barrier, is located in this substrate;
One first electrode, is located on this first insulating barrier; And
One second insulating barrier, is located on this first electrode;
Form a resistance transition layer, this resistance transition layer compliance is covered in that this is stacking with in this substrate;
Form multiple second electrode pair, above-mentioned second electrode pair respectively has two the second electrodes, and compliance is covered in the opposite side walls of this resistance transition layer and this substrate of opposite edge respectively;
Form one first contact plunger between the plurality of second electrode pair, this first contact plunger is electrically connected this first electrode; And
Form multiple second contact plunger, above-mentioned second contact plunger is electrically connected above-mentioned each second electrode respectively.
9. the manufacture method of resistance-type memory according to claim 8, it is characterized in that, the material of this first electrode and this second electrode comprises TaN, TiN, TiAlN, TiW, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni or above-mentioned combination independently of one another.
10. the manufacture method of resistance-type memory according to claim 8, is characterized in that, the material of this resistance transition layer comprises the oxide of Al, Hf, Cr, Cu, Ti, Co, Zn, Mo, Nb, Fe, Ni, W, Pb, Ta, La, Zr, PrCaMnO
3, SrTiO
3, SrZrO
3, or above-mentioned combination.
The manufacture method of 11. resistance-type memories according to claim 8, is characterized in that, the thickness of this first electrode, this second electrode and this resistance transition layer is respectively 1nm to 50nm.
The manufacture method of 12. resistance-type memories according to claim 8, is characterized in that, this first contact plunger and this second contact plunger comprise Cu, Al or W independently of one another.
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Cited By (1)
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| CN110546778A (en) * | 2018-03-16 | 2019-12-06 | 深圳市汇顶科技股份有限公司 | Memristor manufacturing method, memristor and resistive random access memory RRAM |
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| TW201115721A (en) * | 2009-10-29 | 2011-05-01 | Univ Nat Chiao Tung | Resistive random access memory and its manufacturing method |
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