TW201115721A - Resistive random access memory and its manufacturing method - Google Patents

Abstract

This invention relates to a resistive random access memory, which includes a first electrode, a second electrode disposed on the top of the first electrode, a dielectric layer disposed between the first electrode and the second electrode, and an electrode-mixed system layer disposed between the first electrode and the dielectric layer; where at least one of the first electrode and the second electrode is composed of transition metal elements, and moreover, a first resistive transient layer composed of FeO or CoO can be formed between the electrode-mixed system layer and the dielectric layer by means of CVD or annealing treatment.

Description

201115721 • VI. Description of the Invention: [Technical Field] The present invention relates to a resistive random access memory and a method of manufacturing the same, in particular, a resistive memory structure formed by a system with a matching electrode age And its method of production. [Prior Art] Patent Document 1 (TW20〇8l8l9〇) and Patent Document 2 (TW2〇〇824〇46) • Reveals a resistive memory element and its manufacturing method, however, it has the following drawbacks: 1. Patented wire 1 And the special metal oxide (2) is used as a resistance transition layer, which makes the composition of the metal oxide layer usually non-stoichiometric (n〇n-st〇ichi〇metric) and the composition is not easy in the process. Production, that is, process uniformity variation is large. 2. If the non-stoichiometric _ metal oxide is produced by the techniques of Patent Document 1 and Patent Document 2, it is necessary to use the atomic layer insect crystal technology ((10)) for the fine medium control, but this production method requires a large amount of manufacturing cost. Does not meet the mass production needs. 3. The process of using metal oxide as a resistive memory *CM〇s process is incompatible. 4. When metal oxide is used as the resistance transition layer, the etching process is more difficult than the lift-off method, and the metal oxide resistance transition layer often has to be subjected to high temperature treatment, and this step is greatly increased. Process cost and production time. In addition, Non-Patent Document 1 (Lee et al., ‘‘Electr〇migratiQn etfeet Qf Μ

[S 3 201115721 electrodes on the resistive switching characteristics of NiO thin films," Appl. Phys. Lett. 91,082104 (2007).) is the use of a hybrid electrode as an electrode of a resistive memory, although it is disclosed in this document. The transition state, however, since the intermediate transition layer still uses the Ni〇 transition state metal oxide, Non-Patent Document 1 cannot solve the etching problem encountered when fabricating a small size, and the mixed electrode NiPt electrode may be operated for a long time. , causing electromigration effects, making

The introduction of Ni metal into the insulating layer causes excessive metal components in the transition layer to cause the transition characteristics to disappear. Non-Patent Document 2 (SB Lee et al., "Resistance switching in Electroformed Pt/FeOx^>t Structure; 5 Journal of the Korean Physical Society, 51, S96 (2007).) discloses the use of iron oxide as a resistive memory Although the bulk material has a transition property, the thickness of the iron oxide is reduced when the process is miniaturized. The non-patent document 3 (1. S. Park et. al., "Resistance Switching"

Characteristics for Nonvolatile Memory Operation of Binary

Metal Oxides," Jpn. J. Appl. Phys., Vol. 46, No. 4B (2007), pp. 2172-2174.) discloses the use of Si〇2 as an insulating layer, with poor transition characteristics (high and low resistance) It is about 10 or so) and the operating voltage is large (8¥ and 12乂), which causes excessive power consumption during operation of the component, and is low in practical application level. Based on the above-mentioned prior art, the present invention provides A resistive random access memory and a method of manufacturing the same, the invention provides a resistive memory device comprising: a first electrode; a second electrode disposed on the Above the first electrode; a dielectric layer, disposed between the first electrode and the second electrode; a first resistive transition layer disposed between the first electrode and the dielectric layer; and a second The resistance transition layer is disposed between the β-electrode and the 介 介 dielectric layer, wherein at least one of the first electrode and the second electrode is composed of a transition state element. Another object of the present invention Providing a method of manufacturing a resistive memory element, The method comprises: sequentially forming a first electrode, a dielectric layer, an electrode mixing system layer and a second electrode on a substrate, wherein the CVD process can be performed when the dielectric layer and the electrode are mixed with the system layer Or forming an initial resistive transition layer between the electrode mixing system layer and the dielectric layer; wherein at least one of the first electrode and the second electrode is composed of a transition state element. The resistive memory device and the method of manufacturing the same, wherein the transition state element is any one of PtFe, CGFe, PtHf, Fe, Ni, Co, or an alloy thereof. According to the above-described resistive memory device and a method of manufacturing the same The first electrode is composed of Ti, TiN, PtFe, CoFe, PtHf, Fe, Ni, C, and wherein the second electrode is composed of Ti, TiN, ptFe, c〇Fe, gall, Fe According to the above-described resistive recording element and method, the dielectric layer is composed of Wei Lu or Wei Ni reading. According to the above-described resistive memory element and the like Manufacturing method, wherein the Shi Xi oxygen 201115721 The compound is cerium oxide (SiO 2 ). The resistive memory device and the method of manufacturing the same according to the above, wherein the first resistive transition layer and the second resistive transition layer are made of iron oxide (Fe 〇) or an oxidized drill (CoO). A further object of the present invention is to provide a method for manufacturing a resistive memory device, comprising the steps of: preparing a substrate; depositing a first electrode; and depositing an electrode mixing system on the first electrode Layer; deposition of an oxidized insulating layer by a CVD system, followed by a heating system of the deposition environment and an oxygen gas atmosphere introduced during deposition to form a layer-diffusion, transitional ultra-thin resistance transition layer; deposition-second electrode, And the yellow light, the lithography, the side technology to set the shape of the original memory and then cooperate with the metal Lian County to pull out the measuring electrode as the position of the probe when measuring. The invention has the following technical features and effects: The invention is a method for depositing an oxide insulator (such as dioxide dioxide) in a chemical vapor deposition manner in an electrode mixing system (eg, c〇, & Oh,

A resistive transition layer is formed on Cc>Fe, PtHf...etc). The invention is based on PtFe or a transition state element electrode mixing system (such as % Fe,

Ni, WPtFe, C〇Fe".etc) is used as an electrode, and is formed by a chemical vapor deposition method to form a non-volatile resistive memory element. 3. Use of sulphur dioxide and related stone oxides (such as surface, purchased and oxide insulators (such as · · fine 3, Tl 〇 2), with electrode ready system (such as c〇, Fe, pneumatic pick r 201115721

PtFe, (d), chaos.e scare the structure of the memory as a residual memory. When the chemical vapor phase is used to form an oxide insulator layer (the temperature of the deposition (such as 3〇〇c) and the atmosphere of the aerobic atmosphere, or (2) the connection after the deposition is completed, for a long time The thermal annealing process (such as pass. c), accompanied by the formation of a very thin resistance transition layer (such as secret, (5) town for the component electrical rotation _ effective area. This case uses the transition state element easy to oxidize characteristics plus appropriate insulator as insulation

The layer reduces the possibility of passing current due to over-oxide, making the resistive memory element relatively stable in operation and therefore has the potential to be a non-volatile storage memory element for the next generation. 4. Since the dioxotomy is highly compatible with the CMOS process, the present invention can be applied to non-volatile memory. 5. Using the extremely thin resistive layer formed by the dioxoderes and the lower electrode allows the component size to be reduced further down, thereby increasing the storage density. 6. There is no need to reduce the balance and the highest system. c. Chemical vapor deposition The temperature at which an oxide insulator (such as dioxo) is deposited, and is highly compatible with CMOS processes in the latter process. Wang 7. The use of transitional greening, coupled with the use of a suitable insulator as an insulating layer to reduce the possibility of passing current due to excessively thin oxides, makes the resistive memory element of the present invention relatively stable in operation. . The above and other objects, advantages and advantages of the present invention will become more apparent from the following detailed description. [Embodiment] ° 201115721 The application of the present invention is not limited to the descriptions of the following description, drawings or the detailed construction and configuration of the components. The invention has further embodiments and can be implemented or carried out in various ways. In addition, the phrase used in the present invention is intended to be merely illustrative of the invention and is not to be construed as limiting. The manufacturing method of the resistive random access memory will be described in detail with reference to the drawings. Referring to Figure 1, there is shown a cross-sectional view of a resistive random access s memory in accordance with an illustrative embodiment of the present invention. However, the present invention is not limited to this exemplary embodiment, that is, other embodiments are still known to those of ordinary skill in the art in view of the drawings and contents of the present specification. As shown in FIGS. 1A to 1E, the long Si〇2 (the oxide buffer layer may also be on the substrate) after Si is plated with a sputtering method, or a chemical is used. Vapor deposition is used to deposit the dioxide, and the PtFe upper electrode is plated as a different upper electrode size through the yellow light and the engraving process. Finally, the ώ (or 'A1) electrode is pulled out as the probe placement during our measurement. s position. Next, Fig. 2 is a graph showing the voltage of the motor under the structure of the Ti/TiN/Si〇2/ptFe hybrid electrode. In the lower left corner of the figure, the area of the upper electrode is indicated. The lower right corner indicates the scan from the first to the fifth. The arrow indicates the direction of operation after a negative charge has formed gamma. It can be observed from the figure that the use of the dioxide high energy gap oxide can have stable resistance transition characteristics on the transition state mixed electrode, and the use of the small rule method can make the conversion rate low, and increase the practical application of the component. Possible 0 [ S3 201115721 - Sex. Referring to Figures 3 to 4, FIG. 3 is a view showing the decrease in the resistance value when the upper electrode is different (10) and the decrease in the reset current value when the size of the upper electrode is reduced. It can be seen from the figures 3 to 4 that when the size of the upper electrode is different, the LRSf is reduced, so that the ratio of the resistance value (rat1〇) can be increased. In addition, when the size of the upper electrode is reduced, the reset current value is lowered. Next, referring to Fig. 5, the _degree test of the (four) # stream is read by using the Dc voltage to operate the face back and forth. The figure can be divided into two parts: low resistance and high resistance. It can be seen from the figure that after _ times of operation, there is still HM in the high and low resistance states. The resistance can be distinguished by the interval. It can be seen that this structure is both current and reproducible. ' 曰 曰 参 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四Read the secondary current value to see if the original resistance state has changed. It can be seen from the memory test that the maintenance time of the component made by this structure can be (4) live, where is the fragmentation or HRS, and the extrapolation can transfer the memory capacity of mG years. It should be noted that the intermediate transition layer (e.g., composed of FeOx) is naturally formed using the C· redundancy step. Alternatively, the intermediate transition layer can be formed by subsequent additional annealing steps. The above is only a preferred embodiment of the present invention, but the scope of implementation of the present invention is not limited thereto. For example, the insulating layer is also formed by reliable PVD physical weather deposition to 201115721; in addition, the insulating layer is The thickness is at least greater than 5 nm (to prevent tunneling current from occurring), and the electron forming voltage can be controlled by adjusting the thickness; further, the insulating layer can be made of an insulating material containing oxygen (such as dioxide)矽, alumina, titanium oxide, bismuth oxynitride). Therefore, modifications and variations of the present invention in accordance with the scope of the invention and the scope of the invention are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are views showing a resistive random access memory according to an exemplary embodiment of the present invention. Fig. 2 is a graph showing the current pressure curve of the TiN/SiO 2 /PtFe mixed electrode structure of the present invention. Fig. 3 is a view showing a decrease in the LRS resistance value when the upper electrode size is different. Fig. 4 is a view showing a decrease in the reset current value when the size of the upper electrode is reduced. Fig. 5 is a schematic diagram showing the resistance of the current of 〇.5 v when the DC voltage is operated back and forth 1 time. Fig. 6 is a view showing the memory test of the present invention in a high resistance state and a low resistance state. [Description of main component symbols] 10 Ceria layer 201115721 11 First electrode layer 12 Dielectric layer 13 Second electrode layer 14 Protective layer 15、16 Measuring electrode

Claims (1)

201115721 VII. Patent application scope: 1. A resistive memory device, comprising: a first electrode; a second electrode disposed above the first electrode; a dielectric layer disposed on the first electrode and the first Between the two electrodes; and an electrode mixing system layer disposed between the first electrode and the dielectric layer, wherein at least one of the first electrode and the second electrode is composed of a transition state metal element . The resistive memory element of claim 1, wherein the transition metal element is any one of Pt, Ta, Ti, and A1 or an alloy thereof. 3. The resistive memory device of claim 1, wherein the first electrode is made of any one of Ti, TiN, PtFe, CoFe, PtHf, Fe, Ni, and Co. 4. The resistive memory device of claim 1, wherein the second electrode is made of any one of Ti, TiN, PtFe, CoFe, PtHf, Fe, Ni, and Co. 5. The resistive memory device of claim 1, wherein the dielectric layer is composed of a cerium oxide or a cerium oxynitride. 6. The resistive memory device of claim 5, wherein the antimony oxide is cerium oxide (SiO 2 ). 7. The resistive memory device of claim 1, wherein the electrode mixing system layer and the dielectric layer are further encapsulated by a CVD or annealing process. 12 201115721 comprising an iron oxide (FeO) Or a first resistive transition layer formed by a oxidized gutta (CoO). 8. The resistive memory device of claim 1, wherein when the electrode mixing system layer is disposed between the dielectric layer and the second electrode layer, the dielectric layer and the electrode mixing system The second resistive transition layer composed of iron oxide (FeO) or oxidized (CoO) may be further included between the layers by a CVD or annealing process. 9. The resistive memory device of claim 1, wherein the electrode mixing system layer is composed of any one of Co, Fe, Ni, or PtFe, CoFe, PtHf or an alloy thereof. 10. A method of fabricating a resistive memory device, comprising: sequentially forming a first electrode, an electrode mixing system layer, a dielectric layer, and a second electrode on a substrate, wherein the dielectric layer is formed When the system layer is mixed with the electrode, a first resistance transition layer may be formed between the electrode mixing system layer and the dielectric layer by a CVD process or an annealing process; wherein the first electrode and the second electrode are at least One is composed of a transition state element. 11. The method of claim 10, wherein the transition metal element is any one of Pt, Ta, Ti, A1 or an alloy thereof. The method of manufacturing the first aspect of the invention, wherein the first electrode is made of any one of Ti, TiN, PtFe 'CoFe, PtHf, Fe, Ni, and Co. The manufacturing method of the first aspect of the invention, wherein the second electrode is composed of any one of ruthenium, TiN, PtFe, CoFe, PtHf, Fe, Ni, and Co. 14. The method of manufacture of claim 10, wherein the dielectric layer is comprised of tantalum oxide or a shi oxynitride. 15. The method of manufacture of claim 14, wherein the niobium oxide is cerium oxide (SiO 2 ). 16. The method of claim 1, wherein when the electrode mixing system layer is disposed between the dielectric layer and the second electrode layer, the dielectric layer and the electrode mixing system layer are Further, a second resistance transition layer composed of iron oxide (FeO) or cobalt oxide (CoO) may be contained by a CVD or annealing process. 17. The manufacturing method according to claim 10, wherein the electrode mixing system layer is composed of any one of Co, Fe, Ni, or PtFe, CoFe, PtHf or an alloy thereof. 18. A method of fabricating a resistive memory device, comprising: preparing a substrate; depositing a first electrode; depositing an electrode mixing system layer on the first electrode; depositing an oxidized insulating layer using a CVD system, followed by _ deposition The environment's heating system and the squama's oxygen-environment environment are self-contained—layer-diffused, transitional, extremely thin-resistance transition layer; depositing a second electrode; and using yellow, lithography, and side techniques to define memory The original shape is shaped and subsequently matched with the 201115721 metal wire to pull out the measuring electrode as the position where the probe is placed during the measurement. 15