TW200824046A - Resistive random access memory (RRAM) and method for fabricating the same - Google Patents

Abstract

A resistive random access memory device comprises a first electrode, a second electrode and a resistive switching layer sandwiched between the first and second electrodes, wherein the resistive switching layer comprises a non-stoichiometric first metal oxide sub-layer and a stoichiometric second metal oxide sub-layer formed over the non-stoichiometric first metal oxide sub-layer.

Description

200824046 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a non-volatile memory, and more particularly to a resistive random access memory (RRAM) and its application. Memory cell component. [Prior Art] φ Due to the gradual popularization of portable personal devices such as mobile phones, digital cameras and notebook computers, in view of low energy consumption, the above devices have a long time to turn on or standby, and still remain in the boot and standby conditions. Non-volatile memory is one of the must-have components in order to maintain the memory state of information. As a result, the use of non-volatile memory in consumer electronics has grown. At present, non-volatile memory is mainly flash memory. However, flash memory still faces the disadvantages of excessive operating voltage, slow operating speed, and insufficient durability. In addition, it may also face the disadvantage that the memory time caused by the excessively thin gate oxide layer caused by the shrinkage of the element is not long enough. In order to overcome the aforementioned shortcomings, Resistive Memory (RRAM) is one of the many novel memories developed by the industry at present, which utilizes the principle of a variable resistor to make non-volatile memory. The resistive memory currently developed still faces the problem of high reset current (>lmA), and such high operating current makes its commercial application difficult. 0949-A21771TWF(N2); P51950080TW; shawnchang 5 200824046 SUMMARY OF THE INVENTION In view of the above, there is a need for a relatively improved resistive random access memory having a lower reset current, thereby enhancing its commercial Application. According to an embodiment, the present invention provides a resistive random access memory body comprising: a first electrode; a second electrode; and a resistance conversion layer buried between the first electrode and the second electrode. Wherein the resistance conversion layer comprises one of a non-stoichiometric first metal oxide sublayer and a stoichiometric one of the stoichiometric ones disposed on the first metal oxide sublayer Sublayer. According to another embodiment, the present invention provides a method of fabricating a resistive random access memory, comprising: providing a substrate; forming a first electrode on the substrate; forming a resistance conversion layer on the lower electrode and forming A second electrode is on the resistance conversion layer. Wherein the resistance conversion layer comprises one of a non-stoichiometric first metal oxide sublayer and a stoichiometric one disposed on the first metal oxide sublayer, the second metal oxide Sublayer. The above and other objects, features, and advantages of the present invention will become more apparent and understood. It is a series of schematic diagrams for explaining the memory cell structure of the resistive type 0949-A21771TWF(N2); P51950080TW; shawnchang 6 200824046 random access memory and its application of the present invention. First, please refer to Fig. 1, which shows a cross-sectional view of the memory cell structure of a resistive random access memory known to the applicant. The memory cell structure shown in Fig. 1 is used in comparison with the resistive random access memory cell of the present invention, and is not intended to limit the scope of the present invention. Referring to Figure 1, the memory cell mainly comprises a substrate or a dielectric layer 10, which may be provided with an active device such as a transistor or a diode (not shown). A dielectric layer 12 is disposed on the substrate/dielectric layer 10, and a conductive layer 14 is embedded in the dielectric layer 12. Another dielectric layer 16 is disposed on the dielectric layer 12, and a resistance conversion layer 18 is buried in the dielectric layer 16. Here, the resistance conversion layer 18 is a stoichiometric variable resistance material such as nickel oxide (NiO). Another conductive layer 20 is disposed on the dielectric layer 16. The conductive layer 20 covers the resistance conversion layer 18 and partially covers the dielectric layer 16. It has been experimentally proved that when the resistive layer 18 is made of a stoichiometric ratio of nickel oxide material, the resistive memory made of the resistive memory cell structure as shown in FIG. 1 exhibits a reset current higher than 1 mA. The performance is not conducive to its commercial application. Accordingly, the present invention provides a memory cell structure for a resistive random access memory whose reset current can be reduced to less than 1 mA, which is advantageous for commercial applications. Referring to Figure 2, there is shown a cross-sectional view of a memory cell structure in accordance with an embodiment of the present invention. As shown in Fig. 2, the memory cell structure mainly includes a substrate or a dielectric layer 100 in which an active device such as a transistor or a diode (not shown) may be disposed. A dielectric layer 102 is disposed on the substrate/dielectric layer 100, and a conductive layer 104 is embedded in the dielectric layer 0949-A21771TWF(N2); P51950080TW; shawnchang 7 200824046102. Another dielectric layer 1〇6 is disposed on the dielectric layer 102, and a resistance conversion layer 1〇8 is buried in the dielectric layer 106. Here, the resistance conversion layer 1〇8 is a composite metal oxide layer including a variable resistance material such as a binary metal oxide of a metal such as Hf, Ab, Zr, Nb, Ti, Ta, and La (indicated by Z). (z〇x). As shown in Fig. 2, the resistance conversion layer 108 includes a first metal oxide sublayer i 〇 8b and a second metal oxide sublayer disposed on the first metal oxide sublayer l 〇 8b.

L〇8a, wherein the first metal oxide sublayer 108b and the second metal oxide sublayer 108 are made of a metal oxide having the same element, but the materials used are different, and the first metal oxide sublayer is 8b includes a non-stoichiometric metal oxide material such as a metal oxide such as Hf〇h, A12〇3_x, ZrOx, NbOx, TiOx, NiOx, TaOx, La〇x, and the second metal oxide. The sub-layer 8a includes a stoichiometric same metal oxide material, for example, 11 is still 2

Al2〇3, Zr0, Nb0, Ti0, N10, Ta0, La〇, etc. For example, the first metal oxide sub-layer 108b may include Hf〇μ one person 2-χ' and the dianth-to-oxide layer 108a includes Hf〇2, and at this time, the meaning is preferably λ./;· χ α 71 is at 0 · 11 1*5. The ratio of the film thickness of the metal oxide sublayer l〇8b to the second metal _ is about ι:ιοο~ιοο:ι. A dielectric layer 110 is disposed between the dielectric layers 108a. The conductive layer 110 is covered with electricity, and the other layer is provided with another

The dielectric layer 106 is covered. The conductive layers 104 and 11 can be V" replaced with a layer 108 or a conductive material such as Ru. For example, when Pt, Au, and TlN are twisted and used as non-chemical rolling materials, the composite type metal 0949-A21771TWF(N2); P51950080TW is used as shown in the experiment. ;shawnchang 8 200824046 2 The memory cell structure shown in the figure is made of electricity and 々% | eight redundant body and has a reset current of about ΙΟΟμΑ. Because of this memory, the surname of the memory, t, and α alone can be reduced to less than 1 mA, so it is very beneficial for commercial deer. Or, as shown in Figure 3, the resistor The conversion layer 1 〇 8 is a third metal oxide sub-layer 108c, which is disposed on the 篦 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Here, the third metal oxide (3) also employs a <non-stoichiometric metal oxide material which is the same as the first metal oxide sublayer. For example, the third metal oxide sublayer l〇8c, the film between the second metal oxide sublayer 108a and the second metal oxide sublayer 108a; ^士0物久层1〇8b 1:一卜如第2 The thickness of the figure shown in Fig. 3 is about 10 to 100 nm. At this time, the first-eight-layer layer 108 108b and the third metal oxide sub-layer (10)c preferably include a postal-, second-second metal oxide sub-layer including Hf02, and x is preferably = 〇·1~ 1.5 For example, the resistive type shown in Figures 2 and 3 is connected to the six #, +, , , ι electric 丨 and the k-machine access memory is described as follows, first providing a base or - Jie Lei eight + R; 丨 electric layer w〇. Then, a dielectric layer 1〇2 is formed on the substrate/'s tortoise layer 100, and an opening (not numbered) can be set in the dielectric layer 102, and the opening portion is 7^'1nA L ^ The base/dielectric Μ 1 下方 below. The opening shape in the dielectric layer 102 is formed into a conductive layer 104 for use as a lower electrode. Then, a ', 〇6' is formed on the dielectric layer 2, and an opening (4) ticket number is formed in the dielectric layer 106. The above opening: the teeth penetrate the dielectric layer 106 and partially expose the cold electric layer 104 of the lower side + J ° person a. Then, a resistor is formed in the opening in the private dielectric layer 106 and the conversion layer 1〇8 is formed, for example, 〇949~A2l771TWF(N2); P51950080TW; shawnchang 9 200824046 or the composite metal shown in FIG. Oxide layer structure. Each of the metal oxide sublayers in the resistance conversion layer i〇8 may be sequentially or simultaneously formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). The metal oxide sublayer in the resistance conversion layer 108 of the ruthenium is made by atomic layer deposition method to form a resistance conversion layer 1〇8 containing a sublayer of materials such as Hf〇2 and Hf02_x. Hfcl4 and H2 are used as precursors of the reaction, and are deposited at a temperature of 200 to 400 ° C, and the pulse time of each of the above precursors is about 100 to 1000 msec. Further, the ratio of the precursors is moderately adjusted in the atomic layer deposition, thereby forming a composite metal oxide layer structure including a non-stoichiometric ratio and a stoichiometric ratio to the oxide as shown in Fig. 2 or Fig. 3. Alternatively, the resistance conversion layer 108 may also be a metal oxide layer having a non-stoichiometric ratio obtained by treating a metal oxide layer formed by atomic deposition in an oxygen-containing or aqueous atmosphere to prepare a metal oxide layer. The resistance conversion layer 1G8 shown in Figs. 2 and 3. Then, a conductive layer no'v cladding layer is formed on the dielectric layer to cover the resistance conversion layer 1〇8 and a portion of the adjacent dielectric layer 06 for use as an upper electrode, thereby preparing a method suitable for the present invention. Memory cell structure of resistive random access memory. In addition, FIG. 4 and FIG. 5 are a series of schematic diagrams showing a cross-sectional view of the resistive random access memory of the present invention, which is a resistive random access memory cell structure as shown in FIG. 2 or FIG. And an active device. As shown in Fig. 4, a resistive random access memory cell structure of the present invention and a resistive random access memory including a transistor are not shown. Here, the 0949-A21771TWF (N2); P51950080TW; shawnchang 200824046 transistor includes a gate G disposed on a substrate 200 and a source region 220 and a drain region 240 disposed in the substrate 200, and the gate G includes A gate dielectric layer 206 and a gate electrode 208 are stacked on the substrate 200 in sequence. A dielectric layer 210 is additionally disposed on the substrate 210 to cover the above-mentioned electric crystal. The memory cell structure as shown in FIG. 2 and FIG. 3 is embedded in the dielectric layer 210, and is still shown as a resistance conversion layer 1〇8 and conductive layers 1〇4 and 110, wherein the conductive layer 104 is buried. The dielectric layer 110 is electrically connected to the source region 220, and the conductive layer 110 is disposed on the dielectric layer 210, and the resistance conversion layer 108 is buried in the dielectric between the conductive layers no and 〇4. In layer 210. Here, the transistor can be an N- or p-type transistor, so that the source region 220 and the drain region 240 can be an n-type or p-type ion doped region depending on their conductivity type. Conductive plugs 214 and 212 may be further disposed in the dielectric layer 210, which are respectively connected to the gate electrode 208 and the drain region 212 for subsequent electrical connection. Please refer to Fig. 5, which shows a resistive random access memory cell structure of the present invention and a resistive random access memory of a diode. Here, the pole body includes a first well region 302 disposed in a substrate 300, a second well region 304 and a contact region 306 located in the first well region 302. Substrate 300 has a first doping characteristic, such as N or p-type doping, while first well region 302 has a second doping characteristic that is opposite to the first doping characteristic of substrate 3. The doped region 306 has the same doping characteristics as the first well region 302. The ion doping concentration of the spine is higher than that of the first well region. a dielectric layer 3〇8 is disposed on the substrate 3(10), and a memory cell structure as shown in FIG. 2 and FIG. 3 is disposed in the dielectric layer 3〇8, and is still 〇949-A21771TWF(N2); P51950080TW; shawnchang 11 200824046 is shown as a resistance conversion layer 108 and conductive layers 104 and 110, wherein the conductive layer 104 is embedded in the dielectric layer 308 and electrically connected to the second well region 302, and the conductive layer 110 is disposed in the dielectric layer 110 Above the electrical layer 308, the resistive switching layer 108 is embedded in the dielectric layer 308 between the conductive layers 110 and 104. A conductive plug 310 may be further disposed in the dielectric layer 308, which is coupled to the contact region 306 for subsequent electrical connection. In addition to the aforementioned advantages of low reset current, the resistive random access memory of the present invention can also avoid the possibility that the conventional flash memory may be exposed to excessively thin gate oxide layers due to component shrinkage. The shortcomings of memory time are not long enough to enhance the possibility of commercial application. While the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

0949-A21771TWF(N2); P51950080TW; shawnchang 12 200824046 [Simplified Schematic] FIG. 1 is a schematic view showing a cross-sectional view of a resistive random access memory according to an embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic view showing a cross-sectional view of a resistive random access memory according to an embodiment of the present invention; FIG. 3 is a schematic view partially showing a resistive type according to another embodiment of the present invention; a cross-sectional view of the random access memory; φ FIG. 4 is a schematic view showing a cross-sectional view of a resistive random access memory according to an embodiment of the present invention; and FIG. 5 is a schematic view showing the basis A cross-sectional view of a resistive random access memory of another embodiment of the invention. [Main component symbol description] 10~substrate/dielectric layer; 12,16~dielectric layer; φ14,20~conductive layer; 18~resistive conversion layer; 100~substrate/dielectric layer; 102,106~dielectric Layer; 104, 110~ conductive layer; 108a~ first metal oxide sublayer; 108b~ second metal oxide sublayer; 108c~ third metal oxide sublayer; 108~ resistance conversion layer; 0949-A21771TWF(N2 ); P51950080TW; shawnchang 13 200824046 200~ substrate; 206~ gate dielectric layer; 208~ gate electrode; 210~ dielectric layer; 212, 214~ conductive plug; 220~ source region, 24 0~ > Zone, 300~base; 10 302~ first well zone; 304~second well zone; 3 06~ contact zone; 308~ dielectric layer; 310~ conductive plug. 0949-A21771TWF(N2); P51950080TW;shawnchang 14

Claims (1)

200824046 X. Patent application garden: 1. A resistive random access memory comprising: a first electrode, a second electrode; and a resistance conversion layer embedded in the first electrode and the first band ^ ^ The gate of the pole, wherein the resistance conversion layer comprises: s 'metal oxidization non-stoichiometric - the first sub-layer; A stoichiometric second metal layer disposed on the first metal oxide sublayer. Level 2: Resistor type random as described in item 1 of the patent application scope; ^T, Ta, and body, wherein the resistance conversion layer is selected from metals such as Hf, Al, Zr, Nb, and The group of oxides. 3 · If the patent application consumes a power-type random body as described in item 1, wherein the first metal oxide sub-layer and the second full-thickness belong to the emulsifier sub-dance between 1:100~ A film thickness ratio of 100:1. 4. The resistive ρ 八 ⁄ 存取 存取 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The third metal oxide is sub-displayed and disposed on the second metal oxide layer. The resistive random accessor of claim 4, wherein the first metal oxide sublayer and the second metal oxide and the second oxide and the second The metal oxide sublayers have a film thickness ratio of between 曰 and 1.100 〜100:1, respectively. 6. The resistive random access memory of claim 1, wherein the resistance conversion layer has a thickness of between 10 and 100 nm. 7. The resistive random access memory of claim 4, wherein the resistance conversion layer has a thickness of between 10 and 1 nanometer. 8. The resistive random access memory of claim 1, wherein the first metal oxide sublayer comprises Hf〇2_x, the second metal oxide sublayer comprises Hf02, and X is between 0· 1 to 1.5. 9. The resistive random access memory 10 according to claim 4, wherein the first metal oxide sublayer comprises Hf02_x, and the second metal oxide sublayer comprises Hf02, the third metal oxide The secondary layer includes Hf02_y, X is between 0.1 and 1.5 and y is between 0.1 and 1.5. 10. The resistive random access memory of claim 1, wherein the first and second electrodes comprise Pt, Au, TiN or Ru. 11. The resistive random access memory of claim 1, further comprising a substrate disposed under the first electrode, wherein the substrate comprises an active device, and the first electrode is electrically connected In the active device. 12. The resistive random access memory device of claim 11, wherein the active device is a diode or a transistor. 13. The resistive random access memory device of claim 11, wherein the first electrode is electrically coupled to one of the ion doped regions of the active device. A method of manufacturing a resistive random access memory, comprising: providing a substrate to form a first electrode on the substrate; 0949-A21771TWF(N2); P51950080TW; shawnchang 200824046 forming a resistance conversion layer at the first On the electrode, the layer includes: one of the non-stoichiometric ones - the human seven-sub-layer; and one of the stoichiometric ones of the second metal oxide layer 'e a first metal oxide sublayer; and a second electrode formed on the resistance conversion layer. 'is. For example, please refer to the manufacturing method of the m-memory body described in Item 14, in which the resistance conversion layer (ALD) is formed. /Kianjingzi layer 16· As stated in the 15th item of the scope of the patent application, the 愔妒 制 system! Shi, + ^ % 丨 ^ ^ 存取 存取 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The method for manufacturing a resistor-remembered body according to claim 14, wherein the substrate is provided with a scorpion-sucking cage + a buckle; an active device, and 3 brothers An electrode is electrically connected to the active device. For example, the manufacturing method of the electronic memory body described in the πth item of the patent application is as follows: wherein the active device is a 2-pole F body type, and the storage device is a 19. . The manufacturing method of the body of the body, wherein the resistance conversion layer is selected from the group consisting of oxides of metals such as Nb, Ti, Ta, La, etc., and the electric enthalpy according to item 14 of the patent scope of Shenqing. And a method for producing a gas p & a memory in which the first metal oxide is sub-distributed and accessed. The second gold 0949-A21771 TWF(N2); P51950080TW; shawnchang 17 200824046 has a film thickness ratio of 1:100~100:1 between the oxide sublayers. 21. The method of manufacturing a resistive random access memory according to claim 14, wherein the resistance conversion layer further comprises a non-stoichiometric one of the third metal oxide sublayers. On the second metal oxide sublayer. 22. The resistive random access memory according to claim 21, wherein the first metal oxide sublayer and the third metal oxide sublayer and the second metal oxide sublayer respectively have a dielectric layer The film thickness ratio is 1:100~100:1 ® . 23. The method of manufacturing a resistive random access memory according to claim 14, wherein the resistance conversion layer has a thickness of from 10 to 100 nm. 24. The method of manufacturing a resistive random access memory device according to claim 21, wherein the resistance conversion layer has a thickness of from 10 to 100 nm. The method of manufacturing a resistive random access memory according to claim 14, wherein the first metal oxide sublayer comprises Hf〇2_x, and the second metal oxide sublayer comprises Hf02, x Between 0.1 and 1.5. 26. The method of manufacturing a resistive random access memory according to claim 21, wherein the first metal oxide sublayer comprises Hf02_x, and the second metal oxide sublayer comprises Hf02, the third metal The oxide sublayer includes Hf02_y, X is between 0.1 and 1.5 and y is between 0.1 and 1.5. 0949-A21771TWF(N2); P51950080TW; shawnchang 18